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sdhci - Use bus_dmamem_coherent for allocating memory for sdma DMA.
[dragonfly.git] / sys / dev / disk / sdhci / sdhci.c
blob451cbec868fab4455255aebe96bbd5e8023820f5
1 /*-
2 * Copyright (c) 2008 Alexander Motin <mav@FreeBSD.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
16 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
17 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
20 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
21 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
24 *
25 * $FreeBSD: src/sys/dev/sdhci/sdhci.c,v 1.8 2009/02/17 19:12:15 mav Exp $
26 */
27
28 #include <sys/param.h>
29 #include <sys/systm.h>
30 #include <sys/bus.h>
31 #include <sys/callout.h>
32 #include <sys/conf.h>
33 #include <sys/kernel.h>
34 #include <sys/lock.h>
35 #include <sys/module.h>
36 #include <sys/spinlock.h>
37 #include <sys/resource.h>
38 #include <sys/rman.h>
39 #include <sys/sysctl.h>
40 #include <sys/taskqueue.h>
41
42 #include <bus/mmc/bridge.h>
43 #include <bus/mmc/mmcreg.h>
44 #include <bus/mmc/mmcbrvar.h>
45
46 #include "mmcbr_if.h"
47 #include "sdhci.h"
48 #include "sdhci_if.h"
49
50 SYSCTL_NODE(_hw, OID_AUTO, sdhci, CTLFLAG_RD, 0, "sdhci driver");
51
52 int sdhci_debug = 0;
53 TUNABLE_INT("hw.sdhci.debug", &sdhci_debug);
54 SYSCTL_INT(_hw_sdhci, OID_AUTO, debug, CTLFLAG_RW, &sdhci_debug, 0, "Debug level");
55
56 #define RD1(slot, off) SDHCI_READ_1((slot)->bus, (slot), (off))
57 #define RD2(slot, off) SDHCI_READ_2((slot)->bus, (slot), (off))
58 #define RD4(slot, off) SDHCI_READ_4((slot)->bus, (slot), (off))
59 #define RD_MULTI_4(slot, off, ptr, count) \
60 SDHCI_READ_MULTI_4((slot)->bus, (slot), (off), (ptr), (count))
61 #define WR1(slot, off, val) SDHCI_WRITE_1((slot)->bus, (slot), (off), (val))
62 #define WR2(slot, off, val) SDHCI_WRITE_2((slot)->bus, (slot), (off), (val))
63 #define WR4(slot, off, val) SDHCI_WRITE_4((slot)->bus, (slot), (off), (val))
64 #define WR_MULTI_4(slot, off, ptr, count) \
65 SDHCI_WRITE_MULTI_4((slot)->bus, (slot), (off), (ptr), (count))
66
67 static int slot_printf(struct sdhci_slot *, const char *, ...)
68 __printflike(2, 3);
69
70 static void sdhci_set_clock(struct sdhci_slot *slot, uint32_t clock);
71 static void sdhci_start(struct sdhci_slot *slot);
72 static void sdhci_start_data(struct sdhci_slot *slot, struct mmc_data *data);
73
74 static void sdhci_card_task(void *, int);
75
76 /* helper routines */
77 #define SDHCI_LOCK(_slot) lockmgr(&(_slot)->lock, LK_EXCLUSIVE)
78 #define SDHCI_UNLOCK(_slot) lockmgr(&(_slot)->lock, LK_RELEASE)
79 #define SDHCI_LOCK_INIT(_slot) lockinit(&(_slot)->lock, "sdhci", 0, LK_CANRECURSE)
80 #define SDHCI_LOCK_DESTROY(_slot) lockuninit(&(_slot)->lock);
81 #define SDHCI_ASSERT_LOCKED(_slot) KKASSERT(lockstatus(&(_slot)->lock, curthread) != 0);
82 #define SDHCI_ASSERT_UNLOCKED(_slot) KKASSERT(lockstatus(&(_slot)->lock, curthread) == 0);
83
84 #define SDHCI_DEFAULT_MAX_FREQ 50
85
86 #define SDHCI_200_MAX_DIVIDER 256
87 #define SDHCI_300_MAX_DIVIDER 2046
88
89 /*
90 * Broadcom BCM577xx Controller Constants
91 */
92 #define BCM577XX_DEFAULT_MAX_DIVIDER 256 /* Maximum divider supported by the default clock source. */
93 #define BCM577XX_ALT_CLOCK_BASE 63000000 /* Alternative clock's base frequency. */
94
95 #define BCM577XX_HOST_CONTROL 0x198
96 #define BCM577XX_CTRL_CLKSEL_MASK 0xFFFFCFFF
97 #define BCM577XX_CTRL_CLKSEL_SHIFT 12
98 #define BCM577XX_CTRL_CLKSEL_DEFAULT 0x0
99 #define BCM577XX_CTRL_CLKSEL_64MHZ 0x3
100
101
102 static int
103 slot_printf(struct sdhci_slot *slot, const char * fmt, ...)
104 {
105 __va_list ap;
106 int retval;
107
108 retval = kprintf("%s-slot%d: ",
109 device_get_nameunit(slot->bus), slot->num);
110
111 __va_start(ap, fmt);
112 retval += kvprintf(fmt, ap);
113 __va_end(ap);
114 return (retval);
115 }
116
117 static void
118 sdhci_dumpregs(struct sdhci_slot *slot)
119 {
120 slot_printf(slot,
121 "============== REGISTER DUMP ==============\n");
122
123 slot_printf(slot, "SDMA addr: 0x%08x | Version: 0x%08x\n",
124 RD4(slot, SDHCI_SDMA_ADDRESS), RD2(slot, SDHCI_HOST_VERSION));
125 slot_printf(slot, "Blk size: 0x%08x | Blk cnt: 0x%08x\n",
126 RD2(slot, SDHCI_BLOCK_SIZE), RD2(slot, SDHCI_BLOCK_COUNT));
127 slot_printf(slot, "Argument: 0x%08x | Trn mode: 0x%08x\n",
128 RD4(slot, SDHCI_ARGUMENT), RD2(slot, SDHCI_TRANSFER_MODE));
129 slot_printf(slot, "Present: 0x%08x | Host ctl: 0x%08x\n",
130 RD4(slot, SDHCI_PRESENT_STATE), RD1(slot, SDHCI_HOST_CONTROL));
131 slot_printf(slot, "Power: 0x%08x | Blk gap: 0x%08x\n",
132 RD1(slot, SDHCI_POWER_CONTROL), RD1(slot, SDHCI_BLOCK_GAP_CONTROL));
133 slot_printf(slot, "Wake-up: 0x%08x | Clock: 0x%08x\n",
134 RD1(slot, SDHCI_WAKE_UP_CONTROL), RD2(slot, SDHCI_CLOCK_CONTROL));
135 slot_printf(slot, "Timeout: 0x%08x | Int stat: 0x%08x\n",
136 RD1(slot, SDHCI_TIMEOUT_CONTROL), RD4(slot, SDHCI_INT_STATUS));
137 slot_printf(slot, "Int enab: 0x%08x | Sig enab: 0x%08x\n",
138 RD4(slot, SDHCI_INT_ENABLE), RD4(slot, SDHCI_SIGNAL_ENABLE));
139 slot_printf(slot, "AC12 err: 0x%08x | Slot int: 0x%08x\n",
140 RD2(slot, SDHCI_ACMD12_ERR), RD2(slot, SDHCI_SLOT_INT_STATUS));
141 slot_printf(slot, "Caps: 0x%08x | Max curr: 0x%08x\n",
142 RD4(slot, SDHCI_CAPABILITIES), RD4(slot, SDHCI_MAX_CURRENT));
143
144 slot_printf(slot,
145 "===========================================\n");
146 }
147
148 static void
149 sdhci_reset(struct sdhci_slot *slot, uint8_t mask)
150 {
151 int timeout;
152
153 if (slot->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
154 if (!(RD4(slot, SDHCI_PRESENT_STATE) &
155 SDHCI_CARD_PRESENT))
156 return;
157 }
158
159 /* Some controllers need this kick or reset won't work. */
160 if ((mask & SDHCI_RESET_ALL) == 0 &&
161 (slot->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)) {
162 uint32_t clock;
163
164 /* This is to force an update */
165 clock = slot->clock;
166 slot->clock = 0;
167 sdhci_set_clock(slot, clock);
168 }
169
170 if (mask & SDHCI_RESET_ALL) {
171 slot->clock = 0;
172 slot->power = 0;
173 }
174
175 WR1(slot, SDHCI_SOFTWARE_RESET, mask);
176
177 if (slot->quirks & SDHCI_QUIRK_WAITFOR_RESET_ASSERTED) {
178 /*
179 * Resets on TI OMAPs and AM335x are incompatible with SDHCI
180 * specification. The reset bit has internal propagation delay,
181 * so a fast read after write returns 0 even if reset process is
182 * in progress. The workaround is to poll for 1 before polling
183 * for 0. In the worst case, if we miss seeing it asserted the
184 * time we spent waiting is enough to ensure the reset finishes.
185 */
186 timeout = 10000;
187 while ((RD1(slot, SDHCI_SOFTWARE_RESET) & mask) != mask) {
188 if (timeout <= 0)
189 break;
190 timeout--;
191 DELAY(1);
192 }
193 }
194
195 /* Wait max 100 ms */
196 timeout = 10000;
197 /* Controller clears the bits when it's done */
198 while (RD1(slot, SDHCI_SOFTWARE_RESET) & mask) {
199 if (timeout <= 0) {
200 slot_printf(slot, "Reset 0x%x never completed.\n",
201 mask);
202 sdhci_dumpregs(slot);
203 return;
204 }
205 timeout--;
206 DELAY(10);
207 }
208 }
209
210 static void
211 sdhci_init(struct sdhci_slot *slot)
212 {
213
214 sdhci_reset(slot, SDHCI_RESET_ALL);
215
216 /* Enable interrupts. */
217 slot->intmask = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
218 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX |
219 SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT |
220 SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT |
221 SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL |
222 SDHCI_INT_DMA_END | SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE |
223 SDHCI_INT_ACMD12ERR;
224 WR4(slot, SDHCI_INT_ENABLE, slot->intmask);
225 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask);
226 }
227
228 static void
229 sdhci_set_clock(struct sdhci_slot *slot, uint32_t clock)
230 {
231 uint32_t clk_base;
232 uint32_t clk_sel;
233 uint32_t res;
234 uint16_t clk;
235 uint16_t div;
236 int timeout;
237
238 if (clock == slot->clock)
239 return;
240 slot->clock = clock;
241
242 /* Turn off the clock. */
243 clk = RD2(slot, SDHCI_CLOCK_CONTROL);
244 WR2(slot, SDHCI_CLOCK_CONTROL, clk & ~SDHCI_CLOCK_CARD_EN);
245 /* If no clock requested - left it so. */
246 if (clock == 0)
247 return;
248
249 /* Determine the clock base frequency */
250 clk_base = slot->max_clk;
251 if (slot->quirks & SDHCI_QUIRK_BCM577XX_400KHZ_CLKSRC) {
252 clk_sel = RD2(slot, BCM577XX_HOST_CONTROL) & BCM577XX_CTRL_CLKSEL_MASK;
253
254 /* Select clock source appropriate for the requested frequency. */
255 if ((clk_base / BCM577XX_DEFAULT_MAX_DIVIDER) > clock) {
256 clk_base = BCM577XX_ALT_CLOCK_BASE;
257 clk_sel |= (BCM577XX_CTRL_CLKSEL_64MHZ << BCM577XX_CTRL_CLKSEL_SHIFT);
258 } else {
259 clk_sel |= (BCM577XX_CTRL_CLKSEL_DEFAULT << BCM577XX_CTRL_CLKSEL_SHIFT);
260 }
261
262 WR2(slot, BCM577XX_HOST_CONTROL, clk_sel);
263 }
264
265 /* Recalculate timeout clock frequency based on the new sd clock. */
266 if (slot->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)
267 slot->timeout_clk = slot->clock / 1000;
268
269 if (slot->version < SDHCI_SPEC_300) {
270 /* Looking for highest freq <= clock. */
271 res = clk_base;
272 for (div = 1; div < SDHCI_200_MAX_DIVIDER; div <<= 1) {
273 if (res <= clock)
274 break;
275 res >>= 1;
276 }
277 /* Divider 1:1 is 0x00, 2:1 is 0x01, 256:1 is 0x80 ... */
278 div >>= 1;
279 }
280 else {
281 /* Version 3.0 divisors are multiples of two up to 1023*2 */
282 if (clock >= clk_base)
283 div = 0;
284 else {
285 for (div = 2; div < SDHCI_300_MAX_DIVIDER; div += 2) {
286 if ((clk_base / div) <= clock)
287 break;
288 }
289 }
290 div >>= 1;
291 }
292
293 if (bootverbose || sdhci_debug)
294 slot_printf(slot, "Divider %d for freq %d (base %d)\n",
295 div, clock, clk_base);
296
297 /* Now we have got divider, set it. */
298 clk = (div & SDHCI_DIVIDER_MASK) << SDHCI_DIVIDER_SHIFT;
299 clk |= ((div >> SDHCI_DIVIDER_MASK_LEN) & SDHCI_DIVIDER_HI_MASK)
300 << SDHCI_DIVIDER_HI_SHIFT;
301
302 WR2(slot, SDHCI_CLOCK_CONTROL, clk);
303 /* Enable clock. */
304 clk |= SDHCI_CLOCK_INT_EN;
305 WR2(slot, SDHCI_CLOCK_CONTROL, clk);
306 /* Wait up to 10 ms until it stabilize. */
307 timeout = 10;
308 while (!((clk = RD2(slot, SDHCI_CLOCK_CONTROL))
309 & SDHCI_CLOCK_INT_STABLE)) {
310 if (timeout == 0) {
311 slot_printf(slot,
312 "Internal clock never stabilised.\n");
313 sdhci_dumpregs(slot);
314 return;
315 }
316 timeout--;
317 DELAY(1000);
318 }
319 /* Pass clock signal to the bus. */
320 clk |= SDHCI_CLOCK_CARD_EN;
321 WR2(slot, SDHCI_CLOCK_CONTROL, clk);
322 }
323
324 static void
325 sdhci_set_power(struct sdhci_slot *slot, u_char power)
326 {
327 uint8_t pwr;
328
329 if (slot->power == power)
330 return;
331
332 slot->power = power;
333
334 /* Turn off the power. */
335 pwr = 0;
336 WR1(slot, SDHCI_POWER_CONTROL, pwr);
337 /* If power down requested - left it so. */
338 if (power == 0)
339 return;
340 /* Set voltage. */
341 switch (1 << power) {
342 case MMC_OCR_LOW_VOLTAGE:
343 pwr |= SDHCI_POWER_180;
344 break;
345 case MMC_OCR_290_300:
346 case MMC_OCR_300_310:
347 pwr |= SDHCI_POWER_300;
348 break;
349 case MMC_OCR_320_330:
350 case MMC_OCR_330_340:
351 pwr |= SDHCI_POWER_330;
352 break;
353 }
354 WR1(slot, SDHCI_POWER_CONTROL, pwr);
355 /* Turn on the power. */
356 pwr |= SDHCI_POWER_ON;
357 WR1(slot, SDHCI_POWER_CONTROL, pwr);
358 }
359
360 static void
361 sdhci_read_block_pio(struct sdhci_slot *slot)
362 {
363 uint32_t data;
364 char *buffer;
365 size_t left;
366
367 buffer = slot->curcmd->data->data;
368 buffer += slot->offset;
369 /* Transfer one block at a time. */
370 left = min(512, slot->curcmd->data->len - slot->offset);
371 slot->offset += left;
372
373 /* If we are too fast, broken controllers return zeroes. */
374 if (slot->quirks & SDHCI_QUIRK_BROKEN_TIMINGS)
375 DELAY(10);
376 /* Handle unaligned and aligned buffer cases. */
377 if ((intptr_t)buffer & 3) {
378 while (left > 3) {
379 data = RD4(slot, SDHCI_BUFFER);
380 buffer[0] = data;
381 buffer[1] = (data >> 8);
382 buffer[2] = (data >> 16);
383 buffer[3] = (data >> 24);
384 buffer += 4;
385 left -= 4;
386 }
387 } else {
388 RD_MULTI_4(slot, SDHCI_BUFFER,
389 (uint32_t *)buffer, left >> 2);
390 left &= 3;
391 }
392 /* Handle uneven size case. */
393 if (left > 0) {
394 data = RD4(slot, SDHCI_BUFFER);
395 while (left > 0) {
396 *(buffer++) = data;
397 data >>= 8;
398 left--;
399 }
400 }
401 }
402
403 static void
404 sdhci_write_block_pio(struct sdhci_slot *slot)
405 {
406 uint32_t data = 0;
407 char *buffer;
408 size_t left;
409
410 buffer = slot->curcmd->data->data;
411 buffer += slot->offset;
412 /* Transfer one block at a time. */
413 left = min(512, slot->curcmd->data->len - slot->offset);
414 slot->offset += left;
415
416 /* Handle unaligned and aligned buffer cases. */
417 if ((intptr_t)buffer & 3) {
418 while (left > 3) {
419 data = buffer[0] +
420 (buffer[1] << 8) +
421 (buffer[2] << 16) +
422 (buffer[3] << 24);
423 left -= 4;
424 buffer += 4;
425 WR4(slot, SDHCI_BUFFER, data);
426 }
427 } else {
428 WR_MULTI_4(slot, SDHCI_BUFFER,
429 (uint32_t *)buffer, left >> 2);
430 left &= 3;
431 }
432 /* Handle uneven size case. */
433 if (left > 0) {
434 while (left > 0) {
435 data <<= 8;
436 data += *(buffer++);
437 left--;
438 }
439 WR4(slot, SDHCI_BUFFER, data);
440 }
441 }
442
443 static void
444 sdhci_transfer_pio(struct sdhci_slot *slot)
445 {
446
447 /* Read as many blocks as possible. */
448 if (slot->curcmd->data->flags & MMC_DATA_READ) {
449 while (RD4(slot, SDHCI_PRESENT_STATE) &
450 SDHCI_DATA_AVAILABLE) {
451 sdhci_read_block_pio(slot);
452 if (slot->offset >= slot->curcmd->data->len)
453 break;
454 }
455 } else {
456 while (RD4(slot, SDHCI_PRESENT_STATE) &
457 SDHCI_SPACE_AVAILABLE) {
458 sdhci_write_block_pio(slot);
459 if (slot->offset >= slot->curcmd->data->len)
460 break;
461 }
462 }
463 }
464
465 static void
466 sdhci_card_delay(void *arg)
467 {
468 struct sdhci_slot *slot = arg;
469
470 taskqueue_enqueue(taskqueue_swi, &slot->card_task);
471 }
472
473 static void
474 sdhci_card_task(void *arg, int pending)
475 {
476 struct sdhci_slot *slot = arg;
477
478 SDHCI_LOCK(slot);
479 if (RD4(slot, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT) {
480 if (slot->dev == NULL) {
481 /* If card is present - attach mmc bus. */
482 slot->dev = device_add_child(slot->bus, "mmc", -1);
483 device_set_ivars(slot->dev, slot);
484 SDHCI_UNLOCK(slot);
485 device_probe_and_attach(slot->dev);
486 } else
487 SDHCI_UNLOCK(slot);
488 } else {
489 if (slot->dev != NULL) {
490 /* If no card present - detach mmc bus. */
491 device_t d = slot->dev;
492 slot->dev = NULL;
493 SDHCI_UNLOCK(slot);
494 device_delete_child(slot->bus, d);
495 } else
496 SDHCI_UNLOCK(slot);
497 }
498 }
499
500 int
501 sdhci_init_slot(device_t dev, struct sdhci_slot *slot, int num)
502 {
503 uint32_t caps, freq;
504 int err;
505
506 SDHCI_LOCK_INIT(slot);
507 slot->num = num;
508 slot->bus = dev;
509
510 /* Allocate DMA memory for SDMA. */
511 err = bus_dmamem_coherent(bus_get_dma_tag(dev),
512 DMA_BLOCK_SIZE, 0, BUS_SPACE_MAXADDR_32BIT,
513 BUS_SPACE_MAXADDR, DMA_BLOCK_SIZE, BUS_DMA_NOWAIT,
514 &slot->sdma_mem);
515 if (err != 0) {
516 device_printf(dev, "Can't alloc DMA memory for SDMA\n");
517 SDHCI_LOCK_DESTROY(slot);
518 return (err);
519 }
520
521 /* Initialize slot. */
522 sdhci_init(slot);
523 slot->version = (RD2(slot, SDHCI_HOST_VERSION)
524 >> SDHCI_SPEC_VER_SHIFT) & SDHCI_SPEC_VER_MASK;
525 if (slot->quirks & SDHCI_QUIRK_MISSING_CAPS)
526 caps = slot->caps;
527 else
528 caps = RD4(slot, SDHCI_CAPABILITIES);
529 /* Calculate base clock frequency. */
530 if (slot->version >= SDHCI_SPEC_300)
531 freq = (caps & SDHCI_CLOCK_V3_BASE_MASK) >>
532 SDHCI_CLOCK_BASE_SHIFT;
533 else
534 freq = (caps & SDHCI_CLOCK_BASE_MASK) >>
535 SDHCI_CLOCK_BASE_SHIFT;
536 if (freq != 0)
537 slot->max_clk = freq * 1000000;
538 /*
539 * If the frequency wasn't in the capabilities and the hardware driver
540 * hasn't already set max_clk we're probably not going to work right
541 * with an assumption, so complain about it.
542 */
543 if (slot->max_clk == 0) {
544 slot->max_clk = SDHCI_DEFAULT_MAX_FREQ * 1000000;
545 device_printf(dev, "Hardware doesn't specify base clock "
546 "frequency, using %dMHz as default.\n", SDHCI_DEFAULT_MAX_FREQ);
547 }
548 /* Calculate timeout clock frequency. */
549 if (slot->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK) {
550 slot->timeout_clk = slot->max_clk / 1000;
551 } else {
552 slot->timeout_clk =
553 (caps & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT;
554 if (caps & SDHCI_TIMEOUT_CLK_UNIT)
555 slot->timeout_clk *= 1000;
556 }
557 /*
558 * If the frequency wasn't in the capabilities and the hardware driver
559 * hasn't already set timeout_clk we'll probably work okay using the
560 * max timeout, but still mention it.
561 */
562 if (slot->timeout_clk == 0) {
563 device_printf(dev, "Hardware doesn't specify timeout clock "
564 "frequency, setting BROKEN_TIMEOUT quirk.\n");
565 slot->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL;
566 }
567
568 slot->host.f_min = SDHCI_MIN_FREQ(slot->bus, slot);
569 slot->host.f_max = slot->max_clk;
570 slot->host.host_ocr = 0;
571 if (caps & SDHCI_CAN_VDD_330)
572 slot->host.host_ocr |= MMC_OCR_320_330 | MMC_OCR_330_340;
573 if (caps & SDHCI_CAN_VDD_300)
574 slot->host.host_ocr |= MMC_OCR_290_300 | MMC_OCR_300_310;
575 if (caps & SDHCI_CAN_VDD_180)
576 slot->host.host_ocr |= MMC_OCR_LOW_VOLTAGE;
577 if (slot->host.host_ocr == 0) {
578 device_printf(dev, "Hardware doesn't report any "
579 "support voltages.\n");
580 }
581 slot->host.caps = MMC_CAP_4_BIT_DATA;
582 if (caps & SDHCI_CAN_DO_8BITBUS)
583 slot->host.caps |= MMC_CAP_8_BIT_DATA;
584 if (caps & SDHCI_CAN_DO_HISPD)
585 slot->host.caps |= MMC_CAP_HSPEED;
586 /* Decide if we have usable DMA. */
587 if (caps & SDHCI_CAN_DO_DMA)
588 slot->opt |= SDHCI_HAVE_SDMA;
589
590 if (slot->quirks & SDHCI_QUIRK_BROKEN_DMA)
591 slot->opt &= ~SDHCI_HAVE_SDMA;
592 if (slot->quirks & SDHCI_QUIRK_FORCE_SDMA)
593 slot->opt |= SDHCI_HAVE_SDMA;
594
595 /*
596 * Use platform-provided transfer backend
597 * with PIO as a fallback mechanism
598 */
599 if (slot->opt & SDHCI_PLATFORM_TRANSFER)
600 slot->opt &= ~SDHCI_HAVE_SDMA;
601
602 if (bootverbose || sdhci_debug) {
603 slot_printf(slot, "%uMHz%s %s%s%s%s %s\n",
604 slot->max_clk / 1000000,
605 (caps & SDHCI_CAN_DO_HISPD) ? " HS" : "",
606 (caps & MMC_CAP_8_BIT_DATA) ? "8bits" :
607 ((caps & MMC_CAP_4_BIT_DATA) ? "4bits" : "1bit"),
608 (caps & SDHCI_CAN_VDD_330) ? " 3.3V" : "",
609 (caps & SDHCI_CAN_VDD_300) ? " 3.0V" : "",
610 (caps & SDHCI_CAN_VDD_180) ? " 1.8V" : "",
611 (slot->opt & SDHCI_HAVE_SDMA) ? "SDMA" : "PIO");
612 sdhci_dumpregs(slot);
613 }
614
615 slot->timeout = 10;
616 slot->failures = 0;
617 SYSCTL_ADD_INT(device_get_sysctl_ctx(slot->bus),
618 SYSCTL_CHILDREN(device_get_sysctl_tree(slot->bus)), OID_AUTO,
619 "timeout", CTLFLAG_RW, &slot->timeout, 0,
620 "Maximum timeout for SDHCI transfers (in secs)");
621 TASK_INIT(&slot->card_task, 0, sdhci_card_task, slot);
622 callout_init(&slot->card_callout);
623 callout_init_lk(&slot->timeout_callout, &slot->lock);
624 return (0);
625 }
626
627 void
628 sdhci_start_slot(struct sdhci_slot *slot)
629 {
630 sdhci_card_task(slot, 0);
631 }
632
633 int
634 sdhci_cleanup_slot(struct sdhci_slot *slot)
635 {
636 device_t d;
637 bus_dmamem_t *sdma;
638
639 callout_drain(&slot->timeout_callout);
640 callout_drain(&slot->card_callout);
641 taskqueue_drain(taskqueue_swi, &slot->card_task);
642
643 SDHCI_LOCK(slot);
644 d = slot->dev;
645 slot->dev = NULL;
646 SDHCI_UNLOCK(slot);
647 if (d != NULL)
648 device_delete_child(slot->bus, d);
649
650 SDHCI_LOCK(slot);
651 sdhci_reset(slot, SDHCI_RESET_ALL);
652 SDHCI_UNLOCK(slot);
653
654 sdma = &slot->sdma_mem;
655 bus_dmamap_unload(sdma->dmem_tag, sdma->dmem_map);
656 bus_dmamem_free(sdma->dmem_tag, sdma->dmem_addr, sdma->dmem_map);
657 bus_dma_tag_destroy(sdma->dmem_tag);
658
659 SDHCI_LOCK_DESTROY(slot);
660
661 return (0);
662 }
663
664 int
665 sdhci_generic_suspend(struct sdhci_slot *slot)
666 {
667 sdhci_reset(slot, SDHCI_RESET_ALL);
668
669 return (0);
670 }
671
672 int
673 sdhci_generic_resume(struct sdhci_slot *slot)
674 {
675 sdhci_init(slot);
676
677 return (0);
678 }
679
680 uint32_t
681 sdhci_generic_min_freq(device_t brdev, struct sdhci_slot *slot)
682 {
683 if (slot->version >= SDHCI_SPEC_300)
684 return (slot->max_clk / SDHCI_300_MAX_DIVIDER);
685 else
686 return (slot->max_clk / SDHCI_200_MAX_DIVIDER);
687 }
688
689 int
690 sdhci_generic_update_ios(device_t brdev, device_t reqdev)
691 {
692 struct sdhci_slot *slot = device_get_ivars(reqdev);
693 struct mmc_ios *ios = &slot->host.ios;
694
695 SDHCI_LOCK(slot);
696 /* Do full reset on bus power down to clear from any state. */
697 if (ios->power_mode == power_off) {
698 WR4(slot, SDHCI_SIGNAL_ENABLE, 0);
699 sdhci_init(slot);
700 }
701 /* Configure the bus. */
702 sdhci_set_clock(slot, ios->clock);
703 sdhci_set_power(slot, (ios->power_mode == power_off) ? 0 : ios->vdd);
704 if (ios->bus_width == bus_width_8) {
705 slot->hostctrl |= SDHCI_CTRL_8BITBUS;
706 slot->hostctrl &= ~SDHCI_CTRL_4BITBUS;
707 } else if (ios->bus_width == bus_width_4) {
708 slot->hostctrl &= ~SDHCI_CTRL_8BITBUS;
709 slot->hostctrl |= SDHCI_CTRL_4BITBUS;
710 } else if (ios->bus_width == bus_width_1) {
711 slot->hostctrl &= ~SDHCI_CTRL_8BITBUS;
712 slot->hostctrl &= ~SDHCI_CTRL_4BITBUS;
713 } else {
714 panic("Invalid bus width: %d", ios->bus_width);
715 }
716 if (ios->timing == bus_timing_hs &&
717 !(slot->quirks & SDHCI_QUIRK_DONT_SET_HISPD_BIT))
718 slot->hostctrl |= SDHCI_CTRL_HISPD;
719 else
720 slot->hostctrl &= ~SDHCI_CTRL_HISPD;
721 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl);
722 /* Some controllers like reset after bus changes. */
723 if(slot->quirks & SDHCI_QUIRK_RESET_ON_IOS)
724 sdhci_reset(slot, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
725
726 SDHCI_UNLOCK(slot);
727 return (0);
728 }
729
730 static void
731 sdhci_req_done(struct sdhci_slot *slot)
732 {
733 struct mmc_request *req;
734
735 if (slot->req != NULL && slot->curcmd != NULL) {
736 callout_stop(&slot->timeout_callout);
737 if (slot->curcmd->error != MMC_ERR_TIMEOUT)
738 slot->failures = 0;
739 req = slot->req;
740 slot->req = NULL;
741 slot->curcmd = NULL;
742 req->done(req);
743 }
744 }
745
746 static void
747 sdhci_timeout(void *arg)
748 {
749 struct sdhci_slot *slot = arg;
750
751 if (slot->curcmd != NULL) {
752 slot_printf(slot, " Controller timeout\n");
753 sdhci_dumpregs(slot);
754 sdhci_reset(slot, SDHCI_RESET_CMD|SDHCI_RESET_DATA);
755 slot->curcmd->error = MMC_ERR_TIMEOUT;
756 sdhci_req_done(slot);
757 } else {
758 slot_printf(slot, " Spurious timeout - no active command\n");
759 }
760 }
761
762 static void
763 sdhci_set_transfer_mode(struct sdhci_slot *slot,
764 struct mmc_data *data)
765 {
766 uint16_t mode;
767
768 if (data == NULL)
769 return;
770
771 mode = SDHCI_TRNS_BLK_CNT_EN;
772 if (data->len > 512)
773 mode |= SDHCI_TRNS_MULTI;
774 if (data->flags & MMC_DATA_READ)
775 mode |= SDHCI_TRNS_READ;
776 if (slot->req->stop)
777 mode |= SDHCI_TRNS_ACMD12;
778 if (slot->flags & SDHCI_USE_SDMA)
779 mode |= SDHCI_TRNS_DMA;
780
781 WR2(slot, SDHCI_TRANSFER_MODE, mode);
782 }
783
784 static void
785 sdhci_start_command(struct sdhci_slot *slot, struct mmc_command *cmd)
786 {
787 int flags, timeout;
788 uint32_t mask, state;
789
790 slot->curcmd = cmd;
791 slot->cmd_done = 0;
792
793 cmd->error = MMC_ERR_NONE;
794
795 /* This flags combination is not supported by controller. */
796 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
797 slot_printf(slot, "Unsupported response type!\n");
798 cmd->error = MMC_ERR_FAILED;
799 sdhci_req_done(slot);
800 return;
801 }
802
803 /* Read controller present state. */
804 state = RD4(slot, SDHCI_PRESENT_STATE);
805 /* Do not issue command if there is no card, clock or power.
806 * Controller will not detect timeout without clock active. */
807 if ((state & SDHCI_CARD_PRESENT) == 0 ||
808 slot->power == 0 ||
809 slot->clock == 0) {
810 cmd->error = MMC_ERR_FAILED;
811 sdhci_req_done(slot);
812 return;
813 }
814 /* Always wait for free CMD bus. */
815 mask = SDHCI_CMD_INHIBIT;
816 /* Wait for free DAT if we have data or busy signal. */
817 if (cmd->data || (cmd->flags & MMC_RSP_BUSY))
818 mask |= SDHCI_DAT_INHIBIT;
819 /* We shouldn't wait for DAT for stop commands. */
820 if (cmd == slot->req->stop)
821 mask &= ~SDHCI_DAT_INHIBIT;
822 /*
823 * Wait for bus no more then 250 ms. Typically there will be no wait
824 * here at all, but when writing a crash dump we may be bypassing the
825 * host platform's interrupt handler, and in some cases that handler
826 * may be working around hardware quirks such as not respecting r1b
827 * busy indications. In those cases, this wait-loop serves the purpose
828 * of waiting for the prior command and data transfers to be done, and
829 * SD cards are allowed to take up to 250ms for write and erase ops.
830 * (It's usually more like 20-30ms in the real world.)
831 */
832 timeout = 250;
833 while (state & mask) {
834 if (timeout == 0) {
835 slot_printf(slot, "Controller never released "
836 "inhibit bit(s).\n");
837 sdhci_dumpregs(slot);
838 cmd->error = MMC_ERR_FAILED;
839 sdhci_req_done(slot);
840 return;
841 }
842 timeout--;
843 DELAY(1000);
844 state = RD4(slot, SDHCI_PRESENT_STATE);
845 }
846
847 /* Prepare command flags. */
848 if (!(cmd->flags & MMC_RSP_PRESENT))
849 flags = SDHCI_CMD_RESP_NONE;
850 else if (cmd->flags & MMC_RSP_136)
851 flags = SDHCI_CMD_RESP_LONG;
852 else if (cmd->flags & MMC_RSP_BUSY)
853 flags = SDHCI_CMD_RESP_SHORT_BUSY;
854 else
855 flags = SDHCI_CMD_RESP_SHORT;
856 if (cmd->flags & MMC_RSP_CRC)
857 flags |= SDHCI_CMD_CRC;
858 if (cmd->flags & MMC_RSP_OPCODE)
859 flags |= SDHCI_CMD_INDEX;
860 if (cmd->data)
861 flags |= SDHCI_CMD_DATA;
862 if (cmd->opcode == MMC_STOP_TRANSMISSION)
863 flags |= SDHCI_CMD_TYPE_ABORT;
864 /* Prepare data. */
865 sdhci_start_data(slot, cmd->data);
866 /*
867 * Interrupt aggregation: To reduce total number of interrupts
868 * group response interrupt with data interrupt when possible.
869 * If there going to be data interrupt, mask response one.
870 */
871 if (slot->data_done == 0) {
872 WR4(slot, SDHCI_SIGNAL_ENABLE,
873 slot->intmask &= ~SDHCI_INT_RESPONSE);
874 }
875 /* Set command argument. */
876 WR4(slot, SDHCI_ARGUMENT, cmd->arg);
877 /* Set data transfer mode. */
878 sdhci_set_transfer_mode(slot, cmd->data);
879 /* Start command. */
880 WR2(slot, SDHCI_COMMAND_FLAGS, (cmd->opcode << 8) | (flags & 0xff));
881
882 /*
883 * Start timeout callout. Timeout is dropped to 2 seconds with
884 * repeated controller timeouts.
885 */
886 if (slot->failures)
887 timeout = slot->timeout / 5;
888 else
889 timeout = slot->timeout;
890 if (timeout < 2)
891 timeout = 2;
892 callout_reset(&slot->timeout_callout, timeout * hz,
893 sdhci_timeout, slot);
894 }
895
896 static void
897 sdhci_finish_command(struct sdhci_slot *slot)
898 {
899 int i;
900
901 slot->cmd_done = 1;
902 /* Interrupt aggregation: Restore command interrupt.
903 * Main restore point for the case when command interrupt
904 * happened first. */
905 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask |= SDHCI_INT_RESPONSE);
906 /* In case of error - reset host and return. */
907 if (slot->curcmd->error) {
908 sdhci_reset(slot, SDHCI_RESET_CMD);
909 sdhci_reset(slot, SDHCI_RESET_DATA);
910 sdhci_start(slot);
911 return;
912 }
913 /* If command has response - fetch it. */
914 if (slot->curcmd->flags & MMC_RSP_PRESENT) {
915 if (slot->curcmd->flags & MMC_RSP_136) {
916 /* CRC is stripped so we need one byte shift. */
917 uint8_t extra = 0;
918 for (i = 0; i < 4; i++) {
919 uint32_t val = RD4(slot, SDHCI_RESPONSE + i * 4);
920 if (slot->quirks & SDHCI_QUIRK_DONT_SHIFT_RESPONSE) {
921 slot->curcmd->resp[3 - i] = val;
922 } else {
923 slot->curcmd->resp[3 - i] =
924 (val << 8) | extra;
925 extra = val >> 24;
926 }
927 }
928 } else {
929 slot->curcmd->resp[0] = RD4(slot, SDHCI_RESPONSE);
930 }
931 }
932 /* If data ready - finish. */
933 if (slot->data_done)
934 sdhci_start(slot);
935 }
936
937 static void
938 sdhci_start_data(struct sdhci_slot *slot, struct mmc_data *data)
939 {
940 uint32_t target_timeout, current_timeout;
941 uint8_t div;
942
943 if (data == NULL && (slot->curcmd->flags & MMC_RSP_BUSY) == 0) {
944 slot->data_done = 1;
945 return;
946 }
947
948 slot->data_done = 0;
949
950 /* Calculate and set data timeout.*/
951 /* XXX: We should have this from mmc layer, now assume 1 sec. */
952 if (slot->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL) {
953 div = 0xe;
954 } else {
955 target_timeout = 1000000;
956 div = 0;
957 current_timeout = (1 << 13) * 1000 / slot->timeout_clk;
958 while (current_timeout < target_timeout && div < 0xE) {
959 ++div;
960 current_timeout <<= 1;
961 }
962 /* Compensate for an off-by-one error in the CaFe chip.*/
963 if (div < 0xE &&
964 (slot->quirks & SDHCI_QUIRK_INCR_TIMEOUT_CONTROL)) {
965 ++div;
966 }
967 }
968 WR1(slot, SDHCI_TIMEOUT_CONTROL, div);
969
970 if (data == NULL)
971 return;
972
973 /* Use DMA if possible. */
974 if ((slot->opt & SDHCI_HAVE_SDMA))
975 slot->flags |= SDHCI_USE_SDMA;
976 /* If data is small, broken DMA may return zeroes instead of data. */
977 if ((slot->quirks & SDHCI_QUIRK_BROKEN_TIMINGS) &&
978 (data->len <= 512))
979 slot->flags &= ~SDHCI_USE_SDMA;
980 /* Some controllers require even block sizes. */
981 if ((slot->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE) &&
982 ((data->len) & 0x3))
983 slot->flags &= ~SDHCI_USE_SDMA;
984 /* Load DMA buffer. */
985 if (slot->flags & SDHCI_USE_SDMA) {
986 bus_dmamem_t *sdma = &slot->sdma_mem;
987
988 if (data->flags & MMC_DATA_READ) {
989 bus_dmamap_sync(sdma->dmem_tag, sdma->dmem_map,
990 BUS_DMASYNC_PREREAD);
991 } else {
992 memcpy(sdma->dmem_addr, data->data,
993 (data->len < DMA_BLOCK_SIZE) ?
994 data->len : DMA_BLOCK_SIZE);
995 bus_dmamap_sync(sdma->dmem_tag, sdma->dmem_map,
996 BUS_DMASYNC_PREWRITE);
997 }
998 WR4(slot, SDHCI_SDMA_ADDRESS, sdma->dmem_busaddr);
999 /* Interrupt aggregation: Mask border interrupt
1000 * for the last page and unmask else. */
1001 if (data->len == DMA_BLOCK_SIZE)
1002 slot->intmask &= ~SDHCI_INT_DMA_END;
1003 else
1004 slot->intmask |= SDHCI_INT_DMA_END;
1005 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask);
1006 }
1007 /* Current data offset for both PIO and DMA. */
1008 slot->offset = 0;
1009 /* Set block size and request IRQ on 4K border. */
1010 WR2(slot, SDHCI_BLOCK_SIZE,
1011 SDHCI_MAKE_BLKSZ(DMA_BOUNDARY, (data->len < 512)?data->len:512));
1012 /* Set block count. */
1013 WR2(slot, SDHCI_BLOCK_COUNT, (data->len + 511) / 512);
1014 }
1015
1016 void
1017 sdhci_finish_data(struct sdhci_slot *slot)
1018 {
1019 struct mmc_data *data = slot->curcmd->data;
1020
1021 /* Interrupt aggregation: Restore command interrupt.
1022 * Auxiliary restore point for the case when data interrupt
1023 * happened first. */
1024 if (!slot->cmd_done) {
1025 WR4(slot, SDHCI_SIGNAL_ENABLE,
1026 slot->intmask |= SDHCI_INT_RESPONSE);
1027 }
1028 /* Unload rest of data from DMA buffer. */
1029 if (!slot->data_done && (slot->flags & SDHCI_USE_SDMA)) {
1030 bus_dmamem_t *sdma = &slot->sdma_mem;
1031
1032 if (data->flags & MMC_DATA_READ) {
1033 size_t left = data->len - slot->offset;
1034 bus_dmamap_sync(sdma->dmem_tag, sdma->dmem_map,
1035 BUS_DMASYNC_POSTREAD);
1036 memcpy((u_char*)data->data + slot->offset,
1037 sdma->dmem_addr,
1038 (left < DMA_BLOCK_SIZE)?left:DMA_BLOCK_SIZE);
1039 } else
1040 bus_dmamap_sync(sdma->dmem_tag, sdma->dmem_map,
1041 BUS_DMASYNC_POSTWRITE);
1042 }
1043 slot->data_done = 1;
1044 /* If there was error - reset the host. */
1045 if (slot->curcmd->error) {
1046 sdhci_reset(slot, SDHCI_RESET_CMD);
1047 sdhci_reset(slot, SDHCI_RESET_DATA);
1048 sdhci_start(slot);
1049 return;
1050 }
1051 /* If we already have command response - finish. */
1052 if (slot->cmd_done)
1053 sdhci_start(slot);
1054 }
1055
1056 static void
1057 sdhci_start(struct sdhci_slot *slot)
1058 {
1059 struct mmc_request *req;
1060
1061 req = slot->req;
1062 if (req == NULL)
1063 return;
1064
1065 if (!(slot->flags & CMD_STARTED)) {
1066 slot->flags |= CMD_STARTED;
1067 sdhci_start_command(slot, req->cmd);
1068 return;
1069 }
1070 /* We don't need this until using Auto-CMD12 feature
1071 if (!(slot->flags & STOP_STARTED) && req->stop) {
1072 slot->flags |= STOP_STARTED;
1073 sdhci_start_command(slot, req->stop);
1074 return;
1075 }
1076 */
1077 if (sdhci_debug > 1)
1078 slot_printf(slot, "result: %d\n", req->cmd->error);
1079 if (!req->cmd->error &&
1080 (slot->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST)) {
1081 sdhci_reset(slot, SDHCI_RESET_CMD);
1082 sdhci_reset(slot, SDHCI_RESET_DATA);
1083 }
1084
1085 sdhci_req_done(slot);
1086 }
1087
1088 int
1089 sdhci_generic_request(device_t brdev, device_t reqdev, struct mmc_request *req)
1090 {
1091 struct sdhci_slot *slot = device_get_ivars(reqdev);
1092
1093 SDHCI_LOCK(slot);
1094 if (slot->req != NULL) {
1095 SDHCI_UNLOCK(slot);
1096 return (EBUSY);
1097 }
1098 if (sdhci_debug > 1) {
1099 slot_printf(slot, "CMD%u arg %#x flags %#x dlen %u dflags %#x\n",
1100 req->cmd->opcode, req->cmd->arg, req->cmd->flags,
1101 (req->cmd->data)?(u_int)req->cmd->data->len:0,
1102 (req->cmd->data)?req->cmd->data->flags:0);
1103 }
1104 slot->req = req;
1105 slot->flags = 0;
1106 sdhci_start(slot);
1107 SDHCI_UNLOCK(slot);
1108 if (dumping) {
1109 while (slot->req != NULL) {
1110 sdhci_generic_intr(slot);
1111 DELAY(10);
1112 }
1113 }
1114 return (0);
1115 }
1116
1117 int
1118 sdhci_generic_get_ro(device_t brdev, device_t reqdev)
1119 {
1120 struct sdhci_slot *slot = device_get_ivars(reqdev);
1121 uint32_t val;
1122
1123 SDHCI_LOCK(slot);
1124 val = RD4(slot, SDHCI_PRESENT_STATE);
1125 SDHCI_UNLOCK(slot);
1126 return (!(val & SDHCI_WRITE_PROTECT));
1127 }
1128
1129 int
1130 sdhci_generic_acquire_host(device_t brdev, device_t reqdev)
1131 {
1132 struct sdhci_slot *slot = device_get_ivars(reqdev);
1133 int err = 0;
1134
1135 SDHCI_LOCK(slot);
1136 while (slot->bus_busy)
1137 lksleep(slot, &slot->lock, 0, "sdhciah", 0);
1138 slot->bus_busy++;
1139 /* Activate led. */
1140 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl |= SDHCI_CTRL_LED);
1141 SDHCI_UNLOCK(slot);
1142 return (err);
1143 }
1144
1145 int
1146 sdhci_generic_release_host(device_t brdev, device_t reqdev)
1147 {
1148 struct sdhci_slot *slot = device_get_ivars(reqdev);
1149
1150 SDHCI_LOCK(slot);
1151 /* Deactivate led. */
1152 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl &= ~SDHCI_CTRL_LED);
1153 slot->bus_busy--;
1154 SDHCI_UNLOCK(slot);
1155 wakeup(slot);
1156 return (0);
1157 }
1158
1159 static void
1160 sdhci_cmd_irq(struct sdhci_slot *slot, uint32_t intmask)
1161 {
1162
1163 if (!slot->curcmd) {
1164 slot_printf(slot, "Got command interrupt 0x%08x, but "
1165 "there is no active command.\n", intmask);
1166 sdhci_dumpregs(slot);
1167 return;
1168 }
1169 if (intmask & SDHCI_INT_TIMEOUT)
1170 slot->curcmd->error = MMC_ERR_TIMEOUT;
1171 else if (intmask & SDHCI_INT_CRC)
1172 slot->curcmd->error = MMC_ERR_BADCRC;
1173 else if (intmask & (SDHCI_INT_END_BIT | SDHCI_INT_INDEX))
1174 slot->curcmd->error = MMC_ERR_FIFO;
1175
1176 sdhci_finish_command(slot);
1177 }
1178
1179 static void
1180 sdhci_data_irq(struct sdhci_slot *slot, uint32_t intmask)
1181 {
1182
1183 if (!slot->curcmd) {
1184 slot_printf(slot, "Got data interrupt 0x%08x, but "
1185 "there is no active command.\n", intmask);
1186 sdhci_dumpregs(slot);
1187 return;
1188 }
1189 if (slot->curcmd->data == NULL &&
1190 (slot->curcmd->flags & MMC_RSP_BUSY) == 0) {
1191 slot_printf(slot, "Got data interrupt 0x%08x, but "
1192 "there is no active data operation.\n",
1193 intmask);
1194 sdhci_dumpregs(slot);
1195 return;
1196 }
1197 if (intmask & SDHCI_INT_DATA_TIMEOUT)
1198 slot->curcmd->error = MMC_ERR_TIMEOUT;
1199 else if (intmask & (SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_END_BIT))
1200 slot->curcmd->error = MMC_ERR_BADCRC;
1201 if (slot->curcmd->data == NULL &&
1202 (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL |
1203 SDHCI_INT_DMA_END))) {
1204 slot_printf(slot, "Got data interrupt 0x%08x, but "
1205 "there is busy-only command.\n", intmask);
1206 sdhci_dumpregs(slot);
1207 slot->curcmd->error = MMC_ERR_INVALID;
1208 }
1209 if (slot->curcmd->error) {
1210 /* No need to continue after any error. */
1211 goto done;
1212 }
1213
1214 /* Handle PIO interrupt. */
1215 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL)) {
1216 if ((slot->opt & SDHCI_PLATFORM_TRANSFER) &&
1217 SDHCI_PLATFORM_WILL_HANDLE(slot->bus, slot)) {
1218 SDHCI_PLATFORM_START_TRANSFER(slot->bus, slot, &intmask);
1219 slot->flags |= PLATFORM_DATA_STARTED;
1220 } else
1221 sdhci_transfer_pio(slot);
1222 }
1223 /* Handle DMA border. */
1224 if (intmask & SDHCI_INT_DMA_END) {
1225 struct mmc_data *data = slot->curcmd->data;
1226 bus_dmamem_t *sdma = &slot->sdma_mem;
1227 size_t left;
1228
1229 /* Unload DMA buffer... */
1230 left = data->len - slot->offset;
1231 if (data->flags & MMC_DATA_READ) {
1232 bus_dmamap_sync(sdma->dmem_tag, sdma->dmem_map,
1233 BUS_DMASYNC_POSTREAD);
1234 memcpy((u_char*)data->data + slot->offset,
1235 sdma->dmem_addr,
1236 (left < DMA_BLOCK_SIZE)?left:DMA_BLOCK_SIZE);
1237 } else {
1238 bus_dmamap_sync(sdma->dmem_tag, sdma->dmem_map,
1239 BUS_DMASYNC_POSTWRITE);
1240 }
1241 /* ... and reload it again. */
1242 slot->offset += DMA_BLOCK_SIZE;
1243 left = data->len - slot->offset;
1244 if (data->flags & MMC_DATA_READ) {
1245 bus_dmamap_sync(sdma->dmem_tag, sdma->dmem_map,
1246 BUS_DMASYNC_PREREAD);
1247 } else {
1248 memcpy(sdma->dmem_addr,
1249 (u_char*)data->data + slot->offset,
1250 (left < DMA_BLOCK_SIZE)?left:DMA_BLOCK_SIZE);
1251 bus_dmamap_sync(sdma->dmem_tag, sdma->dmem_map,
1252 BUS_DMASYNC_PREWRITE);
1253 }
1254 /* Interrupt aggregation: Mask border interrupt
1255 * for the last page. */
1256 if (left == DMA_BLOCK_SIZE) {
1257 slot->intmask &= ~SDHCI_INT_DMA_END;
1258 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask);
1259 }
1260 /* Restart DMA. */
1261 WR4(slot, SDHCI_SDMA_ADDRESS, sdma->dmem_busaddr);
1262 }
1263 /* We have got all data. */
1264 if (intmask & SDHCI_INT_DATA_END) {
1265 if (slot->flags & PLATFORM_DATA_STARTED) {
1266 slot->flags &= ~PLATFORM_DATA_STARTED;
1267 SDHCI_PLATFORM_FINISH_TRANSFER(slot->bus, slot);
1268 } else {
1269 sdhci_finish_data(slot);
1270 }
1271 }
1272 done:
1273 if (slot->curcmd != NULL && slot->curcmd->error != 0) {
1274 if (slot->flags & PLATFORM_DATA_STARTED) {
1275 slot->flags &= ~PLATFORM_DATA_STARTED;
1276 SDHCI_PLATFORM_FINISH_TRANSFER(slot->bus, slot);
1277 } else
1278 sdhci_finish_data(slot);
1279 return;
1280 }
1281 }
1282
1283 static void
1284 sdhci_acmd_irq(struct sdhci_slot *slot)
1285 {
1286 uint16_t err;
1287
1288 err = RD4(slot, SDHCI_ACMD12_ERR);
1289 if (!slot->curcmd) {
1290 slot_printf(slot, "Got AutoCMD12 error 0x%04x, but "
1291 "there is no active command.\n", err);
1292 sdhci_dumpregs(slot);
1293 return;
1294 }
1295 slot_printf(slot, "Got AutoCMD12 error 0x%04x\n", err);
1296 sdhci_reset(slot, SDHCI_RESET_CMD);
1297 }
1298
1299 void
1300 sdhci_generic_intr(struct sdhci_slot *slot)
1301 {
1302 uint32_t intmask;
1303
1304 SDHCI_LOCK(slot);
1305 /* Read slot interrupt status. */
1306 intmask = RD4(slot, SDHCI_INT_STATUS);
1307 if (intmask == 0 || intmask == 0xffffffff) {
1308 SDHCI_UNLOCK(slot);
1309 return;
1310 }
1311 if (sdhci_debug > 2)
1312 slot_printf(slot, "Interrupt %#x\n", intmask);
1313
1314 /* Handle card presence interrupts. */
1315 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
1316 WR4(slot, SDHCI_INT_STATUS, intmask &
1317 (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE));
1318
1319 if (intmask & SDHCI_INT_CARD_REMOVE) {
1320 if (bootverbose || sdhci_debug)
1321 slot_printf(slot, "Card removed\n");
1322 callout_stop(&slot->card_callout);
1323 taskqueue_enqueue(taskqueue_swi,
1324 &slot->card_task);
1325 }
1326 if (intmask & SDHCI_INT_CARD_INSERT) {
1327 if (bootverbose || sdhci_debug)
1328 slot_printf(slot, "Card inserted\n");
1329 callout_reset(&slot->card_callout, hz / 2,
1330 sdhci_card_delay, slot);
1331 }
1332 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE);
1333 }
1334 /* Handle command interrupts. */
1335 if (intmask & SDHCI_INT_CMD_MASK) {
1336 WR4(slot, SDHCI_INT_STATUS, intmask & SDHCI_INT_CMD_MASK);
1337 sdhci_cmd_irq(slot, intmask & SDHCI_INT_CMD_MASK);
1338 }
1339 /* Handle data interrupts. */
1340 if (intmask & SDHCI_INT_DATA_MASK) {
1341 WR4(slot, SDHCI_INT_STATUS, intmask & SDHCI_INT_DATA_MASK);
1342 /* Dont call data_irq in case of errored command */
1343 if ((intmask & SDHCI_INT_CMD_ERROR_MASK) == 0)
1344 sdhci_data_irq(slot, intmask & SDHCI_INT_DATA_MASK);
1345 }
1346 /* Handle AutoCMD12 error interrupt. */
1347 if (intmask & SDHCI_INT_ACMD12ERR) {
1348 WR4(slot, SDHCI_INT_STATUS, SDHCI_INT_ACMD12ERR);
1349 sdhci_acmd_irq(slot);
1350 }
1351 intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK);
1352 intmask &= ~SDHCI_INT_ACMD12ERR;
1353 intmask &= ~SDHCI_INT_ERROR;
1354 /* Handle bus power interrupt. */
1355 if (intmask & SDHCI_INT_BUS_POWER) {
1356 WR4(slot, SDHCI_INT_STATUS, SDHCI_INT_BUS_POWER);
1357 slot_printf(slot,
1358 "Card is consuming too much power!\n");
1359 intmask &= ~SDHCI_INT_BUS_POWER;
1360 }
1361 /* The rest is unknown. */
1362 if (intmask) {
1363 WR4(slot, SDHCI_INT_STATUS, intmask);
1364 slot_printf(slot, "Unexpected interrupt 0x%08x.\n",
1365 intmask);
1366 sdhci_dumpregs(slot);
1367 }
1368
1369 SDHCI_UNLOCK(slot);
1370 }
1371
1372 int
1373 sdhci_generic_read_ivar(device_t bus, device_t child, int which, uintptr_t *result)
1374 {
1375 struct sdhci_slot *slot = device_get_ivars(child);
1376
1377 switch (which) {
1378 default:
1379 return (EINVAL);
1380 case MMCBR_IVAR_BUS_MODE:
1381 *(int *)result = slot->host.ios.bus_mode;
1382 break;
1383 case MMCBR_IVAR_BUS_WIDTH:
1384 *(int *)result = slot->host.ios.bus_width;
1385 break;
1386 case MMCBR_IVAR_CHIP_SELECT:
1387 *(int *)result = slot->host.ios.chip_select;
1388 break;
1389 case MMCBR_IVAR_CLOCK:
1390 *(int *)result = slot->host.ios.clock;
1391 break;
1392 case MMCBR_IVAR_F_MIN:
1393 *(int *)result = slot->host.f_min;
1394 break;
1395 case MMCBR_IVAR_F_MAX:
1396 *(int *)result = slot->host.f_max;
1397 break;
1398 case MMCBR_IVAR_HOST_OCR:
1399 *(int *)result = slot->host.host_ocr;
1400 break;
1401 case MMCBR_IVAR_MODE:
1402 *(int *)result = slot->host.mode;
1403 break;
1404 case MMCBR_IVAR_OCR:
1405 *(int *)result = slot->host.ocr;
1406 break;
1407 case MMCBR_IVAR_POWER_MODE:
1408 *(int *)result = slot->host.ios.power_mode;
1409 break;
1410 case MMCBR_IVAR_VDD:
1411 *(int *)result = slot->host.ios.vdd;
1412 break;
1413 case MMCBR_IVAR_CAPS:
1414 *(int *)result = slot->host.caps;
1415 break;
1416 case MMCBR_IVAR_TIMING:
1417 *(int *)result = slot->host.ios.timing;
1418 break;
1419 case MMCBR_IVAR_MAX_DATA:
1420 *(int *)result = 65535;
1421 break;
1422 }
1423 return (0);
1424 }
1425
1426 int
1427 sdhci_generic_write_ivar(device_t bus, device_t child, int which, uintptr_t value)
1428 {
1429 struct sdhci_slot *slot = device_get_ivars(child);
1430
1431 switch (which) {
1432 default:
1433 return (EINVAL);
1434 case MMCBR_IVAR_BUS_MODE:
1435 slot->host.ios.bus_mode = value;
1436 break;
1437 case MMCBR_IVAR_BUS_WIDTH:
1438 slot->host.ios.bus_width = value;
1439 break;
1440 case MMCBR_IVAR_CHIP_SELECT:
1441 slot->host.ios.chip_select = value;
1442 break;
1443 case MMCBR_IVAR_CLOCK:
1444 if (value > 0) {
1445 uint32_t max_clock;
1446 uint32_t clock;
1447 int i;
1448
1449 max_clock = slot->max_clk;
1450 clock = max_clock;
1451
1452 if (slot->version < SDHCI_SPEC_300) {
1453 for (i = 0; i < SDHCI_200_MAX_DIVIDER;
1454 i <<= 1) {
1455 if (clock <= value)
1456 break;
1457 clock >>= 1;
1458 }
1459 }
1460 else {
1461 for (i = 0; i < SDHCI_300_MAX_DIVIDER;
1462 i += 2) {
1463 if (clock <= value)
1464 break;
1465 clock = max_clock / (i + 2);
1466 }
1467 }
1468
1469 slot->host.ios.clock = clock;
1470 } else
1471 slot->host.ios.clock = 0;
1472 break;
1473 case MMCBR_IVAR_MODE:
1474 slot->host.mode = value;
1475 break;
1476 case MMCBR_IVAR_OCR:
1477 slot->host.ocr = value;
1478 break;
1479 case MMCBR_IVAR_POWER_MODE:
1480 slot->host.ios.power_mode = value;
1481 break;
1482 case MMCBR_IVAR_VDD:
1483 slot->host.ios.vdd = value;
1484 break;
1485 case MMCBR_IVAR_TIMING:
1486 slot->host.ios.timing = value;
1487 break;
1488 case MMCBR_IVAR_CAPS:
1489 case MMCBR_IVAR_HOST_OCR:
1490 case MMCBR_IVAR_F_MIN:
1491 case MMCBR_IVAR_F_MAX:
1492 case MMCBR_IVAR_MAX_DATA:
1493 return (EINVAL);
1494 }
1495 return (0);
1496 }
1497
1498 MODULE_VERSION(sdhci, 1);
DragonFly BSD