1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
33 #include <uapi_drm/i915_drm.h>
34 #include <uapi_drm/drm_fourcc.h>
37 #include "intel_bios.h"
38 #include "intel_ringbuffer.h"
39 #include "intel_lrc.h"
40 #include "i915_gem_gtt.h"
41 #include "i915_gem_render_state.h"
42 #include <linux/io-mapping.h>
43 #include <linux/i2c.h>
44 #include <drm/intel-gtt.h>
45 #include <drm/drm_legacy.h> /* for struct drm_dma_handle */
46 #include <drm/drm_gem.h>
47 #include <linux/backlight.h>
48 #include <linux/hashtable.h>
49 #include <linux/kref.h>
50 #include <linux/kconfig.h>
51 #include <linux/pm_qos.h>
52 #include <linux/delay.h>
54 #define CONFIG_DRM_FBDEV_EMULATION 1
55 #define CONFIG_DRM_I915_KMS 1
56 #define CONFIG_DRM_I915_PRELIMINARY_HW_SUPPORT 1
60 /* General customization:
63 #define DRIVER_NAME "i915"
64 #define DRIVER_DESC "Intel Graphics"
65 #define DRIVER_DATE "20150731"
68 /* Many gcc seem to no see through this and fall over :( */
70 #define WARN_ON(x) ({ \
71 bool __i915_warn_cond = (x); \
72 if (__builtin_constant_p(__i915_warn_cond)) \
73 BUILD_BUG_ON(__i915_warn_cond); \
74 WARN(__i915_warn_cond, "WARN_ON(" #x ")"); })
76 #define WARN_ON(x) WARN((x), "WARN_ON(%s)", #x )
80 #define WARN_ON_ONCE(x) WARN_ONCE((x), "WARN_ON_ONCE(%s)", #x )
82 #define MISSING_CASE(x) WARN(1, "Missing switch case (%lu) in %s\n", \
83 (long) (x), __func__);
85 /* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and
86 * WARN_ON()) for hw state sanity checks to check for unexpected conditions
87 * which may not necessarily be a user visible problem. This will either
88 * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to
89 * enable distros and users to tailor their preferred amount of i915 abrt
92 #define I915_STATE_WARN(condition, format...) ({ \
93 int __ret_warn_on = !!(condition); \
94 if (unlikely(__ret_warn_on)) { \
95 if (i915.verbose_state_checks) \
100 unlikely(__ret_warn_on); \
103 #define I915_STATE_WARN_ON(condition) ({ \
104 int __ret_warn_on = !!(condition); \
105 if (unlikely(__ret_warn_on)) { \
106 if (i915.verbose_state_checks) \
107 WARN(1, "WARN_ON(" #condition ")\n"); \
109 DRM_ERROR("WARN_ON(" #condition ")\n"); \
111 unlikely(__ret_warn_on); \
120 I915_MAX_PIPES
= _PIPE_EDP
122 #define pipe_name(p) ((p) + 'A')
131 #define transcoder_name(t) ((t) + 'A')
134 * This is the maximum (across all platforms) number of planes (primary +
135 * sprites) that can be active at the same time on one pipe.
137 * This value doesn't count the cursor plane.
139 #define I915_MAX_PLANES 4
146 #define plane_name(p) ((p) + 'A')
148 #define sprite_name(p, s) ((p) * INTEL_INFO(dev)->num_sprites[(p)] + (s) + 'A')
158 #define port_name(p) ((p) + 'A')
160 #define I915_NUM_PHYS_VLV 2
172 enum intel_display_power_domain
{
176 POWER_DOMAIN_PIPE_A_PANEL_FITTER
,
177 POWER_DOMAIN_PIPE_B_PANEL_FITTER
,
178 POWER_DOMAIN_PIPE_C_PANEL_FITTER
,
179 POWER_DOMAIN_TRANSCODER_A
,
180 POWER_DOMAIN_TRANSCODER_B
,
181 POWER_DOMAIN_TRANSCODER_C
,
182 POWER_DOMAIN_TRANSCODER_EDP
,
183 POWER_DOMAIN_PORT_DDI_A_2_LANES
,
184 POWER_DOMAIN_PORT_DDI_A_4_LANES
,
185 POWER_DOMAIN_PORT_DDI_B_2_LANES
,
186 POWER_DOMAIN_PORT_DDI_B_4_LANES
,
187 POWER_DOMAIN_PORT_DDI_C_2_LANES
,
188 POWER_DOMAIN_PORT_DDI_C_4_LANES
,
189 POWER_DOMAIN_PORT_DDI_D_2_LANES
,
190 POWER_DOMAIN_PORT_DDI_D_4_LANES
,
191 POWER_DOMAIN_PORT_DDI_E_2_LANES
,
192 POWER_DOMAIN_PORT_DSI
,
193 POWER_DOMAIN_PORT_CRT
,
194 POWER_DOMAIN_PORT_OTHER
,
207 #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
208 #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
209 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
210 #define POWER_DOMAIN_TRANSCODER(tran) \
211 ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
212 (tran) + POWER_DOMAIN_TRANSCODER_A)
216 HPD_TV
= HPD_NONE
, /* TV is known to be unreliable */
228 #define for_each_hpd_pin(__pin) \
229 for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++)
231 struct i915_hotplug
{
232 struct work_struct hotplug_work
;
235 unsigned long last_jiffies
;
240 HPD_MARK_DISABLED
= 2
242 } stats
[HPD_NUM_PINS
];
244 struct delayed_work reenable_work
;
246 struct intel_digital_port
*irq_port
[I915_MAX_PORTS
];
249 struct work_struct dig_port_work
;
252 * if we get a HPD irq from DP and a HPD irq from non-DP
253 * the non-DP HPD could block the workqueue on a mode config
254 * mutex getting, that userspace may have taken. However
255 * userspace is waiting on the DP workqueue to run which is
256 * blocked behind the non-DP one.
258 struct workqueue_struct
*dp_wq
;
261 #define I915_GEM_GPU_DOMAINS \
262 (I915_GEM_DOMAIN_RENDER | \
263 I915_GEM_DOMAIN_SAMPLER | \
264 I915_GEM_DOMAIN_COMMAND | \
265 I915_GEM_DOMAIN_INSTRUCTION | \
266 I915_GEM_DOMAIN_VERTEX)
268 #define for_each_pipe(__dev_priv, __p) \
269 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++)
270 #define for_each_plane(__dev_priv, __pipe, __p) \
272 (__p) < INTEL_INFO(__dev_priv)->num_sprites[(__pipe)] + 1; \
274 #define for_each_sprite(__dev_priv, __p, __s) \
276 (__s) < INTEL_INFO(__dev_priv)->num_sprites[(__p)]; \
279 #define for_each_crtc(dev, crtc) \
280 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
282 #define for_each_intel_plane(dev, intel_plane) \
283 list_for_each_entry(intel_plane, \
284 &dev->mode_config.plane_list, \
287 #define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) \
288 list_for_each_entry(intel_plane, \
289 &(dev)->mode_config.plane_list, \
291 if ((intel_plane)->pipe == (intel_crtc)->pipe)
293 #define for_each_intel_crtc(dev, intel_crtc) \
294 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head)
296 #define for_each_intel_encoder(dev, intel_encoder) \
297 list_for_each_entry(intel_encoder, \
298 &(dev)->mode_config.encoder_list, \
301 #define for_each_intel_connector(dev, intel_connector) \
302 list_for_each_entry(intel_connector, \
303 &dev->mode_config.connector_list, \
306 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
307 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
308 if ((intel_encoder)->base.crtc == (__crtc))
310 #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
311 list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
312 if ((intel_connector)->base.encoder == (__encoder))
314 #define for_each_power_domain(domain, mask) \
315 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
316 if ((1 << (domain)) & (mask))
318 struct drm_i915_private
;
319 struct i915_mm_struct
;
320 struct i915_mmu_object
;
322 struct drm_i915_file_private
{
323 struct drm_i915_private
*dev_priv
;
324 struct drm_file
*file
;
327 struct spinlock lock
;
328 struct list_head request_list
;
329 /* 20ms is a fairly arbitrary limit (greater than the average frame time)
330 * chosen to prevent the CPU getting more than a frame ahead of the GPU
331 * (when using lax throttling for the frontbuffer). We also use it to
332 * offer free GPU waitboosts for severely congested workloads.
334 #define DRM_I915_THROTTLE_JIFFIES msecs_to_jiffies(20)
336 struct idr context_idr
;
338 struct intel_rps_client
{
339 struct list_head link
;
343 struct intel_engine_cs
*bsd_ring
;
347 DPLL_ID_PRIVATE
= -1, /* non-shared dpll in use */
348 /* real shared dpll ids must be >= 0 */
349 DPLL_ID_PCH_PLL_A
= 0,
350 DPLL_ID_PCH_PLL_B
= 1,
355 DPLL_ID_SKL_DPLL1
= 0,
356 DPLL_ID_SKL_DPLL2
= 1,
357 DPLL_ID_SKL_DPLL3
= 2,
359 #define I915_NUM_PLLS 3
361 struct intel_dpll_hw_state
{
373 * DPLL_CTRL1 has 6 bits for each each this DPLL. We store those in
374 * lower part of ctrl1 and they get shifted into position when writing
375 * the register. This allows us to easily compare the state to share
379 /* HDMI only, 0 when used for DP */
380 uint32_t cfgcr1
, cfgcr2
;
383 uint32_t ebb0
, ebb4
, pll0
, pll1
, pll2
, pll3
, pll6
, pll8
, pll9
, pll10
,
387 struct intel_shared_dpll_config
{
388 unsigned crtc_mask
; /* mask of CRTCs sharing this PLL */
389 struct intel_dpll_hw_state hw_state
;
392 struct intel_shared_dpll
{
393 struct intel_shared_dpll_config config
;
395 int active
; /* count of number of active CRTCs (i.e. DPMS on) */
396 bool on
; /* is the PLL actually active? Disabled during modeset */
398 /* should match the index in the dev_priv->shared_dplls array */
399 enum intel_dpll_id id
;
400 /* The mode_set hook is optional and should be used together with the
401 * intel_prepare_shared_dpll function. */
402 void (*mode_set
)(struct drm_i915_private
*dev_priv
,
403 struct intel_shared_dpll
*pll
);
404 void (*enable
)(struct drm_i915_private
*dev_priv
,
405 struct intel_shared_dpll
*pll
);
406 void (*disable
)(struct drm_i915_private
*dev_priv
,
407 struct intel_shared_dpll
*pll
);
408 bool (*get_hw_state
)(struct drm_i915_private
*dev_priv
,
409 struct intel_shared_dpll
*pll
,
410 struct intel_dpll_hw_state
*hw_state
);
418 /* Used by dp and fdi links */
419 struct intel_link_m_n
{
427 void intel_link_compute_m_n(int bpp
, int nlanes
,
428 int pixel_clock
, int link_clock
,
429 struct intel_link_m_n
*m_n
);
431 /* Interface history:
434 * 1.2: Add Power Management
435 * 1.3: Add vblank support
436 * 1.4: Fix cmdbuffer path, add heap destroy
437 * 1.5: Add vblank pipe configuration
438 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
439 * - Support vertical blank on secondary display pipe
441 #define DRIVER_MAJOR 1
442 #define DRIVER_MINOR 6
443 #define DRIVER_PATCHLEVEL 0
445 #define WATCH_LISTS 0
447 struct opregion_header
;
448 struct opregion_acpi
;
449 struct opregion_swsci
;
450 struct opregion_asle
;
452 struct intel_opregion
{
453 struct opregion_header __iomem
*header
;
454 struct opregion_acpi __iomem
*acpi
;
455 struct opregion_swsci __iomem
*swsci
;
456 u32 swsci_gbda_sub_functions
;
457 u32 swsci_sbcb_sub_functions
;
458 struct opregion_asle __iomem
*asle
;
460 u32 __iomem
*lid_state
;
461 struct work_struct asle_work
;
463 #define OPREGION_SIZE (8*1024)
465 struct intel_overlay
;
466 struct intel_overlay_error_state
;
468 #define I915_FENCE_REG_NONE -1
469 #define I915_MAX_NUM_FENCES 32
470 /* 32 fences + sign bit for FENCE_REG_NONE */
471 #define I915_MAX_NUM_FENCE_BITS 6
473 struct drm_i915_fence_reg
{
474 struct list_head lru_list
;
475 struct drm_i915_gem_object
*obj
;
479 struct sdvo_device_mapping
{
488 struct intel_display_error_state
;
490 struct drm_i915_error_state
{
499 /* Generic register state */
507 u32 error
; /* gen6+ */
508 u32 err_int
; /* gen7 */
509 u32 fault_data0
; /* gen8, gen9 */
510 u32 fault_data1
; /* gen8, gen9 */
516 u32 extra_instdone
[I915_NUM_INSTDONE_REG
];
517 u64 fence
[I915_MAX_NUM_FENCES
];
518 struct intel_overlay_error_state
*overlay
;
519 struct intel_display_error_state
*display
;
520 struct drm_i915_error_object
*semaphore_obj
;
522 struct drm_i915_error_ring
{
524 /* Software tracked state */
527 enum intel_ring_hangcheck_action hangcheck_action
;
530 /* our own tracking of ring head and tail */
534 u32 semaphore_seqno
[I915_NUM_RINGS
- 1];
553 u32 rc_psmi
; /* sleep state */
554 u32 semaphore_mboxes
[I915_NUM_RINGS
- 1];
556 struct drm_i915_error_object
{
560 } *ringbuffer
, *batchbuffer
, *wa_batchbuffer
, *ctx
, *hws_page
;
562 struct drm_i915_error_request
{
577 char comm
[TASK_COMM_LEN
];
578 } ring
[I915_NUM_RINGS
];
580 struct drm_i915_error_buffer
{
583 u32 rseqno
[I915_NUM_RINGS
], wseqno
;
587 s32 fence_reg
:I915_MAX_NUM_FENCE_BITS
;
595 } **active_bo
, **pinned_bo
;
597 u32
*active_bo_count
, *pinned_bo_count
;
601 struct intel_connector
;
602 struct intel_encoder
;
603 struct intel_crtc_state
;
604 struct intel_initial_plane_config
;
609 struct drm_i915_display_funcs
{
610 int (*get_display_clock_speed
)(struct drm_device
*dev
);
611 int (*get_fifo_size
)(struct drm_device
*dev
, int plane
);
613 * find_dpll() - Find the best values for the PLL
614 * @limit: limits for the PLL
615 * @crtc: current CRTC
616 * @target: target frequency in kHz
617 * @refclk: reference clock frequency in kHz
618 * @match_clock: if provided, @best_clock P divider must
619 * match the P divider from @match_clock
620 * used for LVDS downclocking
621 * @best_clock: best PLL values found
623 * Returns true on success, false on failure.
625 bool (*find_dpll
)(const struct intel_limit
*limit
,
626 struct intel_crtc_state
*crtc_state
,
627 int target
, int refclk
,
628 struct dpll
*match_clock
,
629 struct dpll
*best_clock
);
630 void (*update_wm
)(struct drm_crtc
*crtc
);
631 void (*update_sprite_wm
)(struct drm_plane
*plane
,
632 struct drm_crtc
*crtc
,
633 uint32_t sprite_width
, uint32_t sprite_height
,
634 int pixel_size
, bool enable
, bool scaled
);
635 int (*modeset_calc_cdclk
)(struct drm_atomic_state
*state
);
636 void (*modeset_commit_cdclk
)(struct drm_atomic_state
*state
);
637 /* Returns the active state of the crtc, and if the crtc is active,
638 * fills out the pipe-config with the hw state. */
639 bool (*get_pipe_config
)(struct intel_crtc
*,
640 struct intel_crtc_state
*);
641 void (*get_initial_plane_config
)(struct intel_crtc
*,
642 struct intel_initial_plane_config
*);
643 int (*crtc_compute_clock
)(struct intel_crtc
*crtc
,
644 struct intel_crtc_state
*crtc_state
);
645 void (*crtc_enable
)(struct drm_crtc
*crtc
);
646 void (*crtc_disable
)(struct drm_crtc
*crtc
);
647 void (*audio_codec_enable
)(struct drm_connector
*connector
,
648 struct intel_encoder
*encoder
,
649 struct drm_display_mode
*mode
);
650 void (*audio_codec_disable
)(struct intel_encoder
*encoder
);
651 void (*fdi_link_train
)(struct drm_crtc
*crtc
);
652 void (*init_clock_gating
)(struct drm_device
*dev
);
653 int (*queue_flip
)(struct drm_device
*dev
, struct drm_crtc
*crtc
,
654 struct drm_framebuffer
*fb
,
655 struct drm_i915_gem_object
*obj
,
656 struct drm_i915_gem_request
*req
,
658 void (*update_primary_plane
)(struct drm_crtc
*crtc
,
659 struct drm_framebuffer
*fb
,
661 void (*hpd_irq_setup
)(struct drm_device
*dev
);
662 /* clock updates for mode set */
664 /* render clock increase/decrease */
665 /* display clock increase/decrease */
666 /* pll clock increase/decrease */
668 int (*setup_backlight
)(struct intel_connector
*connector
, enum i915_pipe pipe
);
669 uint32_t (*get_backlight
)(struct intel_connector
*connector
);
670 void (*set_backlight
)(struct intel_connector
*connector
,
672 void (*disable_backlight
)(struct intel_connector
*connector
);
673 void (*enable_backlight
)(struct intel_connector
*connector
);
676 enum forcewake_domain_id
{
677 FW_DOMAIN_ID_RENDER
= 0,
678 FW_DOMAIN_ID_BLITTER
,
684 enum forcewake_domains
{
685 FORCEWAKE_RENDER
= (1 << FW_DOMAIN_ID_RENDER
),
686 FORCEWAKE_BLITTER
= (1 << FW_DOMAIN_ID_BLITTER
),
687 FORCEWAKE_MEDIA
= (1 << FW_DOMAIN_ID_MEDIA
),
688 FORCEWAKE_ALL
= (FORCEWAKE_RENDER
|
693 struct intel_uncore_funcs
{
694 void (*force_wake_get
)(struct drm_i915_private
*dev_priv
,
695 enum forcewake_domains domains
);
696 void (*force_wake_put
)(struct drm_i915_private
*dev_priv
,
697 enum forcewake_domains domains
);
699 uint8_t (*mmio_readb
)(struct drm_i915_private
*dev_priv
, off_t offset
, bool trace
);
700 uint16_t (*mmio_readw
)(struct drm_i915_private
*dev_priv
, off_t offset
, bool trace
);
701 uint32_t (*mmio_readl
)(struct drm_i915_private
*dev_priv
, off_t offset
, bool trace
);
702 uint64_t (*mmio_readq
)(struct drm_i915_private
*dev_priv
, off_t offset
, bool trace
);
704 void (*mmio_writeb
)(struct drm_i915_private
*dev_priv
, off_t offset
,
705 uint8_t val
, bool trace
);
706 void (*mmio_writew
)(struct drm_i915_private
*dev_priv
, off_t offset
,
707 uint16_t val
, bool trace
);
708 void (*mmio_writel
)(struct drm_i915_private
*dev_priv
, off_t offset
,
709 uint32_t val
, bool trace
);
710 void (*mmio_writeq
)(struct drm_i915_private
*dev_priv
, off_t offset
,
711 uint64_t val
, bool trace
);
714 struct intel_uncore
{
715 struct lock lock
; /** lock is also taken in irq contexts. */
717 struct intel_uncore_funcs funcs
;
720 enum forcewake_domains fw_domains
;
722 struct intel_uncore_forcewake_domain
{
723 struct drm_i915_private
*i915
;
724 enum forcewake_domain_id id
;
726 struct timer_list timer
;
733 } fw_domain
[FW_DOMAIN_ID_COUNT
];
736 /* Iterate over initialised fw domains */
737 #define for_each_fw_domain_mask(domain__, mask__, dev_priv__, i__) \
738 for ((i__) = 0, (domain__) = &(dev_priv__)->uncore.fw_domain[0]; \
739 (i__) < FW_DOMAIN_ID_COUNT; \
740 (i__)++, (domain__) = &(dev_priv__)->uncore.fw_domain[i__]) \
741 if (((mask__) & (dev_priv__)->uncore.fw_domains) & (1 << (i__)))
743 #define for_each_fw_domain(domain__, dev_priv__, i__) \
744 for_each_fw_domain_mask(domain__, FORCEWAKE_ALL, dev_priv__, i__)
747 FW_UNINITIALIZED
= 0,
754 uint32_t *dmc_payload
;
755 uint32_t dmc_fw_size
;
757 uint32_t mmioaddr
[8];
758 uint32_t mmiodata
[8];
759 enum csr_state state
;
762 #define DEV_INFO_FOR_EACH_FLAG(func, sep) \
763 func(is_mobile) sep \
766 func(is_i945gm) sep \
768 func(need_gfx_hws) sep \
770 func(is_pineview) sep \
771 func(is_broadwater) sep \
772 func(is_crestline) sep \
773 func(is_ivybridge) sep \
774 func(is_valleyview) sep \
775 func(is_haswell) sep \
776 func(is_skylake) sep \
777 func(is_preliminary) sep \
779 func(has_pipe_cxsr) sep \
780 func(has_hotplug) sep \
781 func(cursor_needs_physical) sep \
782 func(has_overlay) sep \
783 func(overlay_needs_physical) sep \
784 func(supports_tv) sep \
789 #define DEFINE_FLAG(name) u8 name:1
790 #define SEP_SEMICOLON ;
792 struct intel_device_info
{
793 u32 display_mmio_offset
;
796 u8 num_sprites
[I915_MAX_PIPES
];
798 u8 ring_mask
; /* Rings supported by the HW */
799 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG
, SEP_SEMICOLON
);
800 /* Register offsets for the various display pipes and transcoders */
801 int pipe_offsets
[I915_MAX_TRANSCODERS
];
802 int trans_offsets
[I915_MAX_TRANSCODERS
];
803 int palette_offsets
[I915_MAX_PIPES
];
804 int cursor_offsets
[I915_MAX_PIPES
];
806 /* Slice/subslice/EU info */
809 u8 subslice_per_slice
;
812 /* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */
815 u8 has_subslice_pg
:1;
822 enum i915_cache_level
{
824 I915_CACHE_LLC
, /* also used for snoopable memory on non-LLC */
825 I915_CACHE_L3_LLC
, /* gen7+, L3 sits between the domain specifc
826 caches, eg sampler/render caches, and the
827 large Last-Level-Cache. LLC is coherent with
828 the CPU, but L3 is only visible to the GPU. */
829 I915_CACHE_WT
, /* hsw:gt3e WriteThrough for scanouts */
832 struct i915_ctx_hang_stats
{
833 /* This context had batch pending when hang was declared */
834 unsigned batch_pending
;
836 /* This context had batch active when hang was declared */
837 unsigned batch_active
;
839 /* Time when this context was last blamed for a GPU reset */
840 unsigned long guilty_ts
;
842 /* If the contexts causes a second GPU hang within this time,
843 * it is permanently banned from submitting any more work.
845 unsigned long ban_period_seconds
;
847 /* This context is banned to submit more work */
851 /* This must match up with the value previously used for execbuf2.rsvd1. */
852 #define DEFAULT_CONTEXT_HANDLE 0
854 #define CONTEXT_NO_ZEROMAP (1<<0)
856 * struct intel_context - as the name implies, represents a context.
857 * @ref: reference count.
858 * @user_handle: userspace tracking identity for this context.
859 * @remap_slice: l3 row remapping information.
860 * @flags: context specific flags:
861 * CONTEXT_NO_ZEROMAP: do not allow mapping things to page 0.
862 * @file_priv: filp associated with this context (NULL for global default
864 * @hang_stats: information about the role of this context in possible GPU
866 * @ppgtt: virtual memory space used by this context.
867 * @legacy_hw_ctx: render context backing object and whether it is correctly
868 * initialized (legacy ring submission mechanism only).
869 * @link: link in the global list of contexts.
871 * Contexts are memory images used by the hardware to store copies of their
874 struct intel_context
{
879 struct drm_i915_private
*i915
;
880 struct drm_i915_file_private
*file_priv
;
881 struct i915_ctx_hang_stats hang_stats
;
882 struct i915_hw_ppgtt
*ppgtt
;
884 /* Legacy ring buffer submission */
886 struct drm_i915_gem_object
*rcs_state
;
891 bool rcs_initialized
;
893 struct drm_i915_gem_object
*state
;
894 struct intel_ringbuffer
*ringbuf
;
896 } engine
[I915_NUM_RINGS
];
898 struct list_head link
;
910 /* This is always the inner lock when overlapping with struct_mutex and
911 * it's the outer lock when overlapping with stolen_lock. */
913 unsigned long uncompressed_size
;
916 unsigned int possible_framebuffer_bits
;
917 unsigned int busy_bits
;
918 struct intel_crtc
*crtc
;
921 struct drm_mm_node compressed_fb
;
922 struct drm_mm_node
*compressed_llb
;
926 /* Tracks whether the HW is actually enabled, not whether the feature is
930 struct intel_fbc_work
{
931 struct delayed_work work
;
932 struct intel_crtc
*crtc
;
933 struct drm_framebuffer
*fb
;
937 FBC_OK
, /* FBC is enabled */
938 FBC_UNSUPPORTED
, /* FBC is not supported by this chipset */
939 FBC_NO_OUTPUT
, /* no outputs enabled to compress */
940 FBC_STOLEN_TOO_SMALL
, /* not enough space for buffers */
941 FBC_UNSUPPORTED_MODE
, /* interlace or doublescanned mode */
942 FBC_MODE_TOO_LARGE
, /* mode too large for compression */
943 FBC_BAD_PLANE
, /* fbc not supported on plane */
944 FBC_NOT_TILED
, /* buffer not tiled */
945 FBC_MULTIPLE_PIPES
, /* more than one pipe active */
947 FBC_CHIP_DEFAULT
, /* disabled by default on this chip */
948 FBC_ROTATION
, /* rotation is not supported */
949 FBC_IN_DBG_MASTER
, /* kernel debugger is active */
952 bool (*fbc_enabled
)(struct drm_i915_private
*dev_priv
);
953 void (*enable_fbc
)(struct intel_crtc
*crtc
);
954 void (*disable_fbc
)(struct drm_i915_private
*dev_priv
);
958 * HIGH_RR is the highest eDP panel refresh rate read from EDID
959 * LOW_RR is the lowest eDP panel refresh rate found from EDID
960 * parsing for same resolution.
962 enum drrs_refresh_rate_type
{
965 DRRS_MAX_RR
, /* RR count */
968 enum drrs_support_type
{
969 DRRS_NOT_SUPPORTED
= 0,
970 STATIC_DRRS_SUPPORT
= 1,
971 SEAMLESS_DRRS_SUPPORT
= 2
977 struct delayed_work work
;
979 unsigned busy_frontbuffer_bits
;
980 enum drrs_refresh_rate_type refresh_rate_type
;
981 enum drrs_support_type type
;
988 struct intel_dp
*enabled
;
990 struct delayed_work work
;
991 unsigned busy_frontbuffer_bits
;
997 PCH_NONE
= 0, /* No PCH present */
998 PCH_IBX
, /* Ibexpeak PCH */
999 PCH_CPT
, /* Cougarpoint PCH */
1000 PCH_LPT
, /* Lynxpoint PCH */
1001 PCH_SPT
, /* Sunrisepoint PCH */
1005 enum intel_sbi_destination
{
1010 #define QUIRK_PIPEA_FORCE (1<<0)
1011 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
1012 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
1013 #define QUIRK_BACKLIGHT_PRESENT (1<<3)
1014 #define QUIRK_PIPEB_FORCE (1<<4)
1015 #define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
1018 struct intel_fbc_work
;
1020 struct intel_gmbus
{
1021 struct i2c_adapter adapter
;
1025 struct drm_i915_private
*dev_priv
;
1028 struct intel_iic_softc
{
1029 struct drm_device
*drm_dev
;
1037 struct i915_suspend_saved_registers
{
1040 u32 savePP_ON_DELAYS
;
1041 u32 savePP_OFF_DELAYS
;
1046 u32 saveFBC_CONTROL
;
1047 u32 saveCACHE_MODE_0
;
1048 u32 saveMI_ARB_STATE
;
1052 uint64_t saveFENCE
[I915_MAX_NUM_FENCES
];
1053 u32 savePCH_PORT_HOTPLUG
;
1057 struct vlv_s0ix_state
{
1064 u32 lra_limits
[GEN7_LRA_LIMITS_REG_NUM
];
1065 u32 media_max_req_count
;
1066 u32 gfx_max_req_count
;
1092 u32 rp_down_timeout
;
1098 /* Display 1 CZ domain */
1103 u32 gt_scratch
[GEN7_GT_SCRATCH_REG_NUM
];
1105 /* GT SA CZ domain */
1112 /* Display 2 CZ domain */
1116 u32 clock_gate_dis2
;
1119 struct intel_rps_ei
{
1125 struct intel_gen6_power_mgmt
{
1127 * work, interrupts_enabled and pm_iir are protected by
1128 * dev_priv->irq_lock
1130 struct work_struct work
;
1131 bool interrupts_enabled
;
1134 /* Frequencies are stored in potentially platform dependent multiples.
1135 * In other words, *_freq needs to be multiplied by X to be interesting.
1136 * Soft limits are those which are used for the dynamic reclocking done
1137 * by the driver (raise frequencies under heavy loads, and lower for
1138 * lighter loads). Hard limits are those imposed by the hardware.
1140 * A distinction is made for overclocking, which is never enabled by
1141 * default, and is considered to be above the hard limit if it's
1144 u8 cur_freq
; /* Current frequency (cached, may not == HW) */
1145 u8 min_freq_softlimit
; /* Minimum frequency permitted by the driver */
1146 u8 max_freq_softlimit
; /* Max frequency permitted by the driver */
1147 u8 max_freq
; /* Maximum frequency, RP0 if not overclocking */
1148 u8 min_freq
; /* AKA RPn. Minimum frequency */
1149 u8 idle_freq
; /* Frequency to request when we are idle */
1150 u8 efficient_freq
; /* AKA RPe. Pre-determined balanced frequency */
1151 u8 rp1_freq
; /* "less than" RP0 power/freqency */
1152 u8 rp0_freq
; /* Non-overclocked max frequency. */
1155 u8 up_threshold
; /* Current %busy required to uplock */
1156 u8 down_threshold
; /* Current %busy required to downclock */
1159 enum { LOW_POWER
, BETWEEN
, HIGH_POWER
} power
;
1161 struct lock client_lock
;
1162 struct list_head clients
;
1166 struct delayed_work delayed_resume_work
;
1169 struct intel_rps_client semaphores
, mmioflips
;
1171 /* manual wa residency calculations */
1172 struct intel_rps_ei up_ei
, down_ei
;
1175 * Protects RPS/RC6 register access and PCU communication.
1176 * Must be taken after struct_mutex if nested. Note that
1177 * this lock may be held for long periods of time when
1178 * talking to hw - so only take it when talking to hw!
1180 struct lock hw_lock
;
1183 /* defined intel_pm.c */
1184 extern struct lock mchdev_lock
;
1186 struct intel_ilk_power_mgmt
{
1194 unsigned long last_time1
;
1195 unsigned long chipset_power
;
1198 unsigned long gfx_power
;
1205 struct drm_i915_private
;
1206 struct i915_power_well
;
1208 struct i915_power_well_ops
{
1210 * Synchronize the well's hw state to match the current sw state, for
1211 * example enable/disable it based on the current refcount. Called
1212 * during driver init and resume time, possibly after first calling
1213 * the enable/disable handlers.
1215 void (*sync_hw
)(struct drm_i915_private
*dev_priv
,
1216 struct i915_power_well
*power_well
);
1218 * Enable the well and resources that depend on it (for example
1219 * interrupts located on the well). Called after the 0->1 refcount
1222 void (*enable
)(struct drm_i915_private
*dev_priv
,
1223 struct i915_power_well
*power_well
);
1225 * Disable the well and resources that depend on it. Called after
1226 * the 1->0 refcount transition.
1228 void (*disable
)(struct drm_i915_private
*dev_priv
,
1229 struct i915_power_well
*power_well
);
1230 /* Returns the hw enabled state. */
1231 bool (*is_enabled
)(struct drm_i915_private
*dev_priv
,
1232 struct i915_power_well
*power_well
);
1235 /* Power well structure for haswell */
1236 struct i915_power_well
{
1239 /* power well enable/disable usage count */
1241 /* cached hw enabled state */
1243 unsigned long domains
;
1245 const struct i915_power_well_ops
*ops
;
1248 struct i915_power_domains
{
1250 * Power wells needed for initialization at driver init and suspend
1251 * time are on. They are kept on until after the first modeset.
1255 int power_well_count
;
1258 int domain_use_count
[POWER_DOMAIN_NUM
];
1259 struct i915_power_well
*power_wells
;
1262 #define MAX_L3_SLICES 2
1263 struct intel_l3_parity
{
1264 u32
*remap_info
[MAX_L3_SLICES
];
1265 struct work_struct error_work
;
1269 struct i915_gem_mm
{
1270 /** Memory allocator for GTT stolen memory */
1271 struct drm_mm stolen
;
1272 /** Protects the usage of the GTT stolen memory allocator. This is
1273 * always the inner lock when overlapping with struct_mutex. */
1274 struct lock stolen_lock
;
1276 /** List of all objects in gtt_space. Used to restore gtt
1277 * mappings on resume */
1278 struct list_head bound_list
;
1280 * List of objects which are not bound to the GTT (thus
1281 * are idle and not used by the GPU) but still have
1282 * (presumably uncached) pages still attached.
1284 struct list_head unbound_list
;
1286 /** Usable portion of the GTT for GEM */
1287 unsigned long stolen_base
; /* limited to low memory (32-bit) */
1289 /** PPGTT used for aliasing the PPGTT with the GTT */
1290 struct i915_hw_ppgtt
*aliasing_ppgtt
;
1292 struct notifier_block oom_notifier
;
1294 struct shrinker shrinker
;
1296 bool shrinker_no_lock_stealing
;
1298 /** LRU list of objects with fence regs on them. */
1299 struct list_head fence_list
;
1302 * We leave the user IRQ off as much as possible,
1303 * but this means that requests will finish and never
1304 * be retired once the system goes idle. Set a timer to
1305 * fire periodically while the ring is running. When it
1306 * fires, go retire requests.
1308 struct delayed_work retire_work
;
1311 * When we detect an idle GPU, we want to turn on
1312 * powersaving features. So once we see that there
1313 * are no more requests outstanding and no more
1314 * arrive within a small period of time, we fire
1315 * off the idle_work.
1317 struct delayed_work idle_work
;
1320 * Are we in a non-interruptible section of code like
1326 * Is the GPU currently considered idle, or busy executing userspace
1327 * requests? Whilst idle, we attempt to power down the hardware and
1328 * display clocks. In order to reduce the effect on performance, there
1329 * is a slight delay before we do so.
1333 /* the indicator for dispatch video commands on two BSD rings */
1334 int bsd_ring_dispatch_index
;
1336 /** Bit 6 swizzling required for X tiling */
1337 uint32_t bit_6_swizzle_x
;
1338 /** Bit 6 swizzling required for Y tiling */
1339 uint32_t bit_6_swizzle_y
;
1341 /* accounting, useful for userland debugging */
1342 struct spinlock object_stat_lock
;
1343 size_t object_memory
;
1347 struct drm_i915_error_state_buf
{
1348 struct drm_i915_private
*i915
;
1357 struct i915_error_state_file_priv
{
1358 struct drm_device
*dev
;
1359 struct drm_i915_error_state
*error
;
1362 struct i915_gpu_error
{
1363 /* For hangcheck timer */
1364 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
1365 #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
1366 /* Hang gpu twice in this window and your context gets banned */
1367 #define DRM_I915_CTX_BAN_PERIOD DIV_ROUND_UP(8*DRM_I915_HANGCHECK_PERIOD, 1000)
1369 struct workqueue_struct
*hangcheck_wq
;
1370 struct delayed_work hangcheck_work
;
1372 /* For reset and error_state handling. */
1374 /* Protected by the above dev->gpu_error.lock. */
1375 struct drm_i915_error_state
*first_error
;
1377 unsigned long missed_irq_rings
;
1380 * State variable controlling the reset flow and count
1382 * This is a counter which gets incremented when reset is triggered,
1383 * and again when reset has been handled. So odd values (lowest bit set)
1384 * means that reset is in progress and even values that
1385 * (reset_counter >> 1):th reset was successfully completed.
1387 * If reset is not completed succesfully, the I915_WEDGE bit is
1388 * set meaning that hardware is terminally sour and there is no
1389 * recovery. All waiters on the reset_queue will be woken when
1392 * This counter is used by the wait_seqno code to notice that reset
1393 * event happened and it needs to restart the entire ioctl (since most
1394 * likely the seqno it waited for won't ever signal anytime soon).
1396 * This is important for lock-free wait paths, where no contended lock
1397 * naturally enforces the correct ordering between the bail-out of the
1398 * waiter and the gpu reset work code.
1400 atomic_t reset_counter
;
1402 #define I915_RESET_IN_PROGRESS_FLAG 1
1403 #define I915_WEDGED (1 << 31)
1406 * Waitqueue to signal when the reset has completed. Used by clients
1407 * that wait for dev_priv->mm.wedged to settle.
1409 wait_queue_head_t reset_queue
;
1411 /* Userspace knobs for gpu hang simulation;
1412 * combines both a ring mask, and extra flags
1415 #define I915_STOP_RING_ALLOW_BAN (1 << 31)
1416 #define I915_STOP_RING_ALLOW_WARN (1 << 30)
1418 /* For missed irq/seqno simulation. */
1419 unsigned int test_irq_rings
;
1421 /* Used to prevent gem_check_wedged returning -EAGAIN during gpu reset */
1422 bool reload_in_reset
;
1425 enum modeset_restore
{
1426 MODESET_ON_LID_OPEN
,
1431 #define DP_AUX_A 0x40
1432 #define DP_AUX_B 0x10
1433 #define DP_AUX_C 0x20
1434 #define DP_AUX_D 0x30
1436 #define DDC_PIN_B 0x05
1437 #define DDC_PIN_C 0x04
1438 #define DDC_PIN_D 0x06
1440 struct ddi_vbt_port_info
{
1442 * This is an index in the HDMI/DVI DDI buffer translation table.
1443 * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't
1444 * populate this field.
1446 #define HDMI_LEVEL_SHIFT_UNKNOWN 0xff
1447 uint8_t hdmi_level_shift
;
1449 uint8_t supports_dvi
:1;
1450 uint8_t supports_hdmi
:1;
1451 uint8_t supports_dp
:1;
1453 uint8_t alternate_aux_channel
;
1454 uint8_t alternate_ddc_pin
;
1456 uint8_t dp_boost_level
;
1457 uint8_t hdmi_boost_level
;
1460 enum psr_lines_to_wait
{
1461 PSR_0_LINES_TO_WAIT
= 0,
1463 PSR_4_LINES_TO_WAIT
,
1467 struct intel_vbt_data
{
1468 struct drm_display_mode
*lfp_lvds_vbt_mode
; /* if any */
1469 struct drm_display_mode
*sdvo_lvds_vbt_mode
; /* if any */
1472 unsigned int int_tv_support
:1;
1473 unsigned int lvds_dither
:1;
1474 unsigned int lvds_vbt
:1;
1475 unsigned int int_crt_support
:1;
1476 unsigned int lvds_use_ssc
:1;
1477 unsigned int display_clock_mode
:1;
1478 unsigned int fdi_rx_polarity_inverted
:1;
1479 unsigned int has_mipi
:1;
1481 unsigned int bios_lvds_val
; /* initial [PCH_]LVDS reg val in VBIOS */
1483 enum drrs_support_type drrs_type
;
1488 int edp_preemphasis
;
1490 bool edp_initialized
;
1493 struct edp_power_seq edp_pps
;
1497 bool require_aux_wakeup
;
1499 enum psr_lines_to_wait lines_to_wait
;
1500 int tp1_wakeup_time
;
1501 int tp2_tp3_wakeup_time
;
1507 bool active_low_pwm
;
1508 u8 min_brightness
; /* min_brightness/255 of max */
1515 struct mipi_config
*config
;
1516 struct mipi_pps_data
*pps
;
1520 u8
*sequence
[MIPI_SEQ_MAX
];
1526 union child_device_config
*child_dev
;
1528 struct ddi_vbt_port_info ddi_port_info
[I915_MAX_PORTS
];
1531 enum intel_ddb_partitioning
{
1533 INTEL_DDB_PART_5_6
, /* IVB+ */
1536 struct intel_wm_level
{
1544 struct ilk_wm_values
{
1545 uint32_t wm_pipe
[3];
1547 uint32_t wm_lp_spr
[3];
1548 uint32_t wm_linetime
[3];
1550 enum intel_ddb_partitioning partitioning
;
1553 struct vlv_pipe_wm
{
1564 struct vlv_wm_values
{
1565 struct vlv_pipe_wm pipe
[3];
1566 struct vlv_sr_wm sr
;
1576 struct skl_ddb_entry
{
1577 uint16_t start
, end
; /* in number of blocks, 'end' is exclusive */
1580 static inline uint16_t skl_ddb_entry_size(const struct skl_ddb_entry
*entry
)
1582 return entry
->end
- entry
->start
;
1585 static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry
*e1
,
1586 const struct skl_ddb_entry
*e2
)
1588 if (e1
->start
== e2
->start
&& e1
->end
== e2
->end
)
1594 struct skl_ddb_allocation
{
1595 struct skl_ddb_entry pipe
[I915_MAX_PIPES
];
1596 struct skl_ddb_entry plane
[I915_MAX_PIPES
][I915_MAX_PLANES
]; /* packed/uv */
1597 struct skl_ddb_entry y_plane
[I915_MAX_PIPES
][I915_MAX_PLANES
]; /* y-plane */
1598 struct skl_ddb_entry cursor
[I915_MAX_PIPES
];
1601 struct skl_wm_values
{
1602 bool dirty
[I915_MAX_PIPES
];
1603 struct skl_ddb_allocation ddb
;
1604 uint32_t wm_linetime
[I915_MAX_PIPES
];
1605 uint32_t plane
[I915_MAX_PIPES
][I915_MAX_PLANES
][8];
1606 uint32_t cursor
[I915_MAX_PIPES
][8];
1607 uint32_t plane_trans
[I915_MAX_PIPES
][I915_MAX_PLANES
];
1608 uint32_t cursor_trans
[I915_MAX_PIPES
];
1611 struct skl_wm_level
{
1612 bool plane_en
[I915_MAX_PLANES
];
1614 uint16_t plane_res_b
[I915_MAX_PLANES
];
1615 uint8_t plane_res_l
[I915_MAX_PLANES
];
1616 uint16_t cursor_res_b
;
1617 uint8_t cursor_res_l
;
1621 * This struct helps tracking the state needed for runtime PM, which puts the
1622 * device in PCI D3 state. Notice that when this happens, nothing on the
1623 * graphics device works, even register access, so we don't get interrupts nor
1626 * Every piece of our code that needs to actually touch the hardware needs to
1627 * either call intel_runtime_pm_get or call intel_display_power_get with the
1628 * appropriate power domain.
1630 * Our driver uses the autosuspend delay feature, which means we'll only really
1631 * suspend if we stay with zero refcount for a certain amount of time. The
1632 * default value is currently very conservative (see intel_runtime_pm_enable), but
1633 * it can be changed with the standard runtime PM files from sysfs.
1635 * The irqs_disabled variable becomes true exactly after we disable the IRQs and
1636 * goes back to false exactly before we reenable the IRQs. We use this variable
1637 * to check if someone is trying to enable/disable IRQs while they're supposed
1638 * to be disabled. This shouldn't happen and we'll print some error messages in
1641 * For more, read the Documentation/power/runtime_pm.txt.
1643 struct i915_runtime_pm
{
1648 enum intel_pipe_crc_source
{
1649 INTEL_PIPE_CRC_SOURCE_NONE
,
1650 INTEL_PIPE_CRC_SOURCE_PLANE1
,
1651 INTEL_PIPE_CRC_SOURCE_PLANE2
,
1652 INTEL_PIPE_CRC_SOURCE_PF
,
1653 INTEL_PIPE_CRC_SOURCE_PIPE
,
1654 /* TV/DP on pre-gen5/vlv can't use the pipe source. */
1655 INTEL_PIPE_CRC_SOURCE_TV
,
1656 INTEL_PIPE_CRC_SOURCE_DP_B
,
1657 INTEL_PIPE_CRC_SOURCE_DP_C
,
1658 INTEL_PIPE_CRC_SOURCE_DP_D
,
1659 INTEL_PIPE_CRC_SOURCE_AUTO
,
1660 INTEL_PIPE_CRC_SOURCE_MAX
,
1663 struct intel_pipe_crc_entry
{
1668 #define INTEL_PIPE_CRC_ENTRIES_NR 128
1669 struct intel_pipe_crc
{
1670 struct spinlock lock
;
1671 bool opened
; /* exclusive access to the result file */
1672 struct intel_pipe_crc_entry
*entries
;
1673 enum intel_pipe_crc_source source
;
1675 wait_queue_head_t wq
;
1678 struct i915_frontbuffer_tracking
{
1682 * Tracking bits for delayed frontbuffer flushing du to gpu activity or
1689 struct i915_wa_reg
{
1692 /* bitmask representing WA bits */
1696 #define I915_MAX_WA_REGS 16
1698 struct i915_workarounds
{
1699 struct i915_wa_reg reg
[I915_MAX_WA_REGS
];
1703 struct i915_virtual_gpu
{
1707 struct i915_execbuffer_params
{
1708 struct drm_device
*dev
;
1709 struct drm_file
*file
;
1710 uint32_t dispatch_flags
;
1711 uint32_t args_batch_start_offset
;
1712 uint32_t batch_obj_vm_offset
;
1713 struct intel_engine_cs
*ring
;
1714 struct drm_i915_gem_object
*batch_obj
;
1715 struct intel_context
*ctx
;
1716 struct drm_i915_gem_request
*request
;
1719 struct drm_local_map
;
1721 struct drm_i915_private
{
1722 struct drm_device
*dev
;
1723 struct kmem_cache
*objects
;
1724 struct kmem_cache
*vmas
;
1725 struct kmem_cache
*requests
;
1727 struct intel_device_info info
;
1729 int relative_constants_mode
;
1731 device_t
*gmbus_bridge
;
1732 device_t
*bbbus_bridge
;
1735 struct drm_local_map
*mmio_map
;
1738 struct intel_uncore uncore
;
1740 struct i915_virtual_gpu vgpu
;
1742 struct intel_csr csr
;
1744 /* Display CSR-related protection */
1745 struct lock csr_lock
;
1750 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
1751 * controller on different i2c buses. */
1752 struct lock gmbus_mutex
;
1755 * Base address of the gmbus and gpio block.
1757 uint32_t gpio_mmio_base
;
1759 /* MMIO base address for MIPI regs */
1760 uint32_t mipi_mmio_base
;
1762 wait_queue_head_t gmbus_wait_queue
;
1764 struct pci_dev
*bridge_dev
;
1765 struct intel_engine_cs ring
[I915_NUM_RINGS
];
1766 struct drm_i915_gem_object
*semaphore_obj
;
1767 uint32_t last_seqno
, next_seqno
;
1769 struct drm_dma_handle
*status_page_dmah
;
1770 struct resource
*mch_res
;
1773 /* protects the irq masks */
1774 struct lock irq_lock
;
1776 /* protects the mmio flip data */
1777 struct spinlock mmio_flip_lock
;
1779 bool display_irqs_enabled
;
1781 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
1782 struct pm_qos_request pm_qos
;
1784 /* Sideband mailbox protection */
1785 struct lock sb_lock
;
1787 /** Cached value of IMR to avoid reads in updating the bitfield */
1790 u32 de_irq_mask
[I915_MAX_PIPES
];
1795 u32 pipestat_irq_mask
[I915_MAX_PIPES
];
1797 struct i915_hotplug hotplug
;
1798 struct i915_fbc fbc
;
1799 struct i915_drrs drrs
;
1800 struct intel_opregion opregion
;
1801 struct intel_vbt_data vbt
;
1803 bool preserve_bios_swizzle
;
1806 struct intel_overlay
*overlay
;
1808 /* backlight registers and fields in struct intel_panel */
1809 struct lock backlight_lock
;
1812 bool no_aux_handshake
;
1814 /* protects panel power sequencer state */
1815 struct lock pps_mutex
;
1817 struct drm_i915_fence_reg fence_regs
[I915_MAX_NUM_FENCES
]; /* assume 965 */
1818 int fence_reg_start
; /* 4 if userland hasn't ioctl'd us yet */
1819 int num_fence_regs
; /* 8 on pre-965, 16 otherwise */
1821 unsigned int fsb_freq
, mem_freq
, is_ddr3
;
1822 unsigned int skl_boot_cdclk
;
1823 unsigned int cdclk_freq
, max_cdclk_freq
;
1824 unsigned int hpll_freq
;
1827 * wq - Driver workqueue for GEM.
1829 * NOTE: Work items scheduled here are not allowed to grab any modeset
1830 * locks, for otherwise the flushing done in the pageflip code will
1831 * result in deadlocks.
1833 struct workqueue_struct
*wq
;
1835 /* Display functions */
1836 struct drm_i915_display_funcs display
;
1838 /* PCH chipset type */
1839 enum intel_pch pch_type
;
1840 unsigned short pch_id
;
1842 unsigned long quirks
;
1844 enum modeset_restore modeset_restore
;
1845 struct lock modeset_restore_lock
;
1847 struct list_head vm_list
; /* Global list of all address spaces */
1848 struct i915_gtt gtt
; /* VM representing the global address space */
1850 struct i915_gem_mm mm
;
1851 DECLARE_HASHTABLE(mm_structs
, 7);
1852 struct lock mm_lock
;
1854 /* Kernel Modesetting */
1856 struct sdvo_device_mapping sdvo_mappings
[2];
1858 struct drm_crtc
*plane_to_crtc_mapping
[I915_MAX_PIPES
];
1859 struct drm_crtc
*pipe_to_crtc_mapping
[I915_MAX_PIPES
];
1860 wait_queue_head_t pending_flip_queue
;
1862 #ifdef CONFIG_DEBUG_FS
1863 struct intel_pipe_crc pipe_crc
[I915_MAX_PIPES
];
1866 int num_shared_dpll
;
1867 struct intel_shared_dpll shared_dplls
[I915_NUM_PLLS
];
1868 int dpio_phy_iosf_port
[I915_NUM_PHYS_VLV
];
1870 struct i915_workarounds workarounds
;
1872 /* Reclocking support */
1873 bool render_reclock_avail
;
1875 struct i915_frontbuffer_tracking fb_tracking
;
1879 bool mchbar_need_disable
;
1881 struct intel_l3_parity l3_parity
;
1883 /* Cannot be determined by PCIID. You must always read a register. */
1886 /* gen6+ rps state */
1887 struct intel_gen6_power_mgmt rps
;
1889 /* ilk-only ips/rps state. Everything in here is protected by the global
1890 * mchdev_lock in intel_pm.c */
1891 struct intel_ilk_power_mgmt ips
;
1893 struct i915_power_domains power_domains
;
1895 struct i915_psr psr
;
1897 struct i915_gpu_error gpu_error
;
1899 struct drm_i915_gem_object
*vlv_pctx
;
1901 #ifdef CONFIG_DRM_FBDEV_EMULATION
1902 /* list of fbdev register on this device */
1903 struct intel_fbdev
*fbdev
;
1904 struct work_struct fbdev_suspend_work
;
1907 struct drm_property
*broadcast_rgb_property
;
1908 struct drm_property
*force_audio_property
;
1910 /* hda/i915 audio component */
1911 struct i915_audio_component
*audio_component
;
1912 bool audio_component_registered
;
1914 uint32_t hw_context_size
;
1915 struct list_head context_list
;
1919 u32 chv_phy_control
;
1922 struct i915_suspend_saved_registers regfile
;
1923 struct vlv_s0ix_state vlv_s0ix_state
;
1927 * Raw watermark latency values:
1928 * in 0.1us units for WM0,
1929 * in 0.5us units for WM1+.
1932 uint16_t pri_latency
[5];
1934 uint16_t spr_latency
[5];
1936 uint16_t cur_latency
[5];
1938 * Raw watermark memory latency values
1939 * for SKL for all 8 levels
1942 uint16_t skl_latency
[8];
1945 * The skl_wm_values structure is a bit too big for stack
1946 * allocation, so we keep the staging struct where we store
1947 * intermediate results here instead.
1949 struct skl_wm_values skl_results
;
1951 /* current hardware state */
1953 struct ilk_wm_values hw
;
1954 struct skl_wm_values skl_hw
;
1955 struct vlv_wm_values vlv
;
1961 struct i915_runtime_pm pm
;
1963 uint32_t bios_vgacntr
;
1965 /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
1967 int (*execbuf_submit
)(struct i915_execbuffer_params
*params
,
1968 struct drm_i915_gem_execbuffer2
*args
,
1969 struct list_head
*vmas
);
1970 int (*init_rings
)(struct drm_device
*dev
);
1971 void (*cleanup_ring
)(struct intel_engine_cs
*ring
);
1972 void (*stop_ring
)(struct intel_engine_cs
*ring
);
1975 bool edp_low_vswing
;
1978 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
1979 * will be rejected. Instead look for a better place.
1983 static inline struct drm_i915_private
*to_i915(const struct drm_device
*dev
)
1985 return dev
->dev_private
;
1988 static inline struct drm_i915_private
*dev_to_i915(struct device
*dev
)
1993 /* Iterate over initialised rings */
1994 #define for_each_ring(ring__, dev_priv__, i__) \
1995 for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \
1996 if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__)))
1998 enum hdmi_force_audio
{
1999 HDMI_AUDIO_OFF_DVI
= -2, /* no aux data for HDMI-DVI converter */
2000 HDMI_AUDIO_OFF
, /* force turn off HDMI audio */
2001 HDMI_AUDIO_AUTO
, /* trust EDID */
2002 HDMI_AUDIO_ON
, /* force turn on HDMI audio */
2005 #define I915_GTT_OFFSET_NONE ((u32)-1)
2007 struct drm_i915_gem_object_ops
{
2008 /* Interface between the GEM object and its backing storage.
2009 * get_pages() is called once prior to the use of the associated set
2010 * of pages before to binding them into the GTT, and put_pages() is
2011 * called after we no longer need them. As we expect there to be
2012 * associated cost with migrating pages between the backing storage
2013 * and making them available for the GPU (e.g. clflush), we may hold
2014 * onto the pages after they are no longer referenced by the GPU
2015 * in case they may be used again shortly (for example migrating the
2016 * pages to a different memory domain within the GTT). put_pages()
2017 * will therefore most likely be called when the object itself is
2018 * being released or under memory pressure (where we attempt to
2019 * reap pages for the shrinker).
2021 int (*get_pages
)(struct drm_i915_gem_object
*);
2022 void (*put_pages
)(struct drm_i915_gem_object
*);
2023 int (*dmabuf_export
)(struct drm_i915_gem_object
*);
2024 void (*release
)(struct drm_i915_gem_object
*);
2028 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
2029 * considered to be the frontbuffer for the given plane interface-vise. This
2030 * doesn't mean that the hw necessarily already scans it out, but that any
2031 * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
2033 * We have one bit per pipe and per scanout plane type.
2035 #define INTEL_FRONTBUFFER_BITS_PER_PIPE 4
2036 #define INTEL_FRONTBUFFER_BITS \
2037 (INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES)
2038 #define INTEL_FRONTBUFFER_PRIMARY(pipe) \
2039 (1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
2040 #define INTEL_FRONTBUFFER_CURSOR(pipe) \
2041 (1 << (1 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2042 #define INTEL_FRONTBUFFER_SPRITE(pipe) \
2043 (1 << (2 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2044 #define INTEL_FRONTBUFFER_OVERLAY(pipe) \
2045 (1 << (3 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2046 #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
2047 (0xf << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
2049 struct drm_i915_gem_object
{
2050 struct drm_gem_object base
;
2052 const struct drm_i915_gem_object_ops
*ops
;
2054 /** List of VMAs backed by this object */
2055 struct list_head vma_list
;
2057 /** Stolen memory for this object, instead of being backed by shmem. */
2058 struct drm_mm_node
*stolen
;
2059 struct list_head global_list
;
2061 struct list_head ring_list
[I915_NUM_RINGS
];
2062 /** Used in execbuf to temporarily hold a ref */
2063 struct list_head obj_exec_link
;
2065 struct list_head batch_pool_link
;
2068 * This is set if the object is on the active lists (has pending
2069 * rendering and so a non-zero seqno), and is not set if it i s on
2070 * inactive (ready to be unbound) list.
2072 unsigned int active
:I915_NUM_RINGS
;
2075 * This is set if the object has been written to since last bound
2078 unsigned int dirty
:1;
2081 * Fence register bits (if any) for this object. Will be set
2082 * as needed when mapped into the GTT.
2083 * Protected by dev->struct_mutex.
2085 signed int fence_reg
:I915_MAX_NUM_FENCE_BITS
;
2088 * Advice: are the backing pages purgeable?
2090 unsigned int madv
:2;
2093 * Current tiling mode for the object.
2095 unsigned int tiling_mode
:2;
2097 * Whether the tiling parameters for the currently associated fence
2098 * register have changed. Note that for the purposes of tracking
2099 * tiling changes we also treat the unfenced register, the register
2100 * slot that the object occupies whilst it executes a fenced
2101 * command (such as BLT on gen2/3), as a "fence".
2103 unsigned int fence_dirty
:1;
2106 * Is the object at the current location in the gtt mappable and
2107 * fenceable? Used to avoid costly recalculations.
2109 unsigned int map_and_fenceable
:1;
2112 * Whether the current gtt mapping needs to be mappable (and isn't just
2113 * mappable by accident). Track pin and fault separate for a more
2114 * accurate mappable working set.
2116 unsigned int fault_mappable
:1;
2119 * Is the object to be mapped as read-only to the GPU
2120 * Only honoured if hardware has relevant pte bit
2122 unsigned long gt_ro
:1;
2123 unsigned int cache_level
:3;
2124 unsigned int cache_dirty
:1;
2126 unsigned int frontbuffer_bits
:INTEL_FRONTBUFFER_BITS
;
2128 unsigned int pin_display
;
2130 struct sg_table
*pages
;
2131 int pages_pin_count
;
2133 struct scatterlist
*sg
;
2137 /* prime dma-buf support */
2138 void *dma_buf_vmapping
;
2141 /** Breadcrumb of last rendering to the buffer.
2142 * There can only be one writer, but we allow for multiple readers.
2143 * If there is a writer that necessarily implies that all other
2144 * read requests are complete - but we may only be lazily clearing
2145 * the read requests. A read request is naturally the most recent
2146 * request on a ring, so we may have two different write and read
2147 * requests on one ring where the write request is older than the
2148 * read request. This allows for the CPU to read from an active
2149 * buffer by only waiting for the write to complete.
2151 struct drm_i915_gem_request
*last_read_req
[I915_NUM_RINGS
];
2152 struct drm_i915_gem_request
*last_write_req
;
2153 /** Breadcrumb of last fenced GPU access to the buffer. */
2154 struct drm_i915_gem_request
*last_fenced_req
;
2156 /** Current tiling stride for the object, if it's tiled. */
2159 /** References from framebuffers, locks out tiling changes. */
2160 unsigned long framebuffer_references
;
2162 /** Record of address bit 17 of each page at last unbind. */
2163 unsigned long *bit_17
;
2166 /** for phy allocated objects */
2167 struct drm_dma_handle
*phys_handle
;
2169 struct i915_gem_userptr
{
2171 unsigned read_only
:1;
2172 unsigned workers
:4;
2173 #define I915_GEM_USERPTR_MAX_WORKERS 15
2175 struct i915_mm_struct
*mm
;
2176 struct i915_mmu_object
*mmu_object
;
2177 struct work_struct
*work
;
2181 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
2183 void i915_gem_track_fb(struct drm_i915_gem_object
*old
,
2184 struct drm_i915_gem_object
*new,
2185 unsigned frontbuffer_bits
);
2188 * Request queue structure.
2190 * The request queue allows us to note sequence numbers that have been emitted
2191 * and may be associated with active buffers to be retired.
2193 * By keeping this list, we can avoid having to do questionable sequence
2194 * number comparisons on buffer last_read|write_seqno. It also allows an
2195 * emission time to be associated with the request for tracking how far ahead
2196 * of the GPU the submission is.
2198 * The requests are reference counted, so upon creation they should have an
2199 * initial reference taken using kref_init
2201 struct drm_i915_gem_request
{
2204 /** On Which ring this request was generated */
2205 struct drm_i915_private
*i915
;
2206 struct intel_engine_cs
*ring
;
2208 /** GEM sequence number associated with this request. */
2211 /** Position in the ringbuffer of the start of the request */
2215 * Position in the ringbuffer of the start of the postfix.
2216 * This is required to calculate the maximum available ringbuffer
2217 * space without overwriting the postfix.
2221 /** Position in the ringbuffer of the end of the whole request */
2225 * Context and ring buffer related to this request
2226 * Contexts are refcounted, so when this request is associated with a
2227 * context, we must increment the context's refcount, to guarantee that
2228 * it persists while any request is linked to it. Requests themselves
2229 * are also refcounted, so the request will only be freed when the last
2230 * reference to it is dismissed, and the code in
2231 * i915_gem_request_free() will then decrement the refcount on the
2234 struct intel_context
*ctx
;
2235 struct intel_ringbuffer
*ringbuf
;
2237 /** Batch buffer related to this request if any (used for
2238 error state dump only) */
2239 struct drm_i915_gem_object
*batch_obj
;
2241 /** Time at which this request was emitted, in jiffies. */
2242 unsigned long emitted_jiffies
;
2244 /** global list entry for this request */
2245 struct list_head list
;
2247 struct drm_i915_file_private
*file_priv
;
2248 /** file_priv list entry for this request */
2249 struct list_head client_list
;
2251 /** process identifier submitting this request */
2255 * The ELSP only accepts two elements at a time, so we queue
2256 * context/tail pairs on a given queue (ring->execlist_queue) until the
2257 * hardware is available. The queue serves a double purpose: we also use
2258 * it to keep track of the up to 2 contexts currently in the hardware
2259 * (usually one in execution and the other queued up by the GPU): We
2260 * only remove elements from the head of the queue when the hardware
2261 * informs us that an element has been completed.
2263 * All accesses to the queue are mediated by a spinlock
2264 * (ring->execlist_lock).
2267 /** Execlist link in the submission queue.*/
2268 struct list_head execlist_link
;
2270 /** Execlists no. of times this request has been sent to the ELSP */
2275 int i915_gem_request_alloc(struct intel_engine_cs
*ring
,
2276 struct intel_context
*ctx
,
2277 struct drm_i915_gem_request
**req_out
);
2278 void i915_gem_request_cancel(struct drm_i915_gem_request
*req
);
2279 void i915_gem_request_free(struct kref
*req_ref
);
2280 int i915_gem_request_add_to_client(struct drm_i915_gem_request
*req
,
2281 struct drm_file
*file
);
2283 static inline uint32_t
2284 i915_gem_request_get_seqno(struct drm_i915_gem_request
*req
)
2286 return req
? req
->seqno
: 0;
2289 static inline struct intel_engine_cs
*
2290 i915_gem_request_get_ring(struct drm_i915_gem_request
*req
)
2292 return req
? req
->ring
: NULL
;
2295 static inline struct drm_i915_gem_request
*
2296 i915_gem_request_reference(struct drm_i915_gem_request
*req
)
2299 kref_get(&req
->ref
);
2304 i915_gem_request_unreference(struct drm_i915_gem_request
*req
)
2306 WARN_ON(!mutex_is_locked(&req
->ring
->dev
->struct_mutex
));
2307 kref_put(&req
->ref
, i915_gem_request_free
);
2311 i915_gem_request_unreference__unlocked(struct drm_i915_gem_request
*req
)
2313 struct drm_device
*dev
;
2318 dev
= req
->ring
->dev
;
2319 if (kref_put_mutex(&req
->ref
, i915_gem_request_free
, &dev
->struct_mutex
))
2320 mutex_unlock(&dev
->struct_mutex
);
2323 static inline void i915_gem_request_assign(struct drm_i915_gem_request
**pdst
,
2324 struct drm_i915_gem_request
*src
)
2327 i915_gem_request_reference(src
);
2330 i915_gem_request_unreference(*pdst
);
2336 * XXX: i915_gem_request_completed should be here but currently needs the
2337 * definition of i915_seqno_passed() which is below. It will be moved in
2338 * a later patch when the call to i915_seqno_passed() is obsoleted...
2342 * A command that requires special handling by the command parser.
2344 struct drm_i915_cmd_descriptor
{
2346 * Flags describing how the command parser processes the command.
2348 * CMD_DESC_FIXED: The command has a fixed length if this is set,
2349 * a length mask if not set
2350 * CMD_DESC_SKIP: The command is allowed but does not follow the
2351 * standard length encoding for the opcode range in
2353 * CMD_DESC_REJECT: The command is never allowed
2354 * CMD_DESC_REGISTER: The command should be checked against the
2355 * register whitelist for the appropriate ring
2356 * CMD_DESC_MASTER: The command is allowed if the submitting process
2360 #define CMD_DESC_FIXED (1<<0)
2361 #define CMD_DESC_SKIP (1<<1)
2362 #define CMD_DESC_REJECT (1<<2)
2363 #define CMD_DESC_REGISTER (1<<3)
2364 #define CMD_DESC_BITMASK (1<<4)
2365 #define CMD_DESC_MASTER (1<<5)
2368 * The command's unique identification bits and the bitmask to get them.
2369 * This isn't strictly the opcode field as defined in the spec and may
2370 * also include type, subtype, and/or subop fields.
2378 * The command's length. The command is either fixed length (i.e. does
2379 * not include a length field) or has a length field mask. The flag
2380 * CMD_DESC_FIXED indicates a fixed length. Otherwise, the command has
2381 * a length mask. All command entries in a command table must include
2382 * length information.
2390 * Describes where to find a register address in the command to check
2391 * against the ring's register whitelist. Only valid if flags has the
2392 * CMD_DESC_REGISTER bit set.
2394 * A non-zero step value implies that the command may access multiple
2395 * registers in sequence (e.g. LRI), in that case step gives the
2396 * distance in dwords between individual offset fields.
2404 #define MAX_CMD_DESC_BITMASKS 3
2406 * Describes command checks where a particular dword is masked and
2407 * compared against an expected value. If the command does not match
2408 * the expected value, the parser rejects it. Only valid if flags has
2409 * the CMD_DESC_BITMASK bit set. Only entries where mask is non-zero
2412 * If the check specifies a non-zero condition_mask then the parser
2413 * only performs the check when the bits specified by condition_mask
2420 u32 condition_offset
;
2422 } bits
[MAX_CMD_DESC_BITMASKS
];
2426 * A table of commands requiring special handling by the command parser.
2428 * Each ring has an array of tables. Each table consists of an array of command
2429 * descriptors, which must be sorted with command opcodes in ascending order.
2431 struct drm_i915_cmd_table
{
2432 const struct drm_i915_cmd_descriptor
*table
;
2436 /* Note that the (struct drm_i915_private *) cast is just to shut up gcc. */
2437 #define __I915__(p) ({ \
2438 const struct drm_i915_private *__p; \
2439 if (__builtin_types_compatible_p(typeof(*p), struct drm_i915_private)) \
2440 __p = (const struct drm_i915_private *)p; \
2441 else if (__builtin_types_compatible_p(typeof(*p), struct drm_device)) \
2442 __p = to_i915((const struct drm_device *)p); \
2445 #define INTEL_INFO(p) (&__I915__(p)->info)
2446 #define INTEL_DEVID(p) (INTEL_INFO(p)->device_id)
2447 #define INTEL_REVID(p) (__I915__(p)->dev->pdev->revision)
2449 #define IS_I830(dev) (INTEL_DEVID(dev) == 0x3577)
2450 #define IS_845G(dev) (INTEL_DEVID(dev) == 0x2562)
2451 #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
2452 #define IS_I865G(dev) (INTEL_DEVID(dev) == 0x2572)
2453 #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
2454 #define IS_I915GM(dev) (INTEL_DEVID(dev) == 0x2592)
2455 #define IS_I945G(dev) (INTEL_DEVID(dev) == 0x2772)
2456 #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
2457 #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
2458 #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
2459 #define IS_GM45(dev) (INTEL_DEVID(dev) == 0x2A42)
2460 #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
2461 #define IS_PINEVIEW_G(dev) (INTEL_DEVID(dev) == 0xa001)
2462 #define IS_PINEVIEW_M(dev) (INTEL_DEVID(dev) == 0xa011)
2463 #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
2464 #define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
2465 #define IS_IRONLAKE_M(dev) (INTEL_DEVID(dev) == 0x0046)
2466 #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge)
2467 #define IS_IVB_GT1(dev) (INTEL_DEVID(dev) == 0x0156 || \
2468 INTEL_DEVID(dev) == 0x0152 || \
2469 INTEL_DEVID(dev) == 0x015a)
2470 #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview)
2471 #define IS_CHERRYVIEW(dev) (INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev))
2472 #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
2473 #define IS_BROADWELL(dev) (!INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev))
2474 #define IS_SKYLAKE(dev) (INTEL_INFO(dev)->is_skylake)
2475 #define IS_BROXTON(dev) (!INTEL_INFO(dev)->is_skylake && IS_GEN9(dev))
2476 #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
2477 #define IS_HSW_EARLY_SDV(dev) (IS_HASWELL(dev) && \
2478 (INTEL_DEVID(dev) & 0xFF00) == 0x0C00)
2479 #define IS_BDW_ULT(dev) (IS_BROADWELL(dev) && \
2480 ((INTEL_DEVID(dev) & 0xf) == 0x6 || \
2481 (INTEL_DEVID(dev) & 0xf) == 0xb || \
2482 (INTEL_DEVID(dev) & 0xf) == 0xe))
2483 /* ULX machines are also considered ULT. */
2484 #define IS_BDW_ULX(dev) (IS_BROADWELL(dev) && \
2485 (INTEL_DEVID(dev) & 0xf) == 0xe)
2486 #define IS_BDW_GT3(dev) (IS_BROADWELL(dev) && \
2487 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2488 #define IS_HSW_ULT(dev) (IS_HASWELL(dev) && \
2489 (INTEL_DEVID(dev) & 0xFF00) == 0x0A00)
2490 #define IS_HSW_GT3(dev) (IS_HASWELL(dev) && \
2491 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2492 /* ULX machines are also considered ULT. */
2493 #define IS_HSW_ULX(dev) (INTEL_DEVID(dev) == 0x0A0E || \
2494 INTEL_DEVID(dev) == 0x0A1E)
2495 #define IS_SKL_ULT(dev) (INTEL_DEVID(dev) == 0x1906 || \
2496 INTEL_DEVID(dev) == 0x1913 || \
2497 INTEL_DEVID(dev) == 0x1916 || \
2498 INTEL_DEVID(dev) == 0x1921 || \
2499 INTEL_DEVID(dev) == 0x1926)
2500 #define IS_SKL_ULX(dev) (INTEL_DEVID(dev) == 0x190E || \
2501 INTEL_DEVID(dev) == 0x1915 || \
2502 INTEL_DEVID(dev) == 0x191E)
2503 #define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary)
2505 #define SKL_REVID_A0 (0x0)
2506 #define SKL_REVID_B0 (0x1)
2507 #define SKL_REVID_C0 (0x2)
2508 #define SKL_REVID_D0 (0x3)
2509 #define SKL_REVID_E0 (0x4)
2510 #define SKL_REVID_F0 (0x5)
2512 #define BXT_REVID_A0 (0x0)
2513 #define BXT_REVID_B0 (0x3)
2514 #define BXT_REVID_C0 (0x6)
2517 * The genX designation typically refers to the render engine, so render
2518 * capability related checks should use IS_GEN, while display and other checks
2519 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
2522 #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2)
2523 #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3)
2524 #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4)
2525 #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5)
2526 #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6)
2527 #define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7)
2528 #define IS_GEN8(dev) (INTEL_INFO(dev)->gen == 8)
2529 #define IS_GEN9(dev) (INTEL_INFO(dev)->gen == 9)
2531 #define RENDER_RING (1<<RCS)
2532 #define BSD_RING (1<<VCS)
2533 #define BLT_RING (1<<BCS)
2534 #define VEBOX_RING (1<<VECS)
2535 #define BSD2_RING (1<<VCS2)
2536 #define HAS_BSD(dev) (INTEL_INFO(dev)->ring_mask & BSD_RING)
2537 #define HAS_BSD2(dev) (INTEL_INFO(dev)->ring_mask & BSD2_RING)
2538 #define HAS_BLT(dev) (INTEL_INFO(dev)->ring_mask & BLT_RING)
2539 #define HAS_VEBOX(dev) (INTEL_INFO(dev)->ring_mask & VEBOX_RING)
2540 #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc)
2541 #define HAS_WT(dev) ((IS_HASWELL(dev) || IS_BROADWELL(dev)) && \
2542 __I915__(dev)->ellc_size)
2543 #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
2545 #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6)
2546 #define HAS_LOGICAL_RING_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 8)
2547 #define USES_PPGTT(dev) (i915.enable_ppgtt)
2548 #define USES_FULL_PPGTT(dev) (i915.enable_ppgtt == 2)
2550 #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
2551 #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
2553 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
2554 #define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev))
2556 * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts
2557 * even when in MSI mode. This results in spurious interrupt warnings if the
2558 * legacy irq no. is shared with another device. The kernel then disables that
2559 * interrupt source and so prevents the other device from working properly.
2561 #define HAS_AUX_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
2562 #define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
2564 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
2565 * rows, which changed the alignment requirements and fence programming.
2567 #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
2569 #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
2570 #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
2572 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
2573 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
2574 #define HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
2576 #define HAS_IPS(dev) (IS_HSW_ULT(dev) || IS_BROADWELL(dev))
2578 #define HAS_DP_MST(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev) || \
2579 INTEL_INFO(dev)->gen >= 9)
2581 #define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi)
2582 #define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg)
2583 #define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev) || \
2584 IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev) || \
2586 #define HAS_RUNTIME_PM(dev) (IS_GEN6(dev) || IS_HASWELL(dev) || \
2587 IS_BROADWELL(dev) || IS_VALLEYVIEW(dev) || \
2589 #define HAS_RC6(dev) (INTEL_INFO(dev)->gen >= 6)
2590 #define HAS_RC6p(dev) (INTEL_INFO(dev)->gen == 6 || IS_IVYBRIDGE(dev))
2592 #define HAS_CSR(dev) (IS_SKYLAKE(dev))
2594 #define HAS_RESOURCE_STREAMER(dev) (IS_HASWELL(dev) || \
2595 INTEL_INFO(dev)->gen >= 8)
2597 #define HAS_CORE_RING_FREQ(dev) (INTEL_INFO(dev)->gen >= 6 && \
2598 !IS_VALLEYVIEW(dev) && !IS_BROXTON(dev))
2600 #define INTEL_PCH_DEVICE_ID_MASK 0xff00
2601 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
2602 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
2603 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
2604 #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
2605 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
2606 #define INTEL_PCH_SPT_DEVICE_ID_TYPE 0xA100
2607 #define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE 0x9D00
2609 #define INTEL_PCH_TYPE(dev) (__I915__(dev)->pch_type)
2610 #define HAS_PCH_SPT(dev) (INTEL_PCH_TYPE(dev) == PCH_SPT)
2611 #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
2612 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
2613 #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
2614 #define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)
2615 #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
2617 #define HAS_GMCH_DISPLAY(dev) (INTEL_INFO(dev)->gen < 5 || IS_VALLEYVIEW(dev))
2619 /* DPF == dynamic parity feature */
2620 #define HAS_L3_DPF(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
2621 #define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev))
2623 #define GT_FREQUENCY_MULTIPLIER 50
2624 #define GEN9_FREQ_SCALER 3
2626 #include "i915_trace.h"
2628 extern const struct drm_ioctl_desc i915_ioctls
[];
2629 extern int i915_max_ioctl
;
2631 extern int i915_suspend_legacy(device_t kdev
);
2632 extern int i915_resume_legacy(struct drm_device
*dev
);
2635 struct i915_params
{
2637 int panel_ignore_lid
;
2639 int lvds_channel_mode
;
2641 int vbt_sdvo_panel_type
;
2645 int enable_execlists
;
2647 unsigned int preliminary_hw_support
;
2648 int disable_power_well
;
2650 int invert_brightness
;
2651 int enable_cmd_parser
;
2652 /* leave bools at the end to not create holes */
2653 bool enable_hangcheck
;
2655 bool prefault_disable
;
2656 bool load_detect_test
;
2658 bool disable_display
;
2659 bool disable_vtd_wa
;
2660 bool enable_guc_submission
;
2664 bool verbose_state_checks
;
2667 extern struct i915_params i915 __read_mostly
;
2670 extern int i915_driver_load(struct drm_device
*, unsigned long flags
);
2671 extern int i915_driver_unload(struct drm_device
*);
2672 extern int i915_driver_open(struct drm_device
*dev
, struct drm_file
*file
);
2673 extern void i915_driver_lastclose(struct drm_device
* dev
);
2674 extern void i915_driver_preclose(struct drm_device
*dev
,
2675 struct drm_file
*file
);
2676 extern void i915_driver_postclose(struct drm_device
*dev
,
2677 struct drm_file
*file
);
2678 #ifdef CONFIG_COMPAT
2679 extern long i915_compat_ioctl(struct file
*filp
, unsigned int cmd
,
2682 extern int intel_gpu_reset(struct drm_device
*dev
);
2683 extern bool intel_has_gpu_reset(struct drm_device
*dev
);
2684 extern int i915_reset(struct drm_device
*dev
);
2685 extern unsigned long i915_chipset_val(struct drm_i915_private
*dev_priv
);
2686 extern unsigned long i915_mch_val(struct drm_i915_private
*dev_priv
);
2687 extern unsigned long i915_gfx_val(struct drm_i915_private
*dev_priv
);
2688 extern void i915_update_gfx_val(struct drm_i915_private
*dev_priv
);
2689 int vlv_force_gfx_clock(struct drm_i915_private
*dev_priv
, bool on
);
2690 void i915_firmware_load_error_print(const char *fw_path
, int err
);
2692 /* intel_hotplug.c */
2693 void intel_hpd_irq_handler(struct drm_device
*dev
, u32 pin_mask
, u32 long_mask
);
2694 void intel_hpd_init(struct drm_i915_private
*dev_priv
);
2695 void intel_hpd_init_work(struct drm_i915_private
*dev_priv
);
2696 void intel_hpd_cancel_work(struct drm_i915_private
*dev_priv
);
2697 bool intel_hpd_pin_to_port(enum hpd_pin pin
, enum port
*port
);
2700 void i915_queue_hangcheck(struct drm_device
*dev
);
2702 void i915_handle_error(struct drm_device
*dev
, bool wedged
,
2703 const char *fmt
, ...);
2705 extern void intel_irq_init(struct drm_i915_private
*dev_priv
);
2706 int intel_irq_install(struct drm_i915_private
*dev_priv
);
2707 void intel_irq_uninstall(struct drm_i915_private
*dev_priv
);
2709 extern void intel_uncore_sanitize(struct drm_device
*dev
);
2710 extern void intel_uncore_early_sanitize(struct drm_device
*dev
,
2711 bool restore_forcewake
);
2712 extern void intel_uncore_init(struct drm_device
*dev
);
2713 extern void intel_uncore_check_errors(struct drm_device
*dev
);
2714 extern void intel_uncore_fini(struct drm_device
*dev
);
2715 extern void intel_uncore_forcewake_reset(struct drm_device
*dev
, bool restore
);
2716 const char *intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id
);
2717 void intel_uncore_forcewake_get(struct drm_i915_private
*dev_priv
,
2718 enum forcewake_domains domains
);
2719 void intel_uncore_forcewake_put(struct drm_i915_private
*dev_priv
,
2720 enum forcewake_domains domains
);
2721 /* Like above but the caller must manage the uncore.lock itself.
2722 * Must be used with I915_READ_FW and friends.
2724 void intel_uncore_forcewake_get__locked(struct drm_i915_private
*dev_priv
,
2725 enum forcewake_domains domains
);
2726 void intel_uncore_forcewake_put__locked(struct drm_i915_private
*dev_priv
,
2727 enum forcewake_domains domains
);
2728 void assert_forcewakes_inactive(struct drm_i915_private
*dev_priv
);
2729 static inline bool intel_vgpu_active(struct drm_device
*dev
)
2731 return to_i915(dev
)->vgpu
.active
;
2735 i915_enable_pipestat(struct drm_i915_private
*dev_priv
, enum i915_pipe pipe
,
2739 i915_disable_pipestat(struct drm_i915_private
*dev_priv
, enum i915_pipe pipe
,
2742 void valleyview_enable_display_irqs(struct drm_i915_private
*dev_priv
);
2743 void valleyview_disable_display_irqs(struct drm_i915_private
*dev_priv
);
2745 ironlake_enable_display_irq(struct drm_i915_private
*dev_priv
, u32 mask
);
2747 ironlake_disable_display_irq(struct drm_i915_private
*dev_priv
, u32 mask
);
2748 void ibx_display_interrupt_update(struct drm_i915_private
*dev_priv
,
2749 uint32_t interrupt_mask
,
2750 uint32_t enabled_irq_mask
);
2751 #define ibx_enable_display_interrupt(dev_priv, bits) \
2752 ibx_display_interrupt_update((dev_priv), (bits), (bits))
2753 #define ibx_disable_display_interrupt(dev_priv, bits) \
2754 ibx_display_interrupt_update((dev_priv), (bits), 0)
2757 int i915_gem_create_ioctl(struct drm_device
*dev
, void *data
,
2758 struct drm_file
*file_priv
);
2759 int i915_gem_pread_ioctl(struct drm_device
*dev
, void *data
,
2760 struct drm_file
*file_priv
);
2761 int i915_gem_pwrite_ioctl(struct drm_device
*dev
, void *data
,
2762 struct drm_file
*file_priv
);
2763 int i915_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
2764 struct drm_file
*file_priv
);
2765 int i915_gem_mmap_gtt_ioctl(struct drm_device
*dev
, void *data
,
2766 struct drm_file
*file_priv
);
2767 int i915_gem_set_domain_ioctl(struct drm_device
*dev
, void *data
,
2768 struct drm_file
*file_priv
);
2769 int i915_gem_sw_finish_ioctl(struct drm_device
*dev
, void *data
,
2770 struct drm_file
*file_priv
);
2771 void i915_gem_execbuffer_move_to_active(struct list_head
*vmas
,
2772 struct drm_i915_gem_request
*req
);
2773 void i915_gem_execbuffer_retire_commands(struct i915_execbuffer_params
*params
);
2774 int i915_gem_ringbuffer_submission(struct i915_execbuffer_params
*params
,
2775 struct drm_i915_gem_execbuffer2
*args
,
2776 struct list_head
*vmas
);
2777 int i915_gem_execbuffer(struct drm_device
*dev
, void *data
,
2778 struct drm_file
*file_priv
);
2779 int i915_gem_execbuffer2(struct drm_device
*dev
, void *data
,
2780 struct drm_file
*file_priv
);
2781 int i915_gem_busy_ioctl(struct drm_device
*dev
, void *data
,
2782 struct drm_file
*file_priv
);
2783 int i915_gem_get_caching_ioctl(struct drm_device
*dev
, void *data
,
2784 struct drm_file
*file
);
2785 int i915_gem_set_caching_ioctl(struct drm_device
*dev
, void *data
,
2786 struct drm_file
*file
);
2787 int i915_gem_throttle_ioctl(struct drm_device
*dev
, void *data
,
2788 struct drm_file
*file_priv
);
2789 int i915_gem_madvise_ioctl(struct drm_device
*dev
, void *data
,
2790 struct drm_file
*file_priv
);
2791 int i915_gem_set_tiling(struct drm_device
*dev
, void *data
,
2792 struct drm_file
*file_priv
);
2793 int i915_gem_get_tiling(struct drm_device
*dev
, void *data
,
2794 struct drm_file
*file_priv
);
2795 int i915_gem_init_userptr(struct drm_device
*dev
);
2796 int i915_gem_userptr_ioctl(struct drm_device
*dev
, void *data
,
2797 struct drm_file
*file
);
2798 int i915_gem_get_aperture_ioctl(struct drm_device
*dev
, void *data
,
2799 struct drm_file
*file_priv
);
2800 int i915_gem_wait_ioctl(struct drm_device
*dev
, void *data
,
2801 struct drm_file
*file_priv
);
2802 void i915_gem_load(struct drm_device
*dev
);
2803 void *i915_gem_object_alloc(struct drm_device
*dev
);
2804 void i915_gem_object_free(struct drm_i915_gem_object
*obj
);
2805 void i915_gem_object_init(struct drm_i915_gem_object
*obj
,
2806 const struct drm_i915_gem_object_ops
*ops
);
2807 struct drm_i915_gem_object
*i915_gem_alloc_object(struct drm_device
*dev
,
2809 struct drm_i915_gem_object
*i915_gem_object_create_from_data(
2810 struct drm_device
*dev
, const void *data
, size_t size
);
2811 void i915_init_vm(struct drm_i915_private
*dev_priv
,
2812 struct i915_address_space
*vm
);
2813 void i915_gem_free_object(struct drm_gem_object
*obj
);
2814 void i915_gem_vma_destroy(struct i915_vma
*vma
);
2816 /* Flags used by pin/bind&friends. */
2817 #define PIN_MAPPABLE (1<<0)
2818 #define PIN_NONBLOCK (1<<1)
2819 #define PIN_GLOBAL (1<<2)
2820 #define PIN_OFFSET_BIAS (1<<3)
2821 #define PIN_USER (1<<4)
2822 #define PIN_UPDATE (1<<5)
2823 #define PIN_OFFSET_MASK (~4095)
2825 i915_gem_object_pin(struct drm_i915_gem_object
*obj
,
2826 struct i915_address_space
*vm
,
2830 i915_gem_object_ggtt_pin(struct drm_i915_gem_object
*obj
,
2831 const struct i915_ggtt_view
*view
,
2835 int i915_vma_bind(struct i915_vma
*vma
, enum i915_cache_level cache_level
,
2837 int __must_check
i915_vma_unbind(struct i915_vma
*vma
);
2838 int i915_gem_object_put_pages(struct drm_i915_gem_object
*obj
);
2839 void i915_gem_release_all_mmaps(struct drm_i915_private
*dev_priv
);
2840 void i915_gem_release_mmap(struct drm_i915_gem_object
*obj
);
2842 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object
*obj
,
2843 int *needs_clflush
);
2845 int __must_check
i915_gem_object_get_pages(struct drm_i915_gem_object
*obj
);
2847 static inline int __sg_page_count(struct scatterlist
*sg
)
2849 return sg
->length
>> PAGE_SHIFT
;
2852 static inline struct vm_page
*
2853 i915_gem_object_get_page(struct drm_i915_gem_object
*obj
, int n
)
2855 if (WARN_ON(n
>= obj
->base
.size
>> PAGE_SHIFT
))
2858 if (n
< obj
->get_page
.last
) {
2859 obj
->get_page
.sg
= obj
->pages
->sgl
;
2860 obj
->get_page
.last
= 0;
2863 while (obj
->get_page
.last
+ __sg_page_count(obj
->get_page
.sg
) <= n
) {
2864 obj
->get_page
.last
+= __sg_page_count(obj
->get_page
.sg
++);
2866 if (unlikely(sg_is_chain(obj
->get_page
.sg
)))
2867 obj
->get_page
.sg
= sg_chain_ptr(obj
->get_page
.sg
);
2871 return nth_page(sg_page(obj
->get_page
.sg
), n
- obj
->get_page
.last
);
2874 static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object
*obj
)
2876 BUG_ON(obj
->pages
== NULL
);
2877 obj
->pages_pin_count
++;
2879 static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object
*obj
)
2881 BUG_ON(obj
->pages_pin_count
== 0);
2882 obj
->pages_pin_count
--;
2885 int __must_check
i915_mutex_lock_interruptible(struct drm_device
*dev
);
2886 int i915_gem_object_sync(struct drm_i915_gem_object
*obj
,
2887 struct intel_engine_cs
*to
,
2888 struct drm_i915_gem_request
**to_req
);
2889 void i915_vma_move_to_active(struct i915_vma
*vma
,
2890 struct drm_i915_gem_request
*req
);
2891 int i915_gem_dumb_create(struct drm_file
*file_priv
,
2892 struct drm_device
*dev
,
2893 struct drm_mode_create_dumb
*args
);
2894 int i915_gem_mmap_gtt(struct drm_file
*file_priv
, struct drm_device
*dev
,
2895 uint32_t handle
, uint64_t *offset
);
2897 * Returns true if seq1 is later than seq2.
2900 i915_seqno_passed(uint32_t seq1
, uint32_t seq2
)
2902 return (int32_t)(seq1
- seq2
) >= 0;
2905 static inline bool i915_gem_request_completed(struct drm_i915_gem_request
*req
,
2906 bool lazy_coherency
)
2910 BUG_ON(req
== NULL
);
2912 seqno
= req
->ring
->get_seqno(req
->ring
, lazy_coherency
);
2914 return i915_seqno_passed(seqno
, req
->seqno
);
2917 int __must_check
i915_gem_get_seqno(struct drm_device
*dev
, u32
*seqno
);
2918 int __must_check
i915_gem_set_seqno(struct drm_device
*dev
, u32 seqno
);
2920 struct drm_i915_gem_request
*
2921 i915_gem_find_active_request(struct intel_engine_cs
*ring
);
2923 bool i915_gem_retire_requests(struct drm_device
*dev
);
2924 void i915_gem_retire_requests_ring(struct intel_engine_cs
*ring
);
2925 int __must_check
i915_gem_check_wedge(struct i915_gpu_error
*error
,
2926 bool interruptible
);
2928 static inline bool i915_reset_in_progress(struct i915_gpu_error
*error
)
2930 return unlikely(atomic_read(&error
->reset_counter
)
2931 & (I915_RESET_IN_PROGRESS_FLAG
| I915_WEDGED
));
2934 static inline bool i915_terminally_wedged(struct i915_gpu_error
*error
)
2936 return atomic_read(&error
->reset_counter
) & I915_WEDGED
;
2939 static inline u32
i915_reset_count(struct i915_gpu_error
*error
)
2941 return ((atomic_read(&error
->reset_counter
) & ~I915_WEDGED
) + 1) / 2;
2944 static inline bool i915_stop_ring_allow_ban(struct drm_i915_private
*dev_priv
)
2946 return dev_priv
->gpu_error
.stop_rings
== 0 ||
2947 dev_priv
->gpu_error
.stop_rings
& I915_STOP_RING_ALLOW_BAN
;
2950 static inline bool i915_stop_ring_allow_warn(struct drm_i915_private
*dev_priv
)
2952 return dev_priv
->gpu_error
.stop_rings
== 0 ||
2953 dev_priv
->gpu_error
.stop_rings
& I915_STOP_RING_ALLOW_WARN
;
2956 void i915_gem_reset(struct drm_device
*dev
);
2957 bool i915_gem_clflush_object(struct drm_i915_gem_object
*obj
, bool force
);
2958 int __must_check
i915_gem_init(struct drm_device
*dev
);
2959 int i915_gem_init_rings(struct drm_device
*dev
);
2960 int __must_check
i915_gem_init_hw(struct drm_device
*dev
);
2961 int i915_gem_l3_remap(struct drm_i915_gem_request
*req
, int slice
);
2962 void i915_gem_init_swizzling(struct drm_device
*dev
);
2963 void i915_gem_cleanup_ringbuffer(struct drm_device
*dev
);
2964 int __must_check
i915_gpu_idle(struct drm_device
*dev
);
2965 int __must_check
i915_gem_suspend(struct drm_device
*dev
);
2966 void __i915_add_request(struct drm_i915_gem_request
*req
,
2967 struct drm_i915_gem_object
*batch_obj
,
2969 #define i915_add_request(req) \
2970 __i915_add_request(req, NULL, true)
2971 #define i915_add_request_no_flush(req) \
2972 __i915_add_request(req, NULL, false)
2973 int __i915_wait_request(struct drm_i915_gem_request
*req
,
2974 unsigned reset_counter
,
2977 struct intel_rps_client
*rps
);
2978 int __must_check
i915_wait_request(struct drm_i915_gem_request
*req
);
2979 int i915_gem_fault(vm_object_t vm_obj
, vm_ooffset_t offset
, int prot
, vm_page_t
*mres
);
2981 i915_gem_object_wait_rendering(struct drm_i915_gem_object
*obj
,
2984 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object
*obj
,
2987 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object
*obj
, bool write
);
2989 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object
*obj
,
2991 struct intel_engine_cs
*pipelined
,
2992 struct drm_i915_gem_request
**pipelined_request
,
2993 const struct i915_ggtt_view
*view
);
2994 void i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object
*obj
,
2995 const struct i915_ggtt_view
*view
);
2996 int i915_gem_object_attach_phys(struct drm_i915_gem_object
*obj
,
2998 int i915_gem_open(struct drm_device
*dev
, struct drm_file
*file
);
2999 void i915_gem_release(struct drm_device
*dev
, struct drm_file
*file
);
3002 i915_gem_get_gtt_size(struct drm_device
*dev
, uint32_t size
, int tiling_mode
);
3004 i915_gem_get_gtt_alignment(struct drm_device
*dev
, uint32_t size
,
3005 int tiling_mode
, bool fenced
);
3007 int i915_gem_object_set_cache_level(struct drm_i915_gem_object
*obj
,
3008 enum i915_cache_level cache_level
);
3011 struct drm_gem_object
*i915_gem_prime_import(struct drm_device
*dev
,
3012 struct dma_buf
*dma_buf
);
3014 struct dma_buf
*i915_gem_prime_export(struct drm_device
*dev
,
3015 struct drm_gem_object
*gem_obj
, int flags
);
3019 i915_gem_obj_ggtt_offset_view(struct drm_i915_gem_object
*o
,
3020 const struct i915_ggtt_view
*view
);
3022 i915_gem_obj_offset(struct drm_i915_gem_object
*o
,
3023 struct i915_address_space
*vm
);
3024 static inline unsigned long
3025 i915_gem_obj_ggtt_offset(struct drm_i915_gem_object
*o
)
3027 return i915_gem_obj_ggtt_offset_view(o
, &i915_ggtt_view_normal
);
3030 bool i915_gem_obj_bound_any(struct drm_i915_gem_object
*o
);
3031 bool i915_gem_obj_ggtt_bound_view(struct drm_i915_gem_object
*o
,
3032 const struct i915_ggtt_view
*view
);
3033 bool i915_gem_obj_bound(struct drm_i915_gem_object
*o
,
3034 struct i915_address_space
*vm
);
3036 unsigned long i915_gem_obj_size(struct drm_i915_gem_object
*o
,
3037 struct i915_address_space
*vm
);
3039 i915_gem_obj_to_vma(struct drm_i915_gem_object
*obj
,
3040 struct i915_address_space
*vm
);
3042 i915_gem_obj_to_ggtt_view(struct drm_i915_gem_object
*obj
,
3043 const struct i915_ggtt_view
*view
);
3046 i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object
*obj
,
3047 struct i915_address_space
*vm
);
3049 i915_gem_obj_lookup_or_create_ggtt_vma(struct drm_i915_gem_object
*obj
,
3050 const struct i915_ggtt_view
*view
);
3052 static inline struct i915_vma
*
3053 i915_gem_obj_to_ggtt(struct drm_i915_gem_object
*obj
)
3055 return i915_gem_obj_to_ggtt_view(obj
, &i915_ggtt_view_normal
);
3057 bool i915_gem_obj_is_pinned(struct drm_i915_gem_object
*obj
);
3059 /* Some GGTT VM helpers */
3060 #define i915_obj_to_ggtt(obj) \
3061 (&((struct drm_i915_private *)(obj)->base.dev->dev_private)->gtt.base)
3062 static inline bool i915_is_ggtt(struct i915_address_space
*vm
)
3064 struct i915_address_space
*ggtt
=
3065 &((struct drm_i915_private
*)(vm
)->dev
->dev_private
)->gtt
.base
;
3069 static inline struct i915_hw_ppgtt
*
3070 i915_vm_to_ppgtt(struct i915_address_space
*vm
)
3072 WARN_ON(i915_is_ggtt(vm
));
3074 return container_of(vm
, struct i915_hw_ppgtt
, base
);
3078 static inline bool i915_gem_obj_ggtt_bound(struct drm_i915_gem_object
*obj
)
3080 return i915_gem_obj_ggtt_bound_view(obj
, &i915_ggtt_view_normal
);
3083 static inline unsigned long
3084 i915_gem_obj_ggtt_size(struct drm_i915_gem_object
*obj
)
3086 return i915_gem_obj_size(obj
, i915_obj_to_ggtt(obj
));
3089 static inline int __must_check
3090 i915_gem_obj_ggtt_pin(struct drm_i915_gem_object
*obj
,
3094 return i915_gem_object_pin(obj
, i915_obj_to_ggtt(obj
),
3095 alignment
, flags
| PIN_GLOBAL
);
3099 i915_gem_object_ggtt_unbind(struct drm_i915_gem_object
*obj
)
3101 return i915_vma_unbind(i915_gem_obj_to_ggtt(obj
));
3104 void i915_gem_object_ggtt_unpin_view(struct drm_i915_gem_object
*obj
,
3105 const struct i915_ggtt_view
*view
);
3107 i915_gem_object_ggtt_unpin(struct drm_i915_gem_object
*obj
)
3109 i915_gem_object_ggtt_unpin_view(obj
, &i915_ggtt_view_normal
);
3112 /* i915_gem_fence.c */
3113 int __must_check
i915_gem_object_get_fence(struct drm_i915_gem_object
*obj
);
3114 int __must_check
i915_gem_object_put_fence(struct drm_i915_gem_object
*obj
);
3116 bool i915_gem_object_pin_fence(struct drm_i915_gem_object
*obj
);
3117 void i915_gem_object_unpin_fence(struct drm_i915_gem_object
*obj
);
3119 void i915_gem_restore_fences(struct drm_device
*dev
);
3121 void i915_gem_detect_bit_6_swizzle(struct drm_device
*dev
);
3122 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object
*obj
);
3123 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object
*obj
);
3125 /* i915_gem_context.c */
3126 int __must_check
i915_gem_context_init(struct drm_device
*dev
);
3127 void i915_gem_context_fini(struct drm_device
*dev
);
3128 void i915_gem_context_reset(struct drm_device
*dev
);
3129 int i915_gem_context_open(struct drm_device
*dev
, struct drm_file
*file
);
3130 int i915_gem_context_enable(struct drm_i915_gem_request
*req
);
3131 void i915_gem_context_close(struct drm_device
*dev
, struct drm_file
*file
);
3132 int i915_switch_context(struct drm_i915_gem_request
*req
);
3133 struct intel_context
*
3134 i915_gem_context_get(struct drm_i915_file_private
*file_priv
, u32 id
);
3135 void i915_gem_context_free(struct kref
*ctx_ref
);
3136 struct drm_i915_gem_object
*
3137 i915_gem_alloc_context_obj(struct drm_device
*dev
, size_t size
);
3138 static inline void i915_gem_context_reference(struct intel_context
*ctx
)
3140 kref_get(&ctx
->ref
);
3143 static inline void i915_gem_context_unreference(struct intel_context
*ctx
)
3145 kref_put(&ctx
->ref
, i915_gem_context_free
);
3148 static inline bool i915_gem_context_is_default(const struct intel_context
*c
)
3150 return c
->user_handle
== DEFAULT_CONTEXT_HANDLE
;
3153 int i915_gem_context_create_ioctl(struct drm_device
*dev
, void *data
,
3154 struct drm_file
*file
);
3155 int i915_gem_context_destroy_ioctl(struct drm_device
*dev
, void *data
,
3156 struct drm_file
*file
);
3157 int i915_gem_context_getparam_ioctl(struct drm_device
*dev
, void *data
,
3158 struct drm_file
*file_priv
);
3159 int i915_gem_context_setparam_ioctl(struct drm_device
*dev
, void *data
,
3160 struct drm_file
*file_priv
);
3162 /* i915_gem_evict.c */
3163 int __must_check
i915_gem_evict_something(struct drm_device
*dev
,
3164 struct i915_address_space
*vm
,
3167 unsigned cache_level
,
3168 unsigned long start
,
3171 int i915_gem_evict_vm(struct i915_address_space
*vm
, bool do_idle
);
3172 int i915_gem_evict_everything(struct drm_device
*dev
);
3174 /* belongs in i915_gem_gtt.h */
3175 static inline void i915_gem_chipset_flush(struct drm_device
*dev
)
3177 if (INTEL_INFO(dev
)->gen
< 6)
3178 intel_gtt_chipset_flush();
3181 /* i915_gem_stolen.c */
3182 int i915_gem_stolen_insert_node(struct drm_i915_private
*dev_priv
,
3183 struct drm_mm_node
*node
, u64 size
,
3184 unsigned alignment
);
3185 void i915_gem_stolen_remove_node(struct drm_i915_private
*dev_priv
,
3186 struct drm_mm_node
*node
);
3187 int i915_gem_init_stolen(struct drm_device
*dev
);
3188 void i915_gem_cleanup_stolen(struct drm_device
*dev
);
3189 struct drm_i915_gem_object
*
3190 i915_gem_object_create_stolen(struct drm_device
*dev
, u32 size
);
3191 struct drm_i915_gem_object
*
3192 i915_gem_object_create_stolen_for_preallocated(struct drm_device
*dev
,
3197 /* i915_gem_shrinker.c */
3198 unsigned long i915_gem_shrink(struct drm_i915_private
*dev_priv
,
3201 #define I915_SHRINK_PURGEABLE 0x1
3202 #define I915_SHRINK_UNBOUND 0x2
3203 #define I915_SHRINK_BOUND 0x4
3204 unsigned long i915_gem_shrink_all(struct drm_i915_private
*dev_priv
);
3205 void i915_gem_shrinker_init(struct drm_i915_private
*dev_priv
);
3208 /* i915_gem_tiling.c */
3209 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object
*obj
)
3211 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
3213 return dev_priv
->mm
.bit_6_swizzle_x
== I915_BIT_6_SWIZZLE_9_10_17
&&
3214 obj
->tiling_mode
!= I915_TILING_NONE
;
3217 /* i915_gem_debug.c */
3219 int i915_verify_lists(struct drm_device
*dev
);
3221 #define i915_verify_lists(dev) 0
3224 /* i915_debugfs.c */
3225 int i915_debugfs_init(struct drm_minor
*minor
);
3226 void i915_debugfs_cleanup(struct drm_minor
*minor
);
3227 #ifdef CONFIG_DEBUG_FS
3228 int i915_debugfs_connector_add(struct drm_connector
*connector
);
3229 void intel_display_crc_init(struct drm_device
*dev
);
3231 static inline int i915_debugfs_connector_add(struct drm_connector
*connector
)
3233 static inline void intel_display_crc_init(struct drm_device
*dev
) {}
3236 /* i915_gpu_error.c */
3238 void i915_error_printf(struct drm_i915_error_state_buf
*e
, const char *f
, ...);
3239 int i915_error_state_to_str(struct drm_i915_error_state_buf
*estr
,
3240 const struct i915_error_state_file_priv
*error
);
3241 int i915_error_state_buf_init(struct drm_i915_error_state_buf
*eb
,
3242 struct drm_i915_private
*i915
,
3243 size_t count
, loff_t pos
);
3244 static inline void i915_error_state_buf_release(
3245 struct drm_i915_error_state_buf
*eb
)
3249 void i915_capture_error_state(struct drm_device
*dev
, bool wedge
,
3250 const char *error_msg
);
3251 void i915_error_state_get(struct drm_device
*dev
,
3252 struct i915_error_state_file_priv
*error_priv
);
3253 void i915_error_state_put(struct i915_error_state_file_priv
*error_priv
);
3254 void i915_destroy_error_state(struct drm_device
*dev
);
3256 void i915_get_extra_instdone(struct drm_device
*dev
, uint32_t *instdone
);
3257 const char *i915_cache_level_str(struct drm_i915_private
*i915
, int type
);
3259 /* i915_cmd_parser.c */
3260 int i915_cmd_parser_get_version(void);
3261 int i915_cmd_parser_init_ring(struct intel_engine_cs
*ring
);
3262 void i915_cmd_parser_fini_ring(struct intel_engine_cs
*ring
);
3263 bool i915_needs_cmd_parser(struct intel_engine_cs
*ring
);
3264 int i915_parse_cmds(struct intel_engine_cs
*ring
,
3265 struct drm_i915_gem_object
*batch_obj
,
3266 struct drm_i915_gem_object
*shadow_batch_obj
,
3267 u32 batch_start_offset
,
3271 /* i915_suspend.c */
3272 extern int i915_save_state(struct drm_device
*dev
);
3273 extern int i915_restore_state(struct drm_device
*dev
);
3276 void i915_setup_sysfs(struct drm_device
*dev_priv
);
3277 void i915_teardown_sysfs(struct drm_device
*dev_priv
);
3280 extern int intel_setup_gmbus(struct drm_device
*dev
);
3281 extern void intel_teardown_gmbus(struct drm_device
*dev
);
3282 extern bool intel_gmbus_is_valid_pin(struct drm_i915_private
*dev_priv
,
3285 extern struct i2c_adapter
*
3286 intel_gmbus_get_adapter(struct drm_i915_private
*dev_priv
, unsigned int pin
);
3287 extern void intel_gmbus_set_speed(struct i2c_adapter
*adapter
, int speed
);
3288 extern void intel_gmbus_force_bit(struct i2c_adapter
*adapter
, bool force_bit
);
3289 static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter
*adapter
)
3291 struct intel_iic_softc
*sc
;
3292 sc
= device_get_softc(device_get_parent(adapter
));
3294 return sc
->force_bit_dev
;
3296 extern void intel_i2c_reset(struct drm_device
*dev
);
3298 /* intel_opregion.c */
3300 extern int intel_opregion_setup(struct drm_device
*dev
);
3301 extern void intel_opregion_init(struct drm_device
*dev
);
3302 extern void intel_opregion_fini(struct drm_device
*dev
);
3303 extern void intel_opregion_asle_intr(struct drm_device
*dev
);
3304 extern int intel_opregion_notify_encoder(struct intel_encoder
*intel_encoder
,
3306 extern int intel_opregion_notify_adapter(struct drm_device
*dev
,
3309 static inline int intel_opregion_setup(struct drm_device
*dev
) { return 0; }
3310 static inline void intel_opregion_init(struct drm_device
*dev
) { return; }
3311 static inline void intel_opregion_fini(struct drm_device
*dev
) { return; }
3312 static inline void intel_opregion_asle_intr(struct drm_device
*dev
) { return; }
3314 intel_opregion_notify_encoder(struct intel_encoder
*intel_encoder
, bool enable
)
3319 intel_opregion_notify_adapter(struct drm_device
*dev
, pci_power_t state
)
3327 extern void intel_register_dsm_handler(void);
3328 extern void intel_unregister_dsm_handler(void);
3330 static inline void intel_register_dsm_handler(void) { return; }
3331 static inline void intel_unregister_dsm_handler(void) { return; }
3332 #endif /* CONFIG_ACPI */
3335 extern void intel_modeset_init_hw(struct drm_device
*dev
);
3336 extern void intel_modeset_init(struct drm_device
*dev
);
3337 extern void intel_modeset_gem_init(struct drm_device
*dev
);
3338 extern void intel_modeset_cleanup(struct drm_device
*dev
);
3339 extern void intel_connector_unregister(struct intel_connector
*);
3340 extern int intel_modeset_vga_set_state(struct drm_device
*dev
, bool state
);
3341 extern void intel_display_resume(struct drm_device
*dev
);
3342 extern void i915_redisable_vga(struct drm_device
*dev
);
3343 extern void i915_redisable_vga_power_on(struct drm_device
*dev
);
3344 extern bool ironlake_set_drps(struct drm_device
*dev
, u8 val
);
3345 extern void intel_init_pch_refclk(struct drm_device
*dev
);
3346 extern void intel_set_rps(struct drm_device
*dev
, u8 val
);
3347 extern void intel_set_memory_cxsr(struct drm_i915_private
*dev_priv
,
3349 extern void intel_detect_pch(struct drm_device
*dev
);
3350 extern int intel_trans_dp_port_sel(struct drm_crtc
*crtc
);
3351 extern int intel_enable_rc6(const struct drm_device
*dev
);
3353 extern bool i915_semaphore_is_enabled(struct drm_device
*dev
);
3354 int i915_reg_read_ioctl(struct drm_device
*dev
, void *data
,
3355 struct drm_file
*file
);
3356 int i915_get_reset_stats_ioctl(struct drm_device
*dev
, void *data
,
3357 struct drm_file
*file
);
3359 struct intel_device_info
*i915_get_device_id(int device
);
3362 extern struct intel_overlay_error_state
*intel_overlay_capture_error_state(struct drm_device
*dev
);
3363 extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf
*e
,
3364 struct intel_overlay_error_state
*error
);
3366 extern struct intel_display_error_state
*intel_display_capture_error_state(struct drm_device
*dev
);
3367 extern void intel_display_print_error_state(struct drm_i915_error_state_buf
*e
,
3368 struct drm_device
*dev
,
3369 struct intel_display_error_state
*error
);
3371 int sandybridge_pcode_read(struct drm_i915_private
*dev_priv
, u32 mbox
, u32
*val
);
3372 int sandybridge_pcode_write(struct drm_i915_private
*dev_priv
, u32 mbox
, u32 val
);
3374 /* intel_sideband.c */
3375 u32
vlv_punit_read(struct drm_i915_private
*dev_priv
, u32 addr
);
3376 void vlv_punit_write(struct drm_i915_private
*dev_priv
, u32 addr
, u32 val
);
3377 u32
vlv_nc_read(struct drm_i915_private
*dev_priv
, u8 addr
);
3378 u32
vlv_gpio_nc_read(struct drm_i915_private
*dev_priv
, u32 reg
);
3379 void vlv_gpio_nc_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
3380 u32
vlv_cck_read(struct drm_i915_private
*dev_priv
, u32 reg
);
3381 void vlv_cck_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
3382 u32
vlv_ccu_read(struct drm_i915_private
*dev_priv
, u32 reg
);
3383 void vlv_ccu_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
3384 u32
vlv_bunit_read(struct drm_i915_private
*dev_priv
, u32 reg
);
3385 void vlv_bunit_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
3386 u32
vlv_gps_core_read(struct drm_i915_private
*dev_priv
, u32 reg
);
3387 void vlv_gps_core_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
3388 u32
vlv_dpio_read(struct drm_i915_private
*dev_priv
, enum i915_pipe pipe
, int reg
);
3389 void vlv_dpio_write(struct drm_i915_private
*dev_priv
, enum i915_pipe pipe
, int reg
, u32 val
);
3390 u32
intel_sbi_read(struct drm_i915_private
*dev_priv
, u16 reg
,
3391 enum intel_sbi_destination destination
);
3392 void intel_sbi_write(struct drm_i915_private
*dev_priv
, u16 reg
, u32 value
,
3393 enum intel_sbi_destination destination
);
3394 u32
vlv_flisdsi_read(struct drm_i915_private
*dev_priv
, u32 reg
);
3395 void vlv_flisdsi_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
3397 int intel_gpu_freq(struct drm_i915_private
*dev_priv
, int val
);
3398 int intel_freq_opcode(struct drm_i915_private
*dev_priv
, int val
);
3400 #define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
3401 #define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)
3403 #define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
3404 #define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
3405 #define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
3406 #define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)
3408 #define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
3409 #define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
3410 #define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
3411 #define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)
3413 /* Be very careful with read/write 64-bit values. On 32-bit machines, they
3414 * will be implemented using 2 32-bit writes in an arbitrary order with
3415 * an arbitrary delay between them. This can cause the hardware to
3416 * act upon the intermediate value, possibly leading to corruption and
3417 * machine death. You have been warned.
3419 #define I915_WRITE64(reg, val) dev_priv->uncore.funcs.mmio_writeq(dev_priv, (reg), (val), true)
3420 #define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
3422 #define I915_READ64_2x32(lower_reg, upper_reg) ({ \
3423 u32 upper, lower, old_upper, loop = 0; \
3424 upper = I915_READ(upper_reg); \
3426 old_upper = upper; \
3427 lower = I915_READ(lower_reg); \
3428 upper = I915_READ(upper_reg); \
3429 } while (upper != old_upper && loop++ < 2); \
3430 (u64)upper << 32 | lower; })
3432 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
3433 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
3435 /* These are untraced mmio-accessors that are only valid to be used inside
3436 * criticial sections inside IRQ handlers where forcewake is explicitly
3438 * Think twice, and think again, before using these.
3439 * Note: Should only be used between intel_uncore_forcewake_irqlock() and
3440 * intel_uncore_forcewake_irqunlock().
3442 #define I915_READ_FW(reg__) readl(dev_priv->regs + (reg__))
3443 #define I915_WRITE_FW(reg__, val__) writel(val__, dev_priv->regs + (reg__))
3444 #define POSTING_READ_FW(reg__) (void)I915_READ_FW(reg__)
3446 /* "Broadcast RGB" property */
3447 #define INTEL_BROADCAST_RGB_AUTO 0
3448 #define INTEL_BROADCAST_RGB_FULL 1
3449 #define INTEL_BROADCAST_RGB_LIMITED 2
3451 static inline uint32_t i915_vgacntrl_reg(struct drm_device
*dev
)
3453 if (IS_VALLEYVIEW(dev
))
3454 return VLV_VGACNTRL
;
3455 else if (INTEL_INFO(dev
)->gen
>= 5)
3456 return CPU_VGACNTRL
;
3461 static inline void __user
*to_user_ptr(u64 address
)
3463 return (void __user
*)(uintptr_t)address
;
3466 static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m
)
3468 unsigned long j
= msecs_to_jiffies(m
);
3470 return min_t(unsigned long, MAX_JIFFY_OFFSET
, j
+ 1);
3473 static inline unsigned long nsecs_to_jiffies_timeout(const u64 n
)
3475 return min_t(u64
, MAX_JIFFY_OFFSET
, nsecs_to_jiffies64(n
) + 1);
3478 static inline unsigned long
3479 timespec_to_jiffies_timeout(const struct timespec
*value
)
3481 unsigned long j
= timespec_to_jiffies(value
);
3483 return min_t(unsigned long, MAX_JIFFY_OFFSET
, j
+ 1);
3487 * If you need to wait X milliseconds between events A and B, but event B
3488 * doesn't happen exactly after event A, you record the timestamp (jiffies) of
3489 * when event A happened, then just before event B you call this function and
3490 * pass the timestamp as the first argument, and X as the second argument.
3493 wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies
, int to_wait_ms
)
3495 unsigned long target_jiffies
, tmp_jiffies
, remaining_jiffies
;
3498 * Don't re-read the value of "jiffies" every time since it may change
3499 * behind our back and break the math.
3501 tmp_jiffies
= jiffies
;
3502 target_jiffies
= timestamp_jiffies
+
3503 msecs_to_jiffies_timeout(to_wait_ms
);
3505 if (time_after(target_jiffies
, tmp_jiffies
)) {
3506 remaining_jiffies
= target_jiffies
- tmp_jiffies
;
3508 while (remaining_jiffies
)
3510 schedule_timeout_uninterruptible(remaining_jiffies
);
3512 msleep(jiffies_to_msecs(remaining_jiffies
));
3517 static inline void i915_trace_irq_get(struct intel_engine_cs
*ring
,
3518 struct drm_i915_gem_request
*req
)
3520 if (ring
->trace_irq_req
== NULL
&& ring
->irq_get(ring
))
3521 i915_gem_request_assign(&ring
->trace_irq_req
, req
);