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- Store tx rate control parameters in drivers, so switching between tx rate
[dragonfly.git] / sys / dev / netif / bwi / if_bwi.c
blobfb0aa18c64a9b4259947164bd336ba7e86b0f0b0
1 /*
2 * Copyright (c) 2007 The DragonFly Project. All rights reserved.
3 *
4 * This code is derived from software contributed to The DragonFly Project
5 * by Sepherosa Ziehau <sepherosa@gmail.com>
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 *
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
16 * distribution.
17 * 3. Neither the name of The DragonFly Project nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific, prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
24 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
25 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
27 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
28 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
29 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
31 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 * SUCH DAMAGE.
33 *
34 * $DragonFly: src/sys/dev/netif/bwi/if_bwi.c,v 1.18 2008/01/15 09:01:13 sephe Exp $
35 */
36
37 #include <sys/param.h>
38 #include <sys/bitops.h>
39 #include <sys/endian.h>
40 #include <sys/kernel.h>
41 #include <sys/bus.h>
42 #include <sys/malloc.h>
43 #include <sys/proc.h>
44 #include <sys/rman.h>
45 #include <sys/serialize.h>
46 #include <sys/socket.h>
47 #include <sys/sockio.h>
48 #include <sys/sysctl.h>
49
50 #include <net/ethernet.h>
51 #include <net/if.h>
52 #include <net/bpf.h>
53 #include <net/if_arp.h>
54 #include <net/if_dl.h>
55 #include <net/if_media.h>
56 #include <net/ifq_var.h>
57
58 #include <netproto/802_11/ieee80211_radiotap.h>
59 #include <netproto/802_11/ieee80211_var.h>
60 #include <netproto/802_11/wlan_ratectl/onoe/ieee80211_onoe_param.h>
61
62 #include <bus/pci/pcireg.h>
63 #include <bus/pci/pcivar.h>
64 #include <bus/pci/pcidevs.h>
65
66 #include <dev/netif/bwi/if_bwireg.h>
67 #include <dev/netif/bwi/if_bwivar.h>
68 #include <dev/netif/bwi/bwimac.h>
69 #include <dev/netif/bwi/bwirf.h>
70
71 struct bwi_clock_freq {
72 u_int clkfreq_min;
73 u_int clkfreq_max;
74 };
75
76 struct bwi_myaddr_bssid {
77 uint8_t myaddr[IEEE80211_ADDR_LEN];
78 uint8_t bssid[IEEE80211_ADDR_LEN];
79 } __packed;
80
81 static int bwi_probe(device_t);
82 static int bwi_attach(device_t);
83 static int bwi_detach(device_t);
84 static int bwi_shutdown(device_t);
85
86 static void bwi_init(void *);
87 static int bwi_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
88 static void bwi_start(struct ifnet *);
89 static void bwi_watchdog(struct ifnet *);
90 static int bwi_newstate(struct ieee80211com *, enum ieee80211_state, int);
91 static void bwi_updateslot(struct ifnet *);
92 static int bwi_media_change(struct ifnet *);
93 static void *bwi_ratectl_attach(struct ieee80211com *, u_int);
94
95 static void bwi_next_scan(void *);
96 static void bwi_calibrate(void *);
97
98 static int bwi_stop(struct bwi_softc *);
99 static int bwi_newbuf(struct bwi_softc *, int, int);
100 static int bwi_encap(struct bwi_softc *, int, struct mbuf *,
101 struct ieee80211_node **, int);
102
103 static void bwi_init_rxdesc_ring32(struct bwi_softc *, uint32_t,
104 bus_addr_t, int, int);
105 static void bwi_reset_rx_ring32(struct bwi_softc *, uint32_t);
106
107 static int bwi_init_tx_ring32(struct bwi_softc *, int);
108 static int bwi_init_rx_ring32(struct bwi_softc *);
109 static int bwi_init_txstats32(struct bwi_softc *);
110 static void bwi_free_tx_ring32(struct bwi_softc *, int);
111 static void bwi_free_rx_ring32(struct bwi_softc *);
112 static void bwi_free_txstats32(struct bwi_softc *);
113 static void bwi_setup_rx_desc32(struct bwi_softc *, int, bus_addr_t, int);
114 static void bwi_setup_tx_desc32(struct bwi_softc *, struct bwi_ring_data *,
115 int, bus_addr_t, int);
116 static int bwi_rxeof32(struct bwi_softc *);
117 static void bwi_start_tx32(struct bwi_softc *, uint32_t, int);
118 static void bwi_txeof_status32(struct bwi_softc *);
119
120 static int bwi_init_tx_ring64(struct bwi_softc *, int);
121 static int bwi_init_rx_ring64(struct bwi_softc *);
122 static int bwi_init_txstats64(struct bwi_softc *);
123 static void bwi_free_tx_ring64(struct bwi_softc *, int);
124 static void bwi_free_rx_ring64(struct bwi_softc *);
125 static void bwi_free_txstats64(struct bwi_softc *);
126 static void bwi_setup_rx_desc64(struct bwi_softc *, int, bus_addr_t, int);
127 static void bwi_setup_tx_desc64(struct bwi_softc *, struct bwi_ring_data *,
128 int, bus_addr_t, int);
129 static int bwi_rxeof64(struct bwi_softc *);
130 static void bwi_start_tx64(struct bwi_softc *, uint32_t, int);
131 static void bwi_txeof_status64(struct bwi_softc *);
132
133 static void bwi_intr(void *);
134 static int bwi_rxeof(struct bwi_softc *, int);
135 static void _bwi_txeof(struct bwi_softc *, uint16_t, int, int);
136 static void bwi_txeof(struct bwi_softc *);
137 static void bwi_txeof_status(struct bwi_softc *, int);
138 static void bwi_enable_intrs(struct bwi_softc *, uint32_t);
139 static void bwi_disable_intrs(struct bwi_softc *, uint32_t);
140 static int bwi_calc_rssi(struct bwi_softc *, const struct bwi_rxbuf_hdr *);
141 static void bwi_rx_radiotap(struct bwi_softc *, struct mbuf *,
142 struct bwi_rxbuf_hdr *, const void *, int, int);
143
144 static int bwi_dma_alloc(struct bwi_softc *);
145 static void bwi_dma_free(struct bwi_softc *);
146 static int bwi_dma_ring_alloc(struct bwi_softc *, bus_dma_tag_t,
147 struct bwi_ring_data *, bus_size_t,
148 uint32_t);
149 static int bwi_dma_mbuf_create(struct bwi_softc *);
150 static void bwi_dma_mbuf_destroy(struct bwi_softc *, int, int);
151 static int bwi_dma_txstats_alloc(struct bwi_softc *, uint32_t, bus_size_t);
152 static void bwi_dma_txstats_free(struct bwi_softc *);
153 static void bwi_dma_ring_addr(void *, bus_dma_segment_t *, int, int);
154 static void bwi_dma_buf_addr(void *, bus_dma_segment_t *, int,
155 bus_size_t, int);
156
157 static void bwi_power_on(struct bwi_softc *, int);
158 static int bwi_power_off(struct bwi_softc *, int);
159 static int bwi_set_clock_mode(struct bwi_softc *, enum bwi_clock_mode);
160 static int bwi_set_clock_delay(struct bwi_softc *);
161 static void bwi_get_clock_freq(struct bwi_softc *, struct bwi_clock_freq *);
162 static int bwi_get_pwron_delay(struct bwi_softc *sc);
163 static void bwi_set_addr_filter(struct bwi_softc *, uint16_t,
164 const uint8_t *);
165 static void bwi_set_bssid(struct bwi_softc *, const uint8_t *);
166 static int bwi_set_chan(struct bwi_softc *, struct ieee80211_channel *);
167
168 static void bwi_get_card_flags(struct bwi_softc *);
169 static void bwi_get_eaddr(struct bwi_softc *, uint16_t, uint8_t *);
170
171 static int bwi_bus_attach(struct bwi_softc *);
172 static int bwi_bbp_attach(struct bwi_softc *);
173 static int bwi_bbp_power_on(struct bwi_softc *, enum bwi_clock_mode);
174 static void bwi_bbp_power_off(struct bwi_softc *);
175
176 static const char *bwi_regwin_name(const struct bwi_regwin *);
177 static uint32_t bwi_regwin_disable_bits(struct bwi_softc *);
178 static void bwi_regwin_info(struct bwi_softc *, uint16_t *, uint8_t *);
179 static int bwi_regwin_select(struct bwi_softc *, int);
180
181 static void bwi_led_attach(struct bwi_softc *);
182 static void bwi_led_newstate(struct bwi_softc *, enum ieee80211_state);
183 static void bwi_led_event(struct bwi_softc *, int);
184 static void bwi_led_blink_start(struct bwi_softc *, int, int);
185 static void bwi_led_blink_next(void *);
186 static void bwi_led_blink_end(void *);
187
188 static const struct bwi_dev {
189 uint16_t vid;
190 uint16_t did;
191 const char *desc;
192 } bwi_devices[] = {
193 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM4301,
194 "Broadcom BCM4301 802.11 Wireless Lan" },
195
196 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM4307,
197 "Broadcom BCM4307 802.11 Wireless Lan" },
198
199 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM4311,
200 "Broadcom BCM4311 802.11 Wireless Lan" },
201
202 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM4312,
203 "Broadcom BCM4312 802.11 Wireless Lan" },
204
205 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM4306_1,
206 "Broadcom BCM4306 802.11 Wireless Lan" },
207
208 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM4306_2,
209 "Broadcom BCM4306 802.11 Wireless Lan" },
210
211 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM4306_3,
212 "Broadcom BCM4306 802.11 Wireless Lan" },
213
214 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM4309,
215 "Broadcom BCM4309 802.11 Wireless Lan" },
216
217 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM4318,
218 "Broadcom BCM4318 802.11 Wireless Lan" },
219
220 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM4319,
221 "Broadcom BCM4319 802.11 Wireless Lan" }
222 };
223
224 static device_method_t bwi_methods[] = {
225 DEVMETHOD(device_probe, bwi_probe),
226 DEVMETHOD(device_attach, bwi_attach),
227 DEVMETHOD(device_detach, bwi_detach),
228 DEVMETHOD(device_shutdown, bwi_shutdown),
229 #if 0
230 DEVMETHOD(device_suspend, bwi_suspend),
231 DEVMETHOD(device_resume, bwi_resume),
232 #endif
233 { 0, 0 }
234 };
235
236 static driver_t bwi_driver = {
237 "bwi",
238 bwi_methods,
239 sizeof(struct bwi_softc)
240 };
241
242 static devclass_t bwi_devclass;
243
244 DRIVER_MODULE(bwi, pci, bwi_driver, bwi_devclass, 0, 0);
245 DRIVER_MODULE(bwi, cardbus, bwi_driver, bwi_devclass, 0, 0);
246
247 MODULE_DEPEND(bwi, wlan, 1, 1, 1);
248 MODULE_DEPEND(bwi, wlan_ratectl_onoe, 1, 1, 1);
249 #if 0
250 MODULE_DEPEND(bwi, wlan_ratectl_amrr, 1, 1, 1);
251 #endif
252 MODULE_DEPEND(bwi, pci, 1, 1, 1);
253 MODULE_DEPEND(bwi, cardbus, 1, 1, 1);
254
255 static const struct {
256 uint16_t did_min;
257 uint16_t did_max;
258 uint16_t bbp_id;
259 } bwi_bbpid_map[] = {
260 { 0x4301, 0x4301, 0x4301 },
261 { 0x4305, 0x4307, 0x4307 },
262 { 0x4403, 0x4403, 0x4402 },
263 { 0x4610, 0x4615, 0x4610 },
264 { 0x4710, 0x4715, 0x4710 },
265 { 0x4720, 0x4725, 0x4309 }
266 };
267
268 static const struct {
269 uint16_t bbp_id;
270 int nregwin;
271 } bwi_regwin_count[] = {
272 { 0x4301, 5 },
273 { 0x4306, 6 },
274 { 0x4307, 5 },
275 { 0x4310, 8 },
276 { 0x4401, 3 },
277 { 0x4402, 3 },
278 { 0x4610, 9 },
279 { 0x4704, 9 },
280 { 0x4710, 9 },
281 { 0x5365, 7 }
282 };
283
284 #define CLKSRC(src) \
285 [BWI_CLKSRC_ ## src] = { \
286 .freq_min = BWI_CLKSRC_ ##src## _FMIN, \
287 .freq_max = BWI_CLKSRC_ ##src## _FMAX \
288 }
289
290 static const struct {
291 u_int freq_min;
292 u_int freq_max;
293 } bwi_clkfreq[BWI_CLKSRC_MAX] = {
294 CLKSRC(LP_OSC),
295 CLKSRC(CS_OSC),
296 CLKSRC(PCI)
297 };
298
299 #undef CLKSRC
300
301 #define VENDOR_LED_ACT(vendor) \
302 { \
303 .vid = PCI_VENDOR_##vendor, \
304 .led_act = { BWI_VENDOR_LED_ACT_##vendor } \
305 }
306
307 static const struct {
308 uint16_t vid;
309 uint8_t led_act[BWI_LED_MAX];
310 } bwi_vendor_led_act[] = {
311 VENDOR_LED_ACT(COMPAQ),
312 VENDOR_LED_ACT(LINKSYS)
313 };
314
315 static const uint8_t bwi_default_led_act[BWI_LED_MAX] =
316 { BWI_VENDOR_LED_ACT_DEFAULT };
317
318 #undef VENDOR_LED_ACT
319
320 static const struct {
321 int on_dur;
322 int off_dur;
323 } bwi_led_duration[109] = {
324 [0] = { 400, 100 },
325 [2] = { 150, 75 },
326 [4] = { 90, 45 },
327 [11] = { 66, 34 },
328 [12] = { 53, 26 },
329 [18] = { 42, 21 },
330 [22] = { 35, 17 },
331 [24] = { 32, 16 },
332 [36] = { 21, 10 },
333 [48] = { 16, 8 },
334 [72] = { 11, 5 },
335 [96] = { 9, 4 },
336 [108] = { 7, 3 }
337 };
338
339 #ifdef BWI_DEBUG
340 #ifdef BWI_DEBUG_VERBOSE
341 static uint32_t bwi_debug = BWI_DBG_ATTACH | BWI_DBG_INIT | BWI_DBG_TXPOWER;
342 #else
343 static uint32_t bwi_debug;
344 #endif
345 TUNABLE_INT("hw.bwi.debug", (int *)&bwi_debug);
346 #endif /* BWI_DEBUG */
347
348 static const uint8_t bwi_zero_addr[IEEE80211_ADDR_LEN];
349
350 static const struct ieee80211_rateset bwi_rateset_11b =
351 { 4, { 2, 4, 11, 22 } };
352 static const struct ieee80211_rateset bwi_rateset_11g =
353 { 12, { 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108 } };
354
355 uint16_t
356 bwi_read_sprom(struct bwi_softc *sc, uint16_t ofs)
357 {
358 return CSR_READ_2(sc, ofs + BWI_SPROM_START);
359 }
360
361 static __inline void
362 bwi_setup_desc32(struct bwi_softc *sc, struct bwi_desc32 *desc_array,
363 int ndesc, int desc_idx, bus_addr_t paddr, int buf_len,
364 int tx)
365 {
366 struct bwi_desc32 *desc = &desc_array[desc_idx];
367 uint32_t ctrl, addr, addr_hi, addr_lo;
368
369 addr_lo = __SHIFTOUT(paddr, BWI_DESC32_A_ADDR_MASK);
370 addr_hi = __SHIFTOUT(paddr, BWI_DESC32_A_FUNC_MASK);
371
372 addr = __SHIFTIN(addr_lo, BWI_DESC32_A_ADDR_MASK) |
373 __SHIFTIN(BWI_DESC32_A_FUNC_TXRX, BWI_DESC32_A_FUNC_MASK);
374
375 ctrl = __SHIFTIN(buf_len, BWI_DESC32_C_BUFLEN_MASK) |
376 __SHIFTIN(addr_hi, BWI_DESC32_C_ADDRHI_MASK);
377 if (desc_idx == ndesc - 1)
378 ctrl |= BWI_DESC32_C_EOR;
379 if (tx) {
380 /* XXX */
381 ctrl |= BWI_DESC32_C_FRAME_START |
382 BWI_DESC32_C_FRAME_END |
383 BWI_DESC32_C_INTR;
384 }
385
386 desc->addr = htole32(addr);
387 desc->ctrl = htole32(ctrl);
388 }
389
390 /* XXX does not belong here */
391 uint8_t
392 bwi_rate2plcp(uint8_t rate)
393 {
394 rate &= IEEE80211_RATE_VAL;
395
396 switch (rate) {
397 case 2: return 0xa;
398 case 4: return 0x14;
399 case 11: return 0x37;
400 case 22: return 0x6e;
401 case 44: return 0xdc;
402
403 case 12: return 0xb;
404 case 18: return 0xf;
405 case 24: return 0xa;
406 case 36: return 0xe;
407 case 48: return 0x9;
408 case 72: return 0xd;
409 case 96: return 0x8;
410 case 108: return 0xc;
411
412 default:
413 panic("unsupported rate %u\n", rate);
414 }
415 }
416
417 /* XXX does not belong here */
418 #define IEEE80211_OFDM_PLCP_RATE_MASK __BITS(3, 0)
419 #define IEEE80211_OFDM_PLCP_LEN_MASK __BITS(16, 5)
420
421 static __inline void
422 bwi_ofdm_plcp_header(uint32_t *plcp0, int pkt_len, uint8_t rate)
423 {
424 uint32_t plcp;
425
426 plcp = __SHIFTIN(bwi_rate2plcp(rate), IEEE80211_OFDM_PLCP_RATE_MASK) |
427 __SHIFTIN(pkt_len, IEEE80211_OFDM_PLCP_LEN_MASK);
428 *plcp0 = htole32(plcp);
429 }
430
431 /* XXX does not belong here */
432 struct ieee80211_ds_plcp_hdr {
433 uint8_t i_signal;
434 uint8_t i_service;
435 uint16_t i_length;
436 uint16_t i_crc;
437 } __packed;
438
439 #define IEEE80211_DS_PLCP_SERVICE_LOCKED 0x04
440 #define IEEE80211_DS_PLCL_SERVICE_PBCC 0x08
441 #define IEEE80211_DS_PLCP_SERVICE_LENEXT5 0x20
442 #define IEEE80211_DS_PLCP_SERVICE_LENEXT6 0x40
443 #define IEEE80211_DS_PLCP_SERVICE_LENEXT7 0x80
444
445 static __inline void
446 bwi_ds_plcp_header(struct ieee80211_ds_plcp_hdr *plcp, int pkt_len,
447 uint8_t rate)
448 {
449 int len, service, pkt_bitlen;
450
451 pkt_bitlen = pkt_len * NBBY;
452 len = howmany(pkt_bitlen * 2, rate);
453
454 service = IEEE80211_DS_PLCP_SERVICE_LOCKED;
455 if (rate == (11 * 2)) {
456 int pkt_bitlen1;
457
458 /*
459 * PLCP service field needs to be adjusted,
460 * if TX rate is 11Mbytes/s
461 */
462 pkt_bitlen1 = len * 11;
463 if (pkt_bitlen1 - pkt_bitlen >= NBBY)
464 service |= IEEE80211_DS_PLCP_SERVICE_LENEXT7;
465 }
466
467 plcp->i_signal = bwi_rate2plcp(rate);
468 plcp->i_service = service;
469 plcp->i_length = htole16(len);
470 /* NOTE: do NOT touch i_crc */
471 }
472
473 static __inline void
474 bwi_plcp_header(void *plcp, int pkt_len, uint8_t rate)
475 {
476 enum ieee80211_modtype modtype;
477
478 /*
479 * Assume caller has zeroed 'plcp'
480 */
481
482 modtype = ieee80211_rate2modtype(rate);
483 if (modtype == IEEE80211_MODTYPE_OFDM)
484 bwi_ofdm_plcp_header(plcp, pkt_len, rate);
485 else if (modtype == IEEE80211_MODTYPE_DS)
486 bwi_ds_plcp_header(plcp, pkt_len, rate);
487 else
488 panic("unsupport modulation type %u\n", modtype);
489 }
490
491 static __inline uint8_t
492 bwi_ofdm_plcp2rate(const uint32_t *plcp0)
493 {
494 uint32_t plcp;
495 uint8_t plcp_rate;
496
497 plcp = le32toh(*plcp0);
498 plcp_rate = __SHIFTOUT(plcp, IEEE80211_OFDM_PLCP_RATE_MASK);
499 return ieee80211_plcp2rate(plcp_rate, 1);
500 }
501
502 static __inline uint8_t
503 bwi_ds_plcp2rate(const struct ieee80211_ds_plcp_hdr *hdr)
504 {
505 return ieee80211_plcp2rate(hdr->i_signal, 0);
506 }
507
508 static int
509 bwi_probe(device_t dev)
510 {
511 const struct bwi_dev *b;
512 uint16_t did, vid;
513
514 did = pci_get_device(dev);
515 vid = pci_get_vendor(dev);
516
517 for (b = bwi_devices; b->desc != NULL; ++b) {
518 if (b->did == did && b->vid == vid) {
519 device_set_desc(dev, b->desc);
520 return 0;
521 }
522 }
523 return ENXIO;
524 }
525
526 static int
527 bwi_attach(device_t dev)
528 {
529 struct bwi_softc *sc = device_get_softc(dev);
530 struct ieee80211com *ic = &sc->sc_ic;
531 struct ifnet *ifp = &ic->ic_if;
532 struct bwi_mac *mac;
533 struct bwi_phy *phy;
534 int i, error;
535
536 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
537 sc->sc_dev = dev;
538
539 /*
540 * Initialize sysctl variables
541 */
542 sc->sc_fw_version = BWI_FW_VERSION3;
543 sc->sc_dwell_time = 200;
544 sc->sc_led_idle = (2350 * hz) / 1000;
545 sc->sc_led_blink = 1;
546 sc->sc_txpwr_calib = 1;
547 #ifdef BWI_DEBUG
548 sc->sc_debug = bwi_debug;
549 #endif
550
551 callout_init(&sc->sc_scan_ch);
552 callout_init(&sc->sc_calib_ch);
553
554 #ifndef BURN_BRIDGES
555 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
556 uint32_t irq, mem;
557
558 /* XXX Save more PCIR */
559 irq = pci_read_config(dev, PCIR_INTLINE, 4);
560 mem = pci_read_config(dev, BWI_PCIR_BAR, 4);
561
562 device_printf(dev, "chip is in D%d power mode "
563 "-- setting to D0\n", pci_get_powerstate(dev));
564
565 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
566
567 pci_write_config(dev, PCIR_INTLINE, irq, 4);
568 pci_write_config(dev, BWI_PCIR_BAR, mem, 4);
569 }
570 #endif /* !BURN_BRIDGE */
571
572 pci_enable_busmaster(dev);
573
574 /* Get more PCI information */
575 sc->sc_pci_revid = pci_get_revid(dev);
576 sc->sc_pci_subvid = pci_get_subvendor(dev);
577 sc->sc_pci_subdid = pci_get_subdevice(dev);
578
579 /*
580 * Allocate IO memory
581 */
582 sc->sc_mem_rid = BWI_PCIR_BAR;
583 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
584 &sc->sc_mem_rid, RF_ACTIVE);
585 if (sc->sc_mem_res == NULL) {
586 device_printf(dev, "can't allocate IO memory\n");
587 return ENXIO;
588 }
589 sc->sc_mem_bt = rman_get_bustag(sc->sc_mem_res);
590 sc->sc_mem_bh = rman_get_bushandle(sc->sc_mem_res);
591
592 /*
593 * Allocate IRQ
594 */
595 sc->sc_irq_rid = 0;
596 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ,
597 &sc->sc_irq_rid,
598 RF_SHAREABLE | RF_ACTIVE);
599 if (sc->sc_irq_res == NULL) {
600 device_printf(dev, "can't allocate irq\n");
601 error = ENXIO;
602 goto fail;
603 }
604
605 /*
606 * Create sysctl tree
607 */
608 sysctl_ctx_init(&sc->sc_sysctl_ctx);
609 sc->sc_sysctl_tree = SYSCTL_ADD_NODE(&sc->sc_sysctl_ctx,
610 SYSCTL_STATIC_CHILDREN(_hw),
611 OID_AUTO,
612 device_get_nameunit(dev),
613 CTLFLAG_RD, 0, "");
614 if (sc->sc_sysctl_tree == NULL) {
615 device_printf(dev, "can't add sysctl node\n");
616 error = ENXIO;
617 goto fail;
618 }
619
620 SYSCTL_ADD_UINT(&sc->sc_sysctl_ctx,
621 SYSCTL_CHILDREN(sc->sc_sysctl_tree), OID_AUTO,
622 "dwell_time", CTLFLAG_RW, &sc->sc_dwell_time, 0,
623 "Channel dwell time during scan (msec)");
624 SYSCTL_ADD_UINT(&sc->sc_sysctl_ctx,
625 SYSCTL_CHILDREN(sc->sc_sysctl_tree), OID_AUTO,
626 "fw_version", CTLFLAG_RD, &sc->sc_fw_version, 0,
627 "Firmware version");
628 SYSCTL_ADD_UINT(&sc->sc_sysctl_ctx,
629 SYSCTL_CHILDREN(sc->sc_sysctl_tree), OID_AUTO,
630 "led_idle", CTLFLAG_RW, &sc->sc_led_idle, 0,
631 "# ticks before LED enters idle state");
632 SYSCTL_ADD_INT(&sc->sc_sysctl_ctx,
633 SYSCTL_CHILDREN(sc->sc_sysctl_tree), OID_AUTO,
634 "led_blink", CTLFLAG_RW, &sc->sc_led_blink, 0,
635 "Allow LED to blink");
636 SYSCTL_ADD_INT(&sc->sc_sysctl_ctx,
637 SYSCTL_CHILDREN(sc->sc_sysctl_tree), OID_AUTO,
638 "txpwr_calib", CTLFLAG_RW, &sc->sc_txpwr_calib, 0,
639 "Enable software TX power calibration");
640 #ifdef BWI_DEBUG
641 SYSCTL_ADD_UINT(&sc->sc_sysctl_ctx,
642 SYSCTL_CHILDREN(sc->sc_sysctl_tree), OID_AUTO,
643 "debug", CTLFLAG_RW, &sc->sc_debug, 0, "Debug flags");
644 #endif
645
646 bwi_power_on(sc, 1);
647
648 error = bwi_bbp_attach(sc);
649 if (error)
650 goto fail;
651
652 error = bwi_bbp_power_on(sc, BWI_CLOCK_MODE_FAST);
653 if (error)
654 goto fail;
655
656 if (BWI_REGWIN_EXIST(&sc->sc_com_regwin)) {
657 error = bwi_set_clock_delay(sc);
658 if (error)
659 goto fail;
660
661 error = bwi_set_clock_mode(sc, BWI_CLOCK_MODE_FAST);
662 if (error)
663 goto fail;
664
665 error = bwi_get_pwron_delay(sc);
666 if (error)
667 goto fail;
668 }
669
670 error = bwi_bus_attach(sc);
671 if (error)
672 goto fail;
673
674 bwi_get_card_flags(sc);
675
676 bwi_led_attach(sc);
677
678 for (i = 0; i < sc->sc_nmac; ++i) {
679 struct bwi_regwin *old;
680
681 mac = &sc->sc_mac[i];
682 error = bwi_regwin_switch(sc, &mac->mac_regwin, &old);
683 if (error)
684 goto fail;
685
686 error = bwi_mac_lateattach(mac);
687 if (error)
688 goto fail;
689
690 error = bwi_regwin_switch(sc, old, NULL);
691 if (error)
692 goto fail;
693 }
694
695 /*
696 * XXX First MAC is known to exist
697 * TODO2
698 */
699 mac = &sc->sc_mac[0];
700 phy = &mac->mac_phy;
701
702 bwi_bbp_power_off(sc);
703
704 error = bwi_dma_alloc(sc);
705 if (error)
706 goto fail;
707
708 ifp->if_softc = sc;
709 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
710 ifp->if_init = bwi_init;
711 ifp->if_ioctl = bwi_ioctl;
712 ifp->if_start = bwi_start;
713 ifp->if_watchdog = bwi_watchdog;
714 ifq_set_maxlen(&ifp->if_snd, IFQ_MAXLEN);
715 ifq_set_ready(&ifp->if_snd);
716
717 /* Get locale */
718 sc->sc_locale = __SHIFTOUT(bwi_read_sprom(sc, BWI_SPROM_CARD_INFO),
719 BWI_SPROM_CARD_INFO_LOCALE);
720 DPRINTF(sc, BWI_DBG_ATTACH, "locale: %d\n", sc->sc_locale);
721
722 /*
723 * Setup ratesets, phytype, channels and get MAC address
724 */
725 if (phy->phy_mode == IEEE80211_MODE_11B ||
726 phy->phy_mode == IEEE80211_MODE_11G) {
727 uint16_t chan_flags;
728
729 ic->ic_sup_rates[IEEE80211_MODE_11B] = bwi_rateset_11b;
730
731 if (phy->phy_mode == IEEE80211_MODE_11B) {
732 chan_flags = IEEE80211_CHAN_B;
733 ic->ic_phytype = IEEE80211_T_DS;
734 } else {
735 chan_flags = IEEE80211_CHAN_CCK |
736 IEEE80211_CHAN_OFDM |
737 IEEE80211_CHAN_DYN |
738 IEEE80211_CHAN_2GHZ;
739 ic->ic_phytype = IEEE80211_T_OFDM;
740 ic->ic_sup_rates[IEEE80211_MODE_11G] =
741 bwi_rateset_11g;
742 }
743
744 /* XXX depend on locale */
745 for (i = 1; i <= 14; ++i) {
746 ic->ic_channels[i].ic_freq =
747 ieee80211_ieee2mhz(i, IEEE80211_CHAN_2GHZ);
748 ic->ic_channels[i].ic_flags = chan_flags;
749 }
750
751 bwi_get_eaddr(sc, BWI_SPROM_11BG_EADDR, ic->ic_myaddr);
752 if (IEEE80211_IS_MULTICAST(ic->ic_myaddr)) {
753 bwi_get_eaddr(sc, BWI_SPROM_11A_EADDR, ic->ic_myaddr);
754 if (IEEE80211_IS_MULTICAST(ic->ic_myaddr)) {
755 device_printf(dev, "invalid MAC address: "
756 "%6D\n", ic->ic_myaddr, ":");
757 }
758 }
759 } else if (phy->phy_mode == IEEE80211_MODE_11A) {
760 /* TODO:11A */
761 error = ENXIO;
762 goto fail;
763 } else {
764 panic("unknown phymode %d\n", phy->phy_mode);
765 }
766
767 ic->ic_caps = IEEE80211_C_SHSLOT |
768 IEEE80211_C_SHPREAMBLE |
769 IEEE80211_C_WPA |
770 IEEE80211_C_MONITOR;
771 ic->ic_state = IEEE80211_S_INIT;
772 ic->ic_opmode = IEEE80211_M_STA;
773
774 IEEE80211_ONOE_PARAM_SETUP(&sc->sc_onoe_param);
775 ic->ic_ratectl.rc_st_ratectl_cap = IEEE80211_RATECTL_CAP_ONOE;
776 ic->ic_ratectl.rc_st_ratectl = IEEE80211_RATECTL_ONOE;
777 ic->ic_ratectl.rc_st_attach = bwi_ratectl_attach;
778
779 ic->ic_updateslot = bwi_updateslot;
780
781 ieee80211_ifattach(ic);
782
783 ic->ic_headroom = sizeof(struct bwi_txbuf_hdr);
784 ic->ic_flags_ext |= IEEE80211_FEXT_SWBMISS;
785
786 sc->sc_newstate = ic->ic_newstate;
787 ic->ic_newstate = bwi_newstate;
788
789 ieee80211_media_init(ic, bwi_media_change, ieee80211_media_status);
790
791 /*
792 * Attach radio tap
793 */
794 bpfattach_dlt(ifp, DLT_IEEE802_11_RADIO,
795 sizeof(struct ieee80211_frame) + sizeof(sc->sc_tx_th),
796 &sc->sc_drvbpf);
797
798 sc->sc_tx_th_len = roundup(sizeof(sc->sc_tx_th), sizeof(uint32_t));
799 sc->sc_tx_th.wt_ihdr.it_len = htole16(sc->sc_tx_th_len);
800 sc->sc_tx_th.wt_ihdr.it_present = htole32(BWI_TX_RADIOTAP_PRESENT);
801
802 sc->sc_rx_th_len = roundup(sizeof(sc->sc_rx_th), sizeof(uint32_t));
803 sc->sc_rx_th.wr_ihdr.it_len = htole16(sc->sc_rx_th_len);
804 sc->sc_rx_th.wr_ihdr.it_present = htole32(BWI_RX_RADIOTAP_PRESENT);
805
806 error = bus_setup_intr(dev, sc->sc_irq_res, INTR_MPSAFE, bwi_intr, sc,
807 &sc->sc_irq_handle, ifp->if_serializer);
808 if (error) {
809 device_printf(dev, "can't setup intr\n");
810 bpfdetach(ifp);
811 ieee80211_ifdetach(ic);
812 goto fail;
813 }
814
815 if (bootverbose)
816 ieee80211_announce(ic);
817
818 return 0;
819 fail:
820 bwi_detach(dev);
821 return error;
822 }
823
824 static int
825 bwi_detach(device_t dev)
826 {
827 struct bwi_softc *sc = device_get_softc(dev);
828
829 if (device_is_attached(dev)) {
830 struct ifnet *ifp = &sc->sc_ic.ic_if;
831 int i;
832
833 lwkt_serialize_enter(ifp->if_serializer);
834 bwi_stop(sc);
835 bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_irq_handle);
836 lwkt_serialize_exit(ifp->if_serializer);
837
838 bpfdetach(ifp);
839 ieee80211_ifdetach(&sc->sc_ic);
840
841 for (i = 0; i < sc->sc_nmac; ++i)
842 bwi_mac_detach(&sc->sc_mac[i]);
843 }
844
845 if (sc->sc_sysctl_tree != NULL)
846 sysctl_ctx_free(&sc->sc_sysctl_ctx);
847
848 if (sc->sc_irq_res != NULL) {
849 bus_release_resource(dev, SYS_RES_IRQ, sc->sc_irq_rid,
850 sc->sc_irq_res);
851 }
852
853 if (sc->sc_mem_res != NULL) {
854 bus_release_resource(dev, SYS_RES_MEMORY, sc->sc_mem_rid,
855 sc->sc_mem_res);
856 }
857
858 bwi_dma_free(sc);
859
860 return 0;
861 }
862
863 static int
864 bwi_shutdown(device_t dev)
865 {
866 struct bwi_softc *sc = device_get_softc(dev);
867 struct ifnet *ifp = &sc->sc_ic.ic_if;
868
869 lwkt_serialize_enter(ifp->if_serializer);
870 bwi_stop(sc);
871 lwkt_serialize_exit(ifp->if_serializer);
872 return 0;
873 }
874
875 static void
876 bwi_power_on(struct bwi_softc *sc, int with_pll)
877 {
878 uint32_t gpio_in, gpio_out, gpio_en;
879 uint16_t status;
880
881 gpio_in = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_IN, 4);
882 if (gpio_in & BWI_PCIM_GPIO_PWR_ON)
883 goto back;
884
885 gpio_out = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, 4);
886 gpio_en = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_ENABLE, 4);
887
888 gpio_out |= BWI_PCIM_GPIO_PWR_ON;
889 gpio_en |= BWI_PCIM_GPIO_PWR_ON;
890 if (with_pll) {
891 /* Turn off PLL first */
892 gpio_out |= BWI_PCIM_GPIO_PLL_PWR_OFF;
893 gpio_en |= BWI_PCIM_GPIO_PLL_PWR_OFF;
894 }
895
896 pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, gpio_out, 4);
897 pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_ENABLE, gpio_en, 4);
898 DELAY(1000);
899
900 if (with_pll) {
901 /* Turn on PLL */
902 gpio_out &= ~BWI_PCIM_GPIO_PLL_PWR_OFF;
903 pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, gpio_out, 4);
904 DELAY(5000);
905 }
906
907 back:
908 /* Clear "Signaled Target Abort" */
909 status = pci_read_config(sc->sc_dev, PCIR_STATUS, 2);
910 status &= ~PCIM_STATUS_STABORT;
911 pci_write_config(sc->sc_dev, PCIR_STATUS, status, 2);
912 }
913
914 static int
915 bwi_power_off(struct bwi_softc *sc, int with_pll)
916 {
917 uint32_t gpio_out, gpio_en;
918
919 pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_IN, 4); /* dummy read */
920 gpio_out = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, 4);
921 gpio_en = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_ENABLE, 4);
922
923 gpio_out &= ~BWI_PCIM_GPIO_PWR_ON;
924 gpio_en |= BWI_PCIM_GPIO_PWR_ON;
925 if (with_pll) {
926 gpio_out |= BWI_PCIM_GPIO_PLL_PWR_OFF;
927 gpio_en |= BWI_PCIM_GPIO_PLL_PWR_OFF;
928 }
929
930 pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, gpio_out, 4);
931 pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_ENABLE, gpio_en, 4);
932 return 0;
933 }
934
935 int
936 bwi_regwin_switch(struct bwi_softc *sc, struct bwi_regwin *rw,
937 struct bwi_regwin **old_rw)
938 {
939 int error;
940
941 if (old_rw != NULL)
942 *old_rw = NULL;
943
944 if (!BWI_REGWIN_EXIST(rw))
945 return EINVAL;
946
947 if (sc->sc_cur_regwin != rw) {
948 error = bwi_regwin_select(sc, rw->rw_id);
949 if (error) {
950 if_printf(&sc->sc_ic.ic_if, "can't select regwin %d\n",
951 rw->rw_id);
952 return error;
953 }
954 }
955
956 if (old_rw != NULL)
957 *old_rw = sc->sc_cur_regwin;
958 sc->sc_cur_regwin = rw;
959 return 0;
960 }
961
962 static int
963 bwi_regwin_select(struct bwi_softc *sc, int id)
964 {
965 uint32_t win = BWI_PCIM_REGWIN(id);
966 int i;
967
968 #define RETRY_MAX 50
969 for (i = 0; i < RETRY_MAX; ++i) {
970 pci_write_config(sc->sc_dev, BWI_PCIR_SEL_REGWIN, win, 4);
971 if (pci_read_config(sc->sc_dev, BWI_PCIR_SEL_REGWIN, 4) == win)
972 return 0;
973 DELAY(10);
974 }
975 #undef RETRY_MAX
976
977 return ENXIO;
978 }
979
980 static void
981 bwi_regwin_info(struct bwi_softc *sc, uint16_t *type, uint8_t *rev)
982 {
983 uint32_t val;
984
985 val = CSR_READ_4(sc, BWI_ID_HI);
986 *type = BWI_ID_HI_REGWIN_TYPE(val);
987 *rev = BWI_ID_HI_REGWIN_REV(val);
988
989 DPRINTF(sc, BWI_DBG_ATTACH, "regwin: type 0x%03x, rev %d, "
990 "vendor 0x%04x\n", *type, *rev,
991 __SHIFTOUT(val, BWI_ID_HI_REGWIN_VENDOR_MASK));
992 }
993
994 static int
995 bwi_bbp_attach(struct bwi_softc *sc)
996 {
997 #define N(arr) (int)(sizeof(arr) / sizeof(arr[0]))
998 uint16_t bbp_id, rw_type;
999 uint8_t rw_rev;
1000 uint32_t info;
1001 int error, nregwin, i;
1002
1003 /*
1004 * Get 0th regwin information
1005 * NOTE: 0th regwin should exist
1006 */
1007 error = bwi_regwin_select(sc, 0);
1008 if (error) {
1009 device_printf(sc->sc_dev, "can't select regwin 0\n");
1010 return error;
1011 }
1012 bwi_regwin_info(sc, &rw_type, &rw_rev);
1013
1014 /*
1015 * Find out BBP id
1016 */
1017 bbp_id = 0;
1018 info = 0;
1019 if (rw_type == BWI_REGWIN_T_COM) {
1020 info = CSR_READ_4(sc, BWI_INFO);
1021 bbp_id = __SHIFTOUT(info, BWI_INFO_BBPID_MASK);
1022
1023 BWI_CREATE_REGWIN(&sc->sc_com_regwin, 0, rw_type, rw_rev);
1024
1025 sc->sc_cap = CSR_READ_4(sc, BWI_CAPABILITY);
1026 } else {
1027 uint16_t did = pci_get_device(sc->sc_dev);
1028 uint8_t revid = pci_get_revid(sc->sc_dev);
1029
1030 for (i = 0; i < N(bwi_bbpid_map); ++i) {
1031 if (did >= bwi_bbpid_map[i].did_min &&
1032 did <= bwi_bbpid_map[i].did_max) {
1033 bbp_id = bwi_bbpid_map[i].bbp_id;
1034 break;
1035 }
1036 }
1037 if (bbp_id == 0) {
1038 device_printf(sc->sc_dev, "no BBP id for device id "
1039 "0x%04x\n", did);
1040 return ENXIO;
1041 }
1042
1043 info = __SHIFTIN(revid, BWI_INFO_BBPREV_MASK) |
1044 __SHIFTIN(0, BWI_INFO_BBPPKG_MASK);
1045 }
1046
1047 /*
1048 * Find out number of regwins
1049 */
1050 nregwin = 0;
1051 if (rw_type == BWI_REGWIN_T_COM && rw_rev >= 4) {
1052 nregwin = __SHIFTOUT(info, BWI_INFO_NREGWIN_MASK);
1053 } else {
1054 for (i = 0; i < N(bwi_regwin_count); ++i) {
1055 if (bwi_regwin_count[i].bbp_id == bbp_id) {
1056 nregwin = bwi_regwin_count[i].nregwin;
1057 break;
1058 }
1059 }
1060 if (nregwin == 0) {
1061 device_printf(sc->sc_dev, "no number of win for "
1062 "BBP id 0x%04x\n", bbp_id);
1063 return ENXIO;
1064 }
1065 }
1066
1067 /* Record BBP id/rev for later using */
1068 sc->sc_bbp_id = bbp_id;
1069 sc->sc_bbp_rev = __SHIFTOUT(info, BWI_INFO_BBPREV_MASK);
1070 sc->sc_bbp_pkg = __SHIFTOUT(info, BWI_INFO_BBPPKG_MASK);
1071 device_printf(sc->sc_dev, "BBP: id 0x%04x, rev 0x%x, pkg %d\n",
1072 sc->sc_bbp_id, sc->sc_bbp_rev, sc->sc_bbp_pkg);
1073
1074 DPRINTF(sc, BWI_DBG_ATTACH, "nregwin %d, cap 0x%08x\n",
1075 nregwin, sc->sc_cap);
1076
1077 /*
1078 * Create rest of the regwins
1079 */
1080
1081 /* Don't re-create common regwin, if it is already created */
1082 i = BWI_REGWIN_EXIST(&sc->sc_com_regwin) ? 1 : 0;
1083
1084 for (; i < nregwin; ++i) {
1085 /*
1086 * Get regwin information
1087 */
1088 error = bwi_regwin_select(sc, i);
1089 if (error) {
1090 device_printf(sc->sc_dev,
1091 "can't select regwin %d\n", i);
1092 return error;
1093 }
1094 bwi_regwin_info(sc, &rw_type, &rw_rev);
1095
1096 /*
1097 * Try attach:
1098 * 1) Bus (PCI/PCIE) regwin
1099 * 2) MAC regwin
1100 * Ignore rest types of regwin
1101 */
1102 if (rw_type == BWI_REGWIN_T_BUSPCI ||
1103 rw_type == BWI_REGWIN_T_BUSPCIE) {
1104 if (BWI_REGWIN_EXIST(&sc->sc_bus_regwin)) {
1105 device_printf(sc->sc_dev,
1106 "bus regwin already exists\n");
1107 } else {
1108 BWI_CREATE_REGWIN(&sc->sc_bus_regwin, i,
1109 rw_type, rw_rev);
1110 }
1111 } else if (rw_type == BWI_REGWIN_T_MAC) {
1112 /* XXX ignore return value */
1113 bwi_mac_attach(sc, i, rw_rev);
1114 }
1115 }
1116
1117 /* At least one MAC shold exist */
1118 if (!BWI_REGWIN_EXIST(&sc->sc_mac[0].mac_regwin)) {
1119 device_printf(sc->sc_dev, "no MAC was found\n");
1120 return ENXIO;
1121 }
1122 KKASSERT(sc->sc_nmac > 0);
1123
1124 /* Bus regwin must exist */
1125 if (!BWI_REGWIN_EXIST(&sc->sc_bus_regwin)) {
1126 device_printf(sc->sc_dev, "no bus regwin was found\n");
1127 return ENXIO;
1128 }
1129
1130 /* Start with first MAC */
1131 error = bwi_regwin_switch(sc, &sc->sc_mac[0].mac_regwin, NULL);
1132 if (error)
1133 return error;
1134
1135 return 0;
1136 #undef N
1137 }
1138
1139 int
1140 bwi_bus_init(struct bwi_softc *sc, struct bwi_mac *mac)
1141 {
1142 struct bwi_regwin *old, *bus;
1143 uint32_t val;
1144 int error;
1145
1146 bus = &sc->sc_bus_regwin;
1147 KKASSERT(sc->sc_cur_regwin == &mac->mac_regwin);
1148
1149 /*
1150 * Tell bus to generate requested interrupts
1151 */
1152 if (bus->rw_rev < 6 && bus->rw_type == BWI_REGWIN_T_BUSPCI) {
1153 /*
1154 * NOTE: Read BWI_FLAGS from MAC regwin
1155 */
1156 val = CSR_READ_4(sc, BWI_FLAGS);
1157
1158 error = bwi_regwin_switch(sc, bus, &old);
1159 if (error)
1160 return error;
1161
1162 CSR_SETBITS_4(sc, BWI_INTRVEC, (val & BWI_FLAGS_INTR_MASK));
1163 } else {
1164 uint32_t mac_mask;
1165
1166 mac_mask = 1 << mac->mac_id;
1167
1168 error = bwi_regwin_switch(sc, bus, &old);
1169 if (error)
1170 return error;
1171
1172 val = pci_read_config(sc->sc_dev, BWI_PCIR_INTCTL, 4);
1173 val |= mac_mask << 8;
1174 pci_write_config(sc->sc_dev, BWI_PCIR_INTCTL, val, 4);
1175 }
1176
1177 if (sc->sc_flags & BWI_F_BUS_INITED)
1178 goto back;
1179
1180 if (bus->rw_type == BWI_REGWIN_T_BUSPCI) {
1181 /*
1182 * Enable prefetch and burst
1183 */
1184 CSR_SETBITS_4(sc, BWI_BUS_CONFIG,
1185 BWI_BUS_CONFIG_PREFETCH | BWI_BUS_CONFIG_BURST);
1186
1187 if (bus->rw_rev < 5) {
1188 struct bwi_regwin *com = &sc->sc_com_regwin;
1189
1190 /*
1191 * Configure timeouts for bus operation
1192 */
1193
1194 /*
1195 * Set service timeout and request timeout
1196 */
1197 CSR_SETBITS_4(sc, BWI_CONF_LO,
1198 __SHIFTIN(BWI_CONF_LO_SERVTO, BWI_CONF_LO_SERVTO_MASK) |
1199 __SHIFTIN(BWI_CONF_LO_REQTO, BWI_CONF_LO_REQTO_MASK));
1200
1201 /*
1202 * If there is common regwin, we switch to that regwin
1203 * and switch back to bus regwin once we have done.
1204 */
1205 if (BWI_REGWIN_EXIST(com)) {
1206 error = bwi_regwin_switch(sc, com, NULL);
1207 if (error)
1208 return error;
1209 }
1210
1211 /* Let bus know what we have changed */
1212 CSR_WRITE_4(sc, BWI_BUS_ADDR, BWI_BUS_ADDR_MAGIC);
1213 CSR_READ_4(sc, BWI_BUS_ADDR); /* Flush */
1214 CSR_WRITE_4(sc, BWI_BUS_DATA, 0);
1215 CSR_READ_4(sc, BWI_BUS_DATA); /* Flush */
1216
1217 if (BWI_REGWIN_EXIST(com)) {
1218 error = bwi_regwin_switch(sc, bus, NULL);
1219 if (error)
1220 return error;
1221 }
1222 } else if (bus->rw_rev >= 11) {
1223 /*
1224 * Enable memory read multiple
1225 */
1226 CSR_SETBITS_4(sc, BWI_BUS_CONFIG, BWI_BUS_CONFIG_MRM);
1227 }
1228 } else {
1229 /* TODO:PCIE */
1230 }
1231
1232 sc->sc_flags |= BWI_F_BUS_INITED;
1233 back:
1234 return bwi_regwin_switch(sc, old, NULL);
1235 }
1236
1237 static void
1238 bwi_get_card_flags(struct bwi_softc *sc)
1239 {
1240 sc->sc_card_flags = bwi_read_sprom(sc, BWI_SPROM_CARD_FLAGS);
1241 if (sc->sc_card_flags == 0xffff)
1242 sc->sc_card_flags = 0;
1243
1244 if (sc->sc_pci_subvid == PCI_VENDOR_APPLE &&
1245 sc->sc_pci_subdid == 0x4e && /* XXX */
1246 sc->sc_pci_revid > 0x40)
1247 sc->sc_card_flags |= BWI_CARD_F_PA_GPIO9;
1248
1249 DPRINTF(sc, BWI_DBG_ATTACH, "card flags 0x%04x\n", sc->sc_card_flags);
1250 }
1251
1252 static void
1253 bwi_get_eaddr(struct bwi_softc *sc, uint16_t eaddr_ofs, uint8_t *eaddr)
1254 {
1255 int i;
1256
1257 for (i = 0; i < 3; ++i) {
1258 *((uint16_t *)eaddr + i) =
1259 htobe16(bwi_read_sprom(sc, eaddr_ofs + 2 * i));
1260 }
1261 }
1262
1263 static void
1264 bwi_get_clock_freq(struct bwi_softc *sc, struct bwi_clock_freq *freq)
1265 {
1266 struct bwi_regwin *com;
1267 uint32_t val;
1268 u_int div;
1269 int src;
1270
1271 bzero(freq, sizeof(*freq));
1272 com = &sc->sc_com_regwin;
1273
1274 KKASSERT(BWI_REGWIN_EXIST(com));
1275 KKASSERT(sc->sc_cur_regwin == com);
1276 KKASSERT(sc->sc_cap & BWI_CAP_CLKMODE);
1277
1278 /*
1279 * Calculate clock frequency
1280 */
1281 src = -1;
1282 div = 0;
1283 if (com->rw_rev < 6) {
1284 val = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, 4);
1285 if (val & BWI_PCIM_GPIO_OUT_CLKSRC) {
1286 src = BWI_CLKSRC_PCI;
1287 div = 64;
1288 } else {
1289 src = BWI_CLKSRC_CS_OSC;
1290 div = 32;
1291 }
1292 } else if (com->rw_rev < 10) {
1293 val = CSR_READ_4(sc, BWI_CLOCK_CTRL);
1294
1295 src = __SHIFTOUT(val, BWI_CLOCK_CTRL_CLKSRC);
1296 if (src == BWI_CLKSRC_LP_OSC) {
1297 div = 1;
1298 } else {
1299 div = (__SHIFTOUT(val, BWI_CLOCK_CTRL_FDIV) + 1) << 2;
1300
1301 /* Unknown source */
1302 if (src >= BWI_CLKSRC_MAX)
1303 src = BWI_CLKSRC_CS_OSC;
1304 }
1305 } else {
1306 val = CSR_READ_4(sc, BWI_CLOCK_INFO);
1307
1308 src = BWI_CLKSRC_CS_OSC;
1309 div = (__SHIFTOUT(val, BWI_CLOCK_INFO_FDIV) + 1) << 2;
1310 }
1311
1312 KKASSERT(src >= 0 && src < BWI_CLKSRC_MAX);
1313 KKASSERT(div != 0);
1314
1315 DPRINTF(sc, BWI_DBG_ATTACH, "clksrc %s\n",
1316 src == BWI_CLKSRC_PCI ? "PCI" :
1317 (src == BWI_CLKSRC_LP_OSC ? "LP_OSC" : "CS_OSC"));
1318
1319 freq->clkfreq_min = bwi_clkfreq[src].freq_min / div;
1320 freq->clkfreq_max = bwi_clkfreq[src].freq_max / div;
1321
1322 DPRINTF(sc, BWI_DBG_ATTACH, "clkfreq min %u, max %u\n",
1323 freq->clkfreq_min, freq->clkfreq_max);
1324 }
1325
1326 static int
1327 bwi_set_clock_mode(struct bwi_softc *sc, enum bwi_clock_mode clk_mode)
1328 {
1329 struct bwi_regwin *old, *com;
1330 uint32_t clk_ctrl, clk_src;
1331 int error, pwr_off = 0;
1332
1333 com = &sc->sc_com_regwin;
1334 if (!BWI_REGWIN_EXIST(com))
1335 return 0;
1336
1337 if (com->rw_rev >= 10 || com->rw_rev < 6)
1338 return 0;
1339
1340 /*
1341 * For common regwin whose rev is [6, 10), the chip
1342 * must be capable to change clock mode.
1343 */
1344 if ((sc->sc_cap & BWI_CAP_CLKMODE) == 0)
1345 return 0;
1346
1347 error = bwi_regwin_switch(sc, com, &old);
1348 if (error)
1349 return error;
1350
1351 if (clk_mode == BWI_CLOCK_MODE_FAST)
1352 bwi_power_on(sc, 0); /* Don't turn on PLL */
1353
1354 clk_ctrl = CSR_READ_4(sc, BWI_CLOCK_CTRL);
1355 clk_src = __SHIFTOUT(clk_ctrl, BWI_CLOCK_CTRL_CLKSRC);
1356
1357 switch (clk_mode) {
1358 case BWI_CLOCK_MODE_FAST:
1359 clk_ctrl &= ~BWI_CLOCK_CTRL_SLOW;
1360 clk_ctrl |= BWI_CLOCK_CTRL_IGNPLL;
1361 break;
1362 case BWI_CLOCK_MODE_SLOW:
1363 clk_ctrl |= BWI_CLOCK_CTRL_SLOW;
1364 break;
1365 case BWI_CLOCK_MODE_DYN:
1366 clk_ctrl &= ~(BWI_CLOCK_CTRL_SLOW |
1367 BWI_CLOCK_CTRL_IGNPLL |
1368 BWI_CLOCK_CTRL_NODYN);
1369 if (clk_src != BWI_CLKSRC_CS_OSC) {
1370 clk_ctrl |= BWI_CLOCK_CTRL_NODYN;
1371 pwr_off = 1;
1372 }
1373 break;
1374 }
1375 CSR_WRITE_4(sc, BWI_CLOCK_CTRL, clk_ctrl);
1376
1377 if (pwr_off)
1378 bwi_power_off(sc, 0); /* Leave PLL as it is */
1379
1380 return bwi_regwin_switch(sc, old, NULL);
1381 }
1382
1383 static int
1384 bwi_set_clock_delay(struct bwi_softc *sc)
1385 {
1386 struct bwi_regwin *old, *com;
1387 int error;
1388
1389 com = &sc->sc_com_regwin;
1390 if (!BWI_REGWIN_EXIST(com))
1391 return 0;
1392
1393 error = bwi_regwin_switch(sc, com, &old);
1394 if (error)
1395 return error;
1396
1397 if (sc->sc_bbp_id == BWI_BBPID_BCM4321) {
1398 if (sc->sc_bbp_rev == 0)
1399 CSR_WRITE_4(sc, BWI_CONTROL, BWI_CONTROL_MAGIC0);
1400 else if (sc->sc_bbp_rev == 1)
1401 CSR_WRITE_4(sc, BWI_CONTROL, BWI_CONTROL_MAGIC1);
1402 }
1403
1404 if (sc->sc_cap & BWI_CAP_CLKMODE) {
1405 if (com->rw_rev >= 10) {
1406 CSR_FILT_SETBITS_4(sc, BWI_CLOCK_INFO, 0xffff, 0x40000);
1407 } else {
1408 struct bwi_clock_freq freq;
1409
1410 bwi_get_clock_freq(sc, &freq);
1411 CSR_WRITE_4(sc, BWI_PLL_ON_DELAY,
1412 howmany(freq.clkfreq_max * 150, 1000000));
1413 CSR_WRITE_4(sc, BWI_FREQ_SEL_DELAY,
1414 howmany(freq.clkfreq_max * 15, 1000000));
1415 }
1416 }
1417
1418 return bwi_regwin_switch(sc, old, NULL);
1419 }
1420
1421 static void
1422 bwi_init(void *xsc)
1423 {
1424 struct bwi_softc *sc = xsc;
1425 struct ieee80211com *ic = &sc->sc_ic;
1426 struct ifnet *ifp = &ic->ic_if;
1427 struct bwi_mac *mac;
1428 int error;
1429
1430 ASSERT_SERIALIZED(ifp->if_serializer);
1431
1432 error = bwi_stop(sc);
1433 if (error) {
1434 if_printf(ifp, "can't stop\n");
1435 return;
1436 }
1437
1438 bwi_bbp_power_on(sc, BWI_CLOCK_MODE_FAST);
1439
1440 /* TODO: 2 MAC */
1441
1442 mac = &sc->sc_mac[0];
1443 error = bwi_regwin_switch(sc, &mac->mac_regwin, NULL);
1444 if (error)
1445 goto back;
1446
1447 error = bwi_mac_init(mac);
1448 if (error)
1449 goto back;
1450
1451 bwi_bbp_power_on(sc, BWI_CLOCK_MODE_DYN);
1452
1453 bcopy(IF_LLADDR(ifp), ic->ic_myaddr, sizeof(ic->ic_myaddr));
1454
1455 bwi_set_bssid(sc, bwi_zero_addr); /* Clear BSSID */
1456 bwi_set_addr_filter(sc, BWI_ADDR_FILTER_MYADDR, ic->ic_myaddr);
1457
1458 bwi_mac_reset_hwkeys(mac);
1459
1460 if ((mac->mac_flags & BWI_MAC_F_HAS_TXSTATS) == 0) {
1461 int i;
1462
1463 #define NRETRY 1000
1464 /*
1465 * Drain any possible pending TX status
1466 */
1467 for (i = 0; i < NRETRY; ++i) {
1468 if ((CSR_READ_4(sc, BWI_TXSTATUS0) &
1469 BWI_TXSTATUS0_VALID) == 0)
1470 break;
1471 CSR_READ_4(sc, BWI_TXSTATUS1);
1472 }
1473 if (i == NRETRY)
1474 if_printf(ifp, "can't drain TX status\n");
1475 #undef NRETRY
1476 }
1477
1478 if (mac->mac_phy.phy_mode == IEEE80211_MODE_11G)
1479 bwi_mac_updateslot(mac, 1);
1480
1481 /* Start MAC */
1482 error = bwi_mac_start(mac);
1483 if (error)
1484 goto back;
1485
1486 /* Enable intrs */
1487 bwi_enable_intrs(sc, BWI_INIT_INTRS);
1488
1489 ifp->if_flags |= IFF_RUNNING;
1490 ifp->if_flags &= ~IFF_OACTIVE;
1491
1492 if (ic->ic_opmode != IEEE80211_M_MONITOR) {
1493 if (ic->ic_roaming != IEEE80211_ROAMING_MANUAL)
1494 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1);
1495 } else {
1496 ieee80211_new_state(ic, IEEE80211_S_RUN, -1);
1497 }
1498 back:
1499 if (error)
1500 bwi_stop(sc);
1501 }
1502
1503 static int
1504 bwi_ioctl(struct ifnet *ifp, u_long cmd, caddr_t req, struct ucred *cr)
1505 {
1506 struct bwi_softc *sc = ifp->if_softc;
1507 int error = 0;
1508
1509 ASSERT_SERIALIZED(ifp->if_serializer);
1510
1511 switch (cmd) {
1512 case SIOCSIFFLAGS:
1513 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) ==
1514 (IFF_UP | IFF_RUNNING)) {
1515 struct bwi_mac *mac;
1516 int promisc = -1;
1517
1518 KKASSERT(sc->sc_cur_regwin->rw_type ==
1519 BWI_REGWIN_T_MAC);
1520 mac = (struct bwi_mac *)sc->sc_cur_regwin;
1521
1522 if ((ifp->if_flags & IFF_PROMISC) &&
1523 (sc->sc_flags & BWI_F_PROMISC) == 0) {
1524 promisc = 1;
1525 sc->sc_flags |= BWI_F_PROMISC;
1526 } else if ((ifp->if_flags & IFF_PROMISC) == 0 &&
1527 (sc->sc_flags & BWI_F_PROMISC)) {
1528 promisc = 0;
1529 sc->sc_flags &= ~BWI_F_PROMISC;
1530 }
1531
1532 if (promisc >= 0)
1533 bwi_mac_set_promisc(mac, promisc);
1534 }
1535
1536 if (ifp->if_flags & IFF_UP) {
1537 if ((ifp->if_flags & IFF_RUNNING) == 0)
1538 bwi_init(sc);
1539 } else {
1540 if (ifp->if_flags & IFF_RUNNING)
1541 bwi_stop(sc);
1542 }
1543 break;
1544 default:
1545 error = ieee80211_ioctl(&sc->sc_ic, cmd, req, cr);
1546 break;
1547 }
1548
1549 if (error == ENETRESET) {
1550 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) ==
1551 (IFF_UP | IFF_RUNNING))
1552 bwi_init(sc);
1553 error = 0;
1554 }
1555 return error;
1556 }
1557
1558 static void
1559 bwi_start(struct ifnet *ifp)
1560 {
1561 struct bwi_softc *sc = ifp->if_softc;
1562 struct ieee80211com *ic = &sc->sc_ic;
1563 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[BWI_TX_DATA_RING];
1564 int trans, idx;
1565
1566 ASSERT_SERIALIZED(ifp->if_serializer);
1567
1568 if ((ifp->if_flags & IFF_OACTIVE) ||
1569 (ifp->if_flags & IFF_RUNNING) == 0)
1570 return;
1571
1572 trans = 0;
1573 idx = tbd->tbd_idx;
1574
1575 while (tbd->tbd_buf[idx].tb_mbuf == NULL) {
1576 struct ieee80211_frame *wh;
1577 struct ieee80211_node *ni;
1578 struct mbuf *m;
1579 int mgt_pkt = 0;
1580
1581 if (!IF_QEMPTY(&ic->ic_mgtq)) {
1582 IF_DEQUEUE(&ic->ic_mgtq, m);
1583
1584 ni = (struct ieee80211_node *)m->m_pkthdr.rcvif;
1585 m->m_pkthdr.rcvif = NULL;
1586
1587 mgt_pkt = 1;
1588 } else if (!ifq_is_empty(&ifp->if_snd)) {
1589 struct ether_header *eh;
1590
1591 if (ic->ic_state != IEEE80211_S_RUN)
1592 break;
1593
1594 m = ifq_dequeue(&ifp->if_snd, NULL);
1595 if (m == NULL)
1596 break;
1597
1598 if (m->m_len < sizeof(*eh)) {
1599 m = m_pullup(m, sizeof(*eh));
1600 if (m == NULL) {
1601 ifp->if_oerrors++;
1602 continue;
1603 }
1604 }
1605 eh = mtod(m, struct ether_header *);
1606
1607 ni = ieee80211_find_txnode(ic, eh->ether_dhost);
1608 if (ni == NULL) {
1609 m_freem(m);
1610 ifp->if_oerrors++;
1611 continue;
1612 }
1613
1614 /* TODO: PS */
1615
1616 BPF_MTAP(ifp, m);
1617
1618 m = ieee80211_encap(ic, m, ni);
1619 if (m == NULL) {
1620 ieee80211_free_node(ni);
1621 ifp->if_oerrors++;
1622 continue;
1623 }
1624 } else {
1625 break;
1626 }
1627
1628 if (ic->ic_rawbpf != NULL)
1629 bpf_mtap(ic->ic_rawbpf, m);
1630
1631 wh = mtod(m, struct ieee80211_frame *);
1632 if (wh->i_fc[1] & IEEE80211_FC1_WEP) {
1633 if (ieee80211_crypto_encap(ic, ni, m) == NULL) {
1634 ieee80211_free_node(ni);
1635 m_freem(m);
1636 ifp->if_oerrors++;
1637 continue;
1638 }
1639 }
1640 wh = NULL; /* Catch any invalid use */
1641
1642 if (bwi_encap(sc, idx, m, &ni, mgt_pkt) != 0) {
1643 /* 'm' is freed in bwi_encap() if we reach here */
1644 if (ni != NULL)
1645 ieee80211_free_node(ni);
1646 ifp->if_oerrors++;
1647 continue;
1648 }
1649
1650 trans = 1;
1651 tbd->tbd_used++;
1652 idx = (idx + 1) % BWI_TX_NDESC;
1653
1654 if (tbd->tbd_used + BWI_TX_NSPRDESC >= BWI_TX_NDESC) {
1655 ifp->if_flags |= IFF_OACTIVE;
1656 break;
1657 }
1658 }
1659 tbd->tbd_idx = idx;
1660
1661 if (trans)
1662 sc->sc_tx_timer = 5;
1663 ifp->if_timer = 1;
1664 }
1665
1666 static void
1667 bwi_watchdog(struct ifnet *ifp)
1668 {
1669 struct bwi_softc *sc = ifp->if_softc;
1670
1671 ASSERT_SERIALIZED(ifp->if_serializer);
1672
1673 ifp->if_timer = 0;
1674
1675 if ((ifp->if_flags & IFF_RUNNING) == 0)
1676 return;
1677
1678 if (sc->sc_tx_timer) {
1679 if (--sc->sc_tx_timer == 0) {
1680 if_printf(ifp, "watchdog timeout\n");
1681 ifp->if_oerrors++;
1682 /* TODO */
1683 } else {
1684 ifp->if_timer = 1;
1685 }
1686 }
1687 ieee80211_watchdog(&sc->sc_ic);
1688 }
1689
1690 static int
1691 bwi_stop(struct bwi_softc *sc)
1692 {
1693 struct ieee80211com *ic = &sc->sc_ic;
1694 struct ifnet *ifp = &ic->ic_if;
1695 struct bwi_mac *mac;
1696 int i, error, pwr_off = 0;
1697
1698 ASSERT_SERIALIZED(ifp->if_serializer);
1699
1700 ieee80211_new_state(ic, IEEE80211_S_INIT, -1);
1701
1702 if (ifp->if_flags & IFF_RUNNING) {
1703 KKASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC);
1704 mac = (struct bwi_mac *)sc->sc_cur_regwin;
1705
1706 bwi_disable_intrs(sc, BWI_ALL_INTRS);
1707 CSR_READ_4(sc, BWI_MAC_INTR_MASK);
1708 bwi_mac_stop(mac);
1709 }
1710
1711 for (i = 0; i < sc->sc_nmac; ++i) {
1712 struct bwi_regwin *old_rw;
1713
1714 mac = &sc->sc_mac[i];
1715 if ((mac->mac_flags & BWI_MAC_F_INITED) == 0)
1716 continue;
1717
1718 error = bwi_regwin_switch(sc, &mac->mac_regwin, &old_rw);
1719 if (error)
1720 continue;
1721
1722 bwi_mac_shutdown(mac);
1723 pwr_off = 1;
1724
1725 bwi_regwin_switch(sc, old_rw, NULL);
1726 }
1727
1728 if (pwr_off)
1729 bwi_bbp_power_off(sc);
1730
1731 sc->sc_tx_timer = 0;
1732 ifp->if_timer = 0;
1733 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1734 return 0;
1735 }
1736
1737 static void
1738 bwi_intr(void *xsc)
1739 {
1740 struct bwi_softc *sc = xsc;
1741 struct ifnet *ifp = &sc->sc_ic.ic_if;
1742 uint32_t intr_status;
1743 uint32_t txrx_intr_status[BWI_TXRX_NRING];
1744 int i, txrx_error, tx = 0, rx_data = -1;
1745
1746 ASSERT_SERIALIZED(ifp->if_serializer);
1747
1748 if ((ifp->if_flags & IFF_RUNNING) == 0)
1749 return;
1750
1751 /*
1752 * Get interrupt status
1753 */
1754 intr_status = CSR_READ_4(sc, BWI_MAC_INTR_STATUS);
1755 if (intr_status == 0xffffffff) /* Not for us */
1756 return;
1757
1758 DPRINTF(sc, BWI_DBG_INTR, "intr status 0x%08x\n", intr_status);
1759
1760 intr_status &= CSR_READ_4(sc, BWI_MAC_INTR_MASK);
1761 if (intr_status == 0) /* Nothing is interesting */
1762 return;
1763
1764 txrx_error = 0;
1765 DPRINTF(sc, BWI_DBG_INTR, "%s\n", "TX/RX intr");
1766 for (i = 0; i < BWI_TXRX_NRING; ++i) {
1767 uint32_t mask;
1768
1769 if (BWI_TXRX_IS_RX(i))
1770 mask = BWI_TXRX_RX_INTRS;
1771 else
1772 mask = BWI_TXRX_TX_INTRS;
1773
1774 txrx_intr_status[i] =
1775 CSR_READ_4(sc, BWI_TXRX_INTR_STATUS(i)) & mask;
1776
1777 _DPRINTF(sc, BWI_DBG_INTR, ", %d 0x%08x",
1778 i, txrx_intr_status[i]);
1779
1780 if (txrx_intr_status[i] & BWI_TXRX_INTR_ERROR) {
1781 if_printf(ifp, "intr fatal TX/RX (%d) error 0x%08x\n",
1782 i, txrx_intr_status[i]);
1783 txrx_error = 1;
1784 }
1785 }
1786 _DPRINTF(sc, BWI_DBG_INTR, "%s\n", "");
1787
1788 /*
1789 * Acknowledge interrupt
1790 */
1791 CSR_WRITE_4(sc, BWI_MAC_INTR_STATUS, intr_status);
1792
1793 for (i = 0; i < BWI_TXRX_NRING; ++i)
1794 CSR_WRITE_4(sc, BWI_TXRX_INTR_STATUS(i), txrx_intr_status[i]);
1795
1796 /* Disable all interrupts */
1797 bwi_disable_intrs(sc, BWI_ALL_INTRS);
1798
1799 if (intr_status & BWI_INTR_PHY_TXERR)
1800 if_printf(ifp, "intr PHY TX error\n");
1801
1802 if (txrx_error) {
1803 /* TODO: reset device */
1804 }
1805
1806 if (intr_status & BWI_INTR_TBTT) {
1807 KKASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC);
1808 bwi_mac_config_ps((struct bwi_mac *)sc->sc_cur_regwin);
1809 }
1810
1811 if (intr_status & BWI_INTR_EO_ATIM)
1812 if_printf(ifp, "EO_ATIM\n");
1813
1814 if (intr_status & BWI_INTR_PMQ) {
1815 for (;;) {
1816 if ((CSR_READ_4(sc, BWI_MAC_PS_STATUS) & 0x8) == 0)
1817 break;
1818 }
1819 CSR_WRITE_2(sc, BWI_MAC_PS_STATUS, 0x2);
1820 }
1821
1822 if (intr_status & BWI_INTR_NOISE)
1823 if_printf(ifp, "intr noise\n");
1824
1825 if (txrx_intr_status[0] & BWI_TXRX_INTR_RX)
1826 rx_data = sc->sc_rxeof(sc);
1827
1828 if (txrx_intr_status[3] & BWI_TXRX_INTR_RX) {
1829 sc->sc_txeof_status(sc);
1830 tx = 1;
1831 }
1832
1833 if (intr_status & BWI_INTR_TX_DONE) {
1834 bwi_txeof(sc);
1835 tx = 1;
1836 }
1837
1838 /* Re-enable interrupts */
1839 bwi_enable_intrs(sc, BWI_INIT_INTRS);
1840
1841 if (sc->sc_blink_led != NULL && sc->sc_led_blink) {
1842 int evt = BWI_LED_EVENT_NONE;
1843
1844 if (tx && rx_data > 0) {
1845 if (sc->sc_rx_rate > sc->sc_tx_rate)
1846 evt = BWI_LED_EVENT_RX;
1847 else
1848 evt = BWI_LED_EVENT_TX;
1849 } else if (tx) {
1850 evt = BWI_LED_EVENT_TX;
1851 } else if (rx_data > 0) {
1852 evt = BWI_LED_EVENT_RX;
1853 } else if (rx_data == 0) {
1854 evt = BWI_LED_EVENT_POLL;
1855 }
1856
1857 if (evt != BWI_LED_EVENT_NONE)
1858 bwi_led_event(sc, evt);
1859 }
1860 }
1861
1862 static int
1863 bwi_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg)
1864 {
1865 struct bwi_softc *sc = ic->ic_if.if_softc;
1866 struct ifnet *ifp = &ic->ic_if;
1867 int error;
1868
1869 ASSERT_SERIALIZED(ifp->if_serializer);
1870
1871 callout_stop(&sc->sc_scan_ch);
1872 callout_stop(&sc->sc_calib_ch);
1873
1874 ieee80211_ratectl_newstate(ic, nstate);
1875 bwi_led_newstate(sc, nstate);
1876
1877 if (nstate == IEEE80211_S_INIT)
1878 goto back;
1879
1880 error = bwi_set_chan(sc, ic->ic_curchan);
1881 if (error) {
1882 if_printf(ifp, "can't set channel to %u\n",
1883 ieee80211_chan2ieee(ic, ic->ic_curchan));
1884 return error;
1885 }
1886
1887 if (ic->ic_opmode == IEEE80211_M_MONITOR) {
1888 /* Nothing to do */
1889 } else if (nstate == IEEE80211_S_RUN) {
1890 struct bwi_mac *mac;
1891
1892 bwi_set_bssid(sc, ic->ic_bss->ni_bssid);
1893
1894 KKASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC);
1895 mac = (struct bwi_mac *)sc->sc_cur_regwin;
1896
1897 /* Initial TX power calibration */
1898 bwi_mac_calibrate_txpower(mac);
1899 } else {
1900 bwi_set_bssid(sc, bwi_zero_addr);
1901 }
1902
1903 back:
1904 error = sc->sc_newstate(ic, nstate, arg);
1905
1906 if (nstate == IEEE80211_S_SCAN) {
1907 callout_reset(&sc->sc_scan_ch,
1908 (sc->sc_dwell_time * hz) / 1000,
1909 bwi_next_scan, sc);
1910 } else if (nstate == IEEE80211_S_RUN) {
1911 /* XXX 15 seconds */
1912 callout_reset(&sc->sc_calib_ch, hz * 15, bwi_calibrate, sc);
1913 }
1914 return error;
1915 }
1916
1917 static int
1918 bwi_media_change(struct ifnet *ifp)
1919 {
1920 int error;
1921
1922 ASSERT_SERIALIZED(ifp->if_serializer);
1923
1924 error = ieee80211_media_change(ifp);
1925 if (error != ENETRESET)
1926 return error;
1927
1928 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == (IFF_UP | IFF_RUNNING))
1929 bwi_init(ifp->if_softc);
1930 return 0;
1931 }
1932
1933 static int
1934 bwi_dma_alloc(struct bwi_softc *sc)
1935 {
1936 int error, i, has_txstats;
1937 bus_addr_t lowaddr = 0;
1938 bus_size_t tx_ring_sz, rx_ring_sz, desc_sz = 0;
1939 uint32_t txrx_ctrl_step = 0;
1940
1941 has_txstats = 0;
1942 for (i = 0; i < sc->sc_nmac; ++i) {
1943 if (sc->sc_mac[i].mac_flags & BWI_MAC_F_HAS_TXSTATS) {
1944 has_txstats = 1;
1945 break;
1946 }
1947 }
1948
1949 switch (sc->sc_bus_space) {
1950 case BWI_BUS_SPACE_30BIT:
1951 case BWI_BUS_SPACE_32BIT:
1952 if (sc->sc_bus_space == BWI_BUS_SPACE_30BIT)
1953 lowaddr = BWI_BUS_SPACE_MAXADDR;
1954 else
1955 lowaddr = BUS_SPACE_MAXADDR_32BIT;
1956 desc_sz = sizeof(struct bwi_desc32);
1957 txrx_ctrl_step = 0x20;
1958
1959 sc->sc_init_tx_ring = bwi_init_tx_ring32;
1960 sc->sc_free_tx_ring = bwi_free_tx_ring32;
1961 sc->sc_init_rx_ring = bwi_init_rx_ring32;
1962 sc->sc_free_rx_ring = bwi_free_rx_ring32;
1963 sc->sc_setup_rxdesc = bwi_setup_rx_desc32;
1964 sc->sc_setup_txdesc = bwi_setup_tx_desc32;
1965 sc->sc_rxeof = bwi_rxeof32;
1966 sc->sc_start_tx = bwi_start_tx32;
1967 if (has_txstats) {
1968 sc->sc_init_txstats = bwi_init_txstats32;
1969 sc->sc_free_txstats = bwi_free_txstats32;
1970 sc->sc_txeof_status = bwi_txeof_status32;
1971 }
1972 break;
1973
1974 case BWI_BUS_SPACE_64BIT:
1975 lowaddr = BUS_SPACE_MAXADDR; /* XXX */
1976 desc_sz = sizeof(struct bwi_desc64);
1977 txrx_ctrl_step = 0x40;
1978
1979 sc->sc_init_tx_ring = bwi_init_tx_ring64;
1980 sc->sc_free_tx_ring = bwi_free_tx_ring64;
1981 sc->sc_init_rx_ring = bwi_init_rx_ring64;
1982 sc->sc_free_rx_ring = bwi_free_rx_ring64;
1983 sc->sc_setup_rxdesc = bwi_setup_rx_desc64;
1984 sc->sc_setup_txdesc = bwi_setup_tx_desc64;
1985 sc->sc_rxeof = bwi_rxeof64;
1986 sc->sc_start_tx = bwi_start_tx64;
1987 if (has_txstats) {
1988 sc->sc_init_txstats = bwi_init_txstats64;
1989 sc->sc_free_txstats = bwi_free_txstats64;
1990 sc->sc_txeof_status = bwi_txeof_status64;
1991 }
1992 break;
1993 }
1994
1995 KKASSERT(lowaddr != 0);
1996 KKASSERT(desc_sz != 0);
1997 KKASSERT(txrx_ctrl_step != 0);
1998
1999 tx_ring_sz = roundup(desc_sz * BWI_TX_NDESC, BWI_RING_ALIGN);
2000 rx_ring_sz = roundup(desc_sz * BWI_RX_NDESC, BWI_RING_ALIGN);
2001
2002 /*
2003 * Create top level DMA tag
2004 */
2005 error = bus_dma_tag_create(NULL, BWI_ALIGN, 0,
2006 lowaddr, BUS_SPACE_MAXADDR,
2007 NULL, NULL,
2008 MAXBSIZE,
2009 BUS_SPACE_UNRESTRICTED,
2010 BUS_SPACE_MAXSIZE_32BIT,
2011 0, &sc->sc_parent_dtag);
2012 if (error) {
2013 device_printf(sc->sc_dev, "can't create parent DMA tag\n");
2014 return error;
2015 }
2016
2017 #define TXRX_CTRL(idx) (BWI_TXRX_CTRL_BASE + (idx) * txrx_ctrl_step)
2018
2019 /*
2020 * Create TX ring DMA stuffs
2021 */
2022 error = bus_dma_tag_create(sc->sc_parent_dtag, BWI_RING_ALIGN, 0,
2023 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
2024 NULL, NULL,
2025 tx_ring_sz, 1, BUS_SPACE_MAXSIZE_32BIT,
2026 0, &sc->sc_txring_dtag);
2027 if (error) {
2028 device_printf(sc->sc_dev, "can't create TX ring DMA tag\n");
2029 return error;
2030 }
2031
2032 for (i = 0; i < BWI_TX_NRING; ++i) {
2033 error = bwi_dma_ring_alloc(sc, sc->sc_txring_dtag,
2034 &sc->sc_tx_rdata[i], tx_ring_sz,
2035 TXRX_CTRL(i));
2036 if (error) {
2037 device_printf(sc->sc_dev, "%dth TX ring "
2038 "DMA alloc failed\n", i);
2039 return error;
2040 }
2041 }
2042
2043 /*
2044 * Create RX ring DMA stuffs
2045 */
2046 error = bus_dma_tag_create(sc->sc_parent_dtag, BWI_RING_ALIGN, 0,
2047 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
2048 NULL, NULL,
2049 rx_ring_sz, 1, BUS_SPACE_MAXSIZE_32BIT,
2050 0, &sc->sc_rxring_dtag);
2051 if (error) {
2052 device_printf(sc->sc_dev, "can't create RX ring DMA tag\n");
2053 return error;
2054 }
2055
2056 error = bwi_dma_ring_alloc(sc, sc->sc_rxring_dtag, &sc->sc_rx_rdata,
2057 rx_ring_sz, TXRX_CTRL(0));
2058 if (error) {
2059 device_printf(sc->sc_dev, "RX ring DMA alloc failed\n");
2060 return error;
2061 }
2062
2063 if (has_txstats) {
2064 error = bwi_dma_txstats_alloc(sc, TXRX_CTRL(3), desc_sz);
2065 if (error) {
2066 device_printf(sc->sc_dev,
2067 "TX stats DMA alloc failed\n");
2068 return error;
2069 }
2070 }
2071
2072 #undef TXRX_CTRL
2073
2074 return bwi_dma_mbuf_create(sc);
2075 }
2076
2077 static void
2078 bwi_dma_free(struct bwi_softc *sc)
2079 {
2080 if (sc->sc_txring_dtag != NULL) {
2081 int i;
2082
2083 for (i = 0; i < BWI_TX_NRING; ++i) {
2084 struct bwi_ring_data *rd = &sc->sc_tx_rdata[i];
2085
2086 if (rd->rdata_desc != NULL) {
2087 bus_dmamap_unload(sc->sc_txring_dtag,
2088 rd->rdata_dmap);
2089 bus_dmamem_free(sc->sc_txring_dtag,
2090 rd->rdata_desc,
2091 rd->rdata_dmap);
2092 }
2093 }
2094 bus_dma_tag_destroy(sc->sc_txring_dtag);
2095 }
2096
2097 if (sc->sc_rxring_dtag != NULL) {
2098 struct bwi_ring_data *rd = &sc->sc_rx_rdata;
2099
2100 if (rd->rdata_desc != NULL) {
2101 bus_dmamap_unload(sc->sc_rxring_dtag, rd->rdata_dmap);
2102 bus_dmamem_free(sc->sc_rxring_dtag, rd->rdata_desc,
2103 rd->rdata_dmap);
2104 }
2105 bus_dma_tag_destroy(sc->sc_rxring_dtag);
2106 }
2107
2108 bwi_dma_txstats_free(sc);
2109 bwi_dma_mbuf_destroy(sc, BWI_TX_NRING, 1);
2110
2111 if (sc->sc_parent_dtag != NULL)
2112 bus_dma_tag_destroy(sc->sc_parent_dtag);
2113 }
2114
2115 static int
2116 bwi_dma_ring_alloc(struct bwi_softc *sc, bus_dma_tag_t dtag,
2117 struct bwi_ring_data *rd, bus_size_t size,
2118 uint32_t txrx_ctrl)
2119 {
2120 int error;
2121
2122 error = bus_dmamem_alloc(dtag, &rd->rdata_desc,
2123 BUS_DMA_WAITOK | BUS_DMA_ZERO,
2124 &rd->rdata_dmap);
2125 if (error) {
2126 device_printf(sc->sc_dev, "can't allocate DMA mem\n");
2127 return error;
2128 }
2129
2130 error = bus_dmamap_load(dtag, rd->rdata_dmap, rd->rdata_desc, size,
2131 bwi_dma_ring_addr, &rd->rdata_paddr,
2132 BUS_DMA_WAITOK);
2133 if (error) {
2134 device_printf(sc->sc_dev, "can't load DMA mem\n");
2135 bus_dmamem_free(dtag, rd->rdata_desc, rd->rdata_dmap);
2136 rd->rdata_desc = NULL;
2137 return error;
2138 }
2139
2140 rd->rdata_txrx_ctrl = txrx_ctrl;
2141 return 0;
2142 }
2143
2144 static int
2145 bwi_dma_txstats_alloc(struct bwi_softc *sc, uint32_t ctrl_base,
2146 bus_size_t desc_sz)
2147 {
2148 struct bwi_txstats_data *st;
2149 bus_size_t dma_size;
2150 int error;
2151
2152 st = kmalloc(sizeof(*st), M_DEVBUF, M_WAITOK | M_ZERO);
2153 sc->sc_txstats = st;
2154
2155 /*
2156 * Create TX stats descriptor DMA stuffs
2157 */
2158 dma_size = roundup(desc_sz * BWI_TXSTATS_NDESC, BWI_RING_ALIGN);
2159
2160 error = bus_dma_tag_create(sc->sc_parent_dtag, BWI_RING_ALIGN, 0,
2161 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
2162 NULL, NULL,
2163 dma_size, 1, BUS_SPACE_MAXSIZE_32BIT,
2164 0, &st->stats_ring_dtag);
2165 if (error) {
2166 device_printf(sc->sc_dev, "can't create txstats ring "
2167 "DMA tag\n");
2168 return error;
2169 }
2170
2171 error = bus_dmamem_alloc(st->stats_ring_dtag, &st->stats_ring,
2172 BUS_DMA_WAITOK | BUS_DMA_ZERO,
2173 &st->stats_ring_dmap);
2174 if (error) {
2175 device_printf(sc->sc_dev, "can't allocate txstats ring "
2176 "DMA mem\n");
2177 bus_dma_tag_destroy(st->stats_ring_dtag);
2178 st->stats_ring_dtag = NULL;
2179 return error;
2180 }
2181
2182 error = bus_dmamap_load(st->stats_ring_dtag, st->stats_ring_dmap,
2183 st->stats_ring, dma_size,
2184 bwi_dma_ring_addr, &st->stats_ring_paddr,
2185 BUS_DMA_WAITOK);
2186 if (error) {
2187 device_printf(sc->sc_dev, "can't load txstats ring DMA mem\n");
2188 bus_dmamem_free(st->stats_ring_dtag, st->stats_ring,
2189 st->stats_ring_dmap);
2190 bus_dma_tag_destroy(st->stats_ring_dtag);
2191 st->stats_ring_dtag = NULL;
2192 return error;
2193 }
2194
2195 /*
2196 * Create TX stats DMA stuffs
2197 */
2198 dma_size = roundup(sizeof(struct bwi_txstats) * BWI_TXSTATS_NDESC,
2199 BWI_ALIGN);
2200
2201 error = bus_dma_tag_create(sc->sc_parent_dtag, BWI_ALIGN, 0,
2202 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
2203 NULL, NULL,
2204 dma_size, 1, BUS_SPACE_MAXSIZE_32BIT,
2205 0, &st->stats_dtag);
2206 if (error) {
2207 device_printf(sc->sc_dev, "can't create txstats DMA tag\n");
2208 return error;
2209 }
2210
2211 error = bus_dmamem_alloc(st->stats_dtag, (void **)&st->stats,
2212 BUS_DMA_WAITOK | BUS_DMA_ZERO,
2213 &st->stats_dmap);
2214 if (error) {
2215 device_printf(sc->sc_dev, "can't allocate txstats DMA mem\n");
2216 bus_dma_tag_destroy(st->stats_dtag);
2217 st->stats_dtag = NULL;
2218 return error;
2219 }
2220
2221 error = bus_dmamap_load(st->stats_dtag, st->stats_dmap, st->stats,
2222 dma_size, bwi_dma_ring_addr, &st->stats_paddr,
2223 BUS_DMA_WAITOK);
2224 if (error) {
2225 device_printf(sc->sc_dev, "can't load txstats DMA mem\n");
2226 bus_dmamem_free(st->stats_dtag, st->stats, st->stats_dmap);
2227 bus_dma_tag_destroy(st->stats_dtag);
2228 st->stats_dtag = NULL;
2229 return error;
2230 }
2231
2232 st->stats_ctrl_base = ctrl_base;
2233 return 0;
2234 }
2235
2236 static void
2237 bwi_dma_txstats_free(struct bwi_softc *sc)
2238 {
2239 struct bwi_txstats_data *st;
2240
2241 if (sc->sc_txstats == NULL)
2242 return;
2243 st = sc->sc_txstats;
2244
2245 if (st->stats_ring_dtag != NULL) {
2246 bus_dmamap_unload(st->stats_ring_dtag, st->stats_ring_dmap);
2247 bus_dmamem_free(st->stats_ring_dtag, st->stats_ring,
2248 st->stats_ring_dmap);
2249 bus_dma_tag_destroy(st->stats_ring_dtag);
2250 }
2251
2252 if (st->stats_dtag != NULL) {
2253 bus_dmamap_unload(st->stats_dtag, st->stats_dmap);
2254 bus_dmamem_free(st->stats_dtag, st->stats, st->stats_dmap);
2255 bus_dma_tag_destroy(st->stats_dtag);
2256 }
2257
2258 kfree(st, M_DEVBUF);
2259 }
2260
2261 static void
2262 bwi_dma_ring_addr(void *arg, bus_dma_segment_t *seg, int nseg, int error)
2263 {
2264 KASSERT(nseg == 1, ("too many segments\n"));
2265 *((bus_addr_t *)arg) = seg->ds_addr;
2266 }
2267
2268 static int
2269 bwi_dma_mbuf_create(struct bwi_softc *sc)
2270 {
2271 struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata;
2272 int i, j, k, ntx, error;
2273
2274 /*
2275 * Create TX/RX mbuf DMA tag
2276 */
2277 error = bus_dma_tag_create(sc->sc_parent_dtag, 1, 0,
2278 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
2279 NULL, NULL, MCLBYTES, 1,
2280 BUS_SPACE_MAXSIZE_32BIT,
2281 0, &sc->sc_buf_dtag);
2282 if (error) {
2283 device_printf(sc->sc_dev, "can't create mbuf DMA tag\n");
2284 return error;
2285 }
2286
2287 ntx = 0;
2288
2289 /*
2290 * Create TX mbuf DMA map
2291 */
2292 for (i = 0; i < BWI_TX_NRING; ++i) {
2293 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[i];
2294
2295 for (j = 0; j < BWI_TX_NDESC; ++j) {
2296 error = bus_dmamap_create(sc->sc_buf_dtag, 0,
2297 &tbd->tbd_buf[j].tb_dmap);
2298 if (error) {
2299 device_printf(sc->sc_dev, "can't create "
2300 "%dth tbd, %dth DMA map\n", i, j);
2301
2302 ntx = i;
2303 for (k = 0; k < j; ++k) {
2304 bus_dmamap_destroy(sc->sc_buf_dtag,
2305 tbd->tbd_buf[k].tb_dmap);
2306 }
2307 goto fail;
2308 }
2309 }
2310 }
2311 ntx = BWI_TX_NRING;
2312
2313 /*
2314 * Create RX mbuf DMA map and a spare DMA map
2315 */
2316 error = bus_dmamap_create(sc->sc_buf_dtag, 0,
2317 &rbd->rbd_tmp_dmap);
2318 if (error) {
2319 device_printf(sc->sc_dev,
2320 "can't create spare RX buf DMA map\n");
2321 goto fail;
2322 }
2323
2324 for (j = 0; j < BWI_RX_NDESC; ++j) {
2325 error = bus_dmamap_create(sc->sc_buf_dtag, 0,
2326 &rbd->rbd_buf[j].rb_dmap);
2327 if (error) {
2328 device_printf(sc->sc_dev, "can't create %dth "
2329 "RX buf DMA map\n", j);
2330
2331 for (k = 0; k < j; ++k) {
2332 bus_dmamap_destroy(sc->sc_buf_dtag,
2333 rbd->rbd_buf[j].rb_dmap);
2334 }
2335 bus_dmamap_destroy(sc->sc_buf_dtag,
2336 rbd->rbd_tmp_dmap);
2337 goto fail;
2338 }
2339 }
2340
2341 return 0;
2342 fail:
2343 bwi_dma_mbuf_destroy(sc, ntx, 0);
2344 return error;
2345 }
2346
2347 static void
2348 bwi_dma_mbuf_destroy(struct bwi_softc *sc, int ntx, int nrx)
2349 {
2350 int i, j;
2351
2352 if (sc->sc_buf_dtag == NULL)
2353 return;
2354
2355 for (i = 0; i < ntx; ++i) {
2356 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[i];
2357
2358 for (j = 0; j < BWI_TX_NDESC; ++j) {
2359 struct bwi_txbuf *tb = &tbd->tbd_buf[j];
2360
2361 if (tb->tb_mbuf != NULL) {
2362 bus_dmamap_unload(sc->sc_buf_dtag,
2363 tb->tb_dmap);
2364 m_freem(tb->tb_mbuf);
2365 }
2366 if (tb->tb_ni != NULL)
2367 ieee80211_free_node(tb->tb_ni);
2368 bus_dmamap_destroy(sc->sc_buf_dtag, tb->tb_dmap);
2369 }
2370 }
2371
2372 if (nrx) {
2373 struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata;
2374
2375 bus_dmamap_destroy(sc->sc_buf_dtag, rbd->rbd_tmp_dmap);
2376 for (j = 0; j < BWI_RX_NDESC; ++j) {
2377 struct bwi_rxbuf *rb = &rbd->rbd_buf[j];
2378
2379 if (rb->rb_mbuf != NULL) {
2380 bus_dmamap_unload(sc->sc_buf_dtag,
2381 rb->rb_dmap);
2382 m_freem(rb->rb_mbuf);
2383 }
2384 bus_dmamap_destroy(sc->sc_buf_dtag, rb->rb_dmap);
2385 }
2386 }
2387
2388 bus_dma_tag_destroy(sc->sc_buf_dtag);
2389 sc->sc_buf_dtag = NULL;
2390 }
2391
2392 static void
2393 bwi_enable_intrs(struct bwi_softc *sc, uint32_t enable_intrs)
2394 {
2395 CSR_SETBITS_4(sc, BWI_MAC_INTR_MASK, enable_intrs);
2396 }
2397
2398 static void
2399 bwi_disable_intrs(struct bwi_softc *sc, uint32_t disable_intrs)
2400 {
2401 CSR_CLRBITS_4(sc, BWI_MAC_INTR_MASK, disable_intrs);
2402 }
2403
2404 static int
2405 bwi_init_tx_ring32(struct bwi_softc *sc, int ring_idx)
2406 {
2407 struct bwi_ring_data *rd;
2408 struct bwi_txbuf_data *tbd;
2409 uint32_t val, addr_hi, addr_lo;
2410
2411 KKASSERT(ring_idx < BWI_TX_NRING);
2412 rd = &sc->sc_tx_rdata[ring_idx];
2413 tbd = &sc->sc_tx_bdata[ring_idx];
2414
2415 tbd->tbd_idx = 0;
2416 tbd->tbd_used = 0;
2417
2418 bzero(rd->rdata_desc, sizeof(struct bwi_desc32) * BWI_TX_NDESC);
2419 bus_dmamap_sync(sc->sc_txring_dtag, rd->rdata_dmap,
2420 BUS_DMASYNC_PREWRITE);
2421
2422 addr_lo = __SHIFTOUT(rd->rdata_paddr, BWI_TXRX32_RINGINFO_ADDR_MASK);
2423 addr_hi = __SHIFTOUT(rd->rdata_paddr, BWI_TXRX32_RINGINFO_FUNC_MASK);
2424
2425 val = __SHIFTIN(addr_lo, BWI_TXRX32_RINGINFO_ADDR_MASK) |
2426 __SHIFTIN(BWI_TXRX32_RINGINFO_FUNC_TXRX,
2427 BWI_TXRX32_RINGINFO_FUNC_MASK);
2428 CSR_WRITE_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_RINGINFO, val);
2429
2430 val = __SHIFTIN(addr_hi, BWI_TXRX32_CTRL_ADDRHI_MASK) |
2431 BWI_TXRX32_CTRL_ENABLE;
2432 CSR_WRITE_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_CTRL, val);
2433
2434 return 0;
2435 }
2436
2437 static void
2438 bwi_init_rxdesc_ring32(struct bwi_softc *sc, uint32_t ctrl_base,
2439 bus_addr_t paddr, int hdr_size, int ndesc)
2440 {
2441 uint32_t val, addr_hi, addr_lo;
2442
2443 addr_lo = __SHIFTOUT(paddr, BWI_TXRX32_RINGINFO_ADDR_MASK);
2444 addr_hi = __SHIFTOUT(paddr, BWI_TXRX32_RINGINFO_FUNC_MASK);
2445
2446 val = __SHIFTIN(addr_lo, BWI_TXRX32_RINGINFO_ADDR_MASK) |
2447 __SHIFTIN(BWI_TXRX32_RINGINFO_FUNC_TXRX,
2448 BWI_TXRX32_RINGINFO_FUNC_MASK);
2449 CSR_WRITE_4(sc, ctrl_base + BWI_RX32_RINGINFO, val);
2450
2451 val = __SHIFTIN(hdr_size, BWI_RX32_CTRL_HDRSZ_MASK) |
2452 __SHIFTIN(addr_hi, BWI_TXRX32_CTRL_ADDRHI_MASK) |
2453 BWI_TXRX32_CTRL_ENABLE;
2454 CSR_WRITE_4(sc, ctrl_base + BWI_RX32_CTRL, val);
2455
2456 CSR_WRITE_4(sc, ctrl_base + BWI_RX32_INDEX,
2457 (ndesc - 1) * sizeof(struct bwi_desc32));
2458 }
2459
2460 static int
2461 bwi_init_rx_ring32(struct bwi_softc *sc)
2462 {
2463 struct bwi_ring_data *rd = &sc->sc_rx_rdata;
2464 int i, error;
2465
2466 sc->sc_rx_bdata.rbd_idx = 0;
2467
2468 for (i = 0; i < BWI_RX_NDESC; ++i) {
2469 error = bwi_newbuf(sc, i, 1);
2470 if (error) {
2471 if_printf(&sc->sc_ic.ic_if,
2472 "can't allocate %dth RX buffer\n", i);
2473 return error;
2474 }
2475 }
2476 bus_dmamap_sync(sc->sc_rxring_dtag, rd->rdata_dmap,
2477 BUS_DMASYNC_PREWRITE);
2478
2479 bwi_init_rxdesc_ring32(sc, rd->rdata_txrx_ctrl, rd->rdata_paddr,
2480 sizeof(struct bwi_rxbuf_hdr), BWI_RX_NDESC);
2481 return 0;
2482 }
2483
2484 static int
2485 bwi_init_txstats32(struct bwi_softc *sc)
2486 {
2487 struct bwi_txstats_data *st = sc->sc_txstats;
2488 bus_addr_t stats_paddr;
2489 int i;
2490
2491 bzero(st->stats, BWI_TXSTATS_NDESC * sizeof(struct bwi_txstats));
2492 bus_dmamap_sync(st->stats_dtag, st->stats_dmap, BUS_DMASYNC_PREWRITE);
2493
2494 st->stats_idx = 0;
2495
2496 stats_paddr = st->stats_paddr;
2497 for (i = 0; i < BWI_TXSTATS_NDESC; ++i) {
2498 bwi_setup_desc32(sc, st->stats_ring, BWI_TXSTATS_NDESC, i,
2499 stats_paddr, sizeof(struct bwi_txstats), 0);
2500 stats_paddr += sizeof(struct bwi_txstats);
2501 }
2502 bus_dmamap_sync(st->stats_ring_dtag, st->stats_ring_dmap,
2503 BUS_DMASYNC_PREWRITE);
2504
2505 bwi_init_rxdesc_ring32(sc, st->stats_ctrl_base,
2506 st->stats_ring_paddr, 0, BWI_TXSTATS_NDESC);
2507 return 0;
2508 }
2509
2510 static void
2511 bwi_setup_rx_desc32(struct bwi_softc *sc, int buf_idx, bus_addr_t paddr,
2512 int buf_len)
2513 {
2514 struct bwi_ring_data *rd = &sc->sc_rx_rdata;
2515
2516 KKASSERT(buf_idx < BWI_RX_NDESC);
2517 bwi_setup_desc32(sc, rd->rdata_desc, BWI_RX_NDESC, buf_idx,
2518 paddr, buf_len, 0);
2519 }
2520
2521 static void
2522 bwi_setup_tx_desc32(struct bwi_softc *sc, struct bwi_ring_data *rd,
2523 int buf_idx, bus_addr_t paddr, int buf_len)
2524 {
2525 KKASSERT(buf_idx < BWI_TX_NDESC);
2526 bwi_setup_desc32(sc, rd->rdata_desc, BWI_TX_NDESC, buf_idx,
2527 paddr, buf_len, 1);
2528 }
2529
2530 static int
2531 bwi_init_tx_ring64(struct bwi_softc *sc, int ring_idx)
2532 {
2533 /* TODO:64 */
2534 return EOPNOTSUPP;
2535 }
2536
2537 static int
2538 bwi_init_rx_ring64(struct bwi_softc *sc)
2539 {
2540 /* TODO:64 */
2541 return EOPNOTSUPP;
2542 }
2543
2544 static int
2545 bwi_init_txstats64(struct bwi_softc *sc)
2546 {
2547 /* TODO:64 */
2548 return EOPNOTSUPP;
2549 }
2550
2551 static void
2552 bwi_setup_rx_desc64(struct bwi_softc *sc, int buf_idx, bus_addr_t paddr,
2553 int buf_len)
2554 {
2555 /* TODO:64 */
2556 }
2557
2558 static void
2559 bwi_setup_tx_desc64(struct bwi_softc *sc, struct bwi_ring_data *rd,
2560 int buf_idx, bus_addr_t paddr, int buf_len)
2561 {
2562 /* TODO:64 */
2563 }
2564
2565 static void
2566 bwi_dma_buf_addr(void *arg, bus_dma_segment_t *seg, int nseg,
2567 bus_size_t mapsz __unused, int error)
2568 {
2569 if (!error) {
2570 KASSERT(nseg == 1, ("too many segments(%d)\n", nseg));
2571 *((bus_addr_t *)arg) = seg->ds_addr;
2572 }
2573 }
2574
2575 static int
2576 bwi_newbuf(struct bwi_softc *sc, int buf_idx, int init)
2577 {
2578 struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata;
2579 struct bwi_rxbuf *rxbuf = &rbd->rbd_buf[buf_idx];
2580 struct bwi_rxbuf_hdr *hdr;
2581 bus_dmamap_t map;
2582 bus_addr_t paddr;
2583 struct mbuf *m;
2584 int error;
2585
2586 KKASSERT(buf_idx < BWI_RX_NDESC);
2587
2588 m = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
2589 if (m == NULL) {
2590 error = ENOBUFS;
2591
2592 /*
2593 * If the NIC is up and running, we need to:
2594 * - Clear RX buffer's header.
2595 * - Restore RX descriptor settings.
2596 */
2597 if (init)
2598 return error;
2599 else
2600 goto back;
2601 }
2602 m->m_len = m->m_pkthdr.len = MCLBYTES;
2603
2604 /*
2605 * Try to load RX buf into temporary DMA map
2606 */
2607 error = bus_dmamap_load_mbuf(sc->sc_buf_dtag, rbd->rbd_tmp_dmap, m,
2608 bwi_dma_buf_addr, &paddr,
2609 init ? BUS_DMA_WAITOK : BUS_DMA_NOWAIT);
2610 if (error) {
2611 m_freem(m);
2612
2613 /*
2614 * See the comment above
2615 */
2616 if (init)
2617 return error;
2618 else
2619 goto back;
2620 }
2621
2622 if (!init)
2623 bus_dmamap_unload(sc->sc_buf_dtag, rxbuf->rb_dmap);
2624 rxbuf->rb_mbuf = m;
2625 rxbuf->rb_paddr = paddr;
2626
2627 /*
2628 * Swap RX buf's DMA map with the loaded temporary one
2629 */
2630 map = rxbuf->rb_dmap;
2631 rxbuf->rb_dmap = rbd->rbd_tmp_dmap;
2632 rbd->rbd_tmp_dmap = map;
2633
2634 back:
2635 /*
2636 * Clear RX buf header
2637 */
2638 hdr = mtod(rxbuf->rb_mbuf, struct bwi_rxbuf_hdr *);
2639 bzero(hdr, sizeof(*hdr));
2640 bus_dmamap_sync(sc->sc_buf_dtag, rxbuf->rb_dmap, BUS_DMASYNC_PREWRITE);
2641
2642 /*
2643 * Setup RX buf descriptor
2644 */
2645 sc->sc_setup_rxdesc(sc, buf_idx, rxbuf->rb_paddr,
2646 rxbuf->rb_mbuf->m_len - sizeof(*hdr));
2647 return error;
2648 }
2649
2650 static void
2651 bwi_set_addr_filter(struct bwi_softc *sc, uint16_t addr_ofs,
2652 const uint8_t *addr)
2653 {
2654 int i;
2655
2656 CSR_WRITE_2(sc, BWI_ADDR_FILTER_CTRL,
2657 BWI_ADDR_FILTER_CTRL_SET | addr_ofs);
2658
2659 for (i = 0; i < (IEEE80211_ADDR_LEN / 2); ++i) {
2660 uint16_t addr_val;
2661
2662 addr_val = (uint16_t)addr[i * 2] |
2663 (((uint16_t)addr[(i * 2) + 1]) << 8);
2664 CSR_WRITE_2(sc, BWI_ADDR_FILTER_DATA, addr_val);
2665 }
2666 }
2667
2668 static int
2669 bwi_set_chan(struct bwi_softc *sc, struct ieee80211_channel *c)
2670 {
2671 struct ieee80211com *ic = &sc->sc_ic;
2672 struct ifnet *ifp = &ic->ic_if;
2673 struct bwi_mac *mac;
2674 uint16_t flags;
2675 u_int chan;
2676
2677 ASSERT_SERIALIZED(ifp->if_serializer);
2678
2679 KKASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC);
2680 mac = (struct bwi_mac *)sc->sc_cur_regwin;
2681
2682 chan = ieee80211_chan2ieee(ic, c);
2683
2684 bwi_rf_set_chan(mac, chan, 0);
2685
2686 /*
2687 * Setup radio tap channel freq and flags
2688 */
2689 if (IEEE80211_IS_CHAN_G(c))
2690 flags = IEEE80211_CHAN_G;
2691 else
2692 flags = IEEE80211_CHAN_B;
2693
2694 sc->sc_tx_th.wt_chan_freq = sc->sc_rx_th.wr_chan_freq =
2695 htole16(c->ic_freq);
2696 sc->sc_tx_th.wt_chan_flags = sc->sc_rx_th.wr_chan_flags =
2697 htole16(flags);
2698
2699 return 0;
2700 }
2701
2702 static void
2703 bwi_next_scan(void *xsc)
2704 {
2705 struct bwi_softc *sc = xsc;
2706 struct ieee80211com *ic = &sc->sc_ic;
2707 struct ifnet *ifp = &ic->ic_if;
2708
2709 lwkt_serialize_enter(ifp->if_serializer);
2710
2711 if (ic->ic_state == IEEE80211_S_SCAN)
2712 ieee80211_next_scan(ic);
2713
2714 lwkt_serialize_exit(ifp->if_serializer);
2715 }
2716
2717 static int
2718 bwi_rxeof(struct bwi_softc *sc, int end_idx)
2719 {
2720 struct bwi_ring_data *rd = &sc->sc_rx_rdata;
2721 struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata;
2722 struct ieee80211com *ic = &sc->sc_ic;
2723 struct ifnet *ifp = &ic->ic_if;
2724 int idx, rx_data = 0;
2725
2726 idx = rbd->rbd_idx;
2727 while (idx != end_idx) {
2728 struct bwi_rxbuf *rb = &rbd->rbd_buf[idx];
2729 struct bwi_rxbuf_hdr *hdr;
2730 struct ieee80211_frame_min *wh;
2731 struct ieee80211_node *ni;
2732 struct mbuf *m;
2733 const void *plcp;
2734 uint16_t flags2;
2735 int buflen, wh_ofs, hdr_extra, rssi, type, rate;
2736
2737 m = rb->rb_mbuf;
2738 bus_dmamap_sync(sc->sc_buf_dtag, rb->rb_dmap,
2739 BUS_DMASYNC_POSTREAD);
2740
2741 if (bwi_newbuf(sc, idx, 0)) {
2742 ifp->if_ierrors++;
2743 goto next;
2744 }
2745
2746 hdr = mtod(m, struct bwi_rxbuf_hdr *);
2747 flags2 = le16toh(hdr->rxh_flags2);
2748
2749 hdr_extra = 0;
2750 if (flags2 & BWI_RXH_F2_TYPE2FRAME)
2751 hdr_extra = 2;
2752 wh_ofs = hdr_extra + 6; /* XXX magic number */
2753
2754 buflen = le16toh(hdr->rxh_buflen);
2755 if (buflen < BWI_FRAME_MIN_LEN(wh_ofs)) {
2756 if_printf(ifp, "short frame %d, hdr_extra %d\n",
2757 buflen, hdr_extra);
2758 ifp->if_ierrors++;
2759 m_freem(m);
2760 goto next;
2761 }
2762
2763 plcp = ((const uint8_t *)(hdr + 1) + hdr_extra);
2764 rssi = bwi_calc_rssi(sc, hdr);
2765
2766 m->m_pkthdr.rcvif = ifp;
2767 m->m_len = m->m_pkthdr.len = buflen + sizeof(*hdr);
2768 m_adj(m, sizeof(*hdr) + wh_ofs);
2769
2770 if (htole16(hdr->rxh_flags1) & BWI_RXH_F1_OFDM)
2771 rate = bwi_ofdm_plcp2rate(plcp);
2772 else
2773 rate = bwi_ds_plcp2rate(plcp);
2774
2775 /* RX radio tap */
2776 if (sc->sc_drvbpf != NULL)
2777 bwi_rx_radiotap(sc, m, hdr, plcp, rate, rssi);
2778
2779 m_adj(m, -IEEE80211_CRC_LEN);
2780
2781 wh = mtod(m, struct ieee80211_frame_min *);
2782 ni = ieee80211_find_rxnode(ic, wh);
2783
2784 type = ieee80211_input(ic, m, ni, rssi - BWI_NOISE_FLOOR,
2785 le16toh(hdr->rxh_tsf));
2786 ieee80211_free_node(ni);
2787
2788 if (type == IEEE80211_FC0_TYPE_DATA) {
2789 rx_data = 1;
2790 sc->sc_rx_rate = rate;
2791 }
2792 next:
2793 idx = (idx + 1) % BWI_RX_NDESC;
2794 }
2795
2796 rbd->rbd_idx = idx;
2797 bus_dmamap_sync(sc->sc_rxring_dtag, rd->rdata_dmap,
2798 BUS_DMASYNC_PREWRITE);
2799 return rx_data;
2800 }
2801
2802 static int
2803 bwi_rxeof32(struct bwi_softc *sc)
2804 {
2805 uint32_t val, rx_ctrl;
2806 int end_idx, rx_data;
2807
2808 rx_ctrl = sc->sc_rx_rdata.rdata_txrx_ctrl;
2809
2810 val = CSR_READ_4(sc, rx_ctrl + BWI_RX32_STATUS);
2811 end_idx = __SHIFTOUT(val, BWI_RX32_STATUS_INDEX_MASK) /
2812 sizeof(struct bwi_desc32);
2813
2814 rx_data = bwi_rxeof(sc, end_idx);
2815
2816 CSR_WRITE_4(sc, rx_ctrl + BWI_RX32_INDEX,
2817 end_idx * sizeof(struct bwi_desc32));
2818
2819 return rx_data;
2820 }
2821
2822 static int
2823 bwi_rxeof64(struct bwi_softc *sc)
2824 {
2825 /* TODO:64 */
2826 return 0;
2827 }
2828
2829 static void
2830 bwi_reset_rx_ring32(struct bwi_softc *sc, uint32_t rx_ctrl)
2831 {
2832 int i;
2833
2834 CSR_WRITE_4(sc, rx_ctrl + BWI_RX32_CTRL, 0);
2835
2836 #define NRETRY 10
2837
2838 for (i = 0; i < NRETRY; ++i) {
2839 uint32_t status;
2840
2841 status = CSR_READ_4(sc, rx_ctrl + BWI_RX32_STATUS);
2842 if (__SHIFTOUT(status, BWI_RX32_STATUS_STATE_MASK) ==
2843 BWI_RX32_STATUS_STATE_DISABLED)
2844 break;
2845
2846 DELAY(1000);
2847 }
2848 if (i == NRETRY)
2849 if_printf(&sc->sc_ic.ic_if, "reset rx ring timedout\n");
2850
2851 #undef NRETRY
2852
2853 CSR_WRITE_4(sc, rx_ctrl + BWI_RX32_RINGINFO, 0);
2854 }
2855
2856 static void
2857 bwi_free_txstats32(struct bwi_softc *sc)
2858 {
2859 bwi_reset_rx_ring32(sc, sc->sc_txstats->stats_ctrl_base);
2860 }
2861
2862 static void
2863 bwi_free_rx_ring32(struct bwi_softc *sc)
2864 {
2865 struct bwi_ring_data *rd = &sc->sc_rx_rdata;
2866 struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata;
2867 int i;
2868
2869 bwi_reset_rx_ring32(sc, rd->rdata_txrx_ctrl);
2870
2871 for (i = 0; i < BWI_RX_NDESC; ++i) {
2872 struct bwi_rxbuf *rb = &rbd->rbd_buf[i];
2873
2874 if (rb->rb_mbuf != NULL) {
2875 bus_dmamap_unload(sc->sc_buf_dtag, rb->rb_dmap);
2876 m_freem(rb->rb_mbuf);
2877 rb->rb_mbuf = NULL;
2878 }
2879 }
2880 }
2881
2882 static void
2883 bwi_free_tx_ring32(struct bwi_softc *sc, int ring_idx)
2884 {
2885 struct bwi_ring_data *rd;
2886 struct bwi_txbuf_data *tbd;
2887 struct ifnet *ifp = &sc->sc_ic.ic_if;
2888 uint32_t state, val;
2889 int i;
2890
2891 KKASSERT(ring_idx < BWI_TX_NRING);
2892 rd = &sc->sc_tx_rdata[ring_idx];
2893 tbd = &sc->sc_tx_bdata[ring_idx];
2894
2895 #define NRETRY 10
2896
2897 for (i = 0; i < NRETRY; ++i) {
2898 val = CSR_READ_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_STATUS);
2899 state = __SHIFTOUT(val, BWI_TX32_STATUS_STATE_MASK);
2900 if (state == BWI_TX32_STATUS_STATE_DISABLED ||
2901 state == BWI_TX32_STATUS_STATE_IDLE ||
2902 state == BWI_TX32_STATUS_STATE_STOPPED)
2903 break;
2904
2905 DELAY(1000);
2906 }
2907 if (i == NRETRY) {
2908 if_printf(ifp, "wait for TX ring(%d) stable timed out\n",
2909 ring_idx);
2910 }
2911
2912 CSR_WRITE_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_CTRL, 0);
2913 for (i = 0; i < NRETRY; ++i) {
2914 val = CSR_READ_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_STATUS);
2915 state = __SHIFTOUT(val, BWI_TX32_STATUS_STATE_MASK);
2916 if (state == BWI_TX32_STATUS_STATE_DISABLED)
2917 break;
2918
2919 DELAY(1000);
2920 }
2921 if (i == NRETRY)
2922 if_printf(ifp, "reset TX ring (%d) timed out\n", ring_idx);
2923
2924 #undef NRETRY
2925
2926 DELAY(1000);
2927
2928 CSR_WRITE_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_RINGINFO, 0);
2929
2930 for (i = 0; i < BWI_TX_NDESC; ++i) {
2931 struct bwi_txbuf *tb = &tbd->tbd_buf[i];
2932
2933 if (tb->tb_mbuf != NULL) {
2934 bus_dmamap_unload(sc->sc_buf_dtag, tb->tb_dmap);
2935 m_freem(tb->tb_mbuf);
2936 tb->tb_mbuf = NULL;
2937 }
2938 if (tb->tb_ni != NULL) {
2939 ieee80211_free_node(tb->tb_ni);
2940 tb->tb_ni = NULL;
2941 }
2942 }
2943 }
2944
2945 static void
2946 bwi_free_txstats64(struct bwi_softc *sc)
2947 {
2948 /* TODO:64 */
2949 }
2950
2951 static void
2952 bwi_free_rx_ring64(struct bwi_softc *sc)
2953 {
2954 /* TODO:64 */
2955 }
2956
2957 static void
2958 bwi_free_tx_ring64(struct bwi_softc *sc, int ring_idx)
2959 {
2960 /* TODO:64 */
2961 }
2962
2963 static int
2964 bwi_encap(struct bwi_softc *sc, int idx, struct mbuf *m,
2965 struct ieee80211_node **ni0, int mgt_pkt)
2966 {
2967 struct ieee80211com *ic = &sc->sc_ic;
2968 struct ieee80211_node *ni = *ni0;
2969 struct bwi_ring_data *rd = &sc->sc_tx_rdata[BWI_TX_DATA_RING];
2970 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[BWI_TX_DATA_RING];
2971 struct bwi_txbuf *tb = &tbd->tbd_buf[idx];
2972 struct bwi_mac *mac;
2973 struct bwi_txbuf_hdr *hdr;
2974 struct ieee80211_frame *wh;
2975 uint8_t rate, rate_fb;
2976 uint32_t mac_ctrl;
2977 uint16_t phy_ctrl;
2978 bus_addr_t paddr;
2979 int pkt_len, error, mcast_pkt = 0;
2980 #if 0
2981 const uint8_t *p;
2982 int i;
2983 #endif
2984
2985 KKASSERT(ni != NULL);
2986 KKASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC);
2987 mac = (struct bwi_mac *)sc->sc_cur_regwin;
2988
2989 wh = mtod(m, struct ieee80211_frame *);
2990
2991 /* Get 802.11 frame len before prepending TX header */
2992 pkt_len = m->m_pkthdr.len + IEEE80211_CRC_LEN;
2993
2994 /*
2995 * Find TX rate
2996 */
2997 bzero(tb->tb_rateidx, sizeof(tb->tb_rateidx));
2998 if (!mgt_pkt) {
2999 if (ic->ic_fixed_rate != IEEE80211_FIXED_RATE_NONE) {
3000 int idx;
3001
3002 rate = IEEE80211_RS_RATE(&ni->ni_rates,
3003 ic->ic_fixed_rate);
3004
3005 if (ic->ic_fixed_rate >= 1)
3006 idx = ic->ic_fixed_rate - 1;
3007 else
3008 idx = 0;
3009 rate_fb = IEEE80211_RS_RATE(&ni->ni_rates, idx);
3010 } else {
3011 tb->tb_rateidx_cnt = ieee80211_ratectl_findrate(ni,
3012 m->m_pkthdr.len, tb->tb_rateidx, BWI_NTXRATE);
3013
3014 rate = IEEE80211_RS_RATE(&ni->ni_rates,
3015 tb->tb_rateidx[0]);
3016 if (tb->tb_rateidx_cnt == BWI_NTXRATE) {
3017 rate_fb = IEEE80211_RS_RATE(&ni->ni_rates,
3018 tb->tb_rateidx[1]);
3019 } else {
3020 rate_fb = rate;
3021 }
3022 tb->tb_buflen = m->m_pkthdr.len;
3023 }
3024 } else {
3025 /* Fixed at 1Mbits/s for mgt frames */
3026 rate = rate_fb = (1 * 2);
3027 }
3028
3029 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) {
3030 rate = rate_fb = ic->ic_mcast_rate;
3031 mcast_pkt = 1;
3032 }
3033
3034 if (rate == 0 || rate_fb == 0) {
3035 /* XXX this should not happen */
3036 if_printf(&ic->ic_if, "invalid rate %u or fallback rate %u",
3037 rate, rate_fb);
3038 rate = rate_fb = (1 * 2); /* Force 1Mbits/s */
3039 }
3040 sc->sc_tx_rate = rate;
3041
3042 /*
3043 * TX radio tap
3044 */
3045 if (sc->sc_drvbpf != NULL) {
3046 sc->sc_tx_th.wt_flags = 0;
3047 if (wh->i_fc[1] & IEEE80211_FC1_WEP)
3048 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_WEP;
3049 if (ieee80211_rate2modtype(rate) == IEEE80211_MODTYPE_DS &&
3050 (ic->ic_flags & IEEE80211_F_SHPREAMBLE) &&
3051 rate != (1 * 2)) {
3052 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE;
3053 }
3054 sc->sc_tx_th.wt_rate = rate;
3055
3056 bpf_ptap(sc->sc_drvbpf, m, &sc->sc_tx_th, sc->sc_tx_th_len);
3057 }
3058
3059 /*
3060 * Setup the embedded TX header
3061 */
3062 M_PREPEND(m, sizeof(*hdr), MB_DONTWAIT);
3063 if (m == NULL) {
3064 if_printf(&ic->ic_if, "prepend TX header failed\n");
3065 return ENOBUFS;
3066 }
3067 hdr = mtod(m, struct bwi_txbuf_hdr *);
3068
3069 bzero(hdr, sizeof(*hdr));
3070
3071 bcopy(wh->i_fc, hdr->txh_fc, sizeof(hdr->txh_fc));
3072 bcopy(wh->i_addr1, hdr->txh_addr1, sizeof(hdr->txh_addr1));
3073
3074 if (!mcast_pkt) {
3075 uint16_t dur;
3076 uint8_t ack_rate;
3077
3078 ack_rate = ieee80211_ack_rate(ni, rate_fb);
3079 dur = ieee80211_txtime(ni,
3080 sizeof(struct ieee80211_frame_ack) + IEEE80211_CRC_LEN,
3081 ack_rate, ic->ic_flags & ~IEEE80211_F_SHPREAMBLE);
3082
3083 hdr->txh_fb_duration = htole16(dur);
3084 }
3085
3086 hdr->txh_id = __SHIFTIN(BWI_TX_DATA_RING, BWI_TXH_ID_RING_MASK) |
3087 __SHIFTIN(idx, BWI_TXH_ID_IDX_MASK);
3088
3089 bwi_plcp_header(hdr->txh_plcp, pkt_len, rate);
3090 bwi_plcp_header(hdr->txh_fb_plcp, pkt_len, rate_fb);
3091
3092 phy_ctrl = __SHIFTIN(mac->mac_rf.rf_ant_mode,
3093 BWI_TXH_PHY_C_ANTMODE_MASK);
3094 if (ieee80211_rate2modtype(rate) == IEEE80211_MODTYPE_OFDM)
3095 phy_ctrl |= BWI_TXH_PHY_C_OFDM;
3096 else if ((ic->ic_flags & IEEE80211_F_SHPREAMBLE) && rate != (2 * 1))
3097 phy_ctrl |= BWI_TXH_PHY_C_SHPREAMBLE;
3098
3099 mac_ctrl = BWI_TXH_MAC_C_HWSEQ | BWI_TXH_MAC_C_FIRST_FRAG;
3100 if (!IEEE80211_IS_MULTICAST(wh->i_addr1))
3101 mac_ctrl |= BWI_TXH_MAC_C_ACK;
3102 if (ieee80211_rate2modtype(rate_fb) == IEEE80211_MODTYPE_OFDM)
3103 mac_ctrl |= BWI_TXH_MAC_C_FB_OFDM;
3104
3105 hdr->txh_mac_ctrl = htole32(mac_ctrl);
3106 hdr->txh_phy_ctrl = htole16(phy_ctrl);
3107
3108 /* Catch any further usage */
3109 hdr = NULL;
3110 wh = NULL;
3111
3112 /* DMA load */
3113 error = bus_dmamap_load_mbuf(sc->sc_buf_dtag, tb->tb_dmap, m,
3114 bwi_dma_buf_addr, &paddr, BUS_DMA_NOWAIT);
3115 if (error && error != EFBIG) {
3116 if_printf(&ic->ic_if, "can't load TX buffer (1) %d\n", error);
3117 goto back;
3118 }
3119
3120 if (error) { /* error == EFBIG */
3121 struct mbuf *m_new;
3122
3123 m_new = m_defrag(m, MB_DONTWAIT);
3124 if (m_new == NULL) {
3125 if_printf(&ic->ic_if, "can't defrag TX buffer\n");
3126 error = ENOBUFS;
3127 goto back;
3128 } else {
3129 m = m_new;
3130 }
3131
3132 error = bus_dmamap_load_mbuf(sc->sc_buf_dtag, tb->tb_dmap, m,
3133 bwi_dma_buf_addr, &paddr,
3134 BUS_DMA_NOWAIT);
3135 if (error) {
3136 if_printf(&ic->ic_if, "can't load TX buffer (2) %d\n",
3137 error);
3138 goto back;
3139 }
3140 }
3141 error = 0;
3142
3143 bus_dmamap_sync(sc->sc_buf_dtag, tb->tb_dmap, BUS_DMASYNC_PREWRITE);
3144
3145 if (mgt_pkt || mcast_pkt) {
3146 /* Don't involve mcast/mgt packets into TX rate control */
3147 ieee80211_free_node(ni);
3148 *ni0 = ni = NULL;
3149 }
3150 tb->tb_mbuf = m;
3151 tb->tb_ni = ni;
3152
3153 #if 0
3154 p = mtod(m, const uint8_t *);
3155 for (i = 0; i < m->m_pkthdr.len; ++i) {
3156 if (i != 0 && i % 8 == 0)
3157 kprintf("\n");
3158 kprintf("%02x ", p[i]);
3159 }
3160 kprintf("\n");
3161 #endif
3162
3163 DPRINTF(sc, BWI_DBG_TX, "idx %d, pkt_len %d, buflen %d\n",
3164 idx, pkt_len, m->m_pkthdr.len);
3165
3166 /* Setup TX descriptor */
3167 sc->sc_setup_txdesc(sc, rd, idx, paddr, m->m_pkthdr.len);
3168 bus_dmamap_sync(sc->sc_txring_dtag, rd->rdata_dmap,
3169 BUS_DMASYNC_PREWRITE);
3170
3171 /* Kick start */
3172 sc->sc_start_tx(sc, rd->rdata_txrx_ctrl, idx);
3173
3174 back:
3175 if (error)
3176 m_freem(m);
3177 return error;
3178 }
3179
3180 static void
3181 bwi_start_tx32(struct bwi_softc *sc, uint32_t tx_ctrl, int idx)
3182 {
3183 idx = (idx + 1) % BWI_TX_NDESC;
3184 CSR_WRITE_4(sc, tx_ctrl + BWI_TX32_INDEX,
3185 idx * sizeof(struct bwi_desc32));
3186 }
3187
3188 static void
3189 bwi_start_tx64(struct bwi_softc *sc, uint32_t tx_ctrl, int idx)
3190 {
3191 /* TODO:64 */
3192 }
3193
3194 static void
3195 bwi_txeof_status32(struct bwi_softc *sc)
3196 {
3197 struct ifnet *ifp = &sc->sc_ic.ic_if;
3198 uint32_t val, ctrl_base;
3199 int end_idx;
3200
3201 ctrl_base = sc->sc_txstats->stats_ctrl_base;
3202
3203 val = CSR_READ_4(sc, ctrl_base + BWI_RX32_STATUS);
3204 end_idx = __SHIFTOUT(val, BWI_RX32_STATUS_INDEX_MASK) /
3205 sizeof(struct bwi_desc32);
3206
3207 bwi_txeof_status(sc, end_idx);
3208
3209 CSR_WRITE_4(sc, ctrl_base + BWI_RX32_INDEX,
3210 end_idx * sizeof(struct bwi_desc32));
3211
3212 if ((ifp->if_flags & IFF_OACTIVE) == 0)
3213 ifp->if_start(ifp);
3214 }
3215
3216 static void
3217 bwi_txeof_status64(struct bwi_softc *sc)
3218 {
3219 /* TODO:64 */
3220 }
3221
3222 static void
3223 _bwi_txeof(struct bwi_softc *sc, uint16_t tx_id, int acked, int data_txcnt)
3224 {
3225 struct ifnet *ifp = &sc->sc_ic.ic_if;
3226 struct bwi_txbuf_data *tbd;
3227 struct bwi_txbuf *tb;
3228 int ring_idx, buf_idx;
3229
3230 if (tx_id == 0) {
3231 if_printf(ifp, "zero tx id\n");
3232 return;
3233 }
3234
3235 ring_idx = __SHIFTOUT(tx_id, BWI_TXH_ID_RING_MASK);
3236 buf_idx = __SHIFTOUT(tx_id, BWI_TXH_ID_IDX_MASK);
3237
3238 KKASSERT(ring_idx == BWI_TX_DATA_RING);
3239 KKASSERT(buf_idx < BWI_TX_NDESC);
3240
3241 tbd = &sc->sc_tx_bdata[ring_idx];
3242 KKASSERT(tbd->tbd_used > 0);
3243 tbd->tbd_used--;
3244
3245 tb = &tbd->tbd_buf[buf_idx];
3246
3247 DPRINTF(sc, BWI_DBG_TXEOF, "txeof idx %d, "
3248 "acked %d, data_txcnt %d, ni %p\n",
3249 buf_idx, acked, data_txcnt, tb->tb_ni);
3250
3251 bus_dmamap_unload(sc->sc_buf_dtag, tb->tb_dmap);
3252 m_freem(tb->tb_mbuf);
3253 tb->tb_mbuf = NULL;
3254
3255 if (tb->tb_ni != NULL) {
3256 struct ieee80211_ratectl_res res[BWI_NTXRATE];
3257 int res_len, retry;
3258
3259 if (data_txcnt <= BWI_SHRETRY_FB || tb->tb_rateidx_cnt == 1) {
3260 res_len = 1;
3261 res[0].rc_res_rateidx = tb->tb_rateidx[0];
3262 res[0].rc_res_tries = data_txcnt;
3263 } else {
3264 res_len = BWI_NTXRATE;
3265 res[0].rc_res_rateidx = tb->tb_rateidx[0];
3266 res[0].rc_res_tries = BWI_SHRETRY_FB;
3267 res[1].rc_res_rateidx = tb->tb_rateidx[1];
3268 res[1].rc_res_tries = data_txcnt - BWI_SHRETRY_FB;
3269 }
3270
3271 if (acked)
3272 retry = data_txcnt > 0 ? data_txcnt - 1 : 0;
3273 else
3274 retry = data_txcnt;
3275
3276 ieee80211_ratectl_tx_complete(tb->tb_ni, tb->tb_buflen,
3277 res, res_len, retry, 0, !acked);
3278
3279 ieee80211_free_node(tb->tb_ni);
3280 tb->tb_ni = NULL;
3281 }
3282
3283 if (tbd->tbd_used == 0)
3284 sc->sc_tx_timer = 0;
3285
3286 ifp->if_flags &= ~IFF_OACTIVE;
3287 }
3288
3289 static void
3290 bwi_txeof_status(struct bwi_softc *sc, int end_idx)
3291 {
3292 struct bwi_txstats_data *st = sc->sc_txstats;
3293 int idx;
3294
3295 bus_dmamap_sync(st->stats_dtag, st->stats_dmap, BUS_DMASYNC_POSTREAD);
3296
3297 idx = st->stats_idx;
3298 while (idx != end_idx) {
3299 const struct bwi_txstats *stats = &st->stats[idx];
3300
3301 if ((stats->txs_flags & BWI_TXS_F_PENDING) == 0) {
3302 int data_txcnt;
3303
3304 data_txcnt = __SHIFTOUT(stats->txs_txcnt,
3305 BWI_TXS_TXCNT_DATA);
3306 _bwi_txeof(sc, le16toh(stats->txs_id),
3307 stats->txs_flags & BWI_TXS_F_ACKED,
3308 data_txcnt);
3309 }
3310 idx = (idx + 1) % BWI_TXSTATS_NDESC;
3311 }
3312 st->stats_idx = idx;
3313 }
3314
3315 static void
3316 bwi_txeof(struct bwi_softc *sc)
3317 {
3318 struct ifnet *ifp = &sc->sc_ic.ic_if;
3319
3320 for (;;) {
3321 uint32_t tx_status0, tx_status1;
3322 uint16_t tx_id;
3323 int data_txcnt;
3324
3325 tx_status0 = CSR_READ_4(sc, BWI_TXSTATUS0);
3326 if ((tx_status0 & BWI_TXSTATUS0_VALID) == 0)
3327 break;
3328 tx_status1 = CSR_READ_4(sc, BWI_TXSTATUS1);
3329
3330 tx_id = __SHIFTOUT(tx_status0, BWI_TXSTATUS0_TXID_MASK);
3331 data_txcnt = __SHIFTOUT(tx_status0,
3332 BWI_TXSTATUS0_DATA_TXCNT_MASK);
3333
3334 if (tx_status0 & (BWI_TXSTATUS0_AMPDU | BWI_TXSTATUS0_PENDING))
3335 continue;
3336
3337 _bwi_txeof(sc, tx_id, tx_status0 & BWI_TXSTATUS0_ACKED,
3338 data_txcnt);
3339 }
3340
3341 if ((ifp->if_flags & IFF_OACTIVE) == 0)
3342 ifp->if_start(ifp);
3343 }
3344
3345 static int
3346 bwi_bbp_power_on(struct bwi_softc *sc, enum bwi_clock_mode clk_mode)
3347 {
3348 bwi_power_on(sc, 1);
3349 return bwi_set_clock_mode(sc, clk_mode);
3350 }
3351
3352 static void
3353 bwi_bbp_power_off(struct bwi_softc *sc)
3354 {
3355 bwi_set_clock_mode(sc, BWI_CLOCK_MODE_SLOW);
3356 bwi_power_off(sc, 1);
3357 }
3358
3359 static int
3360 bwi_get_pwron_delay(struct bwi_softc *sc)
3361 {
3362 struct bwi_regwin *com, *old;
3363 struct bwi_clock_freq freq;
3364 uint32_t val;
3365 int error;
3366
3367 com = &sc->sc_com_regwin;
3368 KKASSERT(BWI_REGWIN_EXIST(com));
3369
3370 if ((sc->sc_cap & BWI_CAP_CLKMODE) == 0)
3371 return 0;
3372
3373 error = bwi_regwin_switch(sc, com, &old);
3374 if (error)
3375 return error;
3376
3377 bwi_get_clock_freq(sc, &freq);
3378
3379 val = CSR_READ_4(sc, BWI_PLL_ON_DELAY);
3380 sc->sc_pwron_delay = howmany((val + 2) * 1000000, freq.clkfreq_min);
3381 DPRINTF(sc, BWI_DBG_ATTACH, "power on delay %u\n", sc->sc_pwron_delay);
3382
3383 return bwi_regwin_switch(sc, old, NULL);
3384 }
3385
3386 static int
3387 bwi_bus_attach(struct bwi_softc *sc)
3388 {
3389 struct bwi_regwin *bus, *old;
3390 int error;
3391
3392 bus = &sc->sc_bus_regwin;
3393
3394 error = bwi_regwin_switch(sc, bus, &old);
3395 if (error)
3396 return error;
3397
3398 if (!bwi_regwin_is_enabled(sc, bus))
3399 bwi_regwin_enable(sc, bus, 0);
3400
3401 /* Disable interripts */
3402 CSR_WRITE_4(sc, BWI_INTRVEC, 0);
3403
3404 return bwi_regwin_switch(sc, old, NULL);
3405 }
3406
3407 static const char *
3408 bwi_regwin_name(const struct bwi_regwin *rw)
3409 {
3410 switch (rw->rw_type) {
3411 case BWI_REGWIN_T_COM:
3412 return "COM";
3413 case BWI_REGWIN_T_BUSPCI:
3414 return "PCI";
3415 case BWI_REGWIN_T_MAC:
3416 return "MAC";
3417 case BWI_REGWIN_T_BUSPCIE:
3418 return "PCIE";
3419 }
3420 panic("unknown regwin type 0x%04x\n", rw->rw_type);
3421 return NULL;
3422 }
3423
3424 static uint32_t
3425 bwi_regwin_disable_bits(struct bwi_softc *sc)
3426 {
3427 uint32_t busrev;
3428
3429 /* XXX cache this */
3430 busrev = __SHIFTOUT(CSR_READ_4(sc, BWI_ID_LO), BWI_ID_LO_BUSREV_MASK);
3431 DPRINTF(sc, BWI_DBG_ATTACH | BWI_DBG_INIT | BWI_DBG_MISC,
3432 "bus rev %u\n", busrev);
3433
3434 if (busrev == BWI_BUSREV_0)
3435 return BWI_STATE_LO_DISABLE1;
3436 else if (busrev == BWI_BUSREV_1)
3437 return BWI_STATE_LO_DISABLE2;
3438 else
3439 return (BWI_STATE_LO_DISABLE1 | BWI_STATE_LO_DISABLE2);
3440 }
3441
3442 int
3443 bwi_regwin_is_enabled(struct bwi_softc *sc, struct bwi_regwin *rw)
3444 {
3445 uint32_t val, disable_bits;
3446
3447 disable_bits = bwi_regwin_disable_bits(sc);
3448 val = CSR_READ_4(sc, BWI_STATE_LO);
3449
3450 if ((val & (BWI_STATE_LO_CLOCK |
3451 BWI_STATE_LO_RESET |
3452 disable_bits)) == BWI_STATE_LO_CLOCK) {
3453 DPRINTF(sc, BWI_DBG_ATTACH | BWI_DBG_INIT, "%s is enabled\n",
3454 bwi_regwin_name(rw));
3455 return 1;
3456 } else {
3457 DPRINTF(sc, BWI_DBG_ATTACH | BWI_DBG_INIT, "%s is disabled\n",
3458 bwi_regwin_name(rw));
3459 return 0;
3460 }
3461 }
3462
3463 void
3464 bwi_regwin_disable(struct bwi_softc *sc, struct bwi_regwin *rw, uint32_t flags)
3465 {
3466 uint32_t state_lo, disable_bits;
3467 int i;
3468
3469 state_lo = CSR_READ_4(sc, BWI_STATE_LO);
3470
3471 /*
3472 * If current regwin is in 'reset' state, it was already disabled.
3473 */
3474 if (state_lo & BWI_STATE_LO_RESET) {
3475 DPRINTF(sc, BWI_DBG_ATTACH | BWI_DBG_INIT,
3476 "%s was already disabled\n", bwi_regwin_name(rw));
3477 return;
3478 }
3479
3480 disable_bits = bwi_regwin_disable_bits(sc);
3481
3482 /*
3483 * Disable normal clock
3484 */
3485 state_lo = BWI_STATE_LO_CLOCK | disable_bits;
3486 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo);
3487
3488 /*
3489 * Wait until normal clock is disabled
3490 */
3491 #define NRETRY 1000
3492 for (i = 0; i < NRETRY; ++i) {
3493 state_lo = CSR_READ_4(sc, BWI_STATE_LO);
3494 if (state_lo & disable_bits)
3495 break;
3496 DELAY(10);
3497 }
3498 if (i == NRETRY) {
3499 device_printf(sc->sc_dev, "%s disable clock timeout\n",
3500 bwi_regwin_name(rw));
3501 }
3502
3503 for (i = 0; i < NRETRY; ++i) {
3504 uint32_t state_hi;
3505
3506 state_hi = CSR_READ_4(sc, BWI_STATE_HI);
3507 if ((state_hi & BWI_STATE_HI_BUSY) == 0)
3508 break;
3509 DELAY(10);
3510 }
3511 if (i == NRETRY) {
3512 device_printf(sc->sc_dev, "%s wait BUSY unset timeout\n",
3513 bwi_regwin_name(rw));
3514 }
3515 #undef NRETRY
3516
3517 /*
3518 * Reset and disable regwin with gated clock
3519 */
3520 state_lo = BWI_STATE_LO_RESET | disable_bits |
3521 BWI_STATE_LO_CLOCK | BWI_STATE_LO_GATED_CLOCK |
3522 __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK);
3523 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo);
3524
3525 /* Flush pending bus write */
3526 CSR_READ_4(sc, BWI_STATE_LO);
3527 DELAY(1);
3528
3529 /* Reset and disable regwin */
3530 state_lo = BWI_STATE_LO_RESET | disable_bits |
3531 __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK);
3532 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo);
3533
3534 /* Flush pending bus write */
3535 CSR_READ_4(sc, BWI_STATE_LO);
3536 DELAY(1);
3537 }
3538
3539 void
3540 bwi_regwin_enable(struct bwi_softc *sc, struct bwi_regwin *rw, uint32_t flags)
3541 {
3542 uint32_t state_lo, state_hi, imstate;
3543
3544 bwi_regwin_disable(sc, rw, flags);
3545
3546 /* Reset regwin with gated clock */
3547 state_lo = BWI_STATE_LO_RESET |
3548 BWI_STATE_LO_CLOCK |
3549 BWI_STATE_LO_GATED_CLOCK |
3550 __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK);
3551 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo);
3552
3553 /* Flush pending bus write */
3554 CSR_READ_4(sc, BWI_STATE_LO);
3555 DELAY(1);
3556
3557 state_hi = CSR_READ_4(sc, BWI_STATE_HI);
3558 if (state_hi & BWI_STATE_HI_SERROR)
3559 CSR_WRITE_4(sc, BWI_STATE_HI, 0);
3560
3561 imstate = CSR_READ_4(sc, BWI_IMSTATE);
3562 if (imstate & (BWI_IMSTATE_INBAND_ERR | BWI_IMSTATE_TIMEOUT)) {
3563 imstate &= ~(BWI_IMSTATE_INBAND_ERR | BWI_IMSTATE_TIMEOUT);
3564 CSR_WRITE_4(sc, BWI_IMSTATE, imstate);
3565 }
3566
3567 /* Enable regwin with gated clock */
3568 state_lo = BWI_STATE_LO_CLOCK |
3569 BWI_STATE_LO_GATED_CLOCK |
3570 __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK);
3571 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo);
3572
3573 /* Flush pending bus write */
3574 CSR_READ_4(sc, BWI_STATE_LO);
3575 DELAY(1);
3576
3577 /* Enable regwin with normal clock */
3578 state_lo = BWI_STATE_LO_CLOCK |
3579 __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK);
3580 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo);
3581
3582 /* Flush pending bus write */
3583 CSR_READ_4(sc, BWI_STATE_LO);
3584 DELAY(1);
3585 }
3586
3587 static void
3588 bwi_set_bssid(struct bwi_softc *sc, const uint8_t *bssid)
3589 {
3590 struct ieee80211com *ic = &sc->sc_ic;
3591 struct bwi_mac *mac;
3592 struct bwi_myaddr_bssid buf;
3593 const uint8_t *p;
3594 uint32_t val;
3595 int n, i;
3596
3597 KKASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC);
3598 mac = (struct bwi_mac *)sc->sc_cur_regwin;
3599
3600 bwi_set_addr_filter(sc, BWI_ADDR_FILTER_BSSID, bssid);
3601
3602 bcopy(ic->ic_myaddr, buf.myaddr, sizeof(buf.myaddr));
3603 bcopy(bssid, buf.bssid, sizeof(buf.bssid));
3604
3605 n = sizeof(buf) / sizeof(val);
3606 p = (const uint8_t *)&buf;
3607 for (i = 0; i < n; ++i) {
3608 int j;
3609
3610 val = 0;
3611 for (j = 0; j < sizeof(val); ++j)
3612 val |= ((uint32_t)(*p++)) << (j * 8);
3613
3614 TMPLT_WRITE_4(mac, 0x20 + (i * sizeof(val)), val);
3615 }
3616 }
3617
3618 static void
3619 bwi_updateslot(struct ifnet *ifp)
3620 {
3621 struct bwi_softc *sc = ifp->if_softc;
3622 struct ieee80211com *ic = &sc->sc_ic;
3623 struct bwi_mac *mac;
3624
3625 if ((ifp->if_flags & IFF_RUNNING) == 0)
3626 return;
3627
3628 ASSERT_SERIALIZED(ifp->if_serializer);
3629
3630 DPRINTF(sc, BWI_DBG_80211, "%s\n", __func__);
3631
3632 KKASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC);
3633 mac = (struct bwi_mac *)sc->sc_cur_regwin;
3634
3635 bwi_mac_updateslot(mac, (ic->ic_flags & IEEE80211_F_SHSLOT));
3636 }
3637
3638 static void
3639 bwi_calibrate(void *xsc)
3640 {
3641 struct bwi_softc *sc = xsc;
3642 struct ieee80211com *ic = &sc->sc_ic;
3643 struct ifnet *ifp = &ic->ic_if;
3644
3645 lwkt_serialize_enter(ifp->if_serializer);
3646
3647 if (ic->ic_state == IEEE80211_S_RUN) {
3648 struct bwi_mac *mac;
3649
3650 KKASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC);
3651 mac = (struct bwi_mac *)sc->sc_cur_regwin;
3652
3653 if (ic->ic_opmode != IEEE80211_M_MONITOR)
3654 bwi_mac_calibrate_txpower(mac);
3655
3656 /* XXX 15 seconds */
3657 callout_reset(&sc->sc_calib_ch, hz * 15, bwi_calibrate, sc);
3658 }
3659
3660 lwkt_serialize_exit(ifp->if_serializer);
3661 }
3662
3663 static int
3664 bwi_calc_rssi(struct bwi_softc *sc, const struct bwi_rxbuf_hdr *hdr)
3665 {
3666 struct bwi_mac *mac;
3667
3668 KKASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC);
3669 mac = (struct bwi_mac *)sc->sc_cur_regwin;
3670
3671 return bwi_rf_calc_rssi(mac, hdr);
3672 }
3673
3674 static void
3675 bwi_rx_radiotap(struct bwi_softc *sc, struct mbuf *m,
3676 struct bwi_rxbuf_hdr *hdr, const void *plcp,
3677 int rate, int rssi)
3678 {
3679 const struct ieee80211_frame_min *wh;
3680
3681 KKASSERT(sc->sc_drvbpf != NULL);
3682
3683 sc->sc_rx_th.wr_flags = IEEE80211_RADIOTAP_F_FCS;
3684 if (htole16(hdr->rxh_flags1) & BWI_RXH_F1_SHPREAMBLE)
3685 sc->sc_rx_th.wr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE;
3686
3687 wh = mtod(m, const struct ieee80211_frame_min *);
3688 if (wh->i_fc[1] & IEEE80211_FC1_WEP)
3689 sc->sc_rx_th.wr_flags |= IEEE80211_RADIOTAP_F_WEP;
3690
3691 sc->sc_rx_th.wr_tsf = hdr->rxh_tsf; /* No endian convertion */
3692 sc->sc_rx_th.wr_rate = rate;
3693 sc->sc_rx_th.wr_antsignal = rssi;
3694 sc->sc_rx_th.wr_antnoise = BWI_NOISE_FLOOR;
3695
3696 bpf_ptap(sc->sc_drvbpf, m, &sc->sc_rx_th, sc->sc_rx_th_len);
3697 }
3698
3699 static void
3700 bwi_led_attach(struct bwi_softc *sc)
3701 {
3702 const uint8_t *led_act = NULL;
3703 uint16_t gpio, val[BWI_LED_MAX];
3704 int i;
3705
3706 #define N(arr) (int)(sizeof(arr) / sizeof(arr[0]))
3707
3708 for (i = 0; i < N(bwi_vendor_led_act); ++i) {
3709 if (sc->sc_pci_subvid == bwi_vendor_led_act[i].vid) {
3710 led_act = bwi_vendor_led_act[i].led_act;
3711 break;
3712 }
3713 }
3714 if (led_act == NULL)
3715 led_act = bwi_default_led_act;
3716
3717 #undef N
3718
3719 gpio = bwi_read_sprom(sc, BWI_SPROM_GPIO01);
3720 val[0] = __SHIFTOUT(gpio, BWI_SPROM_GPIO_0);
3721 val[1] = __SHIFTOUT(gpio, BWI_SPROM_GPIO_1);
3722
3723 gpio = bwi_read_sprom(sc, BWI_SPROM_GPIO23);
3724 val[2] = __SHIFTOUT(gpio, BWI_SPROM_GPIO_2);
3725 val[3] = __SHIFTOUT(gpio, BWI_SPROM_GPIO_3);
3726
3727 for (i = 0; i < BWI_LED_MAX; ++i) {
3728 struct bwi_led *led = &sc->sc_leds[i];
3729
3730 if (val[i] == 0xff) {
3731 led->l_act = led_act[i];
3732 } else {
3733 if (val[i] & BWI_LED_ACT_LOW)
3734 led->l_flags |= BWI_LED_F_ACTLOW;
3735 led->l_act = __SHIFTOUT(val[i], BWI_LED_ACT_MASK);
3736 }
3737 led->l_mask = (1 << i);
3738
3739 if (led->l_act == BWI_LED_ACT_BLINK_SLOW ||
3740 led->l_act == BWI_LED_ACT_BLINK_POLL ||
3741 led->l_act == BWI_LED_ACT_BLINK) {
3742 led->l_flags |= BWI_LED_F_BLINK;
3743 if (led->l_act == BWI_LED_ACT_BLINK_POLL)
3744 led->l_flags |= BWI_LED_F_POLLABLE;
3745 else if (led->l_act == BWI_LED_ACT_BLINK_SLOW)
3746 led->l_flags |= BWI_LED_F_SLOW;
3747
3748 if (sc->sc_blink_led == NULL) {
3749 sc->sc_blink_led = led;
3750 if (led->l_flags & BWI_LED_F_SLOW)
3751 BWI_LED_SLOWDOWN(sc->sc_led_idle);
3752 }
3753 }
3754
3755 DPRINTF(sc, BWI_DBG_LED | BWI_DBG_ATTACH,
3756 "%dth led, act %d, lowact %d\n", i,
3757 led->l_act, led->l_flags & BWI_LED_F_ACTLOW);
3758 }
3759 callout_init(&sc->sc_led_blink_ch);
3760 }
3761
3762 static __inline uint16_t
3763 bwi_led_onoff(const struct bwi_led *led, uint16_t val, int on)
3764 {
3765 if (led->l_flags & BWI_LED_F_ACTLOW)
3766 on = !on;
3767 if (on)
3768 val |= led->l_mask;
3769 else
3770 val &= ~led->l_mask;
3771 return val;
3772 }
3773
3774 static void
3775 bwi_led_newstate(struct bwi_softc *sc, enum ieee80211_state nstate)
3776 {
3777 struct ieee80211com *ic = &sc->sc_ic;
3778 uint16_t val;
3779 int i;
3780
3781 if (nstate == IEEE80211_S_INIT) {
3782 callout_stop(&sc->sc_led_blink_ch);
3783 sc->sc_led_blinking = 0;
3784 }
3785
3786 if ((ic->ic_if.if_flags & IFF_RUNNING) == 0)
3787 return;
3788
3789 val = CSR_READ_2(sc, BWI_MAC_GPIO_CTRL);
3790 for (i = 0; i < BWI_LED_MAX; ++i) {
3791 struct bwi_led *led = &sc->sc_leds[i];
3792 int on;
3793
3794 if (led->l_act == BWI_LED_ACT_UNKN ||
3795 led->l_act == BWI_LED_ACT_NULL)
3796 continue;
3797
3798 if ((led->l_flags & BWI_LED_F_BLINK) &&
3799 nstate != IEEE80211_S_INIT)
3800 continue;
3801
3802 switch (led->l_act) {
3803 case BWI_LED_ACT_ON: /* Always on */
3804 on = 1;
3805 break;
3806 case BWI_LED_ACT_OFF: /* Always off */
3807 case BWI_LED_ACT_5GHZ: /* TODO: 11A */
3808 on = 0;
3809 break;
3810 default:
3811 on = 1;
3812 switch (nstate) {
3813 case IEEE80211_S_INIT:
3814 on = 0;
3815 break;
3816 case IEEE80211_S_RUN:
3817 if (led->l_act == BWI_LED_ACT_11G &&
3818 ic->ic_curmode != IEEE80211_MODE_11G)
3819 on = 0;
3820 break;
3821 default:
3822 if (led->l_act == BWI_LED_ACT_ASSOC)
3823 on = 0;
3824 break;
3825 }
3826 break;
3827 }
3828
3829 val = bwi_led_onoff(led, val, on);
3830 }
3831 CSR_WRITE_2(sc, BWI_MAC_GPIO_CTRL, val);
3832 }
3833
3834 static void
3835 bwi_led_event(struct bwi_softc *sc, int event)
3836 {
3837 struct bwi_led *led = sc->sc_blink_led;
3838 int rate;
3839
3840 if (event == BWI_LED_EVENT_POLL) {
3841 if ((led->l_flags & BWI_LED_F_POLLABLE) == 0)
3842 return;
3843 if (ticks - sc->sc_led_ticks < sc->sc_led_idle)
3844 return;
3845 }
3846
3847 sc->sc_led_ticks = ticks;
3848 if (sc->sc_led_blinking)
3849 return;
3850
3851 switch (event) {
3852 case BWI_LED_EVENT_RX:
3853 rate = sc->sc_rx_rate;
3854 break;
3855 case BWI_LED_EVENT_TX:
3856 rate = sc->sc_tx_rate;
3857 break;
3858 case BWI_LED_EVENT_POLL:
3859 rate = 0;
3860 break;
3861 default:
3862 panic("unknown LED event %d\n", event);
3863 break;
3864 }
3865 bwi_led_blink_start(sc, bwi_led_duration[rate].on_dur,
3866 bwi_led_duration[rate].off_dur);
3867 }
3868
3869 static void
3870 bwi_led_blink_start(struct bwi_softc *sc, int on_dur, int off_dur)
3871 {
3872 struct bwi_led *led = sc->sc_blink_led;
3873 uint16_t val;
3874
3875 val = CSR_READ_2(sc, BWI_MAC_GPIO_CTRL);
3876 val = bwi_led_onoff(led, val, 1);
3877 CSR_WRITE_2(sc, BWI_MAC_GPIO_CTRL, val);
3878
3879 if (led->l_flags & BWI_LED_F_SLOW) {
3880 BWI_LED_SLOWDOWN(on_dur);
3881 BWI_LED_SLOWDOWN(off_dur);
3882 }
3883
3884 sc->sc_led_blinking = 1;
3885 sc->sc_led_blink_offdur = off_dur;
3886
3887 callout_reset(&sc->sc_led_blink_ch, on_dur, bwi_led_blink_next, sc);
3888 }
3889
3890 static void
3891 bwi_led_blink_next(void *xsc)
3892 {
3893 struct bwi_softc *sc = xsc;
3894 uint16_t val;
3895
3896 val = CSR_READ_2(sc, BWI_MAC_GPIO_CTRL);
3897 val = bwi_led_onoff(sc->sc_blink_led, val, 0);
3898 CSR_WRITE_2(sc, BWI_MAC_GPIO_CTRL, val);
3899
3900 callout_reset(&sc->sc_led_blink_ch, sc->sc_led_blink_offdur,
3901 bwi_led_blink_end, sc);
3902 }
3903
3904 static void
3905 bwi_led_blink_end(void *xsc)
3906 {
3907 struct bwi_softc *sc = xsc;
3908
3909 sc->sc_led_blinking = 0;
3910 }
3911
3912 static void *
3913 bwi_ratectl_attach(struct ieee80211com *ic, u_int rc)
3914 {
3915 struct bwi_softc *sc = ic->ic_if.if_softc;
3916
3917 switch (rc) {
3918 case IEEE80211_RATECTL_ONOE:
3919 return &sc->sc_onoe_param;
3920 case IEEE80211_RATECTL_NONE:
3921 /* This could only happen during detaching */
3922 return NULL;
3923 default:
3924 panic("unknown rate control algo %u\n", rc);
3925 return NULL;
3926 }
3927 }
DragonFly BSD