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- Store tx rate control parameters in drivers, so switching between tx rate
[dragonfly.git] / sys / dev / netif / bwi / bwirf.c
blobabed0129a71112faae34443538ec5ef12b14ff25
1 /*
2 * Copyright (c) 2007 The DragonFly Project. All rights reserved.
3 *
4 * This code is derived from software contributed to The DragonFly Project
5 * by Sepherosa Ziehau <sepherosa@gmail.com>
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 *
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
16 * distribution.
17 * 3. Neither the name of The DragonFly Project nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific, prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
24 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
25 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
27 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
28 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
29 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
31 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 * SUCH DAMAGE.
33 *
34 * $DragonFly: src/sys/dev/netif/bwi/bwirf.c,v 1.8 2008/01/15 09:01:13 sephe Exp $
35 */
36
37 #include <sys/param.h>
38 #include <sys/bitops.h>
39 #include <sys/endian.h>
40 #include <sys/kernel.h>
41 #include <sys/bus.h>
42 #include <sys/malloc.h>
43 #include <sys/proc.h>
44 #include <sys/rman.h>
45 #include <sys/serialize.h>
46 #include <sys/socket.h>
47 #include <sys/sysctl.h>
48
49 #include <net/ethernet.h>
50 #include <net/if.h>
51 #include <net/bpf.h>
52 #include <net/if_arp.h>
53 #include <net/if_dl.h>
54 #include <net/if_media.h>
55 #include <net/ifq_var.h>
56
57 #include <netproto/802_11/ieee80211_radiotap.h>
58 #include <netproto/802_11/ieee80211_var.h>
59 #include <netproto/802_11/wlan_ratectl/onoe/ieee80211_onoe_param.h>
60
61 #include <bus/pci/pcireg.h>
62 #include <bus/pci/pcivar.h>
63 #include <bus/pci/pcidevs.h>
64
65 #include <dev/netif/bwi/if_bwireg.h>
66 #include <dev/netif/bwi/if_bwivar.h>
67 #include <dev/netif/bwi/bwiphy.h>
68 #include <dev/netif/bwi/bwirf.h>
69 #include <dev/netif/bwi/bwimac.h>
70
71 #define RF_LO_WRITE(mac, lo) bwi_rf_lo_write((mac), (lo))
72
73 #define BWI_RF_2GHZ_CHAN(chan) \
74 (ieee80211_ieee2mhz((chan), IEEE80211_CHAN_2GHZ) - 2400)
75
76 #define BWI_DEFAULT_IDLE_TSSI 52
77
78 struct rf_saveregs {
79 uint16_t phy_01;
80 uint16_t phy_03;
81 uint16_t phy_0a;
82 uint16_t phy_15;
83 uint16_t phy_2a;
84 uint16_t phy_30;
85 uint16_t phy_35;
86 uint16_t phy_60;
87 uint16_t phy_429;
88 uint16_t phy_802;
89 uint16_t phy_811;
90 uint16_t phy_812;
91 uint16_t phy_814;
92 uint16_t phy_815;
93
94 uint16_t rf_43;
95 uint16_t rf_52;
96 uint16_t rf_7a;
97 };
98
99 #define SAVE_RF_REG(mac, regs, n) (regs)->rf_##n = RF_READ((mac), 0x##n)
100 #define RESTORE_RF_REG(mac, regs, n) RF_WRITE((mac), 0x##n, (regs)->rf_##n)
101
102 #define SAVE_PHY_REG(mac, regs, n) (regs)->phy_##n = PHY_READ((mac), 0x##n)
103 #define RESTORE_PHY_REG(mac, regs, n) PHY_WRITE((mac), 0x##n, (regs)->phy_##n)
104
105 static int bwi_rf_calc_txpower(int8_t *, uint8_t, const int16_t[]);
106 static void bwi_rf_workaround(struct bwi_mac *, u_int);
107 static int bwi_rf_gain_max_reached(struct bwi_mac *, int);
108 static uint16_t bwi_rf_calibval(struct bwi_mac *);
109 static uint16_t bwi_rf_get_tp_ctrl2(struct bwi_mac *);
110
111 static void bwi_rf_lo_update_11b(struct bwi_mac *);
112 static uint16_t bwi_rf_lo_measure_11b(struct bwi_mac *);
113
114 static void bwi_rf_lo_update_11g(struct bwi_mac *);
115 static uint32_t bwi_rf_lo_devi_measure(struct bwi_mac *, uint16_t);
116 static void bwi_rf_lo_measure_11g(struct bwi_mac *,
117 const struct bwi_rf_lo *, struct bwi_rf_lo *, uint8_t);
118 static uint8_t _bwi_rf_lo_update_11g(struct bwi_mac *, uint16_t);
119 static void bwi_rf_lo_write(struct bwi_mac *, const struct bwi_rf_lo *);
120
121 static void bwi_rf_set_nrssi_ofs_11g(struct bwi_mac *);
122 static void bwi_rf_calc_nrssi_slope_11b(struct bwi_mac *);
123 static void bwi_rf_calc_nrssi_slope_11g(struct bwi_mac *);
124 static void bwi_rf_set_nrssi_thr_11b(struct bwi_mac *);
125 static void bwi_rf_set_nrssi_thr_11g(struct bwi_mac *);
126
127 static void bwi_rf_init_sw_nrssi_table(struct bwi_mac *);
128
129 static int bwi_rf_calc_rssi_bcm2050(struct bwi_mac *,
130 const struct bwi_rxbuf_hdr *);
131 static int bwi_rf_calc_rssi_bcm2053(struct bwi_mac *,
132 const struct bwi_rxbuf_hdr *);
133 static int bwi_rf_calc_rssi_bcm2060(struct bwi_mac *,
134 const struct bwi_rxbuf_hdr *);
135
136 static void bwi_rf_on_11a(struct bwi_mac *);
137 static void bwi_rf_on_11bg(struct bwi_mac *);
138
139 static void bwi_rf_off_11a(struct bwi_mac *);
140 static void bwi_rf_off_11bg(struct bwi_mac *);
141 static void bwi_rf_off_11g_rev5(struct bwi_mac *);
142
143 static const int8_t bwi_txpower_map_11b[BWI_TSSI_MAX] =
144 { BWI_TXPOWER_MAP_11B };
145 static const int8_t bwi_txpower_map_11g[BWI_TSSI_MAX] =
146 { BWI_TXPOWER_MAP_11G };
147
148 static __inline int16_t
149 bwi_nrssi_11g(struct bwi_mac *mac)
150 {
151 int16_t val;
152
153 #define NRSSI_11G_MASK __BITS(13, 8)
154
155 val = (int16_t)__SHIFTOUT(PHY_READ(mac, 0x47f), NRSSI_11G_MASK);
156 if (val >= 32)
157 val -= 64;
158 return val;
159
160 #undef NRSSI_11G_MASK
161 }
162
163 static __inline struct bwi_rf_lo *
164 bwi_get_rf_lo(struct bwi_mac *mac, uint16_t rf_atten, uint16_t bbp_atten)
165 {
166 int n;
167
168 n = rf_atten + (14 * (bbp_atten / 2));
169 KKASSERT(n < BWI_RFLO_MAX);
170
171 return &mac->mac_rf.rf_lo[n];
172 }
173
174 static __inline int
175 bwi_rf_lo_isused(struct bwi_mac *mac, const struct bwi_rf_lo *lo)
176 {
177 struct bwi_rf *rf = &mac->mac_rf;
178 int idx;
179
180 idx = lo - rf->rf_lo;
181 KKASSERT(idx >= 0 && idx < BWI_RFLO_MAX);
182
183 return isset(rf->rf_lo_used, idx);
184 }
185
186 void
187 bwi_rf_write(struct bwi_mac *mac, uint16_t ctrl, uint16_t data)
188 {
189 struct bwi_softc *sc = mac->mac_sc;
190
191 CSR_WRITE_2(sc, BWI_RF_CTRL, ctrl);
192 CSR_WRITE_2(sc, BWI_RF_DATA_LO, data);
193 }
194
195 uint16_t
196 bwi_rf_read(struct bwi_mac *mac, uint16_t ctrl)
197 {
198 struct bwi_rf *rf = &mac->mac_rf;
199 struct bwi_softc *sc = mac->mac_sc;
200
201 ctrl |= rf->rf_ctrl_rd;
202 if (rf->rf_ctrl_adj) {
203 /* XXX */
204 if (ctrl < 0x70)
205 ctrl += 0x80;
206 else if (ctrl < 0x80)
207 ctrl += 0x70;
208 }
209
210 CSR_WRITE_2(sc, BWI_RF_CTRL, ctrl);
211 return CSR_READ_2(sc, BWI_RF_DATA_LO);
212 }
213
214 int
215 bwi_rf_attach(struct bwi_mac *mac)
216 {
217 struct bwi_softc *sc = mac->mac_sc;
218 struct bwi_phy *phy = &mac->mac_phy;
219 struct bwi_rf *rf = &mac->mac_rf;
220 uint16_t type, manu;
221 uint8_t rev;
222
223 /*
224 * Get RF manufacture/type/revision
225 */
226 if (sc->sc_bbp_id == BWI_BBPID_BCM4317) {
227 /*
228 * Fake a BCM2050 RF
229 */
230 manu = BWI_RF_MANUFACT_BCM;
231 type = BWI_RF_T_BCM2050;
232 if (sc->sc_bbp_rev == 0)
233 rev = 3;
234 else if (sc->sc_bbp_rev == 1)
235 rev = 4;
236 else
237 rev = 5;
238 } else {
239 uint32_t val;
240
241 CSR_WRITE_2(sc, BWI_RF_CTRL, BWI_RF_CTRL_RFINFO);
242 val = CSR_READ_2(sc, BWI_RF_DATA_HI);
243 val <<= 16;
244
245 CSR_WRITE_2(sc, BWI_RF_CTRL, BWI_RF_CTRL_RFINFO);
246 val |= CSR_READ_2(sc, BWI_RF_DATA_LO);
247
248 manu = __SHIFTOUT(val, BWI_RFINFO_MANUFACT_MASK);
249 type = __SHIFTOUT(val, BWI_RFINFO_TYPE_MASK);
250 rev = __SHIFTOUT(val, BWI_RFINFO_REV_MASK);
251 }
252 device_printf(sc->sc_dev, "RF: manu 0x%03x, type 0x%04x, rev %u\n",
253 manu, type, rev);
254
255 /*
256 * Verify whether the RF is supported
257 */
258 rf->rf_ctrl_rd = 0;
259 rf->rf_ctrl_adj = 0;
260 switch (phy->phy_mode) {
261 case IEEE80211_MODE_11A:
262 if (manu != BWI_RF_MANUFACT_BCM ||
263 type != BWI_RF_T_BCM2060 ||
264 rev != 1) {
265 device_printf(sc->sc_dev, "only BCM2060 rev 1 RF "
266 "is supported for 11A PHY\n");
267 return ENXIO;
268 }
269 rf->rf_ctrl_rd = BWI_RF_CTRL_RD_11A;
270 rf->rf_on = bwi_rf_on_11a;
271 rf->rf_off = bwi_rf_off_11a;
272 rf->rf_calc_rssi = bwi_rf_calc_rssi_bcm2060;
273 break;
274 case IEEE80211_MODE_11B:
275 if (type == BWI_RF_T_BCM2050) {
276 rf->rf_ctrl_rd = BWI_RF_CTRL_RD_11BG;
277 rf->rf_calc_rssi = bwi_rf_calc_rssi_bcm2050;
278 } else if (type == BWI_RF_T_BCM2053) {
279 rf->rf_ctrl_adj = 1;
280 rf->rf_calc_rssi = bwi_rf_calc_rssi_bcm2053;
281 } else {
282 device_printf(sc->sc_dev, "only BCM2050/BCM2053 RF "
283 "is supported for 11B PHY\n");
284 return ENXIO;
285 }
286 rf->rf_on = bwi_rf_on_11bg;
287 rf->rf_off = bwi_rf_off_11bg;
288 rf->rf_calc_nrssi_slope = bwi_rf_calc_nrssi_slope_11b;
289 rf->rf_set_nrssi_thr = bwi_rf_set_nrssi_thr_11b;
290 if (phy->phy_rev == 6)
291 rf->rf_lo_update = bwi_rf_lo_update_11g;
292 else
293 rf->rf_lo_update = bwi_rf_lo_update_11b;
294 break;
295 case IEEE80211_MODE_11G:
296 if (type != BWI_RF_T_BCM2050) {
297 device_printf(sc->sc_dev, "only BCM2050 RF "
298 "is supported for 11G PHY\n");
299 return ENXIO;
300 }
301 rf->rf_ctrl_rd = BWI_RF_CTRL_RD_11BG;
302 rf->rf_on = bwi_rf_on_11bg;
303 if (mac->mac_rev >= 5)
304 rf->rf_off = bwi_rf_off_11g_rev5;
305 else
306 rf->rf_off = bwi_rf_off_11bg;
307 rf->rf_calc_nrssi_slope = bwi_rf_calc_nrssi_slope_11g;
308 rf->rf_set_nrssi_thr = bwi_rf_set_nrssi_thr_11g;
309 rf->rf_calc_rssi = bwi_rf_calc_rssi_bcm2050;
310 rf->rf_lo_update = bwi_rf_lo_update_11g;
311 break;
312 default:
313 device_printf(sc->sc_dev, "unsupported PHY mode\n");
314 return ENXIO;
315 }
316
317 rf->rf_type = type;
318 rf->rf_rev = rev;
319 rf->rf_manu = manu;
320 rf->rf_curchan = IEEE80211_CHAN_ANY;
321 rf->rf_ant_mode = BWI_ANT_MODE_AUTO;
322 return 0;
323 }
324
325 void
326 bwi_rf_set_chan(struct bwi_mac *mac, u_int chan, int work_around)
327 {
328 struct bwi_softc *sc = mac->mac_sc;
329
330 if (chan == IEEE80211_CHAN_ANY)
331 return;
332
333 MOBJ_WRITE_2(mac, BWI_COMM_MOBJ, BWI_COMM_MOBJ_CHAN, chan);
334
335 /* TODO: 11A */
336
337 if (work_around)
338 bwi_rf_workaround(mac, chan);
339
340 CSR_WRITE_2(sc, BWI_RF_CHAN, BWI_RF_2GHZ_CHAN(chan));
341
342 if (chan == 14) {
343 if (sc->sc_locale == BWI_SPROM_LOCALE_JAPAN)
344 HFLAGS_CLRBITS(mac, BWI_HFLAG_NOT_JAPAN);
345 else
346 HFLAGS_SETBITS(mac, BWI_HFLAG_NOT_JAPAN);
347 CSR_SETBITS_2(sc, BWI_RF_CHAN_EX, (1 << 11)); /* XXX */
348 } else {
349 CSR_CLRBITS_2(sc, BWI_RF_CHAN_EX, 0x840); /* XXX */
350 }
351 DELAY(8000); /* DELAY(2000); */
352
353 mac->mac_rf.rf_curchan = chan;
354 }
355
356 void
357 bwi_rf_get_gains(struct bwi_mac *mac)
358 {
359 #define SAVE_PHY_MAX 15
360 #define SAVE_RF_MAX 3
361
362 static const uint16_t save_rf_regs[SAVE_RF_MAX] =
363 { 0x52, 0x43, 0x7a };
364 static const uint16_t save_phy_regs[SAVE_PHY_MAX] = {
365 0x0429, 0x0001, 0x0811, 0x0812,
366 0x0814, 0x0815, 0x005a, 0x0059,
367 0x0058, 0x000a, 0x0003, 0x080f,
368 0x0810, 0x002b, 0x0015
369 };
370
371 struct bwi_phy *phy = &mac->mac_phy;
372 struct bwi_rf *rf = &mac->mac_rf;
373 uint16_t save_phy[SAVE_PHY_MAX];
374 uint16_t save_rf[SAVE_RF_MAX];
375 uint16_t trsw;
376 int i, j, loop1_max, loop1, loop2;
377
378 /*
379 * Save PHY/RF registers for later restoration
380 */
381 for (i = 0; i < SAVE_PHY_MAX; ++i)
382 save_phy[i] = PHY_READ(mac, save_phy_regs[i]);
383 PHY_READ(mac, 0x2d); /* dummy read */
384
385 for (i = 0; i < SAVE_RF_MAX; ++i)
386 save_rf[i] = RF_READ(mac, save_rf_regs[i]);
387
388 PHY_CLRBITS(mac, 0x429, 0xc000);
389 PHY_SETBITS(mac, 0x1, 0x8000);
390
391 PHY_SETBITS(mac, 0x811, 0x2);
392 PHY_CLRBITS(mac, 0x812, 0x2);
393 PHY_SETBITS(mac, 0x811, 0x1);
394 PHY_CLRBITS(mac, 0x812, 0x1);
395
396 PHY_SETBITS(mac, 0x814, 0x1);
397 PHY_CLRBITS(mac, 0x815, 0x1);
398 PHY_SETBITS(mac, 0x814, 0x2);
399 PHY_CLRBITS(mac, 0x815, 0x2);
400
401 PHY_SETBITS(mac, 0x811, 0xc);
402 PHY_SETBITS(mac, 0x812, 0xc);
403 PHY_SETBITS(mac, 0x811, 0x30);
404 PHY_FILT_SETBITS(mac, 0x812, 0xffcf, 0x10);
405
406 PHY_WRITE(mac, 0x5a, 0x780);
407 PHY_WRITE(mac, 0x59, 0xc810);
408 PHY_WRITE(mac, 0x58, 0xd);
409 PHY_SETBITS(mac, 0xa, 0x2000);
410
411 PHY_SETBITS(mac, 0x814, 0x4);
412 PHY_CLRBITS(mac, 0x815, 0x4);
413
414 PHY_FILT_SETBITS(mac, 0x3, 0xff9f, 0x40);
415
416 if (rf->rf_rev == 8) {
417 loop1_max = 15;
418 RF_WRITE(mac, 0x43, loop1_max);
419 } else {
420 loop1_max = 9;
421 RF_WRITE(mac, 0x52, 0x0);
422 RF_FILT_SETBITS(mac, 0x43, 0xfff0, loop1_max);
423 }
424
425 bwi_phy_set_bbp_atten(mac, 11);
426
427 if (phy->phy_rev >= 3)
428 PHY_WRITE(mac, 0x80f, 0xc020);
429 else
430 PHY_WRITE(mac, 0x80f, 0x8020);
431 PHY_WRITE(mac, 0x810, 0);
432
433 PHY_FILT_SETBITS(mac, 0x2b, 0xffc0, 0x1);
434 PHY_FILT_SETBITS(mac, 0x2b, 0xc0ff, 0x800);
435 PHY_SETBITS(mac, 0x811, 0x100);
436 PHY_CLRBITS(mac, 0x812, 0x3000);
437
438 if ((mac->mac_sc->sc_card_flags & BWI_CARD_F_EXT_LNA) &&
439 phy->phy_rev >= 7) {
440 PHY_SETBITS(mac, 0x811, 0x800);
441 PHY_SETBITS(mac, 0x812, 0x8000);
442 }
443 RF_CLRBITS(mac, 0x7a, 0xff08);
444
445 /*
446 * Find out 'loop1/loop2', which will be used to calculate
447 * max loopback gain later
448 */
449 j = 0;
450 for (i = 0; i < loop1_max; ++i) {
451 for (j = 0; j < 16; ++j) {
452 RF_WRITE(mac, 0x43, i);
453
454 if (bwi_rf_gain_max_reached(mac, j))
455 goto loop1_exit;
456 }
457 }
458 loop1_exit:
459 loop1 = i;
460 loop2 = j;
461
462 /*
463 * Find out 'trsw', which will be used to calculate
464 * TRSW(TX/RX switch) RX gain later
465 */
466 if (loop2 >= 8) {
467 PHY_SETBITS(mac, 0x812, 0x30);
468 trsw = 0x1b;
469 for (i = loop2 - 8; i < 16; ++i) {
470 trsw -= 3;
471 if (bwi_rf_gain_max_reached(mac, i))
472 break;
473 }
474 } else {
475 trsw = 0x18;
476 }
477
478 /*
479 * Restore saved PHY/RF registers
480 */
481 /* First 4 saved PHY registers need special processing */
482 for (i = 4; i < SAVE_PHY_MAX; ++i)
483 PHY_WRITE(mac, save_phy_regs[i], save_phy[i]);
484
485 bwi_phy_set_bbp_atten(mac, mac->mac_tpctl.bbp_atten);
486
487 for (i = 0; i < SAVE_RF_MAX; ++i)
488 RF_WRITE(mac, save_rf_regs[i], save_rf[i]);
489
490 PHY_WRITE(mac, save_phy_regs[2], save_phy[2] | 0x3);
491 DELAY(10);
492 PHY_WRITE(mac, save_phy_regs[2], save_phy[2]);
493 PHY_WRITE(mac, save_phy_regs[3], save_phy[3]);
494 PHY_WRITE(mac, save_phy_regs[0], save_phy[0]);
495 PHY_WRITE(mac, save_phy_regs[1], save_phy[1]);
496
497 /*
498 * Calculate gains
499 */
500 rf->rf_lo_gain = (loop2 * 6) - (loop1 * 4) - 11;
501 rf->rf_rx_gain = trsw * 2;
502 DPRINTF(mac->mac_sc, BWI_DBG_RF | BWI_DBG_INIT,
503 "lo gain: %u, rx gain: %u\n",
504 rf->rf_lo_gain, rf->rf_rx_gain);
505
506 #undef SAVE_RF_MAX
507 #undef SAVE_PHY_MAX
508 }
509
510 void
511 bwi_rf_init(struct bwi_mac *mac)
512 {
513 struct bwi_rf *rf = &mac->mac_rf;
514
515 if (rf->rf_type == BWI_RF_T_BCM2060) {
516 /* TODO: 11A */
517 } else {
518 if (rf->rf_flags & BWI_RF_F_INITED)
519 RF_WRITE(mac, 0x78, rf->rf_calib);
520 else
521 bwi_rf_init_bcm2050(mac);
522 }
523 }
524
525 static void
526 bwi_rf_off_11a(struct bwi_mac *mac)
527 {
528 RF_WRITE(mac, 0x4, 0xff);
529 RF_WRITE(mac, 0x5, 0xfb);
530
531 PHY_SETBITS(mac, 0x10, 0x8);
532 PHY_SETBITS(mac, 0x11, 0x8);
533
534 PHY_WRITE(mac, 0x15, 0xaa00);
535 }
536
537 static void
538 bwi_rf_off_11bg(struct bwi_mac *mac)
539 {
540 PHY_WRITE(mac, 0x15, 0xaa00);
541 }
542
543 static void
544 bwi_rf_off_11g_rev5(struct bwi_mac *mac)
545 {
546 PHY_SETBITS(mac, 0x811, 0x8c);
547 PHY_CLRBITS(mac, 0x812, 0x8c);
548 }
549
550 static void
551 bwi_rf_workaround(struct bwi_mac *mac, u_int chan)
552 {
553 struct bwi_softc *sc = mac->mac_sc;
554 struct bwi_rf *rf = &mac->mac_rf;
555
556 if (chan == IEEE80211_CHAN_ANY) {
557 if_printf(&mac->mac_sc->sc_ic.ic_if,
558 "%s invalid channel!!\n", __func__);
559 return;
560 }
561
562 if (rf->rf_type != BWI_RF_T_BCM2050 || rf->rf_rev >= 6)
563 return;
564
565 if (chan <= 10)
566 CSR_WRITE_2(sc, BWI_RF_CHAN, BWI_RF_2GHZ_CHAN(chan + 4));
567 else
568 CSR_WRITE_2(sc, BWI_RF_CHAN, BWI_RF_2GHZ_CHAN(1));
569 DELAY(1000);
570 CSR_WRITE_2(sc, BWI_RF_CHAN, BWI_RF_2GHZ_CHAN(chan));
571 }
572
573 static __inline struct bwi_rf_lo *
574 bwi_rf_lo_find(struct bwi_mac *mac, const struct bwi_tpctl *tpctl)
575 {
576 uint16_t rf_atten, bbp_atten;
577 int remap_rf_atten;
578
579 remap_rf_atten = 1;
580 if (tpctl == NULL) {
581 bbp_atten = 2;
582 rf_atten = 3;
583 } else {
584 if (tpctl->tp_ctrl1 == 3)
585 remap_rf_atten = 0;
586
587 bbp_atten = tpctl->bbp_atten;
588 rf_atten = tpctl->rf_atten;
589
590 if (bbp_atten > 6)
591 bbp_atten = 6;
592 }
593
594 if (remap_rf_atten) {
595 #define MAP_MAX 10
596 static const uint16_t map[MAP_MAX] =
597 { 11, 10, 11, 12, 13, 12, 13, 12, 13, 12 };
598
599 #if 0
600 KKASSERT(rf_atten < MAP_MAX);
601 rf_atten = map[rf_atten];
602 #else
603 if (rf_atten >= MAP_MAX) {
604 rf_atten = 0; /* XXX */
605 } else {
606 rf_atten = map[rf_atten];
607 }
608 #endif
609 #undef MAP_MAX
610 }
611
612 return bwi_get_rf_lo(mac, rf_atten, bbp_atten);
613 }
614
615 void
616 bwi_rf_lo_adjust(struct bwi_mac *mac, const struct bwi_tpctl *tpctl)
617 {
618 const struct bwi_rf_lo *lo;
619
620 lo = bwi_rf_lo_find(mac, tpctl);
621 RF_LO_WRITE(mac, lo);
622 }
623
624 static void
625 bwi_rf_lo_write(struct bwi_mac *mac, const struct bwi_rf_lo *lo)
626 {
627 uint16_t val;
628
629 val = (uint8_t)lo->ctrl_lo;
630 val |= ((uint8_t)lo->ctrl_hi) << 8;
631
632 PHY_WRITE(mac, BWI_PHYR_RF_LO, val);
633 }
634
635 static int
636 bwi_rf_gain_max_reached(struct bwi_mac *mac, int idx)
637 {
638 PHY_FILT_SETBITS(mac, 0x812, 0xf0ff, idx << 8);
639 PHY_FILT_SETBITS(mac, 0x15, 0xfff, 0xa000);
640 PHY_SETBITS(mac, 0x15, 0xf000);
641
642 DELAY(20);
643
644 return (PHY_READ(mac, 0x2d) >= 0xdfc);
645 }
646
647 /* XXX use bitmap array */
648 static __inline uint16_t
649 bitswap4(uint16_t val)
650 {
651 uint16_t ret;
652
653 ret = (val & 0x8) >> 3;
654 ret |= (val & 0x4) >> 1;
655 ret |= (val & 0x2) << 1;
656 ret |= (val & 0x1) << 3;
657 return ret;
658 }
659
660 static __inline uint16_t
661 bwi_phy812_value(struct bwi_mac *mac, uint16_t lpd)
662 {
663 struct bwi_softc *sc = mac->mac_sc;
664 struct bwi_phy *phy = &mac->mac_phy;
665 struct bwi_rf *rf = &mac->mac_rf;
666 uint16_t lo_gain, ext_lna, loop;
667
668 if ((phy->phy_flags & BWI_PHY_F_LINKED) == 0)
669 return 0;
670
671 lo_gain = rf->rf_lo_gain;
672 if (rf->rf_rev == 8)
673 lo_gain += 0x3e;
674 else
675 lo_gain += 0x26;
676
677 if (lo_gain >= 0x46) {
678 lo_gain -= 0x46;
679 ext_lna = 0x3000;
680 } else if (lo_gain >= 0x3a) {
681 lo_gain -= 0x3a;
682 ext_lna = 0x1000;
683 } else if (lo_gain >= 0x2e) {
684 lo_gain -= 0x2e;
685 ext_lna = 0x2000;
686 } else {
687 lo_gain -= 0x10;
688 ext_lna = 0;
689 }
690
691 for (loop = 0; loop < 16; ++loop) {
692 lo_gain -= (6 * loop);
693 if (lo_gain < 6)
694 break;
695 }
696
697 if (phy->phy_rev >= 7 && (sc->sc_card_flags & BWI_CARD_F_EXT_LNA)) {
698 if (ext_lna)
699 ext_lna |= 0x8000;
700 ext_lna |= (loop << 8);
701 switch (lpd) {
702 case 0x011:
703 return 0x8f92;
704 case 0x001:
705 return (0x8092 | ext_lna);
706 case 0x101:
707 return (0x2092 | ext_lna);
708 case 0x100:
709 return (0x2093 | ext_lna);
710 default:
711 panic("unsupported lpd\n");
712 }
713 } else {
714 ext_lna |= (loop << 8);
715 switch (lpd) {
716 case 0x011:
717 return 0xf92;
718 case 0x001:
719 case 0x101:
720 return (0x92 | ext_lna);
721 case 0x100:
722 return (0x93 | ext_lna);
723 default:
724 panic("unsupported lpd\n");
725 }
726 }
727
728 panic("never reached\n");
729 return 0;
730 }
731
732 void
733 bwi_rf_init_bcm2050(struct bwi_mac *mac)
734 {
735 #define SAVE_RF_MAX 3
736 #define SAVE_PHY_COMM_MAX 4
737 #define SAVE_PHY_11G_MAX 6
738
739 static const uint16_t save_rf_regs[SAVE_RF_MAX] =
740 { 0x0043, 0x0051, 0x0052 };
741 static const uint16_t save_phy_regs_comm[SAVE_PHY_COMM_MAX] =
742 { 0x0015, 0x005a, 0x0059, 0x0058 };
743 static const uint16_t save_phy_regs_11g[SAVE_PHY_11G_MAX] =
744 { 0x0811, 0x0812, 0x0814, 0x0815, 0x0429, 0x0802 };
745
746 uint16_t save_rf[SAVE_RF_MAX];
747 uint16_t save_phy_comm[SAVE_PHY_COMM_MAX];
748 uint16_t save_phy_11g[SAVE_PHY_11G_MAX];
749 uint16_t phyr_35, phyr_30 = 0, rfr_78, phyr_80f = 0, phyr_810 = 0;
750 uint16_t bphy_ctrl = 0, bbp_atten, rf_chan_ex;
751 uint16_t phy812_val;
752 uint16_t calib;
753 uint32_t test_lim, test;
754 struct bwi_softc *sc = mac->mac_sc;
755 struct bwi_phy *phy = &mac->mac_phy;
756 struct bwi_rf *rf = &mac->mac_rf;
757 int i;
758
759 /*
760 * Save registers for later restoring
761 */
762 for (i = 0; i < SAVE_RF_MAX; ++i)
763 save_rf[i] = RF_READ(mac, save_rf_regs[i]);
764 for (i = 0; i < SAVE_PHY_COMM_MAX; ++i)
765 save_phy_comm[i] = PHY_READ(mac, save_phy_regs_comm[i]);
766
767 if (phy->phy_mode == IEEE80211_MODE_11B) {
768 phyr_30 = PHY_READ(mac, 0x30);
769 bphy_ctrl = CSR_READ_2(sc, BWI_BPHY_CTRL);
770
771 PHY_WRITE(mac, 0x30, 0xff);
772 CSR_WRITE_2(sc, BWI_BPHY_CTRL, 0x3f3f);
773 } else if ((phy->phy_flags & BWI_PHY_F_LINKED) || phy->phy_rev >= 2) {
774 for (i = 0; i < SAVE_PHY_11G_MAX; ++i) {
775 save_phy_11g[i] =
776 PHY_READ(mac, save_phy_regs_11g[i]);
777 }
778
779 PHY_SETBITS(mac, 0x814, 0x3);
780 PHY_CLRBITS(mac, 0x815, 0x3);
781 PHY_CLRBITS(mac, 0x429, 0x8000);
782 PHY_CLRBITS(mac, 0x802, 0x3);
783
784 phyr_80f = PHY_READ(mac, 0x80f);
785 phyr_810 = PHY_READ(mac, 0x810);
786
787 if (phy->phy_rev >= 3)
788 PHY_WRITE(mac, 0x80f, 0xc020);
789 else
790 PHY_WRITE(mac, 0x80f, 0x8020);
791 PHY_WRITE(mac, 0x810, 0);
792
793 phy812_val = bwi_phy812_value(mac, 0x011);
794 PHY_WRITE(mac, 0x812, phy812_val);
795 if (phy->phy_rev < 7 ||
796 (sc->sc_card_flags & BWI_CARD_F_EXT_LNA) == 0)
797 PHY_WRITE(mac, 0x811, 0x1b3);
798 else
799 PHY_WRITE(mac, 0x811, 0x9b3);
800 }
801 CSR_SETBITS_2(sc, BWI_RF_ANTDIV, 0x8000);
802
803 phyr_35 = PHY_READ(mac, 0x35);
804 PHY_CLRBITS(mac, 0x35, 0x80);
805
806 bbp_atten = CSR_READ_2(sc, BWI_BBP_ATTEN);
807 rf_chan_ex = CSR_READ_2(sc, BWI_RF_CHAN_EX);
808
809 if (phy->phy_version == 0) {
810 CSR_WRITE_2(sc, BWI_BBP_ATTEN, 0x122);
811 } else {
812 if (phy->phy_version >= 2)
813 PHY_FILT_SETBITS(mac, 0x3, 0xffbf, 0x40);
814 CSR_SETBITS_2(sc, BWI_RF_CHAN_EX, 0x2000);
815 }
816
817 calib = bwi_rf_calibval(mac);
818
819 if (phy->phy_mode == IEEE80211_MODE_11B)
820 RF_WRITE(mac, 0x78, 0x26);
821
822 if ((phy->phy_flags & BWI_PHY_F_LINKED) || phy->phy_rev >= 2) {
823 phy812_val = bwi_phy812_value(mac, 0x011);
824 PHY_WRITE(mac, 0x812, phy812_val);
825 }
826
827 PHY_WRITE(mac, 0x15, 0xbfaf);
828 PHY_WRITE(mac, 0x2b, 0x1403);
829
830 if ((phy->phy_flags & BWI_PHY_F_LINKED) || phy->phy_rev >= 2) {
831 phy812_val = bwi_phy812_value(mac, 0x001);
832 PHY_WRITE(mac, 0x812, phy812_val);
833 }
834
835 PHY_WRITE(mac, 0x15, 0xbfa0);
836
837 RF_SETBITS(mac, 0x51, 0x4);
838 if (rf->rf_rev == 8) {
839 RF_WRITE(mac, 0x43, 0x1f);
840 } else {
841 RF_WRITE(mac, 0x52, 0);
842 RF_FILT_SETBITS(mac, 0x43, 0xfff0, 0x9);
843 }
844
845 test_lim = 0;
846 PHY_WRITE(mac, 0x58, 0);
847 for (i = 0; i < 16; ++i) {
848 PHY_WRITE(mac, 0x5a, 0x480);
849 PHY_WRITE(mac, 0x59, 0xc810);
850
851 PHY_WRITE(mac, 0x58, 0xd);
852 if ((phy->phy_flags & BWI_PHY_F_LINKED) || phy->phy_rev >= 2) {
853 phy812_val = bwi_phy812_value(mac, 0x101);
854 PHY_WRITE(mac, 0x812, phy812_val);
855 }
856 PHY_WRITE(mac, 0x15, 0xafb0);
857 DELAY(10);
858
859 if ((phy->phy_flags & BWI_PHY_F_LINKED) || phy->phy_rev >= 2) {
860 phy812_val = bwi_phy812_value(mac, 0x101);
861 PHY_WRITE(mac, 0x812, phy812_val);
862 }
863 PHY_WRITE(mac, 0x15, 0xefb0);
864 DELAY(10);
865
866 if ((phy->phy_flags & BWI_PHY_F_LINKED) || phy->phy_rev >= 2) {
867 phy812_val = bwi_phy812_value(mac, 0x100);
868 PHY_WRITE(mac, 0x812, phy812_val);
869 }
870 PHY_WRITE(mac, 0x15, 0xfff0);
871 DELAY(20);
872
873 test_lim += PHY_READ(mac, 0x2d);
874
875 PHY_WRITE(mac, 0x58, 0);
876 if ((phy->phy_flags & BWI_PHY_F_LINKED) || phy->phy_rev >= 2) {
877 phy812_val = bwi_phy812_value(mac, 0x101);
878 PHY_WRITE(mac, 0x812, phy812_val);
879 }
880 PHY_WRITE(mac, 0x15, 0xafb0);
881 }
882 ++test_lim;
883 test_lim >>= 9;
884
885 DELAY(10);
886
887 test = 0;
888 PHY_WRITE(mac, 0x58, 0);
889 for (i = 0; i < 16; ++i) {
890 int j;
891
892 rfr_78 = (bitswap4(i) << 1) | 0x20;
893 RF_WRITE(mac, 0x78, rfr_78);
894 DELAY(10);
895
896 /* NB: This block is slight different than the above one */
897 for (j = 0; j < 16; ++j) {
898 PHY_WRITE(mac, 0x5a, 0xd80);
899 PHY_WRITE(mac, 0x59, 0xc810);
900
901 PHY_WRITE(mac, 0x58, 0xd);
902 if ((phy->phy_flags & BWI_PHY_F_LINKED) ||
903 phy->phy_rev >= 2) {
904 phy812_val = bwi_phy812_value(mac, 0x101);
905 PHY_WRITE(mac, 0x812, phy812_val);
906 }
907 PHY_WRITE(mac, 0x15, 0xafb0);
908 DELAY(10);
909
910 if ((phy->phy_flags & BWI_PHY_F_LINKED) ||
911 phy->phy_rev >= 2) {
912 phy812_val = bwi_phy812_value(mac, 0x101);
913 PHY_WRITE(mac, 0x812, phy812_val);
914 }
915 PHY_WRITE(mac, 0x15, 0xefb0);
916 DELAY(10);
917
918 if ((phy->phy_flags & BWI_PHY_F_LINKED) ||
919 phy->phy_rev >= 2) {
920 phy812_val = bwi_phy812_value(mac, 0x100);
921 PHY_WRITE(mac, 0x812, phy812_val);
922 }
923 PHY_WRITE(mac, 0x15, 0xfff0);
924 DELAY(10);
925
926 test += PHY_READ(mac, 0x2d);
927
928 PHY_WRITE(mac, 0x58, 0);
929 if ((phy->phy_flags & BWI_PHY_F_LINKED) ||
930 phy->phy_rev >= 2) {
931 phy812_val = bwi_phy812_value(mac, 0x101);
932 PHY_WRITE(mac, 0x812, phy812_val);
933 }
934 PHY_WRITE(mac, 0x15, 0xafb0);
935 }
936
937 ++test;
938 test >>= 8;
939
940 if (test > test_lim)
941 break;
942 }
943 if (i > 15)
944 rf->rf_calib = rfr_78;
945 else
946 rf->rf_calib = calib;
947 if (rf->rf_calib != 0xffff) {
948 DPRINTF(sc, BWI_DBG_RF | BWI_DBG_INIT,
949 "RF calibration value: 0x%04x\n", rf->rf_calib);
950 rf->rf_flags |= BWI_RF_F_INITED;
951 }
952
953 /*
954 * Restore trashes registers
955 */
956 PHY_WRITE(mac, save_phy_regs_comm[0], save_phy_comm[0]);
957
958 for (i = 0; i < SAVE_RF_MAX; ++i) {
959 int pos = (i + 1) % SAVE_RF_MAX;
960
961 RF_WRITE(mac, save_rf_regs[pos], save_rf[pos]);
962 }
963 for (i = 1; i < SAVE_PHY_COMM_MAX; ++i)
964 PHY_WRITE(mac, save_phy_regs_comm[i], save_phy_comm[i]);
965
966 CSR_WRITE_2(sc, BWI_BBP_ATTEN, bbp_atten);
967 if (phy->phy_version != 0)
968 CSR_WRITE_2(sc, BWI_RF_CHAN_EX, rf_chan_ex);
969
970 PHY_WRITE(mac, 0x35, phyr_35);
971 bwi_rf_workaround(mac, rf->rf_curchan);
972
973 if (phy->phy_mode == IEEE80211_MODE_11B) {
974 PHY_WRITE(mac, 0x30, phyr_30);
975 CSR_WRITE_2(sc, BWI_BPHY_CTRL, bphy_ctrl);
976 } else if ((phy->phy_flags & BWI_PHY_F_LINKED) || phy->phy_rev >= 2) {
977 /* XXX Spec only says when PHY is linked (gmode) */
978 CSR_CLRBITS_2(sc, BWI_RF_ANTDIV, 0x8000);
979
980 for (i = 0; i < SAVE_PHY_11G_MAX; ++i) {
981 PHY_WRITE(mac, save_phy_regs_11g[i],
982 save_phy_11g[i]);
983 }
984
985 PHY_WRITE(mac, 0x80f, phyr_80f);
986 PHY_WRITE(mac, 0x810, phyr_810);
987 }
988
989 #undef SAVE_PHY_11G_MAX
990 #undef SAVE_PHY_COMM_MAX
991 #undef SAVE_RF_MAX
992 }
993
994 static uint16_t
995 bwi_rf_calibval(struct bwi_mac *mac)
996 {
997 /* http://bcm-specs.sipsolutions.net/RCCTable */
998 static const uint16_t rf_calibvals[] = {
999 0x2, 0x3, 0x1, 0xf, 0x6, 0x7, 0x5, 0xf,
1000 0xa, 0xb, 0x9, 0xf, 0xe, 0xf, 0xd, 0xf
1001 };
1002 uint16_t val, calib;
1003 int idx;
1004
1005 val = RF_READ(mac, BWI_RFR_BBP_ATTEN);
1006 idx = __SHIFTOUT(val, BWI_RFR_BBP_ATTEN_CALIB_IDX);
1007 KKASSERT(idx < (int)(sizeof(rf_calibvals) / sizeof(rf_calibvals[0])));
1008
1009 calib = rf_calibvals[idx] << 1;
1010 if (val & BWI_RFR_BBP_ATTEN_CALIB_BIT)
1011 calib |= 0x1;
1012 calib |= 0x20;
1013
1014 return calib;
1015 }
1016
1017 static __inline int32_t
1018 _bwi_adjust_devide(int32_t num, int32_t den)
1019 {
1020 if (num < 0)
1021 return (num / den);
1022 else
1023 return (num + den / 2) / den;
1024 }
1025
1026 /*
1027 * http://bcm-specs.sipsolutions.net/TSSI_to_DBM_Table
1028 * "calculating table entries"
1029 */
1030 static int
1031 bwi_rf_calc_txpower(int8_t *txpwr, uint8_t idx, const int16_t pa_params[])
1032 {
1033 int32_t m1, m2, f, dbm;
1034 int i;
1035
1036 m1 = _bwi_adjust_devide(16 * pa_params[0] + idx * pa_params[1], 32);
1037 m2 = imax(_bwi_adjust_devide(32768 + idx * pa_params[2], 256), 1);
1038
1039 #define ITER_MAX 16
1040
1041 f = 256;
1042 for (i = 0; i < ITER_MAX; ++i) {
1043 int32_t q, d;
1044
1045 q = _bwi_adjust_devide(
1046 f * 4096 - _bwi_adjust_devide(m2 * f, 16) * f, 2048);
1047 d = abs(q - f);
1048 f = q;
1049
1050 if (d < 2)
1051 break;
1052 }
1053 if (i == ITER_MAX)
1054 return EINVAL;
1055
1056 #undef ITER_MAX
1057
1058 dbm = _bwi_adjust_devide(m1 * f, 8192);
1059 if (dbm < -127)
1060 dbm = -127;
1061 else if (dbm > 128)
1062 dbm = 128;
1063
1064 *txpwr = dbm;
1065 return 0;
1066 }
1067
1068 int
1069 bwi_rf_map_txpower(struct bwi_mac *mac)
1070 {
1071 struct bwi_softc *sc = mac->mac_sc;
1072 struct bwi_rf *rf = &mac->mac_rf;
1073 struct bwi_phy *phy = &mac->mac_phy;
1074 uint16_t sprom_ofs, val, mask;
1075 int16_t pa_params[3];
1076 int error = 0, i, ant_gain, reg_txpower_max;
1077
1078 /*
1079 * Find out max TX power
1080 */
1081 val = bwi_read_sprom(sc, BWI_SPROM_MAX_TXPWR);
1082 if (phy->phy_mode == IEEE80211_MODE_11A) {
1083 rf->rf_txpower_max = __SHIFTOUT(val,
1084 BWI_SPROM_MAX_TXPWR_MASK_11A);
1085 } else {
1086 rf->rf_txpower_max = __SHIFTOUT(val,
1087 BWI_SPROM_MAX_TXPWR_MASK_11BG);
1088
1089 if ((sc->sc_card_flags & BWI_CARD_F_PA_GPIO9) &&
1090 phy->phy_mode == IEEE80211_MODE_11G)
1091 rf->rf_txpower_max -= 3;
1092 }
1093 if (rf->rf_txpower_max <= 0) {
1094 device_printf(sc->sc_dev, "invalid max txpower in sprom\n");
1095 rf->rf_txpower_max = 74;
1096 }
1097 DPRINTF(sc, BWI_DBG_RF | BWI_DBG_TXPOWER | BWI_DBG_ATTACH,
1098 "max txpower from sprom: %d dBm\n", rf->rf_txpower_max);
1099
1100 /*
1101 * Find out region/domain max TX power, which is adjusted
1102 * by antenna gain and 1.5 dBm fluctuation as mentioned
1103 * in v3 spec.
1104 */
1105 val = bwi_read_sprom(sc, BWI_SPROM_ANT_GAIN);
1106 if (phy->phy_mode == IEEE80211_MODE_11A)
1107 ant_gain = __SHIFTOUT(val, BWI_SPROM_ANT_GAIN_MASK_11A);
1108 else
1109 ant_gain = __SHIFTOUT(val, BWI_SPROM_ANT_GAIN_MASK_11BG);
1110 if (ant_gain == 0xff) {
1111 device_printf(sc->sc_dev, "invalid antenna gain in sprom\n");
1112 ant_gain = 2;
1113 }
1114 ant_gain *= 4;
1115 DPRINTF(sc, BWI_DBG_RF | BWI_DBG_TXPOWER | BWI_DBG_ATTACH,
1116 "ant gain %d dBm\n", ant_gain);
1117
1118 reg_txpower_max = 90 - ant_gain - 6; /* XXX magic number */
1119 DPRINTF(sc, BWI_DBG_RF | BWI_DBG_TXPOWER | BWI_DBG_ATTACH,
1120 "region/domain max txpower %d dBm\n", reg_txpower_max);
1121
1122 /*
1123 * Force max TX power within region/domain TX power limit
1124 */
1125 if (rf->rf_txpower_max > reg_txpower_max)
1126 rf->rf_txpower_max = reg_txpower_max;
1127 DPRINTF(sc, BWI_DBG_RF | BWI_DBG_TXPOWER | BWI_DBG_ATTACH,
1128 "max txpower %d dBm\n", rf->rf_txpower_max);
1129
1130 /*
1131 * Create TSSI to TX power mapping
1132 */
1133
1134 if (sc->sc_bbp_id == BWI_BBPID_BCM4301 &&
1135 rf->rf_type != BWI_RF_T_BCM2050) {
1136 rf->rf_idle_tssi0 = BWI_DEFAULT_IDLE_TSSI;
1137 bcopy(bwi_txpower_map_11b, rf->rf_txpower_map0,
1138 sizeof(rf->rf_txpower_map0));
1139 goto back;
1140 }
1141
1142 #define IS_VALID_PA_PARAM(p) ((p) != 0 && (p) != -1)
1143 #define N(arr) (int)(sizeof(arr) / sizeof(arr[0]))
1144
1145 /*
1146 * Extract PA parameters
1147 */
1148 if (phy->phy_mode == IEEE80211_MODE_11A)
1149 sprom_ofs = BWI_SPROM_PA_PARAM_11A;
1150 else
1151 sprom_ofs = BWI_SPROM_PA_PARAM_11BG;
1152 for (i = 0; i < N(pa_params); ++i)
1153 pa_params[i] = (int16_t)bwi_read_sprom(sc, sprom_ofs + (i * 2));
1154
1155 for (i = 0; i < N(pa_params); ++i) {
1156 /*
1157 * If one of the PA parameters from SPROM is not valid,
1158 * fall back to the default values, if there are any.
1159 */
1160 if (!IS_VALID_PA_PARAM(pa_params[i])) {
1161 const int8_t *txpower_map;
1162
1163 if (phy->phy_mode == IEEE80211_MODE_11A) {
1164 if_printf(&sc->sc_ic.ic_if,
1165 "no tssi2dbm table for 11a PHY\n");
1166 return ENXIO;
1167 }
1168
1169 if (phy->phy_mode == IEEE80211_MODE_11G) {
1170 DPRINTF(sc,
1171 BWI_DBG_RF | BWI_DBG_TXPOWER | BWI_DBG_ATTACH,
1172 "%s\n", "use default 11g TSSI map");
1173 txpower_map = bwi_txpower_map_11g;
1174 } else {
1175 DPRINTF(sc,
1176 BWI_DBG_RF | BWI_DBG_TXPOWER | BWI_DBG_ATTACH,
1177 "%s\n", "use default 11b TSSI map");
1178 txpower_map = bwi_txpower_map_11b;
1179 }
1180
1181 rf->rf_idle_tssi0 = BWI_DEFAULT_IDLE_TSSI;
1182 bcopy(txpower_map, rf->rf_txpower_map0,
1183 sizeof(rf->rf_txpower_map0));
1184 goto back;
1185 }
1186 }
1187
1188 #undef N
1189
1190 /*
1191 * All of the PA parameters from SPROM are valid.
1192 */
1193
1194 /*
1195 * Extract idle TSSI from SPROM.
1196 */
1197 val = bwi_read_sprom(sc, BWI_SPROM_IDLE_TSSI);
1198 DPRINTF(sc, BWI_DBG_RF | BWI_DBG_TXPOWER | BWI_DBG_ATTACH,
1199 "sprom idle tssi: 0x%04x\n", val);
1200
1201 if (phy->phy_mode == IEEE80211_MODE_11A)
1202 mask = BWI_SPROM_IDLE_TSSI_MASK_11A;
1203 else
1204 mask = BWI_SPROM_IDLE_TSSI_MASK_11BG;
1205
1206 rf->rf_idle_tssi0 = (int)__SHIFTOUT(val, mask);
1207 if (!IS_VALID_PA_PARAM(rf->rf_idle_tssi0))
1208 rf->rf_idle_tssi0 = 62;
1209
1210 #undef IS_VALID_PA_PARAM
1211
1212 /*
1213 * Calculate TX power map, which is indexed by TSSI
1214 */
1215 DPRINTF(sc, BWI_DBG_RF | BWI_DBG_ATTACH | BWI_DBG_TXPOWER,
1216 "%s\n", "TSSI-TX power map:");
1217 for (i = 0; i < BWI_TSSI_MAX; ++i) {
1218 error = bwi_rf_calc_txpower(&rf->rf_txpower_map0[i], i,
1219 pa_params);
1220 if (error) {
1221 if_printf(&sc->sc_ic.ic_if,
1222 "bwi_rf_calc_txpower failed\n");
1223 break;
1224 }
1225
1226 #ifdef BWI_DEBUG
1227 if (i != 0 && i % 8 == 0) {
1228 _DPRINTF(sc,
1229 BWI_DBG_RF | BWI_DBG_ATTACH | BWI_DBG_TXPOWER,
1230 "%s\n", "");
1231 }
1232 #endif
1233 _DPRINTF(sc, BWI_DBG_RF | BWI_DBG_ATTACH | BWI_DBG_TXPOWER,
1234 "%d ", rf->rf_txpower_map0[i]);
1235 }
1236 _DPRINTF(sc, BWI_DBG_RF | BWI_DBG_ATTACH | BWI_DBG_TXPOWER,
1237 "%s\n", "");
1238 back:
1239 DPRINTF(sc, BWI_DBG_RF | BWI_DBG_TXPOWER | BWI_DBG_ATTACH,
1240 "idle tssi0: %d\n", rf->rf_idle_tssi0);
1241 return error;
1242 }
1243
1244 static void
1245 bwi_rf_lo_update_11g(struct bwi_mac *mac)
1246 {
1247 struct bwi_softc *sc = mac->mac_sc;
1248 struct ifnet *ifp = &sc->sc_ic.ic_if;
1249 struct bwi_rf *rf = &mac->mac_rf;
1250 struct bwi_phy *phy = &mac->mac_phy;
1251 struct bwi_tpctl *tpctl = &mac->mac_tpctl;
1252 struct rf_saveregs regs;
1253 uint16_t ant_div, chan_ex;
1254 uint8_t devi_ctrl;
1255 u_int orig_chan;
1256
1257 DPRINTF(sc, BWI_DBG_RF | BWI_DBG_INIT, "%s enter\n", __func__);
1258
1259 /*
1260 * Save RF/PHY registers for later restoration
1261 */
1262 orig_chan = rf->rf_curchan;
1263 bzero(&regs, sizeof(regs));
1264
1265 if (phy->phy_flags & BWI_PHY_F_LINKED) {
1266 SAVE_PHY_REG(mac, &regs, 429);
1267 SAVE_PHY_REG(mac, &regs, 802);
1268
1269 PHY_WRITE(mac, 0x429, regs.phy_429 & 0x7fff);
1270 PHY_WRITE(mac, 0x802, regs.phy_802 & 0xfffc);
1271 }
1272
1273 ant_div = CSR_READ_2(sc, BWI_RF_ANTDIV);
1274 CSR_WRITE_2(sc, BWI_RF_ANTDIV, ant_div | 0x8000);
1275 chan_ex = CSR_READ_2(sc, BWI_RF_CHAN_EX);
1276
1277 SAVE_PHY_REG(mac, &regs, 15);
1278 SAVE_PHY_REG(mac, &regs, 2a);
1279 SAVE_PHY_REG(mac, &regs, 35);
1280 SAVE_PHY_REG(mac, &regs, 60);
1281 SAVE_RF_REG(mac, &regs, 43);
1282 SAVE_RF_REG(mac, &regs, 7a);
1283 SAVE_RF_REG(mac, &regs, 52);
1284 if (phy->phy_flags & BWI_PHY_F_LINKED) {
1285 SAVE_PHY_REG(mac, &regs, 811);
1286 SAVE_PHY_REG(mac, &regs, 812);
1287 SAVE_PHY_REG(mac, &regs, 814);
1288 SAVE_PHY_REG(mac, &regs, 815);
1289 }
1290
1291 /* Force to channel 6 */
1292 bwi_rf_set_chan(mac, 6, 0);
1293
1294 if (phy->phy_flags & BWI_PHY_F_LINKED) {
1295 PHY_WRITE(mac, 0x429, regs.phy_429 & 0x7fff);
1296 PHY_WRITE(mac, 0x802, regs.phy_802 & 0xfffc);
1297 bwi_mac_dummy_xmit(mac);
1298 }
1299 RF_WRITE(mac, 0x43, 0x6);
1300
1301 bwi_phy_set_bbp_atten(mac, 2);
1302
1303 CSR_WRITE_2(sc, BWI_RF_CHAN_EX, 0);
1304
1305 PHY_WRITE(mac, 0x2e, 0x7f);
1306 PHY_WRITE(mac, 0x80f, 0x78);
1307 PHY_WRITE(mac, 0x35, regs.phy_35 & 0xff7f);
1308 RF_WRITE(mac, 0x7a, regs.rf_7a & 0xfff0);
1309 PHY_WRITE(mac, 0x2b, 0x203);
1310 PHY_WRITE(mac, 0x2a, 0x8a3);
1311
1312 if (phy->phy_flags & BWI_PHY_F_LINKED) {
1313 PHY_WRITE(mac, 0x814, regs.phy_814 | 0x3);
1314 PHY_WRITE(mac, 0x815, regs.phy_815 & 0xfffc);
1315 PHY_WRITE(mac, 0x811, 0x1b3);
1316 PHY_WRITE(mac, 0x812, 0xb2);
1317 }
1318
1319 if ((ifp->if_flags & IFF_RUNNING) == 0)
1320 tpctl->tp_ctrl2 = bwi_rf_get_tp_ctrl2(mac);
1321 PHY_WRITE(mac, 0x80f, 0x8078);
1322
1323 /*
1324 * Measure all RF LO
1325 */
1326 devi_ctrl = _bwi_rf_lo_update_11g(mac, regs.rf_7a);
1327
1328 /*
1329 * Restore saved RF/PHY registers
1330 */
1331 if (phy->phy_flags & BWI_PHY_F_LINKED) {
1332 PHY_WRITE(mac, 0x15, 0xe300);
1333 PHY_WRITE(mac, 0x812, (devi_ctrl << 8) | 0xa0);
1334 DELAY(5);
1335 PHY_WRITE(mac, 0x812, (devi_ctrl << 8) | 0xa2);
1336 DELAY(2);
1337 PHY_WRITE(mac, 0x812, (devi_ctrl << 8) | 0xa3);
1338 } else {
1339 PHY_WRITE(mac, 0x15, devi_ctrl | 0xefa0);
1340 }
1341
1342 if ((ifp->if_flags & IFF_RUNNING) == 0)
1343 tpctl = NULL;
1344 bwi_rf_lo_adjust(mac, tpctl);
1345
1346 PHY_WRITE(mac, 0x2e, 0x807f);
1347 if (phy->phy_flags & BWI_PHY_F_LINKED)
1348 PHY_WRITE(mac, 0x2f, 0x202);
1349 else
1350 PHY_WRITE(mac, 0x2f, 0x101);
1351
1352 CSR_WRITE_2(sc, BWI_RF_CHAN_EX, chan_ex);
1353
1354 RESTORE_PHY_REG(mac, &regs, 15);
1355 RESTORE_PHY_REG(mac, &regs, 2a);
1356 RESTORE_PHY_REG(mac, &regs, 35);
1357 RESTORE_PHY_REG(mac, &regs, 60);
1358
1359 RESTORE_RF_REG(mac, &regs, 43);
1360 RESTORE_RF_REG(mac, &regs, 7a);
1361
1362 regs.rf_52 &= 0xf0;
1363 regs.rf_52 |= (RF_READ(mac, 0x52) & 0xf);
1364 RF_WRITE(mac, 0x52, regs.rf_52);
1365
1366 CSR_WRITE_2(sc, BWI_RF_ANTDIV, ant_div);
1367
1368 if (phy->phy_flags & BWI_PHY_F_LINKED) {
1369 RESTORE_PHY_REG(mac, &regs, 811);
1370 RESTORE_PHY_REG(mac, &regs, 812);
1371 RESTORE_PHY_REG(mac, &regs, 814);
1372 RESTORE_PHY_REG(mac, &regs, 815);
1373 RESTORE_PHY_REG(mac, &regs, 429);
1374 RESTORE_PHY_REG(mac, &regs, 802);
1375 }
1376
1377 bwi_rf_set_chan(mac, orig_chan, 1);
1378 }
1379
1380 static uint32_t
1381 bwi_rf_lo_devi_measure(struct bwi_mac *mac, uint16_t ctrl)
1382 {
1383 struct bwi_phy *phy = &mac->mac_phy;
1384 uint32_t devi = 0;
1385 int i;
1386
1387 if (phy->phy_flags & BWI_PHY_F_LINKED)
1388 ctrl <<= 8;
1389
1390 for (i = 0; i < 8; ++i) {
1391 if (phy->phy_flags & BWI_PHY_F_LINKED) {
1392 PHY_WRITE(mac, 0x15, 0xe300);
1393 PHY_WRITE(mac, 0x812, ctrl | 0xb0);
1394 DELAY(5);
1395 PHY_WRITE(mac, 0x812, ctrl | 0xb2);
1396 DELAY(2);
1397 PHY_WRITE(mac, 0x812, ctrl | 0xb3);
1398 DELAY(4);
1399 PHY_WRITE(mac, 0x15, 0xf300);
1400 } else {
1401 PHY_WRITE(mac, 0x15, ctrl | 0xefa0);
1402 DELAY(2);
1403 PHY_WRITE(mac, 0x15, ctrl | 0xefe0);
1404 DELAY(4);
1405 PHY_WRITE(mac, 0x15, ctrl | 0xffe0);
1406 }
1407 DELAY(8);
1408 devi += PHY_READ(mac, 0x2d);
1409 }
1410 return devi;
1411 }
1412
1413 static uint16_t
1414 bwi_rf_get_tp_ctrl2(struct bwi_mac *mac)
1415 {
1416 uint32_t devi_min;
1417 uint16_t tp_ctrl2 = 0;
1418 int i;
1419
1420 RF_WRITE(mac, 0x52, 0);
1421 DELAY(10);
1422 devi_min = bwi_rf_lo_devi_measure(mac, 0);
1423
1424 for (i = 0; i < 16; ++i) {
1425 uint32_t devi;
1426
1427 RF_WRITE(mac, 0x52, i);
1428 DELAY(10);
1429 devi = bwi_rf_lo_devi_measure(mac, 0);
1430
1431 if (devi < devi_min) {
1432 devi_min = devi;
1433 tp_ctrl2 = i;
1434 }
1435 }
1436 return tp_ctrl2;
1437 }
1438
1439 static uint8_t
1440 _bwi_rf_lo_update_11g(struct bwi_mac *mac, uint16_t orig_rf7a)
1441 {
1442 #define RF_ATTEN_LISTSZ 14
1443 #define BBP_ATTEN_MAX 4 /* half */
1444
1445 static const int rf_atten_list[RF_ATTEN_LISTSZ] =
1446 { 3, 1, 5, 7, 9, 2, 0, 4, 6, 8, 1, 2, 3, 4 };
1447 static const int rf_atten_init_list[RF_ATTEN_LISTSZ] =
1448 { 0, 3, 1, 5, 7, 3, 2, 0, 4, 6, -1, -1, -1, -1 };
1449 static const int rf_lo_measure_order[RF_ATTEN_LISTSZ] =
1450 { 3, 1, 5, 7, 9, 2, 0, 4, 6, 8, 10, 11, 12, 13 };
1451
1452 struct ifnet *ifp = &mac->mac_sc->sc_ic.ic_if;
1453 struct bwi_rf_lo lo_save, *lo;
1454 uint8_t devi_ctrl = 0;
1455 int idx, adj_rf7a = 0;
1456
1457 bzero(&lo_save, sizeof(lo_save));
1458 for (idx = 0; idx < RF_ATTEN_LISTSZ; ++idx) {
1459 int init_rf_atten = rf_atten_init_list[idx];
1460 int rf_atten = rf_atten_list[idx];
1461 int bbp_atten;
1462
1463 for (bbp_atten = 0; bbp_atten < BBP_ATTEN_MAX; ++bbp_atten) {
1464 uint16_t tp_ctrl2, rf7a;
1465
1466 if ((ifp->if_flags & IFF_RUNNING) == 0) {
1467 if (idx == 0) {
1468 bzero(&lo_save, sizeof(lo_save));
1469 } else if (init_rf_atten < 0) {
1470 lo = bwi_get_rf_lo(mac,
1471 rf_atten, 2 * bbp_atten);
1472 bcopy(lo, &lo_save, sizeof(lo_save));
1473 } else {
1474 lo = bwi_get_rf_lo(mac,
1475 init_rf_atten, 0);
1476 bcopy(lo, &lo_save, sizeof(lo_save));
1477 }
1478
1479 devi_ctrl = 0;
1480 adj_rf7a = 0;
1481
1482 /*
1483 * XXX
1484 * Linux driver overflows 'val'
1485 */
1486 if (init_rf_atten >= 0) {
1487 int val;
1488
1489 val = rf_atten * 2 + bbp_atten;
1490 if (val > 14) {
1491 adj_rf7a = 1;
1492 if (val > 17)
1493 devi_ctrl = 1;
1494 if (val > 19)
1495 devi_ctrl = 2;
1496 }
1497 }
1498 } else {
1499 lo = bwi_get_rf_lo(mac,
1500 rf_atten, 2 * bbp_atten);
1501 if (!bwi_rf_lo_isused(mac, lo))
1502 continue;
1503 bcopy(lo, &lo_save, sizeof(lo_save));
1504
1505 devi_ctrl = 3;
1506 adj_rf7a = 0;
1507 }
1508
1509 RF_WRITE(mac, BWI_RFR_ATTEN, rf_atten);
1510
1511 tp_ctrl2 = mac->mac_tpctl.tp_ctrl2;
1512 if (init_rf_atten < 0)
1513 tp_ctrl2 |= (3 << 4);
1514 RF_WRITE(mac, BWI_RFR_TXPWR, tp_ctrl2);
1515
1516 DELAY(10);
1517
1518 bwi_phy_set_bbp_atten(mac, bbp_atten * 2);
1519
1520 rf7a = orig_rf7a & 0xfff0;
1521 if (adj_rf7a)
1522 rf7a |= 0x8;
1523 RF_WRITE(mac, 0x7a, rf7a);
1524
1525 lo = bwi_get_rf_lo(mac,
1526 rf_lo_measure_order[idx], bbp_atten * 2);
1527 bwi_rf_lo_measure_11g(mac, &lo_save, lo, devi_ctrl);
1528 }
1529 }
1530 return devi_ctrl;
1531
1532 #undef RF_ATTEN_LISTSZ
1533 #undef BBP_ATTEN_MAX
1534 }
1535
1536 static void
1537 bwi_rf_lo_measure_11g(struct bwi_mac *mac, const struct bwi_rf_lo *src_lo,
1538 struct bwi_rf_lo *dst_lo, uint8_t devi_ctrl)
1539 {
1540 #define LO_ADJUST_MIN 1
1541 #define LO_ADJUST_MAX 8
1542 #define LO_ADJUST(hi, lo) { .ctrl_hi = hi, .ctrl_lo = lo }
1543 static const struct bwi_rf_lo rf_lo_adjust[LO_ADJUST_MAX] = {
1544 LO_ADJUST(1, 1),
1545 LO_ADJUST(1, 0),
1546 LO_ADJUST(1, -1),
1547 LO_ADJUST(0, -1),
1548 LO_ADJUST(-1, -1),
1549 LO_ADJUST(-1, 0),
1550 LO_ADJUST(-1, 1),
1551 LO_ADJUST(0, 1)
1552 };
1553 #undef LO_ADJUST
1554
1555 struct bwi_rf_lo lo_min;
1556 uint32_t devi_min;
1557 int found, loop_count, adjust_state;
1558
1559 bcopy(src_lo, &lo_min, sizeof(lo_min));
1560 RF_LO_WRITE(mac, &lo_min);
1561 devi_min = bwi_rf_lo_devi_measure(mac, devi_ctrl);
1562
1563 loop_count = 12; /* XXX */
1564 adjust_state = 0;
1565 do {
1566 struct bwi_rf_lo lo_base;
1567 int i, fin;
1568
1569 found = 0;
1570 if (adjust_state == 0) {
1571 i = LO_ADJUST_MIN;
1572 fin = LO_ADJUST_MAX;
1573 } else if (adjust_state % 2 == 0) {
1574 i = adjust_state - 1;
1575 fin = adjust_state + 1;
1576 } else {
1577 i = adjust_state - 2;
1578 fin = adjust_state + 2;
1579 }
1580
1581 if (i < LO_ADJUST_MIN)
1582 i += LO_ADJUST_MAX;
1583 KKASSERT(i <= LO_ADJUST_MAX && i >= LO_ADJUST_MIN);
1584
1585 if (fin > LO_ADJUST_MAX)
1586 fin -= LO_ADJUST_MAX;
1587 KKASSERT(fin <= LO_ADJUST_MAX && fin >= LO_ADJUST_MIN);
1588
1589 bcopy(&lo_min, &lo_base, sizeof(lo_base));
1590 for (;;) {
1591 struct bwi_rf_lo lo;
1592
1593 lo.ctrl_hi = lo_base.ctrl_hi +
1594 rf_lo_adjust[i - 1].ctrl_hi;
1595 lo.ctrl_lo = lo_base.ctrl_lo +
1596 rf_lo_adjust[i - 1].ctrl_lo;
1597
1598 if (abs(lo.ctrl_lo) < 9 && abs(lo.ctrl_hi) < 9) {
1599 uint32_t devi;
1600
1601 RF_LO_WRITE(mac, &lo);
1602 devi = bwi_rf_lo_devi_measure(mac, devi_ctrl);
1603 if (devi < devi_min) {
1604 devi_min = devi;
1605 adjust_state = i;
1606 found = 1;
1607 bcopy(&lo, &lo_min, sizeof(lo_min));
1608 }
1609 }
1610 if (i == fin)
1611 break;
1612 if (i == LO_ADJUST_MAX)
1613 i = LO_ADJUST_MIN;
1614 else
1615 ++i;
1616 }
1617 } while (loop_count-- && found);
1618
1619 bcopy(&lo_min, dst_lo, sizeof(*dst_lo));
1620
1621 #undef LO_ADJUST_MIN
1622 #undef LO_ADJUST_MAX
1623 }
1624
1625 static void
1626 bwi_rf_calc_nrssi_slope_11b(struct bwi_mac *mac)
1627 {
1628 #define SAVE_RF_MAX 3
1629 #define SAVE_PHY_MAX 8
1630
1631 static const uint16_t save_rf_regs[SAVE_RF_MAX] =
1632 { 0x7a, 0x52, 0x43 };
1633 static const uint16_t save_phy_regs[SAVE_PHY_MAX] =
1634 { 0x30, 0x26, 0x15, 0x2a, 0x20, 0x5a, 0x59, 0x58 };
1635
1636 struct bwi_softc *sc = mac->mac_sc;
1637 struct bwi_rf *rf = &mac->mac_rf;
1638 struct bwi_phy *phy = &mac->mac_phy;
1639 uint16_t save_rf[SAVE_RF_MAX];
1640 uint16_t save_phy[SAVE_PHY_MAX];
1641 uint16_t ant_div, bbp_atten, chan_ex;
1642 int16_t nrssi[2];
1643 int i;
1644
1645 /*
1646 * Save RF/PHY registers for later restoration
1647 */
1648 for (i = 0; i < SAVE_RF_MAX; ++i)
1649 save_rf[i] = RF_READ(mac, save_rf_regs[i]);
1650 for (i = 0; i < SAVE_PHY_MAX; ++i)
1651 save_phy[i] = PHY_READ(mac, save_phy_regs[i]);
1652
1653 ant_div = CSR_READ_2(sc, BWI_RF_ANTDIV);
1654 bbp_atten = CSR_READ_2(sc, BWI_BBP_ATTEN);
1655 chan_ex = CSR_READ_2(sc, BWI_RF_CHAN_EX);
1656
1657 /*
1658 * Calculate nrssi0
1659 */
1660 if (phy->phy_rev >= 5)
1661 RF_CLRBITS(mac, 0x7a, 0xff80);
1662 else
1663 RF_CLRBITS(mac, 0x7a, 0xfff0);
1664 PHY_WRITE(mac, 0x30, 0xff);
1665
1666 CSR_WRITE_2(sc, BWI_BPHY_CTRL, 0x7f7f);
1667
1668 PHY_WRITE(mac, 0x26, 0);
1669 PHY_SETBITS(mac, 0x15, 0x20);
1670 PHY_WRITE(mac, 0x2a, 0x8a3);
1671 RF_SETBITS(mac, 0x7a, 0x80);
1672
1673 nrssi[0] = (int16_t)PHY_READ(mac, 0x27);
1674
1675 /*
1676 * Calculate nrssi1
1677 */
1678 RF_CLRBITS(mac, 0x7a, 0xff80);
1679 if (phy->phy_version >= 2)
1680 CSR_WRITE_2(sc, BWI_BBP_ATTEN, 0x40);
1681 else if (phy->phy_version == 0)
1682 CSR_WRITE_2(sc, BWI_BBP_ATTEN, 0x122);
1683 else
1684 CSR_CLRBITS_2(sc, BWI_RF_CHAN_EX, 0xdfff);
1685
1686 PHY_WRITE(mac, 0x20, 0x3f3f);
1687 PHY_WRITE(mac, 0x15, 0xf330);
1688
1689 RF_WRITE(mac, 0x5a, 0x60);
1690 RF_CLRBITS(mac, 0x43, 0xff0f);
1691
1692 PHY_WRITE(mac, 0x5a, 0x480);
1693 PHY_WRITE(mac, 0x59, 0x810);
1694 PHY_WRITE(mac, 0x58, 0xd);
1695
1696 DELAY(20);
1697
1698 nrssi[1] = (int16_t)PHY_READ(mac, 0x27);
1699
1700 /*
1701 * Restore saved RF/PHY registers
1702 */
1703 PHY_WRITE(mac, save_phy_regs[0], save_phy[0]);
1704 RF_WRITE(mac, save_rf_regs[0], save_rf[0]);
1705
1706 CSR_WRITE_2(sc, BWI_RF_ANTDIV, ant_div);
1707
1708 for (i = 1; i < 4; ++i)
1709 PHY_WRITE(mac, save_phy_regs[i], save_phy[i]);
1710
1711 bwi_rf_workaround(mac, rf->rf_curchan);
1712
1713 if (phy->phy_version != 0)
1714 CSR_WRITE_2(sc, BWI_RF_CHAN_EX, chan_ex);
1715
1716 for (; i < SAVE_PHY_MAX; ++i)
1717 PHY_WRITE(mac, save_phy_regs[i], save_phy[i]);
1718
1719 for (i = 1; i < SAVE_RF_MAX; ++i)
1720 RF_WRITE(mac, save_rf_regs[i], save_rf[i]);
1721
1722 /*
1723 * Install calculated narrow RSSI values
1724 */
1725 if (nrssi[0] == nrssi[1])
1726 rf->rf_nrssi_slope = 0x10000;
1727 else
1728 rf->rf_nrssi_slope = 0x400000 / (nrssi[0] - nrssi[1]);
1729 if (nrssi[0] <= -4) {
1730 rf->rf_nrssi[0] = nrssi[0];
1731 rf->rf_nrssi[1] = nrssi[1];
1732 }
1733
1734 #undef SAVE_RF_MAX
1735 #undef SAVE_PHY_MAX
1736 }
1737
1738 static void
1739 bwi_rf_set_nrssi_ofs_11g(struct bwi_mac *mac)
1740 {
1741 #define SAVE_RF_MAX 2
1742 #define SAVE_PHY_COMM_MAX 10
1743 #define SAVE_PHY6_MAX 8
1744
1745 static const uint16_t save_rf_regs[SAVE_RF_MAX] =
1746 { 0x7a, 0x43 };
1747 static const uint16_t save_phy_comm_regs[SAVE_PHY_COMM_MAX] = {
1748 0x0001, 0x0811, 0x0812, 0x0814,
1749 0x0815, 0x005a, 0x0059, 0x0058,
1750 0x000a, 0x0003
1751 };
1752 static const uint16_t save_phy6_regs[SAVE_PHY6_MAX] = {
1753 0x002e, 0x002f, 0x080f, 0x0810,
1754 0x0801, 0x0060, 0x0014, 0x0478
1755 };
1756
1757 struct bwi_phy *phy = &mac->mac_phy;
1758 uint16_t save_rf[SAVE_RF_MAX];
1759 uint16_t save_phy_comm[SAVE_PHY_COMM_MAX];
1760 uint16_t save_phy6[SAVE_PHY6_MAX];
1761 uint16_t rf7b = 0xffff;
1762 int16_t nrssi;
1763 int i, phy6_idx = 0;
1764
1765 for (i = 0; i < SAVE_PHY_COMM_MAX; ++i)
1766 save_phy_comm[i] = PHY_READ(mac, save_phy_comm_regs[i]);
1767 for (i = 0; i < SAVE_RF_MAX; ++i)
1768 save_rf[i] = RF_READ(mac, save_rf_regs[i]);
1769
1770 PHY_CLRBITS(mac, 0x429, 0x8000);
1771 PHY_FILT_SETBITS(mac, 0x1, 0x3fff, 0x4000);
1772 PHY_SETBITS(mac, 0x811, 0xc);
1773 PHY_FILT_SETBITS(mac, 0x812, 0xfff3, 0x4);
1774 PHY_CLRBITS(mac, 0x802, 0x3);
1775
1776 if (phy->phy_rev >= 6) {
1777 for (i = 0; i < SAVE_PHY6_MAX; ++i)
1778 save_phy6[i] = PHY_READ(mac, save_phy6_regs[i]);
1779
1780 PHY_WRITE(mac, 0x2e, 0);
1781 PHY_WRITE(mac, 0x2f, 0);
1782 PHY_WRITE(mac, 0x80f, 0);
1783 PHY_WRITE(mac, 0x810, 0);
1784 PHY_SETBITS(mac, 0x478, 0x100);
1785 PHY_SETBITS(mac, 0x801, 0x40);
1786 PHY_SETBITS(mac, 0x60, 0x40);
1787 PHY_SETBITS(mac, 0x14, 0x200);
1788 }
1789
1790 RF_SETBITS(mac, 0x7a, 0x70);
1791 RF_SETBITS(mac, 0x7a, 0x80);
1792
1793 DELAY(30);
1794
1795 nrssi = bwi_nrssi_11g(mac);
1796 if (nrssi == 31) {
1797 for (i = 7; i >= 4; --i) {
1798 RF_WRITE(mac, 0x7b, i);
1799 DELAY(20);
1800 nrssi = bwi_nrssi_11g(mac);
1801 if (nrssi < 31 && rf7b == 0xffff)
1802 rf7b = i;
1803 }
1804 if (rf7b == 0xffff)
1805 rf7b = 4;
1806 } else {
1807 struct bwi_gains gains;
1808
1809 RF_CLRBITS(mac, 0x7a, 0xff80);
1810
1811 PHY_SETBITS(mac, 0x814, 0x1);
1812 PHY_CLRBITS(mac, 0x815, 0x1);
1813 PHY_SETBITS(mac, 0x811, 0xc);
1814 PHY_SETBITS(mac, 0x812, 0xc);
1815 PHY_SETBITS(mac, 0x811, 0x30);
1816 PHY_SETBITS(mac, 0x812, 0x30);
1817 PHY_WRITE(mac, 0x5a, 0x480);
1818 PHY_WRITE(mac, 0x59, 0x810);
1819 PHY_WRITE(mac, 0x58, 0xd);
1820 if (phy->phy_version == 0)
1821 PHY_WRITE(mac, 0x3, 0x122);
1822 else
1823 PHY_SETBITS(mac, 0xa, 0x2000);
1824 PHY_SETBITS(mac, 0x814, 0x4);
1825 PHY_CLRBITS(mac, 0x815, 0x4);
1826 PHY_FILT_SETBITS(mac, 0x3, 0xff9f, 0x40);
1827 RF_SETBITS(mac, 0x7a, 0xf);
1828
1829 bzero(&gains, sizeof(gains));
1830 gains.tbl_gain1 = 3;
1831 gains.tbl_gain2 = 0;
1832 gains.phy_gain = 1;
1833 bwi_set_gains(mac, &gains);
1834
1835 RF_FILT_SETBITS(mac, 0x43, 0xf0, 0xf);
1836 DELAY(30);
1837
1838 nrssi = bwi_nrssi_11g(mac);
1839 if (nrssi == -32) {
1840 for (i = 0; i < 4; ++i) {
1841 RF_WRITE(mac, 0x7b, i);
1842 DELAY(20);
1843 nrssi = bwi_nrssi_11g(mac);
1844 if (nrssi > -31 && rf7b == 0xffff)
1845 rf7b = i;
1846 }
1847 if (rf7b == 0xffff)
1848 rf7b = 3;
1849 } else {
1850 rf7b = 0;
1851 }
1852 }
1853 RF_WRITE(mac, 0x7b, rf7b);
1854
1855 /*
1856 * Restore saved RF/PHY registers
1857 */
1858 if (phy->phy_rev >= 6) {
1859 for (phy6_idx = 0; phy6_idx < 4; ++phy6_idx) {
1860 PHY_WRITE(mac, save_phy6_regs[phy6_idx],
1861 save_phy6[phy6_idx]);
1862 }
1863 }
1864
1865 /* Saved PHY registers 0, 1, 2 are handled later */
1866 for (i = 3; i < SAVE_PHY_COMM_MAX; ++i)
1867 PHY_WRITE(mac, save_phy_comm_regs[i], save_phy_comm[i]);
1868
1869 for (i = SAVE_RF_MAX - 1; i >= 0; --i)
1870 RF_WRITE(mac, save_rf_regs[i], save_rf[i]);
1871
1872 PHY_SETBITS(mac, 0x802, 0x3);
1873 PHY_SETBITS(mac, 0x429, 0x8000);
1874
1875 bwi_set_gains(mac, NULL);
1876
1877 if (phy->phy_rev >= 6) {
1878 for (; phy6_idx < SAVE_PHY6_MAX; ++phy6_idx) {
1879 PHY_WRITE(mac, save_phy6_regs[phy6_idx],
1880 save_phy6[phy6_idx]);
1881 }
1882 }
1883
1884 PHY_WRITE(mac, save_phy_comm_regs[0], save_phy_comm[0]);
1885 PHY_WRITE(mac, save_phy_comm_regs[2], save_phy_comm[2]);
1886 PHY_WRITE(mac, save_phy_comm_regs[1], save_phy_comm[1]);
1887
1888 #undef SAVE_RF_MAX
1889 #undef SAVE_PHY_COMM_MAX
1890 #undef SAVE_PHY6_MAX
1891 }
1892
1893 static void
1894 bwi_rf_calc_nrssi_slope_11g(struct bwi_mac *mac)
1895 {
1896 #define SAVE_RF_MAX 3
1897 #define SAVE_PHY_COMM_MAX 4
1898 #define SAVE_PHY3_MAX 8
1899
1900 static const uint16_t save_rf_regs[SAVE_RF_MAX] =
1901 { 0x7a, 0x52, 0x43 };
1902 static const uint16_t save_phy_comm_regs[SAVE_PHY_COMM_MAX] =
1903 { 0x15, 0x5a, 0x59, 0x58 };
1904 static const uint16_t save_phy3_regs[SAVE_PHY3_MAX] = {
1905 0x002e, 0x002f, 0x080f, 0x0810,
1906 0x0801, 0x0060, 0x0014, 0x0478
1907 };
1908
1909 struct bwi_softc *sc = mac->mac_sc;
1910 struct bwi_phy *phy = &mac->mac_phy;
1911 struct bwi_rf *rf = &mac->mac_rf;
1912 uint16_t save_rf[SAVE_RF_MAX];
1913 uint16_t save_phy_comm[SAVE_PHY_COMM_MAX];
1914 uint16_t save_phy3[SAVE_PHY3_MAX];
1915 uint16_t ant_div, bbp_atten, chan_ex;
1916 struct bwi_gains gains;
1917 int16_t nrssi[2];
1918 int i, phy3_idx = 0;
1919
1920 if (rf->rf_rev >= 9)
1921 return;
1922 else if (rf->rf_rev == 8)
1923 bwi_rf_set_nrssi_ofs_11g(mac);
1924
1925 PHY_CLRBITS(mac, 0x429, 0x8000);
1926 PHY_CLRBITS(mac, 0x802, 0x3);
1927
1928 /*
1929 * Save RF/PHY registers for later restoration
1930 */
1931 ant_div = CSR_READ_2(sc, BWI_RF_ANTDIV);
1932 CSR_SETBITS_2(sc, BWI_RF_ANTDIV, 0x8000);
1933
1934 for (i = 0; i < SAVE_RF_MAX; ++i)
1935 save_rf[i] = RF_READ(mac, save_rf_regs[i]);
1936 for (i = 0; i < SAVE_PHY_COMM_MAX; ++i)
1937 save_phy_comm[i] = PHY_READ(mac, save_phy_comm_regs[i]);
1938
1939 bbp_atten = CSR_READ_2(sc, BWI_BBP_ATTEN);
1940 chan_ex = CSR_READ_2(sc, BWI_RF_CHAN_EX);
1941
1942 if (phy->phy_rev >= 3) {
1943 for (i = 0; i < SAVE_PHY3_MAX; ++i)
1944 save_phy3[i] = PHY_READ(mac, save_phy3_regs[i]);
1945
1946 PHY_WRITE(mac, 0x2e, 0);
1947 PHY_WRITE(mac, 0x810, 0);
1948
1949 if (phy->phy_rev == 4 || phy->phy_rev == 6 ||
1950 phy->phy_rev == 7) {
1951 PHY_SETBITS(mac, 0x478, 0x100);
1952 PHY_SETBITS(mac, 0x810, 0x40);
1953 } else if (phy->phy_rev == 3 || phy->phy_rev == 5) {
1954 PHY_CLRBITS(mac, 0x810, 0x40);
1955 }
1956
1957 PHY_SETBITS(mac, 0x60, 0x40);
1958 PHY_SETBITS(mac, 0x14, 0x200);
1959 }
1960
1961 /*
1962 * Calculate nrssi0
1963 */
1964 RF_SETBITS(mac, 0x7a, 0x70);
1965
1966 bzero(&gains, sizeof(gains));
1967 gains.tbl_gain1 = 0;
1968 gains.tbl_gain2 = 8;
1969 gains.phy_gain = 0;
1970 bwi_set_gains(mac, &gains);
1971
1972 RF_CLRBITS(mac, 0x7a, 0xff08);
1973 if (phy->phy_rev >= 2) {
1974 PHY_FILT_SETBITS(mac, 0x811, 0xffcf, 0x30);
1975 PHY_FILT_SETBITS(mac, 0x812, 0xffcf, 0x10);
1976 }
1977
1978 RF_SETBITS(mac, 0x7a, 0x80);
1979 DELAY(20);
1980 nrssi[0] = bwi_nrssi_11g(mac);
1981
1982 /*
1983 * Calculate nrssi1
1984 */
1985 RF_CLRBITS(mac, 0x7a, 0xff80);
1986 if (phy->phy_version >= 2)
1987 PHY_FILT_SETBITS(mac, 0x3, 0xff9f, 0x40);
1988 CSR_SETBITS_2(sc, BWI_RF_CHAN_EX, 0x2000);
1989
1990 RF_SETBITS(mac, 0x7a, 0xf);
1991 PHY_WRITE(mac, 0x15, 0xf330);
1992 if (phy->phy_rev >= 2) {
1993 PHY_FILT_SETBITS(mac, 0x812, 0xffcf, 0x20);
1994 PHY_FILT_SETBITS(mac, 0x811, 0xffcf, 0x20);
1995 }
1996
1997 bzero(&gains, sizeof(gains));
1998 gains.tbl_gain1 = 3;
1999 gains.tbl_gain2 = 0;
2000 gains.phy_gain = 1;
2001 bwi_set_gains(mac, &gains);
2002
2003 if (rf->rf_rev == 8) {
2004 RF_WRITE(mac, 0x43, 0x1f);
2005 } else {
2006 RF_FILT_SETBITS(mac, 0x52, 0xff0f, 0x60);
2007 RF_FILT_SETBITS(mac, 0x43, 0xfff0, 0x9);
2008 }
2009 PHY_WRITE(mac, 0x5a, 0x480);
2010 PHY_WRITE(mac, 0x59, 0x810);
2011 PHY_WRITE(mac, 0x58, 0xd);
2012 DELAY(20);
2013
2014 nrssi[1] = bwi_nrssi_11g(mac);
2015
2016 /*
2017 * Install calculated narrow RSSI values
2018 */
2019 if (nrssi[1] == nrssi[0])
2020 rf->rf_nrssi_slope = 0x10000;
2021 else
2022 rf->rf_nrssi_slope = 0x400000 / (nrssi[0] - nrssi[1]);
2023 if (nrssi[0] >= -4) {
2024 rf->rf_nrssi[0] = nrssi[1];
2025 rf->rf_nrssi[1] = nrssi[0];
2026 }
2027
2028 /*
2029 * Restore saved RF/PHY registers
2030 */
2031 if (phy->phy_rev >= 3) {
2032 for (phy3_idx = 0; phy3_idx < 4; ++phy3_idx) {
2033 PHY_WRITE(mac, save_phy3_regs[phy3_idx],
2034 save_phy3[phy3_idx]);
2035 }
2036 }
2037 if (phy->phy_rev >= 2) {
2038 PHY_CLRBITS(mac, 0x812, 0x30);
2039 PHY_CLRBITS(mac, 0x811, 0x30);
2040 }
2041
2042 for (i = 0; i < SAVE_RF_MAX; ++i)
2043 RF_WRITE(mac, save_rf_regs[i], save_rf[i]);
2044
2045 CSR_WRITE_2(sc, BWI_RF_ANTDIV, ant_div);
2046 CSR_WRITE_2(sc, BWI_BBP_ATTEN, bbp_atten);
2047 CSR_WRITE_2(sc, BWI_RF_CHAN_EX, chan_ex);
2048
2049 for (i = 0; i < SAVE_PHY_COMM_MAX; ++i)
2050 PHY_WRITE(mac, save_phy_comm_regs[i], save_phy_comm[i]);
2051
2052 bwi_rf_workaround(mac, rf->rf_curchan);
2053 PHY_SETBITS(mac, 0x802, 0x3);
2054 bwi_set_gains(mac, NULL);
2055 PHY_SETBITS(mac, 0x429, 0x8000);
2056
2057 if (phy->phy_rev >= 3) {
2058 for (; phy3_idx < SAVE_PHY3_MAX; ++phy3_idx) {
2059 PHY_WRITE(mac, save_phy3_regs[phy3_idx],
2060 save_phy3[phy3_idx]);
2061 }
2062 }
2063
2064 bwi_rf_init_sw_nrssi_table(mac);
2065 bwi_rf_set_nrssi_thr_11g(mac);
2066
2067 #undef SAVE_RF_MAX
2068 #undef SAVE_PHY_COMM_MAX
2069 #undef SAVE_PHY3_MAX
2070 }
2071
2072 static void
2073 bwi_rf_init_sw_nrssi_table(struct bwi_mac *mac)
2074 {
2075 struct bwi_rf *rf = &mac->mac_rf;
2076 int d, i;
2077
2078 d = 0x1f - rf->rf_nrssi[0];
2079 for (i = 0; i < BWI_NRSSI_TBLSZ; ++i) {
2080 int val;
2081
2082 val = (((i - d) * rf->rf_nrssi_slope) / 0x10000) + 0x3a;
2083 if (val < 0)
2084 val = 0;
2085 else if (val > 0x3f)
2086 val = 0x3f;
2087
2088 rf->rf_nrssi_table[i] = val;
2089 }
2090 }
2091
2092 void
2093 bwi_rf_init_hw_nrssi_table(struct bwi_mac *mac, uint16_t adjust)
2094 {
2095 int i;
2096
2097 for (i = 0; i < BWI_NRSSI_TBLSZ; ++i) {
2098 int16_t val;
2099
2100 val = bwi_nrssi_read(mac, i);
2101
2102 val -= adjust;
2103 if (val < -32)
2104 val = -32;
2105 else if (val > 31);
2106 val = 31;
2107
2108 bwi_nrssi_write(mac, i, val);
2109 }
2110 }
2111
2112 static void
2113 bwi_rf_set_nrssi_thr_11b(struct bwi_mac *mac)
2114 {
2115 struct bwi_rf *rf = &mac->mac_rf;
2116 int32_t thr;
2117
2118 if (rf->rf_type != BWI_RF_T_BCM2050 ||
2119 (mac->mac_sc->sc_card_flags & BWI_CARD_F_SW_NRSSI) == 0)
2120 return;
2121
2122 /*
2123 * Calculate nrssi threshold
2124 */
2125 if (rf->rf_rev >= 6) {
2126 thr = (rf->rf_nrssi[1] - rf->rf_nrssi[0]) * 32;
2127 thr += 20 * (rf->rf_nrssi[0] + 1);
2128 thr /= 40;
2129 } else {
2130 thr = rf->rf_nrssi[1] - 5;
2131 }
2132 if (thr < 0)
2133 thr = 0;
2134 else if (thr > 0x3e)
2135 thr = 0x3e;
2136
2137 PHY_READ(mac, BWI_PHYR_NRSSI_THR_11B); /* dummy read */
2138 PHY_WRITE(mac, BWI_PHYR_NRSSI_THR_11B, (((uint16_t)thr) << 8) | 0x1c);
2139
2140 if (rf->rf_rev >= 6) {
2141 PHY_WRITE(mac, 0x87, 0xe0d);
2142 PHY_WRITE(mac, 0x86, 0xc0b);
2143 PHY_WRITE(mac, 0x85, 0xa09);
2144 PHY_WRITE(mac, 0x84, 0x808);
2145 PHY_WRITE(mac, 0x83, 0x808);
2146 PHY_WRITE(mac, 0x82, 0x604);
2147 PHY_WRITE(mac, 0x81, 0x302);
2148 PHY_WRITE(mac, 0x80, 0x100);
2149 }
2150 }
2151
2152 static __inline int32_t
2153 _nrssi_threshold(const struct bwi_rf *rf, int32_t val)
2154 {
2155 val *= (rf->rf_nrssi[1] - rf->rf_nrssi[0]);
2156 val += (rf->rf_nrssi[0] << 6);
2157 if (val < 32)
2158 val += 31;
2159 else
2160 val += 32;
2161 val >>= 6;
2162 if (val < -31)
2163 val = -31;
2164 else if (val > 31)
2165 val = 31;
2166 return val;
2167 }
2168
2169 static void
2170 bwi_rf_set_nrssi_thr_11g(struct bwi_mac *mac)
2171 {
2172 int32_t thr1, thr2;
2173 uint16_t thr;
2174
2175 /*
2176 * Find the two nrssi thresholds
2177 */
2178 if ((mac->mac_phy.phy_flags & BWI_PHY_F_LINKED) == 0 ||
2179 (mac->mac_sc->sc_card_flags & BWI_CARD_F_SW_NRSSI) == 0) {
2180 int16_t nrssi;
2181
2182 nrssi = bwi_nrssi_read(mac, 0x20);
2183 if (nrssi >= 32)
2184 nrssi -= 64;
2185
2186 if (nrssi < 3) {
2187 thr1 = 0x2b;
2188 thr2 = 0x27;
2189 } else {
2190 thr1 = 0x2d;
2191 thr2 = 0x2b;
2192 }
2193 } else {
2194 /* TODO Interfere mode */
2195 thr1 = _nrssi_threshold(&mac->mac_rf, 0x11);
2196 thr2 = _nrssi_threshold(&mac->mac_rf, 0xe);
2197 }
2198
2199 #define NRSSI_THR1_MASK __BITS(5, 0)
2200 #define NRSSI_THR2_MASK __BITS(11, 6)
2201
2202 thr = __SHIFTIN((uint32_t)thr1, NRSSI_THR1_MASK) |
2203 __SHIFTIN((uint32_t)thr2, NRSSI_THR2_MASK);
2204 PHY_FILT_SETBITS(mac, BWI_PHYR_NRSSI_THR_11G, 0xf000, thr);
2205
2206 #undef NRSSI_THR1_MASK
2207 #undef NRSSI_THR2_MASK
2208 }
2209
2210 void
2211 bwi_rf_clear_tssi(struct bwi_mac *mac)
2212 {
2213 /* XXX use function pointer */
2214 if (mac->mac_phy.phy_mode == IEEE80211_MODE_11A) {
2215 /* TODO:11A */
2216 } else {
2217 uint16_t val;
2218 int i;
2219
2220 val = __SHIFTIN(BWI_INVALID_TSSI, BWI_LO_TSSI_MASK) |
2221 __SHIFTIN(BWI_INVALID_TSSI, BWI_HI_TSSI_MASK);
2222
2223 for (i = 0; i < 2; ++i) {
2224 MOBJ_WRITE_2(mac, BWI_COMM_MOBJ,
2225 BWI_COMM_MOBJ_TSSI_DS + (i * 2), val);
2226 }
2227
2228 for (i = 0; i < 2; ++i) {
2229 MOBJ_WRITE_2(mac, BWI_COMM_MOBJ,
2230 BWI_COMM_MOBJ_TSSI_OFDM + (i * 2), val);
2231 }
2232 }
2233 }
2234
2235 void
2236 bwi_rf_clear_state(struct bwi_rf *rf)
2237 {
2238 int i;
2239
2240 rf->rf_flags &= ~BWI_RF_CLEAR_FLAGS;
2241 bzero(rf->rf_lo, sizeof(rf->rf_lo));
2242 bzero(rf->rf_lo_used, sizeof(rf->rf_lo_used));
2243
2244 rf->rf_nrssi_slope = 0;
2245 rf->rf_nrssi[0] = BWI_INVALID_NRSSI;
2246 rf->rf_nrssi[1] = BWI_INVALID_NRSSI;
2247
2248 for (i = 0; i < BWI_NRSSI_TBLSZ; ++i)
2249 rf->rf_nrssi_table[i] = i;
2250
2251 rf->rf_lo_gain = 0;
2252 rf->rf_rx_gain = 0;
2253
2254 bcopy(rf->rf_txpower_map0, rf->rf_txpower_map,
2255 sizeof(rf->rf_txpower_map));
2256 rf->rf_idle_tssi = rf->rf_idle_tssi0;
2257 }
2258
2259 static void
2260 bwi_rf_on_11a(struct bwi_mac *mac)
2261 {
2262 /* TODO:11A */
2263 }
2264
2265 static void
2266 bwi_rf_on_11bg(struct bwi_mac *mac)
2267 {
2268 struct bwi_phy *phy = &mac->mac_phy;
2269
2270 PHY_WRITE(mac, 0x15, 0x8000);
2271 PHY_WRITE(mac, 0x15, 0xcc00);
2272 if (phy->phy_flags & BWI_PHY_F_LINKED)
2273 PHY_WRITE(mac, 0x15, 0xc0);
2274 else
2275 PHY_WRITE(mac, 0x15, 0);
2276
2277 bwi_rf_set_chan(mac, 6 /* XXX */, 1);
2278 }
2279
2280 void
2281 bwi_rf_set_ant_mode(struct bwi_mac *mac, int ant_mode)
2282 {
2283 struct bwi_softc *sc = mac->mac_sc;
2284 struct bwi_phy *phy = &mac->mac_phy;
2285 uint16_t val;
2286
2287 KKASSERT(ant_mode == BWI_ANT_MODE_0 ||
2288 ant_mode == BWI_ANT_MODE_1 ||
2289 ant_mode == BWI_ANT_MODE_AUTO);
2290
2291 HFLAGS_CLRBITS(mac, BWI_HFLAG_AUTO_ANTDIV);
2292
2293 if (phy->phy_mode == IEEE80211_MODE_11B) {
2294 /* NOTE: v4/v3 conflicts, take v3 */
2295 if (mac->mac_rev == 2)
2296 val = BWI_ANT_MODE_AUTO;
2297 else
2298 val = ant_mode;
2299 val <<= 7;
2300 PHY_FILT_SETBITS(mac, 0x3e2, 0xfe7f, val);
2301 } else { /* 11a/g */
2302 /* XXX reg/value naming */
2303 val = ant_mode << 7;
2304 PHY_FILT_SETBITS(mac, 0x401, 0x7e7f, val);
2305
2306 if (ant_mode == BWI_ANT_MODE_AUTO)
2307 PHY_CLRBITS(mac, 0x42b, 0x100);
2308
2309 if (phy->phy_mode == IEEE80211_MODE_11A) {
2310 /* TODO:11A */
2311 } else { /* 11g */
2312 if (ant_mode == BWI_ANT_MODE_AUTO)
2313 PHY_SETBITS(mac, 0x48c, 0x2000);
2314 else
2315 PHY_CLRBITS(mac, 0x48c, 0x2000);
2316
2317 if (phy->phy_rev >= 2) {
2318 PHY_SETBITS(mac, 0x461, 0x10);
2319 PHY_FILT_SETBITS(mac, 0x4ad, 0xff00, 0x15);
2320 if (phy->phy_rev == 2) {
2321 PHY_WRITE(mac, 0x427, 0x8);
2322 } else {
2323 PHY_FILT_SETBITS(mac, 0x427,
2324 0xff00, 0x8);
2325 }
2326
2327 if (phy->phy_rev >= 6)
2328 PHY_WRITE(mac, 0x49b, 0xdc);
2329 }
2330 }
2331 }
2332
2333 /* XXX v4 set AUTO_ANTDIV unconditionally */
2334 if (ant_mode == BWI_ANT_MODE_AUTO)
2335 HFLAGS_SETBITS(mac, BWI_HFLAG_AUTO_ANTDIV);
2336
2337 val = ant_mode << 8;
2338 MOBJ_FILT_SETBITS_2(mac, BWI_COMM_MOBJ, BWI_COMM_MOBJ_TX_BEACON,
2339 0xfc3f, val);
2340 MOBJ_FILT_SETBITS_2(mac, BWI_COMM_MOBJ, BWI_COMM_MOBJ_TX_ACK,
2341 0xfc3f, val);
2342 MOBJ_FILT_SETBITS_2(mac, BWI_COMM_MOBJ, BWI_COMM_MOBJ_TX_PROBE_RESP,
2343 0xfc3f, val);
2344
2345 /* XXX what's these */
2346 if (phy->phy_mode == IEEE80211_MODE_11B)
2347 CSR_SETBITS_2(sc, 0x5e, 0x4);
2348
2349 CSR_WRITE_4(sc, 0x100, 0x1000000);
2350 if (mac->mac_rev < 5)
2351 CSR_WRITE_4(sc, 0x10c, 0x1000000);
2352
2353 mac->mac_rf.rf_ant_mode = ant_mode;
2354 }
2355
2356 int
2357 bwi_rf_get_latest_tssi(struct bwi_mac *mac, int8_t tssi[], uint16_t ofs)
2358 {
2359 int i;
2360
2361 for (i = 0; i < 4; ) {
2362 uint16_t val;
2363
2364 val = MOBJ_READ_2(mac, BWI_COMM_MOBJ, ofs + i);
2365 tssi[i++] = (int8_t)__SHIFTOUT(val, BWI_LO_TSSI_MASK);
2366 tssi[i++] = (int8_t)__SHIFTOUT(val, BWI_HI_TSSI_MASK);
2367 }
2368
2369 for (i = 0; i < 4; ++i) {
2370 if (tssi[i] == BWI_INVALID_TSSI)
2371 return EINVAL;
2372 }
2373 return 0;
2374 }
2375
2376 int
2377 bwi_rf_tssi2dbm(struct bwi_mac *mac, int8_t tssi, int8_t *txpwr)
2378 {
2379 struct bwi_rf *rf = &mac->mac_rf;
2380 int pwr_idx;
2381
2382 pwr_idx = rf->rf_idle_tssi + (int)tssi - rf->rf_base_tssi;
2383 #if 0
2384 if (pwr_idx < 0 || pwr_idx >= BWI_TSSI_MAX)
2385 return EINVAL;
2386 #else
2387 if (pwr_idx < 0)
2388 pwr_idx = 0;
2389 else if (pwr_idx >= BWI_TSSI_MAX)
2390 pwr_idx = BWI_TSSI_MAX - 1;
2391 #endif
2392
2393 *txpwr = rf->rf_txpower_map[pwr_idx];
2394 return 0;
2395 }
2396
2397 static int
2398 bwi_rf_calc_rssi_bcm2050(struct bwi_mac *mac, const struct bwi_rxbuf_hdr *hdr)
2399 {
2400 uint16_t flags1, flags3;
2401 int rssi, lna_gain;
2402
2403 rssi = hdr->rxh_rssi;
2404 flags1 = le16toh(hdr->rxh_flags1);
2405 flags3 = le16toh(hdr->rxh_flags3);
2406
2407 #define NEW_BCM2050_RSSI
2408 #ifdef NEW_BCM2050_RSSI
2409 if (flags1 & BWI_RXH_F1_OFDM) {
2410 if (rssi > 127)
2411 rssi -= 256;
2412 if (flags3 & BWI_RXH_F3_BCM2050_RSSI)
2413 rssi += 17;
2414 else
2415 rssi -= 4;
2416 return rssi;
2417 }
2418
2419 if (mac->mac_sc->sc_card_flags & BWI_CARD_F_SW_NRSSI) {
2420 struct bwi_rf *rf = &mac->mac_rf;
2421
2422 if (rssi >= BWI_NRSSI_TBLSZ)
2423 rssi = BWI_NRSSI_TBLSZ - 1;
2424
2425 rssi = ((31 - (int)rf->rf_nrssi_table[rssi]) * -131) / 128;
2426 rssi -= 67;
2427 } else {
2428 rssi = ((31 - rssi) * -149) / 128;
2429 rssi -= 68;
2430 }
2431
2432 if (mac->mac_phy.phy_mode != IEEE80211_MODE_11G)
2433 return rssi;
2434
2435 if (flags3 & BWI_RXH_F3_BCM2050_RSSI)
2436 rssi += 20;
2437
2438 lna_gain = __SHIFTOUT(le16toh(hdr->rxh_phyinfo),
2439 BWI_RXH_PHYINFO_LNAGAIN);
2440 DPRINTF(mac->mac_sc, BWI_DBG_RF | BWI_DBG_RX,
2441 "lna_gain %d, phyinfo 0x%04x\n",
2442 lna_gain, le16toh(hdr->rxh_phyinfo));
2443 switch (lna_gain) {
2444 case 0:
2445 rssi += 27;
2446 break;
2447 case 1:
2448 rssi += 6;
2449 break;
2450 case 2:
2451 rssi += 12;
2452 break;
2453 case 3:
2454 /*
2455 * XXX
2456 * According to v3 spec, we should do _nothing_ here,
2457 * but it seems that the result RSSI will be too low
2458 * (relative to what ath(4) says). Raise it a little
2459 * bit.
2460 */
2461 rssi += 5;
2462 break;
2463 default:
2464 panic("impossible lna gain %d", lna_gain);
2465 }
2466 #else /* !NEW_BCM2050_RSSI */
2467 lna_gain = 0; /* shut up gcc warning */
2468
2469 if (flags1 & BWI_RXH_F1_OFDM) {
2470 if (rssi > 127)
2471 rssi -= 256;
2472 rssi = (rssi * 73) / 64;
2473
2474 if (flags3 & BWI_RXH_F3_BCM2050_RSSI)
2475 rssi += 25;
2476 else
2477 rssi -= 3;
2478 return rssi;
2479 }
2480
2481 if (mac->mac_sc->sc_card_flags & BWI_CARD_F_SW_NRSSI) {
2482 struct bwi_rf *rf = &mac->mac_rf;
2483
2484 if (rssi >= BWI_NRSSI_TBLSZ)
2485 rssi = BWI_NRSSI_TBLSZ - 1;
2486
2487 rssi = ((31 - (int)rf->rf_nrssi_table[rssi]) * -131) / 128;
2488 rssi -= 57;
2489 } else {
2490 rssi = ((31 - rssi) * -149) / 128;
2491 rssi -= 68;
2492 }
2493
2494 if (mac->mac_phy.phy_mode != IEEE80211_MODE_11G)
2495 return rssi;
2496
2497 if (flags3 & BWI_RXH_F3_BCM2050_RSSI)
2498 rssi += 25;
2499 #endif /* NEW_BCM2050_RSSI */
2500 return rssi;
2501 }
2502
2503 static int
2504 bwi_rf_calc_rssi_bcm2053(struct bwi_mac *mac, const struct bwi_rxbuf_hdr *hdr)
2505 {
2506 uint16_t flags1;
2507 int rssi;
2508
2509 rssi = (((int)hdr->rxh_rssi - 11) * 103) / 64;
2510
2511 flags1 = le16toh(hdr->rxh_flags1);
2512 if (flags1 & BWI_RXH_F1_BCM2053_RSSI)
2513 rssi -= 109;
2514 else
2515 rssi -= 83;
2516 return rssi;
2517 }
2518
2519 static int
2520 bwi_rf_calc_rssi_bcm2060(struct bwi_mac *mac, const struct bwi_rxbuf_hdr *hdr)
2521 {
2522 int rssi;
2523
2524 rssi = hdr->rxh_rssi;
2525 if (rssi > 127)
2526 rssi -= 256;
2527 return rssi;
2528 }
2529
2530 static uint16_t
2531 bwi_rf_lo_measure_11b(struct bwi_mac *mac)
2532 {
2533 uint16_t val;
2534 int i;
2535
2536 val = 0;
2537 for (i = 0; i < 10; ++i) {
2538 PHY_WRITE(mac, 0x15, 0xafa0);
2539 DELAY(1);
2540 PHY_WRITE(mac, 0x15, 0xefa0);
2541 DELAY(10);
2542 PHY_WRITE(mac, 0x15, 0xffa0);
2543 DELAY(40);
2544
2545 val += PHY_READ(mac, 0x2c);
2546 }
2547 return val;
2548 }
2549
2550 static void
2551 bwi_rf_lo_update_11b(struct bwi_mac *mac)
2552 {
2553 struct bwi_softc *sc = mac->mac_sc;
2554 struct bwi_rf *rf = &mac->mac_rf;
2555 struct rf_saveregs regs;
2556 uint16_t rf_val, phy_val, min_val, val;
2557 uint16_t rf52, bphy_ctrl;
2558 int i;
2559
2560 DPRINTF(sc, BWI_DBG_RF | BWI_DBG_INIT, "%s enter\n", __func__);
2561
2562 bzero(&regs, sizeof(regs));
2563 bphy_ctrl = 0;
2564
2565 /*
2566 * Save RF/PHY registers for later restoration
2567 */
2568 SAVE_PHY_REG(mac, &regs, 15);
2569 rf52 = RF_READ(mac, 0x52) & 0xfff0;
2570 if (rf->rf_type == BWI_RF_T_BCM2050) {
2571 SAVE_PHY_REG(mac, &regs, 0a);
2572 SAVE_PHY_REG(mac, &regs, 2a);
2573 SAVE_PHY_REG(mac, &regs, 35);
2574 SAVE_PHY_REG(mac, &regs, 03);
2575 SAVE_PHY_REG(mac, &regs, 01);
2576 SAVE_PHY_REG(mac, &regs, 30);
2577
2578 SAVE_RF_REG(mac, &regs, 43);
2579 SAVE_RF_REG(mac, &regs, 7a);
2580
2581 bphy_ctrl = CSR_READ_2(sc, BWI_BPHY_CTRL);
2582
2583 SAVE_RF_REG(mac, &regs, 52);
2584 regs.rf_52 &= 0xf0;
2585
2586 PHY_WRITE(mac, 0x30, 0xff);
2587 CSR_WRITE_2(sc, BWI_PHY_CTRL, 0x3f3f);
2588 PHY_WRITE(mac, 0x35, regs.phy_35 & 0xff7f);
2589 RF_WRITE(mac, 0x7a, regs.rf_7a & 0xfff0);
2590 }
2591
2592 PHY_WRITE(mac, 0x15, 0xb000);
2593
2594 if (rf->rf_type == BWI_RF_T_BCM2050) {
2595 PHY_WRITE(mac, 0x2b, 0x203);
2596 PHY_WRITE(mac, 0x2a, 0x8a3);
2597 } else {
2598 PHY_WRITE(mac, 0x2b, 0x1402);
2599 }
2600
2601 /*
2602 * Setup RF signal
2603 */
2604 rf_val = 0;
2605 min_val = UINT16_MAX;
2606
2607 for (i = 0; i < 4; ++i) {
2608 RF_WRITE(mac, 0x52, rf52 | i);
2609 bwi_rf_lo_measure_11b(mac); /* Ignore return value */
2610 }
2611 for (i = 0; i < 10; ++i) {
2612 RF_WRITE(mac, 0x52, rf52 | i);
2613
2614 val = bwi_rf_lo_measure_11b(mac) / 10;
2615 if (val < min_val) {
2616 min_val = val;
2617 rf_val = i;
2618 }
2619 }
2620 RF_WRITE(mac, 0x52, rf52 | rf_val);
2621
2622 /*
2623 * Setup PHY signal
2624 */
2625 phy_val = 0;
2626 min_val = UINT16_MAX;
2627
2628 for (i = -4; i < 5; i += 2) {
2629 int j;
2630
2631 for (j = -4; j < 5; j += 2) {
2632 uint16_t phy2f;
2633
2634 phy2f = (0x100 * i) + j;
2635 if (j < 0)
2636 phy2f += 0x100;
2637 PHY_WRITE(mac, 0x2f, phy2f);
2638
2639 val = bwi_rf_lo_measure_11b(mac) / 10;
2640 if (val < min_val) {
2641 min_val = val;
2642 phy_val = phy2f;
2643 }
2644 }
2645 }
2646 PHY_WRITE(mac, 0x2f, phy_val + 0x101);
2647
2648 /*
2649 * Restore saved RF/PHY registers
2650 */
2651 if (rf->rf_type == BWI_RF_T_BCM2050) {
2652 RESTORE_PHY_REG(mac, &regs, 0a);
2653 RESTORE_PHY_REG(mac, &regs, 2a);
2654 RESTORE_PHY_REG(mac, &regs, 35);
2655 RESTORE_PHY_REG(mac, &regs, 03);
2656 RESTORE_PHY_REG(mac, &regs, 01);
2657 RESTORE_PHY_REG(mac, &regs, 30);
2658
2659 RESTORE_RF_REG(mac, &regs, 43);
2660 RESTORE_RF_REG(mac, &regs, 7a);
2661
2662 RF_FILT_SETBITS(mac, 0x52, 0xf, regs.rf_52);
2663
2664 CSR_WRITE_2(sc, BWI_BPHY_CTRL, bphy_ctrl);
2665 }
2666 RESTORE_PHY_REG(mac, &regs, 15);
2667
2668 bwi_rf_workaround(mac, rf->rf_curchan);
2669 }
DragonFly BSD