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* Add support for the nVidia MCP61, MCP65, MCP67, MCP73 and MCP77
[dragonfly.git] / sys / dev / disk / nata / ata-chipset.c
blob9d7307a1c9d7413e6ecb7b62b4befc629e17f76e
1 /*-
2 * Copyright (c) 1998 - 2006 Søren Schmidt <sos@FreeBSD.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification, immediately at the beginning of the file.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 *
26 * $FreeBSD: src/sys/dev/ata/ata-chipset.c,v 1.196 2007/04/08 19:18:51 sos Exp $
27 * $DragonFly: src/sys/dev/disk/nata/ata-chipset.c,v 1.15 2008/07/12 16:38:10 mneumann Exp $
28 */
29
30 #include "opt_ata.h"
31
32 #include <sys/param.h>
33 #include <sys/bus.h>
34 #include <sys/bus_dma.h>
35 #include <sys/bus_resource.h>
36 #include <sys/callout.h>
37 #include <sys/endian.h>
38 #include <sys/libkern.h>
39 #include <sys/lock.h> /* for {get,rel}_mplock() */
40 #include <sys/malloc.h>
41 #include <sys/nata.h>
42 #include <sys/queue.h>
43 #include <sys/rman.h>
44 #include <sys/spinlock.h>
45 #include <sys/spinlock2.h>
46 #include <sys/systm.h>
47 #include <sys/taskqueue.h>
48
49 #include <machine/bus_dma.h>
50
51 #include <bus/pci/pcireg.h>
52 #include <bus/pci/pcivar.h>
53
54 #include "ata-all.h"
55 #include "ata-pci.h"
56 #include "ata_if.h"
57
58 /* local prototypes */
59 /* ata-chipset.c */
60 static int ata_generic_chipinit(device_t dev);
61 static void ata_generic_intr(void *data);
62 static void ata_generic_setmode(device_t dev, int mode);
63 static void ata_sata_phy_check_events(device_t dev);
64 static void ata_sata_phy_event(void *context, int dummy);
65 static int ata_sata_phy_reset(device_t dev);
66 static int ata_sata_connect(struct ata_channel *ch);
67 static void ata_sata_setmode(device_t dev, int mode);
68 static int ata_request2fis_h2d(struct ata_request *request, u_int8_t *fis);
69 static int ata_ahci_chipinit(device_t dev);
70 static int ata_ahci_allocate(device_t dev);
71 static int ata_ahci_status(device_t dev);
72 static int ata_ahci_begin_transaction(struct ata_request *request);
73 static int ata_ahci_end_transaction(struct ata_request *request);
74 static void ata_ahci_reset(device_t dev);
75 static void ata_ahci_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error);
76 static void ata_ahci_dmainit(device_t dev);
77 static int ata_ahci_setup_fis(struct ata_ahci_cmd_tab *ctp, struct ata_request *request);
78 static int ata_acard_chipinit(device_t dev);
79 static int ata_acard_allocate(device_t dev);
80 static int ata_acard_status(device_t dev);
81 static void ata_acard_850_setmode(device_t dev, int mode);
82 static void ata_acard_86X_setmode(device_t dev, int mode);
83 static int ata_ali_chipinit(device_t dev);
84 static int ata_ali_allocate(device_t dev);
85 static int ata_ali_sata_allocate(device_t dev);
86 static void ata_ali_reset(device_t dev);
87 static void ata_ali_setmode(device_t dev, int mode);
88 static int ata_amd_chipinit(device_t dev);
89 static int ata_ati_chipinit(device_t dev);
90 static void ata_ati_setmode(device_t dev, int mode);
91 static int ata_cyrix_chipinit(device_t dev);
92 static void ata_cyrix_setmode(device_t dev, int mode);
93 static int ata_cypress_chipinit(device_t dev);
94 static void ata_cypress_setmode(device_t dev, int mode);
95 static int ata_highpoint_chipinit(device_t dev);
96 static int ata_highpoint_allocate(device_t dev);
97 static void ata_highpoint_setmode(device_t dev, int mode);
98 static int ata_highpoint_check_80pin(device_t dev, int mode);
99 static int ata_intel_chipinit(device_t dev);
100 static int ata_intel_allocate(device_t dev);
101 static void ata_intel_reset(device_t dev);
102 static void ata_intel_old_setmode(device_t dev, int mode);
103 static void ata_intel_new_setmode(device_t dev, int mode);
104 static int ata_intel_31244_allocate(device_t dev);
105 static int ata_intel_31244_status(device_t dev);
106 static int ata_intel_31244_command(struct ata_request *request);
107 static void ata_intel_31244_reset(device_t dev);
108 static int ata_ite_chipinit(device_t dev);
109 static void ata_ite_setmode(device_t dev, int mode);
110 static int ata_jmicron_chipinit(device_t dev);
111 static int ata_jmicron_allocate(device_t dev);
112 static void ata_jmicron_reset(device_t dev);
113 static void ata_jmicron_dmainit(device_t dev);
114 static void ata_jmicron_setmode(device_t dev, int mode);
115 static int ata_marvell_pata_chipinit(device_t dev);
116 static int ata_marvell_pata_allocate(device_t dev);
117 static void ata_marvell_pata_setmode(device_t dev, int mode);
118 static int ata_marvell_edma_chipinit(device_t dev);
119 static int ata_marvell_edma_allocate(device_t dev);
120 static int ata_marvell_edma_status(device_t dev);
121 static int ata_marvell_edma_begin_transaction(struct ata_request *request);
122 static int ata_marvell_edma_end_transaction(struct ata_request *request);
123 static void ata_marvell_edma_reset(device_t dev);
124 static void ata_marvell_edma_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error);
125 static void ata_marvell_edma_dmainit(device_t dev);
126 static int ata_national_chipinit(device_t dev);
127 static void ata_national_setmode(device_t dev, int mode);
128 static int ata_netcell_chipinit(device_t dev);
129 static int ata_netcell_allocate(device_t dev);
130 static int ata_nvidia_chipinit(device_t dev);
131 static int ata_nvidia_allocate(device_t dev);
132 static int ata_nvidia_status(device_t dev);
133 static void ata_nvidia_reset(device_t dev);
134 static int ata_promise_chipinit(device_t dev);
135 static int ata_promise_allocate(device_t dev);
136 static int ata_promise_status(device_t dev);
137 static int ata_promise_dmastart(device_t dev);
138 static int ata_promise_dmastop(device_t dev);
139 static void ata_promise_dmareset(device_t dev);
140 static void ata_promise_dmainit(device_t dev);
141 static void ata_promise_setmode(device_t dev, int mode);
142 static int ata_promise_tx2_allocate(device_t dev);
143 static int ata_promise_tx2_status(device_t dev);
144 static int ata_promise_mio_allocate(device_t dev);
145 static void ata_promise_mio_intr(void *data);
146 static int ata_promise_mio_status(device_t dev);
147 static int ata_promise_mio_command(struct ata_request *request);
148 static void ata_promise_mio_reset(device_t dev);
149 static void ata_promise_mio_dmainit(device_t dev);
150 static void ata_promise_mio_setmode(device_t dev, int mode);
151 static void ata_promise_sx4_intr(void *data);
152 static int ata_promise_sx4_command(struct ata_request *request);
153 static int ata_promise_apkt(u_int8_t *bytep, struct ata_request *request);
154 static void ata_promise_queue_hpkt(struct ata_pci_controller *ctlr, u_int32_t hpkt);
155 static void ata_promise_next_hpkt(struct ata_pci_controller *ctlr);
156 static int ata_serverworks_chipinit(device_t dev);
157 static int ata_serverworks_allocate(device_t dev);
158 static void ata_serverworks_setmode(device_t dev, int mode);
159 static int ata_sii_chipinit(device_t dev);
160 static int ata_cmd_allocate(device_t dev);
161 static int ata_cmd_status(device_t dev);
162 static void ata_cmd_setmode(device_t dev, int mode);
163 static int ata_sii_allocate(device_t dev);
164 static int ata_sii_status(device_t dev);
165 static void ata_sii_reset(device_t dev);
166 static void ata_sii_setmode(device_t dev, int mode);
167 static int ata_siiprb_allocate(device_t dev);
168 static int ata_siiprb_status(device_t dev);
169 static int ata_siiprb_begin_transaction(struct ata_request *request);
170 static int ata_siiprb_end_transaction(struct ata_request *request);
171 static void ata_siiprb_reset(device_t dev);
172 static void ata_siiprb_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error);
173 static void ata_siiprb_dmainit(device_t dev);
174 static int ata_sis_chipinit(device_t dev);
175 static int ata_sis_allocate(device_t dev);
176 static void ata_sis_reset(device_t dev);
177 static void ata_sis_setmode(device_t dev, int mode);
178 static int ata_via_chipinit(device_t dev);
179 static int ata_via_allocate(device_t dev);
180 static void ata_via_reset(device_t dev);
181 static void ata_via_setmode(device_t dev, int mode);
182 static void ata_via_southbridge_fixup(device_t dev);
183 static void ata_via_family_setmode(device_t dev, int mode);
184 static struct ata_chip_id *ata_match_chip(device_t dev, struct ata_chip_id *index);
185 static struct ata_chip_id *ata_find_chip(device_t dev, struct ata_chip_id *index, int slot);
186 static int ata_setup_interrupt(device_t dev);
187 static int ata_serialize(device_t dev, int flags);
188 static void ata_print_cable(device_t dev, u_int8_t *who);
189 static int ata_atapi(device_t dev);
190 static int ata_check_80pin(device_t dev, int mode);
191 static int ata_mode2idx(int mode);
192
193
194 /*
195 * generic ATA support functions
196 */
197 int
198 ata_generic_ident(device_t dev)
199 {
200 struct ata_pci_controller *ctlr = device_get_softc(dev);
201 char buffer[64];
202
203 ksnprintf(buffer, sizeof(buffer),
204 "%s ATA controller", ata_pcivendor2str(dev));
205 device_set_desc_copy(dev, buffer);
206 ctlr->chipinit = ata_generic_chipinit;
207 return 0;
208 }
209
210 static int
211 ata_generic_chipinit(device_t dev)
212 {
213 struct ata_pci_controller *ctlr = device_get_softc(dev);
214
215 if (ata_setup_interrupt(dev))
216 return ENXIO;
217 ctlr->setmode = ata_generic_setmode;
218 return 0;
219 }
220
221 static void
222 ata_generic_intr(void *data)
223 {
224 struct ata_pci_controller *ctlr = data;
225 struct ata_channel *ch;
226 int unit;
227
228 for (unit = 0; unit < ctlr->channels; unit++) {
229 if ((ch = ctlr->interrupt[unit].argument))
230 ctlr->interrupt[unit].function(ch);
231 }
232 }
233
234 static void
235 ata_generic_setmode(device_t dev, int mode)
236 {
237 struct ata_device *atadev = device_get_softc(dev);
238
239 mode = ata_limit_mode(dev, mode, ATA_UDMA2);
240 mode = ata_check_80pin(dev, mode);
241 if (!ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode))
242 atadev->mode = mode;
243 }
244
245
246 /*
247 * SATA support functions
248 */
249 static void
250 ata_sata_phy_check_events(device_t dev)
251 {
252 struct ata_channel *ch = device_get_softc(dev);
253 u_int32_t error = ATA_IDX_INL(ch, ATA_SERROR);
254
255 /* clear error bits/interrupt */
256 ATA_IDX_OUTL(ch, ATA_SERROR, error);
257
258 /* do we have any events flagged ? */
259 if (error) {
260 struct ata_connect_task *tp;
261 u_int32_t status = ATA_IDX_INL(ch, ATA_SSTATUS);
262
263 /* if we have a connection event deal with it */
264 if ((error & ATA_SE_PHY_CHANGED) &&
265 (tp = (struct ata_connect_task *)
266 kmalloc(sizeof(struct ata_connect_task),
267 M_ATA, M_INTWAIT | M_ZERO))) {
268
269 if (((status & ATA_SS_CONWELL_MASK) == ATA_SS_CONWELL_GEN1) ||
270 ((status & ATA_SS_CONWELL_MASK) == ATA_SS_CONWELL_GEN2)) {
271 if (bootverbose)
272 device_printf(ch->dev, "CONNECT requested\n");
273 tp->action = ATA_C_ATTACH;
274 }
275 else {
276 if (bootverbose)
277 device_printf(ch->dev, "DISCONNECT requested\n");
278 tp->action = ATA_C_DETACH;
279 }
280 tp->dev = ch->dev;
281 TASK_INIT(&tp->task, 0, ata_sata_phy_event, tp);
282 taskqueue_enqueue(taskqueue_thread[mycpuid], &tp->task);
283 }
284 }
285 }
286
287 static void
288 ata_sata_phy_event(void *context, int dummy)
289 {
290 struct ata_connect_task *tp = (struct ata_connect_task *)context;
291 struct ata_channel *ch = device_get_softc(tp->dev);
292 device_t *children;
293 int nchildren, i;
294
295 get_mplock();
296 if (tp->action == ATA_C_ATTACH) {
297 if (bootverbose)
298 device_printf(tp->dev, "CONNECTED\n");
299 ATA_RESET(tp->dev);
300 ata_identify(tp->dev);
301 }
302 if (tp->action == ATA_C_DETACH) {
303 if (!device_get_children(tp->dev, &children, &nchildren)) {
304 for (i = 0; i < nchildren; i++)
305 if (children[i])
306 device_delete_child(tp->dev, children[i]);
307 kfree(children, M_TEMP);
308 }
309 spin_lock_wr(&ch->state_mtx);
310 ch->state = ATA_IDLE;
311 spin_unlock_wr(&ch->state_mtx);
312 if (bootverbose)
313 device_printf(tp->dev, "DISCONNECTED\n");
314 }
315 rel_mplock();
316 kfree(tp, M_ATA);
317 }
318
319 static int
320 ata_sata_phy_reset(device_t dev)
321 {
322 struct ata_channel *ch = device_get_softc(dev);
323 int loop, retry;
324
325 if ((ATA_IDX_INL(ch, ATA_SCONTROL) & ATA_SC_DET_MASK) == ATA_SC_DET_IDLE)
326 return ata_sata_connect(ch);
327
328 for (retry = 0; retry < 10; retry++) {
329 for (loop = 0; loop < 10; loop++) {
330 ATA_IDX_OUTL(ch, ATA_SCONTROL, ATA_SC_DET_RESET);
331 ata_udelay(100);
332 if ((ATA_IDX_INL(ch, ATA_SCONTROL) &
333 ATA_SC_DET_MASK) == ATA_SC_DET_RESET)
334 break;
335 }
336 ata_udelay(5000);
337 for (loop = 0; loop < 10; loop++) {
338 ATA_IDX_OUTL(ch, ATA_SCONTROL, ATA_SC_DET_IDLE |
339 ATA_SC_IPM_DIS_PARTIAL |
340 ATA_SC_IPM_DIS_SLUMBER);
341 ata_udelay(100);
342 if ((ATA_IDX_INL(ch, ATA_SCONTROL) & ATA_SC_DET_MASK) == 0)
343 return ata_sata_connect(ch);
344 }
345 }
346 return 0;
347 }
348
349 static int
350 ata_sata_connect(struct ata_channel *ch)
351 {
352 u_int32_t status;
353 int timeout;
354
355 /* wait up to 1 second for "connect well" */
356 for (timeout = 0; timeout < 100 ; timeout++) {
357 status = ATA_IDX_INL(ch, ATA_SSTATUS);
358 if ((status & ATA_SS_CONWELL_MASK) == ATA_SS_CONWELL_GEN1 ||
359 (status & ATA_SS_CONWELL_MASK) == ATA_SS_CONWELL_GEN2)
360 break;
361 ata_udelay(10000);
362 }
363 if (timeout >= 100) {
364 if (bootverbose)
365 device_printf(ch->dev, "SATA connect status=%08x\n", status);
366 return 0;
367 }
368
369 if (bootverbose)
370 device_printf(ch->dev, "SATA connect time=%dms\n", timeout * 10);
371
372 /* clear SATA error register */
373 ATA_IDX_OUTL(ch, ATA_SERROR, ATA_IDX_INL(ch, ATA_SERROR));
374
375 return 1;
376 }
377
378 static void
379 ata_sata_setmode(device_t dev, int mode)
380 {
381 struct ata_device *atadev = device_get_softc(dev);
382
383 /*
384 * if we detect that the device isn't a real SATA device we limit
385 * the transfer mode to UDMA5/ATA100.
386 * this works around the problems some devices has with the
387 * Marvell 88SX8030 SATA->PATA converters and UDMA6/ATA133.
388 */
389 if (atadev->param.satacapabilities != 0x0000 &&
390 atadev->param.satacapabilities != 0xffff) {
391 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
392
393 /* on some drives we need to set the transfer mode */
394 ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0,
395 ata_limit_mode(dev, mode, ATA_UDMA6));
396
397 /* query SATA STATUS for the speed */
398 if (ch->r_io[ATA_SSTATUS].res &&
399 ((ATA_IDX_INL(ch, ATA_SSTATUS) & ATA_SS_CONWELL_MASK) ==
400 ATA_SS_CONWELL_GEN2))
401 atadev->mode = ATA_SA300;
402 else
403 atadev->mode = ATA_SA150;
404 }
405 else {
406 mode = ata_limit_mode(dev, mode, ATA_UDMA5);
407 if (!ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode))
408 atadev->mode = mode;
409 }
410 }
411
412 static int
413 ata_request2fis_h2d(struct ata_request *request, u_int8_t *fis)
414 {
415 struct ata_device *atadev = device_get_softc(request->dev);
416
417 if (request->flags & ATA_R_ATAPI) {
418 fis[0] = 0x27; /* host to device */
419 fis[1] = 0x80; /* command FIS (note PM goes here) */
420 fis[2] = ATA_PACKET_CMD;
421 if (request->flags & (ATA_R_READ | ATA_R_WRITE))
422 fis[3] = ATA_F_DMA;
423 else {
424 fis[5] = request->transfersize;
425 fis[6] = request->transfersize >> 8;
426 }
427 fis[7] = ATA_D_LBA | atadev->unit;
428 fis[15] = ATA_A_4BIT;
429 return 20;
430 }
431 else {
432 ata_modify_if_48bit(request);
433 fis[0] = 0x27; /* host to device */
434 fis[1] = 0x80; /* command FIS (note PM goes here) */
435 fis[2] = request->u.ata.command;
436 fis[3] = request->u.ata.feature;
437 fis[4] = request->u.ata.lba;
438 fis[5] = request->u.ata.lba >> 8;
439 fis[6] = request->u.ata.lba >> 16;
440 fis[7] = ATA_D_LBA | atadev->unit;
441 if (!(atadev->flags & ATA_D_48BIT_ACTIVE))
442 fis[7] |= (request->u.ata.lba >> 24 & 0x0f);
443 fis[8] = request->u.ata.lba >> 24;
444 fis[9] = request->u.ata.lba >> 32;
445 fis[10] = request->u.ata.lba >> 40;
446 fis[11] = request->u.ata.feature >> 8;
447 fis[12] = request->u.ata.count;
448 fis[13] = request->u.ata.count >> 8;
449 fis[15] = ATA_A_4BIT;
450 return 20;
451 }
452 return 0;
453 }
454
455 /*
456 * AHCI v1.x compliant SATA chipset support functions
457 */
458 int
459 ata_ahci_ident(device_t dev)
460 {
461 struct ata_pci_controller *ctlr = device_get_softc(dev);
462 static struct ata_chip_id id = {0, 0, 0, 0x00, ATA_SA300, "AHCI"};
463 char buffer[64];
464
465 if (pci_read_config(dev, PCIR_PROGIF, 1) != PCIP_STORAGE_SATA_AHCI_1_0)
466 return ENXIO;
467
468 if (bootverbose)
469 ksnprintf(buffer, sizeof(buffer), "%s (ID=%08x) AHCI controller",
470 ata_pcivendor2str(dev), pci_get_devid(dev));
471 else
472 ksnprintf(buffer, sizeof(buffer), "%s AHCI controller",
473 ata_pcivendor2str(dev));
474 device_set_desc_copy(dev, buffer);
475 ctlr->chip = &id;
476 ctlr->chipinit = ata_ahci_chipinit;
477 return 0;
478 }
479
480
481 /*
482 * AHCI v1.x compliant SATA chipset support functions
483 */
484 int
485 ata_ahci_chipinit(device_t dev)
486 {
487 struct ata_pci_controller *ctlr = device_get_softc(dev);
488 u_int32_t version;
489 int unit;
490
491 /* if we have a memory BAR(5) we are likely on an AHCI part */
492 ctlr->r_type2 = SYS_RES_MEMORY;
493 ctlr->r_rid2 = PCIR_BAR(5);
494 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
495 &ctlr->r_rid2, RF_ACTIVE)))
496 return ENXIO;
497
498 /* setup interrupt delivery if not done allready by a vendor driver */
499 if (!ctlr->r_irq) {
500 if (ata_setup_interrupt(dev))
501 return ENXIO;
502 }
503 else
504 device_printf(dev, "AHCI called from vendor specific driver\n");
505
506 /* enable AHCI mode */
507 ATA_OUTL(ctlr->r_res2, ATA_AHCI_GHC, ATA_AHCI_GHC_AE);
508
509 /* reset AHCI controller */
510 ATA_OUTL(ctlr->r_res2, ATA_AHCI_GHC, ATA_AHCI_GHC_HR);
511 DELAY(1000000);
512 if (ATA_INL(ctlr->r_res2, ATA_AHCI_GHC) & ATA_AHCI_GHC_HR) {
513 bus_release_resource(dev, ctlr->r_type2, ctlr->r_rid2, ctlr->r_res2);
514 device_printf(dev, "AHCI controller reset failure\n");
515 return ENXIO;
516 }
517
518 /* reenable AHCI mode */
519 ATA_OUTL(ctlr->r_res2, ATA_AHCI_GHC, ATA_AHCI_GHC_AE);
520
521 /* get the number of HW channels */
522 ctlr->channels =
523 MAX(flsl(ATA_INL(ctlr->r_res2, ATA_AHCI_PI)),
524 (ATA_INL(ctlr->r_res2, ATA_AHCI_CAP) & ATA_AHCI_NPMASK) + 1);
525
526 /* disable interrupt sources and clear interrupts */
527 for (unit = 0; unit < ctlr->channels; unit++) {
528 int offset = unit << 7;
529 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_IE + offset, 0);
530 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_IS + offset, -1);
531 }
532 ATA_OUTL(ctlr->r_res2, ATA_AHCI_IS, ATA_INL(ctlr->r_res2, ATA_AHCI_IS));
533
534 /* enable AHCI interrupts */
535 ATA_OUTL(ctlr->r_res2, ATA_AHCI_GHC,
536 ATA_INL(ctlr->r_res2, ATA_AHCI_GHC) | ATA_AHCI_GHC_IE);
537
538 ctlr->reset = ata_ahci_reset;
539 ctlr->dmainit = ata_ahci_dmainit;
540 ctlr->allocate = ata_ahci_allocate;
541 ctlr->setmode = ata_sata_setmode;
542
543 /* enable PCI interrupt */
544 pci_write_config(dev, PCIR_COMMAND,
545 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400, 2);
546
547 /* announce we support the HW */
548 version = ATA_INL(ctlr->r_res2, ATA_AHCI_VS);
549 device_printf(dev,
550 "AHCI Version %x%x.%x%x controller with %d ports detected\n",
551 (version >> 24) & 0xff, (version >> 16) & 0xff,
552 (version >> 8) & 0xff, version & 0xff,
553 (ATA_INL(ctlr->r_res2, ATA_AHCI_CAP) & ATA_AHCI_NPMASK) + 1);
554 return 0;
555 }
556
557 static int
558 ata_ahci_allocate(device_t dev)
559 {
560 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
561 struct ata_channel *ch = device_get_softc(dev);
562 u_int64_t work;
563 int offset = ch->unit << 7;
564
565 /* set the SATA resources */
566 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2;
567 ch->r_io[ATA_SSTATUS].offset = ATA_AHCI_P_SSTS + offset;
568 ch->r_io[ATA_SERROR].res = ctlr->r_res2;
569 ch->r_io[ATA_SERROR].offset = ATA_AHCI_P_SERR + offset;
570 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2;
571 ch->r_io[ATA_SCONTROL].offset = ATA_AHCI_P_SCTL + offset;
572 ch->r_io[ATA_SACTIVE].res = ctlr->r_res2;
573 ch->r_io[ATA_SACTIVE].offset = ATA_AHCI_P_SACT + offset;
574
575 ch->hw.status = ata_ahci_status;
576 ch->hw.begin_transaction = ata_ahci_begin_transaction;
577 ch->hw.end_transaction = ata_ahci_end_transaction;
578 ch->hw.command = NULL; /* not used here */
579
580 /* setup work areas */
581 work = ch->dma->work_bus + ATA_AHCI_CL_OFFSET;
582 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CLB + offset, work & 0xffffffff);
583 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CLBU + offset, work >> 32);
584
585 work = ch->dma->work_bus + ATA_AHCI_FB_OFFSET;
586 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_FB + offset, work & 0xffffffff);
587 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_FBU + offset, work >> 32);
588
589 /* enable wanted port interrupts */
590 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_IE + offset,
591 (ATA_AHCI_P_IX_CPD | ATA_AHCI_P_IX_TFE | ATA_AHCI_P_IX_HBF |
592 ATA_AHCI_P_IX_HBD | ATA_AHCI_P_IX_IF | ATA_AHCI_P_IX_OF |
593 ATA_AHCI_P_IX_PRC | ATA_AHCI_P_IX_PC | ATA_AHCI_P_IX_DP |
594 ATA_AHCI_P_IX_UF | ATA_AHCI_P_IX_SDB | ATA_AHCI_P_IX_DS |
595 ATA_AHCI_P_IX_PS | ATA_AHCI_P_IX_DHR));
596
597 /* start operations on this channel */
598 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset,
599 (ATA_AHCI_P_CMD_ACTIVE | ATA_AHCI_P_CMD_FRE |
600 ATA_AHCI_P_CMD_POD | ATA_AHCI_P_CMD_SUD | ATA_AHCI_P_CMD_ST));
601 return 0;
602 }
603
604 static int
605 ata_ahci_status(device_t dev)
606 {
607 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
608 struct ata_channel *ch = device_get_softc(dev);
609 u_int32_t action = ATA_INL(ctlr->r_res2, ATA_AHCI_IS);
610 int offset = ch->unit << 7;
611 int tag = 0;
612
613 if (action & (1 << ch->unit)) {
614 u_int32_t istatus = ATA_INL(ctlr->r_res2, ATA_AHCI_P_IS + offset);
615 u_int32_t cstatus = ATA_INL(ctlr->r_res2, ATA_AHCI_P_CI + offset);
616
617 /* clear interrupt(s) */
618 ATA_OUTL(ctlr->r_res2, ATA_AHCI_IS, action & (1 << ch->unit));
619 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_IS + offset, istatus);
620
621 /* do we have any PHY events ? */
622 /* XXX SOS check istatus phy bits */
623 ata_sata_phy_check_events(dev);
624
625 /* do we have a potentially hanging engine to take care of? */
626 if ((istatus & 0x78400050) && (cstatus & (1 << tag))) {
627
628 u_int32_t cmd = ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset);
629 int timeout = 0;
630
631 /* kill off all activity on this channel */
632 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset,
633 cmd & ~(ATA_AHCI_P_CMD_FRE | ATA_AHCI_P_CMD_ST));
634
635 /* XXX SOS this is not entirely wrong */
636 do {
637 DELAY(1000);
638 if (timeout++ > 500) {
639 device_printf(dev, "stopping AHCI engine failed\n");
640 break;
641 }
642 } while (ATA_INL(ctlr->r_res2,
643 ATA_AHCI_P_CMD + offset) & ATA_AHCI_P_CMD_CR);
644
645 /* start operations on this channel */
646 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset,
647 cmd | (ATA_AHCI_P_CMD_FRE | ATA_AHCI_P_CMD_ST));
648
649 return 1;
650 }
651 else
652 return (!(cstatus & (1 << tag)));
653 }
654 return 0;
655 }
656
657 /* must be called with ATA channel locked and state_mtx held */
658 static int
659 ata_ahci_begin_transaction(struct ata_request *request)
660 {
661 struct ata_pci_controller *ctlr=device_get_softc(GRANDPARENT(request->dev));
662 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev));
663 struct ata_ahci_cmd_tab *ctp;
664 struct ata_ahci_cmd_list *clp;
665 int offset = ch->unit << 7;
666 int tag = 0, entries = 0;
667 int fis_size;
668
669 /* get a piece of the workspace for this request */
670 ctp = (struct ata_ahci_cmd_tab *)
671 (ch->dma->work + ATA_AHCI_CT_OFFSET + (ATA_AHCI_CT_SIZE * tag));
672
673 /* setup the FIS for this request */
674 if (!(fis_size = ata_ahci_setup_fis(ctp, request))) {
675 device_printf(request->dev, "setting up SATA FIS failed\n");
676 request->result = EIO;
677 return ATA_OP_FINISHED;
678 }
679
680 /* if request moves data setup and load SG list */
681 if (request->flags & (ATA_R_READ | ATA_R_WRITE)) {
682 if (ch->dma->load(ch->dev, request->data, request->bytecount,
683 request->flags & ATA_R_READ,
684 ctp->prd_tab, &entries)) {
685 device_printf(request->dev, "setting up DMA failed\n");
686 request->result = EIO;
687 return ATA_OP_FINISHED;
688 }
689 }
690
691 /* setup the command list entry */
692 clp = (struct ata_ahci_cmd_list *)
693 (ch->dma->work + ATA_AHCI_CL_OFFSET + (ATA_AHCI_CL_SIZE * tag));
694
695 clp->prd_length = entries;
696 clp->cmd_flags = (request->flags & ATA_R_WRITE ? (1<<6) : 0) |
697 (request->flags & ATA_R_ATAPI ? ((1<<5) | (1<<7)) : 0) |
698 (fis_size / sizeof(u_int32_t));
699 clp->bytecount = 0;
700 clp->cmd_table_phys = htole64(ch->dma->work_bus + ATA_AHCI_CT_OFFSET +
701 (ATA_AHCI_CT_SIZE * tag));
702
703 /* clear eventual ACTIVE bit */
704 ATA_IDX_OUTL(ch, ATA_SACTIVE, ATA_IDX_INL(ch, ATA_SACTIVE) & (1 << tag));
705
706 /* set command type bit */
707 if (request->flags & ATA_R_ATAPI)
708 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset,
709 ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset) |
710 ATA_AHCI_P_CMD_ATAPI);
711 else
712 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset,
713 ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset) &
714 ~ATA_AHCI_P_CMD_ATAPI);
715
716 /* issue command to controller */
717 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CI + offset, (1 << tag));
718
719 if (!(request->flags & ATA_R_ATAPI)) {
720 /* device reset doesn't interrupt */
721 if (request->u.ata.command == ATA_DEVICE_RESET) {
722 u_int32_t tf_data;
723 int timeout = 1000000;
724
725 do {
726 DELAY(10);
727 tf_data = ATA_INL(ctlr->r_res2, ATA_AHCI_P_TFD + (ch->unit<<7));
728 } while ((tf_data & ATA_S_BUSY) && timeout--);
729 if (bootverbose)
730 device_printf(ch->dev, "device_reset timeout=%dus\n",
731 (1000000-timeout)*10);
732 request->status = tf_data;
733 if (request->status & ATA_S_ERROR)
734 request->error = tf_data >> 8;
735 return ATA_OP_FINISHED;
736 }
737 }
738
739 /* start the timeout */
740 callout_reset(&request->callout, request->timeout * hz,
741 (timeout_t*)ata_timeout, request);
742 return ATA_OP_CONTINUES;
743 }
744
745 /* must be called with ATA channel locked and state_mtx held */
746 static int
747 ata_ahci_end_transaction(struct ata_request *request)
748 {
749 struct ata_pci_controller *ctlr=device_get_softc(GRANDPARENT(request->dev));
750 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev));
751 struct ata_ahci_cmd_list *clp;
752 u_int32_t tf_data;
753 int offset = ch->unit << 7;
754 int tag = 0;
755
756 /* kill the timeout */
757 callout_stop(&request->callout);
758
759 /* get status */
760 tf_data = ATA_INL(ctlr->r_res2, ATA_AHCI_P_TFD + offset);
761 request->status = tf_data;
762
763 /* if error status get details */
764 if (request->status & ATA_S_ERROR)
765 request->error = tf_data >> 8;
766
767 /* record how much data we actually moved */
768 clp = (struct ata_ahci_cmd_list *)
769 (ch->dma->work + ATA_AHCI_CL_OFFSET + (ATA_AHCI_CL_SIZE * tag));
770 request->donecount = clp->bytecount;
771
772 /* release SG list etc */
773 ch->dma->unload(ch->dev);
774
775 return ATA_OP_FINISHED;
776 }
777
778 static void
779 ata_ahci_reset(device_t dev)
780 {
781 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
782 struct ata_channel *ch = device_get_softc(dev);
783 u_int32_t cmd, signature;
784 int offset = ch->unit << 7;
785 int timeout;
786
787 if (!(ATA_INL(ctlr->r_res2, ATA_AHCI_PI) & (1 << ch->unit))) {
788 device_printf(dev, "port not implemented\n");
789 return;
790 }
791 ch->devices = 0;
792
793 /* kill off all activity on this channel */
794 cmd = ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset);
795 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset,
796 cmd & ~(ATA_AHCI_P_CMD_FRE | ATA_AHCI_P_CMD_ST));
797
798 /* XXX SOS this is not entirely wrong */
799 timeout = 0;
800 do {
801 DELAY(1000);
802 if (timeout++ > 500) {
803 device_printf(dev, "stopping AHCI engine failed\n");
804 break;
805 }
806 }
807 while (ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset) & ATA_AHCI_P_CMD_CR);
808
809 /* issue Command List Override if supported */
810 if (ATA_INL(ctlr->r_res2, ATA_AHCI_CAP) & ATA_AHCI_CAP_CLO) {
811 cmd = ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset);
812 cmd |= ATA_AHCI_P_CMD_CLO;
813 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset, cmd);
814 timeout = 0;
815 do {
816 DELAY(1000);
817 if (timeout++ > 500) {
818 device_printf(dev, "executing CLO failed\n");
819 break;
820 }
821 }
822 while (ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD+offset)&ATA_AHCI_P_CMD_CLO);
823 }
824
825 /* reset PHY and decide what is present */
826 if (ata_sata_phy_reset(dev)) {
827
828 /* clear any interrupts pending on this channel */
829 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_IS + offset,
830 ATA_INL(ctlr->r_res2, ATA_AHCI_P_IS + offset));
831
832 /* clear SATA error register */
833 ATA_IDX_OUTL(ch, ATA_SERROR, ATA_IDX_INL(ch, ATA_SERROR));
834
835 /* start operations on this channel */
836 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset,
837 (ATA_AHCI_P_CMD_ACTIVE | ATA_AHCI_P_CMD_FRE |
838 ATA_AHCI_P_CMD_POD | ATA_AHCI_P_CMD_SUD | ATA_AHCI_P_CMD_ST));
839
840 signature = ATA_INL(ctlr->r_res2, ATA_AHCI_P_SIG + offset);
841 switch (signature) {
842 case 0x00000101:
843 ch->devices = ATA_ATA_MASTER;
844 break;
845 case 0x96690101:
846 ch->devices = ATA_PORTMULTIPLIER;
847 device_printf(ch->dev, "Portmultipliers not supported yet\n");
848 ch->devices = 0;
849 break;
850 case 0xeb140101:
851 ch->devices = ATA_ATAPI_MASTER;
852 break;
853 default: /* SOS XXX */
854 if (bootverbose)
855 device_printf(ch->dev, "No signature, assuming disk device\n");
856 ch->devices = ATA_ATA_MASTER;
857 }
858 }
859 if (bootverbose)
860 device_printf(dev, "ahci_reset devices=0x%b\n", ch->devices,
861 "\20\4ATAPI_SLAVE\3ATAPI_MASTER\2ATA_SLAVE\1ATA_MASTER");
862 }
863
864 static void
865 ata_ahci_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error)
866 {
867 struct ata_dmasetprd_args *args = xsc;
868 struct ata_ahci_dma_prd *prd = args->dmatab;
869 int i;
870
871 if (!(args->error = error)) {
872 for (i = 0; i < nsegs; i++) {
873 prd[i].dba = htole64(segs[i].ds_addr);
874 prd[i].dbc = htole32((segs[i].ds_len - 1) & ATA_AHCI_PRD_MASK);
875 }
876 }
877 args->nsegs = nsegs;
878 }
879
880 static void
881 ata_ahci_dmainit(device_t dev)
882 {
883 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
884 struct ata_channel *ch = device_get_softc(dev);
885
886 ata_dmainit(dev);
887 if (ch->dma) {
888 /* note start and stop are not used here */
889 ch->dma->setprd = ata_ahci_dmasetprd;
890 ch->dma->max_iosize = 8192 * DEV_BSIZE;
891 if (ATA_INL(ctlr->r_res2, ATA_AHCI_CAP) & ATA_AHCI_CAP_64BIT)
892 ch->dma->max_address = BUS_SPACE_MAXADDR;
893 }
894 }
895
896 static int
897 ata_ahci_setup_fis(struct ata_ahci_cmd_tab *ctp, struct ata_request *request)
898 {
899 bzero(ctp->cfis, 64);
900 if (request->flags & ATA_R_ATAPI) {
901 bzero(ctp->acmd, 32);
902 bcopy(request->u.atapi.ccb, ctp->acmd, 16);
903 }
904 return ata_request2fis_h2d(request, &ctp->cfis[0]);
905 }
906
907 /*
908 * Acard chipset support functions
909 */
910 int
911 ata_acard_ident(device_t dev)
912 {
913 struct ata_pci_controller *ctlr = device_get_softc(dev);
914 struct ata_chip_id *idx;
915 static struct ata_chip_id ids[] =
916 {{ ATA_ATP850R, 0, ATPOLD, 0x00, ATA_UDMA2, "ATP850" },
917 { ATA_ATP860A, 0, 0, 0x00, ATA_UDMA4, "ATP860A" },
918 { ATA_ATP860R, 0, 0, 0x00, ATA_UDMA4, "ATP860R" },
919 { ATA_ATP865A, 0, 0, 0x00, ATA_UDMA6, "ATP865A" },
920 { ATA_ATP865R, 0, 0, 0x00, ATA_UDMA6, "ATP865R" },
921 { 0, 0, 0, 0, 0, 0}};
922 char buffer[64];
923
924 if (!(idx = ata_match_chip(dev, ids)))
925 return ENXIO;
926
927 ksprintf(buffer, "Acard %s %s controller",
928 idx->text, ata_mode2str(idx->max_dma));
929 device_set_desc_copy(dev, buffer);
930 ctlr->chip = idx;
931 ctlr->chipinit = ata_acard_chipinit;
932 return 0;
933 }
934
935 static int
936 ata_acard_chipinit(device_t dev)
937 {
938 struct ata_pci_controller *ctlr = device_get_softc(dev);
939
940 if (ata_setup_interrupt(dev))
941 return ENXIO;
942
943 ctlr->allocate = ata_acard_allocate;
944 if (ctlr->chip->cfg1 == ATPOLD) {
945 ctlr->setmode = ata_acard_850_setmode;
946 ctlr->locking = ata_serialize;
947 }
948 else
949 ctlr->setmode = ata_acard_86X_setmode;
950 return 0;
951 }
952
953 static int
954 ata_acard_allocate(device_t dev)
955 {
956 struct ata_channel *ch = device_get_softc(dev);
957
958 /* setup the usual register normal pci style */
959 if (ata_pci_allocate(dev))
960 return ENXIO;
961
962 ch->hw.status = ata_acard_status;
963 return 0;
964 }
965
966 static int
967 ata_acard_status(device_t dev)
968 {
969 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
970 struct ata_channel *ch = device_get_softc(dev);
971
972 if (ctlr->chip->cfg1 == ATPOLD &&
973 ATA_LOCKING(ch->dev, ATA_LF_WHICH) != ch->unit)
974 return 0;
975 if (ch->dma && (ch->dma->flags & ATA_DMA_ACTIVE)) {
976 int bmstat = ATA_IDX_INB(ch, ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK;
977
978 if ((bmstat & (ATA_BMSTAT_ACTIVE | ATA_BMSTAT_INTERRUPT)) !=
979 ATA_BMSTAT_INTERRUPT)
980 return 0;
981 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, bmstat & ~ATA_BMSTAT_ERROR);
982 DELAY(1);
983 ATA_IDX_OUTB(ch, ATA_BMCMD_PORT,
984 ATA_IDX_INB(ch, ATA_BMCMD_PORT) & ~ATA_BMCMD_START_STOP);
985 DELAY(1);
986 }
987 if (ATA_IDX_INB(ch, ATA_ALTSTAT) & ATA_S_BUSY) {
988 DELAY(100);
989 if (ATA_IDX_INB(ch, ATA_ALTSTAT) & ATA_S_BUSY)
990 return 0;
991 }
992 return 1;
993 }
994
995 static void
996 ata_acard_850_setmode(device_t dev, int mode)
997 {
998 device_t gparent = GRANDPARENT(dev);
999 struct ata_pci_controller *ctlr = device_get_softc(gparent);
1000 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
1001 struct ata_device *atadev = device_get_softc(dev);
1002 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
1003 int error;
1004
1005 mode = ata_limit_mode(dev, mode,
1006 ata_atapi(dev) ? ATA_PIO_MAX : ctlr->chip->max_dma);
1007
1008 /* XXX SOS missing WDMA0+1 + PIO modes */
1009 if (mode >= ATA_WDMA2) {
1010 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
1011 if (bootverbose)
1012 device_printf(dev, "%ssetting %s on %s chip\n",
1013 (error) ? "FAILURE " : "",
1014 ata_mode2str(mode), ctlr->chip->text);
1015 if (!error) {
1016 u_int8_t reg54 = pci_read_config(gparent, 0x54, 1);
1017
1018 reg54 &= ~(0x03 << (devno << 1));
1019 if (mode >= ATA_UDMA0)
1020 reg54 |= (((mode & ATA_MODE_MASK) + 1) << (devno << 1));
1021 pci_write_config(gparent, 0x54, reg54, 1);
1022 pci_write_config(gparent, 0x4a, 0xa6, 1);
1023 pci_write_config(gparent, 0x40 + (devno << 1), 0x0301, 2);
1024 atadev->mode = mode;
1025 return;
1026 }
1027 }
1028 /* we could set PIO mode timings, but we assume the BIOS did that */
1029 }
1030
1031 static void
1032 ata_acard_86X_setmode(device_t dev, int mode)
1033 {
1034 device_t gparent = GRANDPARENT(dev);
1035 struct ata_pci_controller *ctlr = device_get_softc(gparent);
1036 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
1037 struct ata_device *atadev = device_get_softc(dev);
1038 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
1039 int error;
1040
1041
1042 mode = ata_limit_mode(dev, mode,
1043 ata_atapi(dev) ? ATA_PIO_MAX : ctlr->chip->max_dma);
1044
1045 mode = ata_check_80pin(dev, mode);
1046
1047 /* XXX SOS missing WDMA0+1 + PIO modes */
1048 if (mode >= ATA_WDMA2) {
1049 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
1050 if (bootverbose)
1051 device_printf(dev, "%ssetting %s on %s chip\n",
1052 (error) ? "FAILURE " : "",
1053 ata_mode2str(mode), ctlr->chip->text);
1054 if (!error) {
1055 u_int16_t reg44 = pci_read_config(gparent, 0x44, 2);
1056
1057 reg44 &= ~(0x000f << (devno << 2));
1058 if (mode >= ATA_UDMA0)
1059 reg44 |= (((mode & ATA_MODE_MASK) + 1) << (devno << 2));
1060 pci_write_config(gparent, 0x44, reg44, 2);
1061 pci_write_config(gparent, 0x4a, 0xa6, 1);
1062 pci_write_config(gparent, 0x40 + devno, 0x31, 1);
1063 atadev->mode = mode;
1064 return;
1065 }
1066 }
1067 /* we could set PIO mode timings, but we assume the BIOS did that */
1068 }
1069
1070
1071 /*
1072 * Acer Labs Inc (ALI) chipset support functions
1073 */
1074 int
1075 ata_ali_ident(device_t dev)
1076 {
1077 struct ata_pci_controller *ctlr = device_get_softc(dev);
1078 struct ata_chip_id *idx;
1079 static struct ata_chip_id ids[] =
1080 {{ ATA_ALI_5289, 0x00, 2, ALISATA, ATA_SA150, "M5289" },
1081 { ATA_ALI_5288, 0x00, 4, ALISATA, ATA_SA300, "M5288" },
1082 { ATA_ALI_5287, 0x00, 4, ALISATA, ATA_SA150, "M5287" },
1083 { ATA_ALI_5281, 0x00, 2, ALISATA, ATA_SA150, "M5281" },
1084 { ATA_ALI_5229, 0xc5, 0, ALINEW, ATA_UDMA6, "M5229" },
1085 { ATA_ALI_5229, 0xc4, 0, ALINEW, ATA_UDMA5, "M5229" },
1086 { ATA_ALI_5229, 0xc2, 0, ALINEW, ATA_UDMA4, "M5229" },
1087 { ATA_ALI_5229, 0x20, 0, ALIOLD, ATA_UDMA2, "M5229" },
1088 { ATA_ALI_5229, 0x00, 0, ALIOLD, ATA_WDMA2, "M5229" },
1089 { 0, 0, 0, 0, 0, 0}};
1090 char buffer[64];
1091
1092 if (!(idx = ata_match_chip(dev, ids)))
1093 return ENXIO;
1094
1095 ksprintf(buffer, "AcerLabs %s %s controller",
1096 idx->text, ata_mode2str(idx->max_dma));
1097 device_set_desc_copy(dev, buffer);
1098 ctlr->chip = idx;
1099 ctlr->chipinit = ata_ali_chipinit;
1100 return 0;
1101 }
1102
1103 static int
1104 ata_ali_chipinit(device_t dev)
1105 {
1106 struct ata_pci_controller *ctlr = device_get_softc(dev);
1107
1108 if (ata_setup_interrupt(dev))
1109 return ENXIO;
1110
1111 switch (ctlr->chip->cfg2) {
1112 case ALISATA:
1113 ctlr->channels = ctlr->chip->cfg1;
1114 ctlr->allocate = ata_ali_sata_allocate;
1115 ctlr->setmode = ata_sata_setmode;
1116
1117 /* AHCI mode is correctly supported only on the ALi 5288. */
1118 if ((ctlr->chip->chipid == ATA_ALI_5288) &&
1119 (ata_ahci_chipinit(dev) != ENXIO))
1120 return 0;
1121
1122 /* enable PCI interrupt */
1123 pci_write_config(dev, PCIR_COMMAND,
1124 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400, 2);
1125 break;
1126
1127 case ALINEW:
1128 /* use device interrupt as byte count end */
1129 pci_write_config(dev, 0x4a, pci_read_config(dev, 0x4a, 1) | 0x20, 1);
1130
1131 /* enable cable detection and UDMA support on newer chips */
1132 pci_write_config(dev, 0x4b, pci_read_config(dev, 0x4b, 1) | 0x09, 1);
1133
1134 /* enable ATAPI UDMA mode */
1135 pci_write_config(dev, 0x53, pci_read_config(dev, 0x53, 1) | 0x01, 1);
1136
1137 /* only chips with revision > 0xc4 can do 48bit DMA */
1138 if (ctlr->chip->chiprev <= 0xc4)
1139 device_printf(dev,
1140 "using PIO transfers above 137GB as workaround for "
1141 "48bit DMA access bug, expect reduced performance\n");
1142 ctlr->allocate = ata_ali_allocate;
1143 ctlr->reset = ata_ali_reset;
1144 ctlr->setmode = ata_ali_setmode;
1145 break;
1146
1147 case ALIOLD:
1148 /* deactivate the ATAPI FIFO and enable ATAPI UDMA */
1149 pci_write_config(dev, 0x53, pci_read_config(dev, 0x53, 1) | 0x03, 1);
1150 ctlr->setmode = ata_ali_setmode;
1151 break;
1152 }
1153 return 0;
1154 }
1155
1156 static int
1157 ata_ali_allocate(device_t dev)
1158 {
1159 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
1160 struct ata_channel *ch = device_get_softc(dev);
1161
1162 /* setup the usual register normal pci style */
1163 if (ata_pci_allocate(dev))
1164 return ENXIO;
1165
1166 /* older chips can't do 48bit DMA transfers */
1167 if (ctlr->chip->chiprev <= 0xc4)
1168 ch->flags |= ATA_NO_48BIT_DMA;
1169
1170 return 0;
1171 }
1172
1173 static int
1174 ata_ali_sata_allocate(device_t dev)
1175 {
1176 device_t parent = device_get_parent(dev);
1177 struct ata_pci_controller *ctlr = device_get_softc(parent);
1178 struct ata_channel *ch = device_get_softc(dev);
1179 struct resource *io = NULL, *ctlio = NULL;
1180 int unit01 = (ch->unit & 1), unit10 = (ch->unit & 2);
1181 int i, rid;
1182
1183 rid = PCIR_BAR(0) + (unit01 ? 8 : 0);
1184 io = bus_alloc_resource_any(parent, SYS_RES_IOPORT, &rid, RF_ACTIVE);
1185 if (!io)
1186 return ENXIO;
1187
1188 rid = PCIR_BAR(1) + (unit01 ? 8 : 0);
1189 ctlio = bus_alloc_resource_any(parent, SYS_RES_IOPORT, &rid, RF_ACTIVE);
1190 if (!ctlio) {
1191 bus_release_resource(dev, SYS_RES_IOPORT, ATA_IOADDR_RID, io);
1192 return ENXIO;
1193 }
1194
1195 for (i = ATA_DATA; i <= ATA_COMMAND; i ++) {
1196 ch->r_io[i].res = io;
1197 ch->r_io[i].offset = i + (unit10 ? 8 : 0);
1198 }
1199 ch->r_io[ATA_CONTROL].res = ctlio;
1200 ch->r_io[ATA_CONTROL].offset = 2 + (unit10 ? 4 : 0);
1201 ch->r_io[ATA_IDX_ADDR].res = io;
1202 ata_default_registers(dev);
1203 if (ctlr->r_res1) {
1204 for (i = ATA_BMCMD_PORT; i <= ATA_BMDTP_PORT; i++) {
1205 ch->r_io[i].res = ctlr->r_res1;
1206 ch->r_io[i].offset = (i - ATA_BMCMD_PORT)+(ch->unit * ATA_BMIOSIZE);
1207 }
1208 }
1209 ch->flags |= ATA_NO_SLAVE;
1210
1211 /* XXX SOS PHY handling awkward in ALI chip not supported yet */
1212 ata_pci_hw(dev);
1213 return 0;
1214 }
1215
1216 static void
1217 ata_ali_reset(device_t dev)
1218 {
1219 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
1220 struct ata_channel *ch = device_get_softc(dev);
1221 device_t *children;
1222 int nchildren, i;
1223
1224 ata_generic_reset(dev);
1225
1226 /*
1227 * workaround for datacorruption bug found on at least SUN Blade-100
1228 * find the ISA function on the southbridge and disable then enable
1229 * the ATA channel tristate buffer
1230 */
1231 if (ctlr->chip->chiprev == 0xc3 || ctlr->chip->chiprev == 0xc2) {
1232 if (!device_get_children(GRANDPARENT(dev), &children, &nchildren)) {
1233 for (i = 0; i < nchildren; i++) {
1234 if (pci_get_devid(children[i]) == ATA_ALI_1533) {
1235 pci_write_config(children[i], 0x58,
1236 pci_read_config(children[i], 0x58, 1) &
1237 ~(0x04 << ch->unit), 1);
1238 pci_write_config(children[i], 0x58,
1239 pci_read_config(children[i], 0x58, 1) |
1240 (0x04 << ch->unit), 1);
1241 break;
1242 }
1243 }
1244 kfree(children, M_TEMP);
1245 }
1246 }
1247 }
1248
1249 static void
1250 ata_ali_setmode(device_t dev, int mode)
1251 {
1252 device_t gparent = GRANDPARENT(dev);
1253 struct ata_pci_controller *ctlr = device_get_softc(gparent);
1254 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
1255 struct ata_device *atadev = device_get_softc(dev);
1256 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
1257 int error;
1258
1259 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma);
1260
1261 if (ctlr->chip->cfg2 & ALINEW) {
1262 if (mode > ATA_UDMA2 &&
1263 pci_read_config(gparent, 0x4a, 1) & (1 << ch->unit)) {
1264 ata_print_cable(dev, "controller");
1265 mode = ATA_UDMA2;
1266 }
1267 }
1268 else
1269 mode = ata_check_80pin(dev, mode);
1270
1271 if (ctlr->chip->cfg2 & ALIOLD) {
1272 /* doesn't support ATAPI DMA on write */
1273 ch->flags |= ATA_ATAPI_DMA_RO;
1274 if (ch->devices & ATA_ATAPI_MASTER && ch->devices & ATA_ATAPI_SLAVE) {
1275 /* doesn't support ATAPI DMA on two ATAPI devices */
1276 device_printf(dev, "two atapi devices on this channel, no DMA\n");
1277 mode = ata_limit_mode(dev, mode, ATA_PIO_MAX);
1278 }
1279 }
1280
1281 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
1282
1283 if (bootverbose)
1284 device_printf(dev, "%ssetting %s on %s chip\n",
1285 (error) ? "FAILURE " : "",
1286 ata_mode2str(mode), ctlr->chip->text);
1287 if (!error) {
1288 if (mode >= ATA_UDMA0) {
1289 u_int8_t udma[] = {0x0c, 0x0b, 0x0a, 0x09, 0x08, 0x0f, 0x0d};
1290 u_int32_t word54 = pci_read_config(gparent, 0x54, 4);
1291
1292 word54 &= ~(0x000f000f << (devno << 2));
1293 word54 |= (((udma[mode&ATA_MODE_MASK]<<16)|0x05)<<(devno<<2));
1294 pci_write_config(gparent, 0x54, word54, 4);
1295 pci_write_config(gparent, 0x58 + (ch->unit << 2),
1296 0x00310001, 4);
1297 }
1298 else {
1299 u_int32_t piotimings[] =
1300 { 0x006d0003, 0x00580002, 0x00440001, 0x00330001,
1301 0x00310001, 0x00440001, 0x00330001, 0x00310001};
1302
1303 pci_write_config(gparent, 0x54, pci_read_config(gparent, 0x54, 4) &
1304 ~(0x0008000f << (devno << 2)), 4);
1305 pci_write_config(gparent, 0x58 + (ch->unit << 2),
1306 piotimings[ata_mode2idx(mode)], 4);
1307 }
1308 atadev->mode = mode;
1309 }
1310 }
1311
1312
1313 /*
1314 * American Micro Devices (AMD) chipset support functions
1315 */
1316 int
1317 ata_amd_ident(device_t dev)
1318 {
1319 struct ata_pci_controller *ctlr = device_get_softc(dev);
1320 struct ata_chip_id *idx;
1321 static struct ata_chip_id ids[] =
1322 {{ ATA_AMD756, 0x00, AMDNVIDIA, 0x00, ATA_UDMA4, "756" },
1323 { ATA_AMD766, 0x00, AMDNVIDIA, AMDCABLE|AMDBUG, ATA_UDMA5, "766" },
1324 { ATA_AMD768, 0x00, AMDNVIDIA, AMDCABLE, ATA_UDMA5, "768" },
1325 { ATA_AMD8111, 0x00, AMDNVIDIA, AMDCABLE, ATA_UDMA6, "8111" },
1326 { 0, 0, 0, 0, 0, 0}};
1327 char buffer[64];
1328
1329 if (!(idx = ata_match_chip(dev, ids)))
1330 return ENXIO;
1331
1332 ksprintf(buffer, "AMD %s %s controller",
1333 idx->text, ata_mode2str(idx->max_dma));
1334 device_set_desc_copy(dev, buffer);
1335 ctlr->chip = idx;
1336 ctlr->chipinit = ata_amd_chipinit;
1337 return 0;
1338 }
1339
1340 static int
1341 ata_amd_chipinit(device_t dev)
1342 {
1343 struct ata_pci_controller *ctlr = device_get_softc(dev);
1344
1345 if (ata_setup_interrupt(dev))
1346 return ENXIO;
1347
1348 /* disable/set prefetch, postwrite */
1349 if (ctlr->chip->cfg2 & AMDBUG)
1350 pci_write_config(dev, 0x41, pci_read_config(dev, 0x41, 1) & 0x0f, 1);
1351 else
1352 pci_write_config(dev, 0x41, pci_read_config(dev, 0x41, 1) | 0xf0, 1);
1353
1354 ctlr->setmode = ata_via_family_setmode;
1355 return 0;
1356 }
1357
1358
1359 /*
1360 * ATI chipset support functions
1361 */
1362 int
1363 ata_ati_ident(device_t dev)
1364 {
1365 struct ata_pci_controller *ctlr = device_get_softc(dev);
1366 struct ata_chip_id *idx;
1367 static struct ata_chip_id ids[] =
1368 {{ ATA_ATI_IXP200, 0x00, 0, 0, ATA_UDMA5, "IXP200" },
1369 { ATA_ATI_IXP300, 0x00, 0, 0, ATA_UDMA6, "IXP300" },
1370 { ATA_ATI_IXP400, 0x00, 0, 0, ATA_UDMA6, "IXP400" },
1371 { ATA_ATI_SB600, 0x00, 0, 0, ATA_UDMA6, "SB600" },
1372 { ATA_ATI_IXP300_S1, 0x00, SIIMEMIO, 0, ATA_SA150, "IXP300" },
1373 { ATA_ATI_IXP400_S1, 0x00, SIIMEMIO, 0, ATA_SA150, "IXP400" },
1374 { ATA_ATI_IXP400_S2, 0x00, SIIMEMIO, 0, ATA_SA150, "IXP400" },
1375 { ATA_ATI_SB600_S1, 0x00, ATIAHCI, 0, ATA_SA300, "SB600" },
1376 { ATA_ATI_SB600_S2, 0x00, ATIAHCI, 0, ATA_SA300, "SB600" },
1377 { 0, 0, 0, 0, 0, 0}};
1378 char buffer[64];
1379
1380 if (!(idx = ata_match_chip(dev, ids)))
1381 return ENXIO;
1382
1383 ksprintf(buffer, "ATI %s %s controller",
1384 idx->text, ata_mode2str(idx->max_dma));
1385 device_set_desc_copy(dev, buffer);
1386 ctlr->chip = idx;
1387
1388 /*
1389 * The ATI SATA controllers are actually a SiI 3112 controller, except
1390 * for the SB600.
1391 */
1392 if (ctlr->chip->cfg1 & SIIMEMIO)
1393 ctlr->chipinit = ata_sii_chipinit;
1394 else
1395 ctlr->chipinit = ata_ati_chipinit;
1396 return 0;
1397 }
1398
1399 static int
1400 ata_ati_chipinit(device_t dev)
1401 {
1402 struct ata_pci_controller *ctlr = device_get_softc(dev);
1403
1404 if (ata_setup_interrupt(dev))
1405 return ENXIO;
1406
1407 /* The SB600 needs special treatment. */
1408 if (ctlr->chip->cfg1 & ATIAHCI) {
1409 /* Check if the chip is configured as an AHCI part. */
1410 if ((pci_get_subclass(dev) == PCIS_STORAGE_SATA) &&
1411 (pci_read_config(dev, PCIR_PROGIF, 1) == PCIP_STORAGE_SATA_AHCI_1_0)) {
1412 if (ata_ahci_chipinit(dev) != ENXIO)
1413 return 0;
1414 }
1415 }
1416
1417 ctlr->setmode = ata_ati_setmode;
1418 return 0;
1419 }
1420
1421 static void
1422 ata_ati_setmode(device_t dev, int mode)
1423 {
1424 device_t gparent = GRANDPARENT(dev);
1425 struct ata_pci_controller *ctlr = device_get_softc(gparent);
1426 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
1427 struct ata_device *atadev = device_get_softc(dev);
1428 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
1429 int offset = (devno ^ 0x01) << 3;
1430 int error;
1431 u_int8_t piotimings[] = { 0x5d, 0x47, 0x34, 0x22, 0x20, 0x34, 0x22, 0x20,
1432 0x20, 0x20, 0x20, 0x20, 0x20, 0x20 };
1433 u_int8_t dmatimings[] = { 0x77, 0x21, 0x20 };
1434
1435 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma);
1436
1437 mode = ata_check_80pin(dev, mode);
1438
1439 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
1440
1441 if (bootverbose)
1442 device_printf(dev, "%ssetting %s on %s chip\n",
1443 (error) ? "FAILURE " : "",
1444 ata_mode2str(mode), ctlr->chip->text);
1445 if (!error) {
1446 if (mode >= ATA_UDMA0) {
1447 pci_write_config(gparent, 0x56,
1448 (pci_read_config(gparent, 0x56, 2) &
1449 ~(0xf << (devno << 2))) |
1450 ((mode & ATA_MODE_MASK) << (devno << 2)), 2);
1451 pci_write_config(gparent, 0x54,
1452 pci_read_config(gparent, 0x54, 1) |
1453 (0x01 << devno), 1);
1454 pci_write_config(gparent, 0x44,
1455 (pci_read_config(gparent, 0x44, 4) &
1456 ~(0xff << offset)) |
1457 (dmatimings[2] << offset), 4);
1458 }
1459 else if (mode >= ATA_WDMA0) {
1460 pci_write_config(gparent, 0x54,
1461 pci_read_config(gparent, 0x54, 1) &
1462 ~(0x01 << devno), 1);
1463 pci_write_config(gparent, 0x44,
1464 (pci_read_config(gparent, 0x44, 4) &
1465 ~(0xff << offset)) |
1466 (dmatimings[mode & ATA_MODE_MASK] << offset), 4);
1467 }
1468 else
1469 pci_write_config(gparent, 0x54,
1470 pci_read_config(gparent, 0x54, 1) &
1471 ~(0x01 << devno), 1);
1472
1473 pci_write_config(gparent, 0x4a,
1474 (pci_read_config(gparent, 0x4a, 2) &
1475 ~(0xf << (devno << 2))) |
1476 (((mode - ATA_PIO0) & ATA_MODE_MASK) << (devno<<2)),2);
1477 pci_write_config(gparent, 0x40,
1478 (pci_read_config(gparent, 0x40, 4) &
1479 ~(0xff << offset)) |
1480 (piotimings[ata_mode2idx(mode)] << offset), 4);
1481 atadev->mode = mode;
1482 }
1483 }
1484
1485 /*
1486 * Cyrix chipset support functions
1487 */
1488 int
1489 ata_cyrix_ident(device_t dev)
1490 {
1491 struct ata_pci_controller *ctlr = device_get_softc(dev);
1492
1493 if (pci_get_devid(dev) == ATA_CYRIX_5530) {
1494 device_set_desc(dev, "Cyrix 5530 ATA33 controller");
1495 ctlr->chipinit = ata_cyrix_chipinit;
1496 return 0;
1497 }
1498 return ENXIO;
1499 }
1500
1501 static int
1502 ata_cyrix_chipinit(device_t dev)
1503 {
1504 struct ata_pci_controller *ctlr = device_get_softc(dev);
1505
1506 if (ata_setup_interrupt(dev))
1507 return ENXIO;
1508
1509 if (ctlr->r_res1)
1510 ctlr->setmode = ata_cyrix_setmode;
1511 else
1512 ctlr->setmode = ata_generic_setmode;
1513 return 0;
1514 }
1515
1516 static void
1517 ata_cyrix_setmode(device_t dev, int mode)
1518 {
1519 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
1520 struct ata_device *atadev = device_get_softc(dev);
1521 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
1522 u_int32_t piotiming[] =
1523 { 0x00009172, 0x00012171, 0x00020080, 0x00032010, 0x00040010 };
1524 u_int32_t dmatiming[] = { 0x00077771, 0x00012121, 0x00002020 };
1525 u_int32_t udmatiming[] = { 0x00921250, 0x00911140, 0x00911030 };
1526 int error;
1527
1528 ch->dma->alignment = 16;
1529 ch->dma->max_iosize = 126 * DEV_BSIZE;
1530
1531 mode = ata_limit_mode(dev, mode, ATA_UDMA2);
1532
1533 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
1534
1535 if (bootverbose)
1536 device_printf(dev, "%ssetting %s on Cyrix chip\n",
1537 (error) ? "FAILURE " : "", ata_mode2str(mode));
1538 if (!error) {
1539 if (mode >= ATA_UDMA0) {
1540 ATA_OUTL(ch->r_io[ATA_BMCMD_PORT].res,
1541 0x24 + (devno << 3), udmatiming[mode & ATA_MODE_MASK]);
1542 }
1543 else if (mode >= ATA_WDMA0) {
1544 ATA_OUTL(ch->r_io[ATA_BMCMD_PORT].res,
1545 0x24 + (devno << 3), dmatiming[mode & ATA_MODE_MASK]);
1546 }
1547 else {
1548 ATA_OUTL(ch->r_io[ATA_BMCMD_PORT].res,
1549 0x20 + (devno << 3), piotiming[mode & ATA_MODE_MASK]);
1550 }
1551 atadev->mode = mode;
1552 }
1553 }
1554
1555
1556 /*
1557 * Cypress chipset support functions
1558 */
1559 int
1560 ata_cypress_ident(device_t dev)
1561 {
1562 struct ata_pci_controller *ctlr = device_get_softc(dev);
1563
1564 /*
1565 * the Cypress chip is a mess, it contains two ATA functions, but
1566 * both channels are visible on the first one.
1567 * simply ignore the second function for now, as the right
1568 * solution (ignoring the second channel on the first function)
1569 * doesn't work with the crappy ATA interrupt setup on the alpha.
1570 */
1571 if (pci_get_devid(dev) == ATA_CYPRESS_82C693 &&
1572 pci_get_function(dev) == 1 &&
1573 pci_get_subclass(dev) == PCIS_STORAGE_IDE) {
1574 device_set_desc(dev, "Cypress 82C693 ATA controller");
1575 ctlr->chipinit = ata_cypress_chipinit;
1576 return 0;
1577 }
1578 return ENXIO;
1579 }
1580
1581 static int
1582 ata_cypress_chipinit(device_t dev)
1583 {
1584 struct ata_pci_controller *ctlr = device_get_softc(dev);
1585
1586 if (ata_setup_interrupt(dev))
1587 return ENXIO;
1588
1589 ctlr->setmode = ata_cypress_setmode;
1590 return 0;
1591 }
1592
1593 static void
1594 ata_cypress_setmode(device_t dev, int mode)
1595 {
1596 device_t gparent = GRANDPARENT(dev);
1597 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
1598 struct ata_device *atadev = device_get_softc(dev);
1599 int error;
1600
1601 mode = ata_limit_mode(dev, mode, ATA_WDMA2);
1602
1603 /* XXX SOS missing WDMA0+1 + PIO modes */
1604 if (mode == ATA_WDMA2) {
1605 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
1606 if (bootverbose)
1607 device_printf(dev, "%ssetting WDMA2 on Cypress chip\n",
1608 error ? "FAILURE " : "");
1609 if (!error) {
1610 pci_write_config(gparent, ch->unit ? 0x4e : 0x4c, 0x2020, 2);
1611 atadev->mode = mode;
1612 return;
1613 }
1614 }
1615 /* we could set PIO mode timings, but we assume the BIOS did that */
1616 }
1617
1618
1619 /*
1620 * HighPoint chipset support functions
1621 */
1622 int
1623 ata_highpoint_ident(device_t dev)
1624 {
1625 struct ata_pci_controller *ctlr = device_get_softc(dev);
1626 struct ata_chip_id *idx;
1627 static struct ata_chip_id ids[] =
1628 {{ ATA_HPT374, 0x07, HPT374, 0x00, ATA_UDMA6, "HPT374" },
1629 { ATA_HPT372, 0x02, HPT372, 0x00, ATA_UDMA6, "HPT372N" },
1630 { ATA_HPT372, 0x01, HPT372, 0x00, ATA_UDMA6, "HPT372" },
1631 { ATA_HPT371, 0x01, HPT372, 0x00, ATA_UDMA6, "HPT371" },
1632 { ATA_HPT366, 0x05, HPT372, 0x00, ATA_UDMA6, "HPT372" },
1633 { ATA_HPT366, 0x03, HPT370, 0x00, ATA_UDMA5, "HPT370" },
1634 { ATA_HPT366, 0x02, HPT366, 0x00, ATA_UDMA4, "HPT368" },
1635 { ATA_HPT366, 0x00, HPT366, HPTOLD, ATA_UDMA4, "HPT366" },
1636 { ATA_HPT302, 0x01, HPT372, 0x00, ATA_UDMA6, "HPT302" },
1637 { 0, 0, 0, 0, 0, 0}};
1638 char buffer[64];
1639
1640 if (!(idx = ata_match_chip(dev, ids)))
1641 return ENXIO;
1642
1643 strcpy(buffer, "HighPoint ");
1644 strcat(buffer, idx->text);
1645 if (idx->cfg1 == HPT374) {
1646 if (pci_get_function(dev) == 0)
1647 strcat(buffer, " (channel 0+1)");
1648 if (pci_get_function(dev) == 1)
1649 strcat(buffer, " (channel 2+3)");
1650 }
1651 ksprintf(buffer, "%s %s controller", buffer, ata_mode2str(idx->max_dma));
1652 device_set_desc_copy(dev, buffer);
1653 ctlr->chip = idx;
1654 ctlr->chipinit = ata_highpoint_chipinit;
1655 return 0;
1656 }
1657
1658 static int
1659 ata_highpoint_chipinit(device_t dev)
1660 {
1661 struct ata_pci_controller *ctlr = device_get_softc(dev);
1662
1663 if (ata_setup_interrupt(dev))
1664 return ENXIO;
1665
1666 if (ctlr->chip->cfg2 == HPTOLD) {
1667 /* disable interrupt prediction */
1668 pci_write_config(dev, 0x51, (pci_read_config(dev, 0x51, 1) & ~0x80), 1);
1669 }
1670 else {
1671 /* disable interrupt prediction */
1672 pci_write_config(dev, 0x51, (pci_read_config(dev, 0x51, 1) & ~0x03), 1);
1673 pci_write_config(dev, 0x55, (pci_read_config(dev, 0x55, 1) & ~0x03), 1);
1674
1675 /* enable interrupts */
1676 pci_write_config(dev, 0x5a, (pci_read_config(dev, 0x5a, 1) & ~0x10), 1);
1677
1678 /* set clocks etc */
1679 if (ctlr->chip->cfg1 < HPT372)
1680 pci_write_config(dev, 0x5b, 0x22, 1);
1681 else
1682 pci_write_config(dev, 0x5b,
1683 (pci_read_config(dev, 0x5b, 1) & 0x01) | 0x20, 1);
1684 }
1685 ctlr->allocate = ata_highpoint_allocate;
1686 ctlr->setmode = ata_highpoint_setmode;
1687 return 0;
1688 }
1689
1690 static int
1691 ata_highpoint_allocate(device_t dev)
1692 {
1693 struct ata_channel *ch = device_get_softc(dev);
1694
1695 /* setup the usual register normal pci style */
1696 if (ata_pci_allocate(dev))
1697 return ENXIO;
1698
1699 ch->flags |= ATA_ALWAYS_DMASTAT;
1700 return 0;
1701 }
1702
1703 static void
1704 ata_highpoint_setmode(device_t dev, int mode)
1705 {
1706 device_t gparent = GRANDPARENT(dev);
1707 struct ata_pci_controller *ctlr = device_get_softc(gparent);
1708 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
1709 struct ata_device *atadev = device_get_softc(dev);
1710 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
1711 int error;
1712 u_int32_t timings33[][4] = {
1713 /* HPT366 HPT370 HPT372 HPT374 mode */
1714 { 0x40d0a7aa, 0x06914e57, 0x0d029d5e, 0x0ac1f48a }, /* PIO 0 */
1715 { 0x40d0a7a3, 0x06914e43, 0x0d029d26, 0x0ac1f465 }, /* PIO 1 */
1716 { 0x40d0a753, 0x06514e33, 0x0c829ca6, 0x0a81f454 }, /* PIO 2 */
1717 { 0x40c8a742, 0x06514e22, 0x0c829c84, 0x0a81f443 }, /* PIO 3 */
1718 { 0x40c8a731, 0x06514e21, 0x0c829c62, 0x0a81f442 }, /* PIO 4 */
1719 { 0x20c8a797, 0x26514e97, 0x2c82922e, 0x228082ea }, /* MWDMA 0 */
1720 { 0x20c8a732, 0x26514e33, 0x2c829266, 0x22808254 }, /* MWDMA 1 */
1721 { 0x20c8a731, 0x26514e21, 0x2c829262, 0x22808242 }, /* MWDMA 2 */
1722 { 0x10c8a731, 0x16514e31, 0x1c829c62, 0x121882ea }, /* UDMA 0 */
1723 { 0x10cba731, 0x164d4e31, 0x1c9a9c62, 0x12148254 }, /* UDMA 1 */
1724 { 0x10caa731, 0x16494e31, 0x1c929c62, 0x120c8242 }, /* UDMA 2 */
1725 { 0x10cfa731, 0x166d4e31, 0x1c8e9c62, 0x128c8242 }, /* UDMA 3 */
1726 { 0x10c9a731, 0x16454e31, 0x1c8a9c62, 0x12ac8242 }, /* UDMA 4 */
1727 { 0, 0x16454e31, 0x1c8a9c62, 0x12848242 }, /* UDMA 5 */
1728 { 0, 0, 0x1c869c62, 0x12808242 } /* UDMA 6 */
1729 };
1730
1731 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma);
1732
1733 if (ctlr->chip->cfg1 == HPT366 && ata_atapi(dev))
1734 mode = ata_limit_mode(dev, mode, ATA_PIO_MAX);
1735
1736 mode = ata_highpoint_check_80pin(dev, mode);
1737
1738 /*
1739 * most if not all HPT chips cant really handle that the device is
1740 * running at ATA_UDMA6/ATA133 speed, so we cheat at set the device to
1741 * a max of ATA_UDMA5/ATA100 to guard against suboptimal performance
1742 */
1743 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0,
1744 ata_limit_mode(dev, mode, ATA_UDMA5));
1745 if (bootverbose)
1746 device_printf(dev, "%ssetting %s on HighPoint chip\n",
1747 (error) ? "FAILURE " : "", ata_mode2str(mode));
1748 if (!error)
1749 pci_write_config(gparent, 0x40 + (devno << 2),
1750 timings33[ata_mode2idx(mode)][ctlr->chip->cfg1], 4);
1751 atadev->mode = mode;
1752 }
1753
1754 static int
1755 ata_highpoint_check_80pin(device_t dev, int mode)
1756 {
1757 device_t gparent = GRANDPARENT(dev);
1758 struct ata_pci_controller *ctlr = device_get_softc(gparent);
1759 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
1760 u_int8_t reg, val, res;
1761
1762 if (ctlr->chip->cfg1 == HPT374 && pci_get_function(gparent) == 1) {
1763 reg = ch->unit ? 0x57 : 0x53;
1764 val = pci_read_config(gparent, reg, 1);
1765 pci_write_config(gparent, reg, val | 0x80, 1);
1766 }
1767 else {
1768 reg = 0x5b;
1769 val = pci_read_config(gparent, reg, 1);
1770 pci_write_config(gparent, reg, val & 0xfe, 1);
1771 }
1772 res = pci_read_config(gparent, 0x5a, 1) & (ch->unit ? 0x1:0x2);
1773 pci_write_config(gparent, reg, val, 1);
1774
1775 if (mode > ATA_UDMA2 && res) {
1776 ata_print_cable(dev, "controller");
1777 mode = ATA_UDMA2;
1778 }
1779 return mode;
1780 }
1781
1782
1783 /*
1784 * Intel chipset support functions
1785 */
1786 int
1787 ata_intel_ident(device_t dev)
1788 {
1789 struct ata_pci_controller *ctlr = device_get_softc(dev);
1790 struct ata_chip_id *idx;
1791 static struct ata_chip_id ids[] =
1792 {{ ATA_I82371FB, 0, 0, 0x00, ATA_WDMA2, "PIIX" },
1793 { ATA_I82371SB, 0, 0, 0x00, ATA_WDMA2, "PIIX3" },
1794 { ATA_I82371AB, 0, 0, 0x00, ATA_UDMA2, "PIIX4" },
1795 { ATA_I82443MX, 0, 0, 0x00, ATA_UDMA2, "PIIX4" },
1796 { ATA_I82451NX, 0, 0, 0x00, ATA_UDMA2, "PIIX4" },
1797 { ATA_I82801AB, 0, 0, 0x00, ATA_UDMA2, "ICH0" },
1798 { ATA_I82801AA, 0, 0, 0x00, ATA_UDMA4, "ICH" },
1799 { ATA_I82372FB, 0, 0, 0x00, ATA_UDMA4, "ICH" },
1800 { ATA_I82801BA, 0, 0, 0x00, ATA_UDMA5, "ICH2" },
1801 { ATA_I82801BA_1, 0, 0, 0x00, ATA_UDMA5, "ICH2" },
1802 { ATA_I82801CA, 0, 0, 0x00, ATA_UDMA5, "ICH3" },
1803 { ATA_I82801CA_1, 0, 0, 0x00, ATA_UDMA5, "ICH3" },
1804 { ATA_I82801DB, 0, 0, 0x00, ATA_UDMA5, "ICH4" },
1805 { ATA_I82801DB_1, 0, 0, 0x00, ATA_UDMA5, "ICH4" },
1806 { ATA_I82801EB, 0, 0, 0x00, ATA_UDMA5, "ICH5" },
1807 { ATA_I82801EB_S1, 0, 0, 0x00, ATA_SA150, "ICH5" },
1808 { ATA_I82801EB_R1, 0, 0, 0x00, ATA_SA150, "ICH5" },
1809 { ATA_I6300ESB, 0, 0, 0x00, ATA_UDMA5, "6300ESB" },
1810 { ATA_I6300ESB_S1, 0, 0, 0x00, ATA_SA150, "6300ESB" },
1811 { ATA_I6300ESB_R1, 0, 0, 0x00, ATA_SA150, "6300ESB" },
1812 { ATA_I82801FB, 0, 0, 0x00, ATA_UDMA5, "ICH6" },
1813 { ATA_I82801FB_S1, 0, AHCI, 0x00, ATA_SA150, "ICH6" },
1814 { ATA_I82801FB_R1, 0, AHCI, 0x00, ATA_SA150, "ICH6" },
1815 { ATA_I82801FBM, 0, AHCI, 0x00, ATA_SA150, "ICH6M" },
1816 { ATA_I82801GB, 0, 0, 0x00, ATA_UDMA5, "ICH7" },
1817 { ATA_I82801GB_S1, 0, AHCI, 0x00, ATA_SA300, "ICH7" },
1818 { ATA_I82801GB_R1, 0, AHCI, 0x00, ATA_SA300, "ICH7" },
1819 { ATA_I82801GB_AH, 0, AHCI, 0x00, ATA_SA300, "ICH7" },
1820 { ATA_I82801GBM_S1, 0, AHCI, 0x00, ATA_SA300, "ICH7M" },
1821 { ATA_I82801GBM_R1, 0, AHCI, 0x00, ATA_SA300, "ICH7M" },
1822 { ATA_I82801GBM_AH, 0, AHCI, 0x00, ATA_SA300, "ICH7M" },
1823 { ATA_I63XXESB2, 0, 0, 0x00, ATA_UDMA5, "63XXESB2" },
1824 { ATA_I63XXESB2_S1, 0, AHCI, 0x00, ATA_SA300, "63XXESB2" },
1825 { ATA_I63XXESB2_S2, 0, AHCI, 0x00, ATA_SA300, "63XXESB2" },
1826 { ATA_I63XXESB2_R1, 0, AHCI, 0x00, ATA_SA300, "63XXESB2" },
1827 { ATA_I63XXESB2_R2, 0, AHCI, 0x00, ATA_SA300, "63XXESB2" },
1828 { ATA_I82801HB_S1, 0, AHCI, 0x00, ATA_SA300, "ICH8" },
1829 { ATA_I82801HB_S2, 0, AHCI, 0x00, ATA_SA300, "ICH8" },
1830 { ATA_I82801HB_R1, 0, AHCI, 0x00, ATA_SA300, "ICH8" },
1831 { ATA_I82801HB_AH4, 0, AHCI, 0x00, ATA_SA300, "ICH8" },
1832 { ATA_I82801HB_AH6, 0, AHCI, 0x00, ATA_SA300, "ICH8" },
1833 { ATA_I82801HBM_S1, 0, 0, 0x00, ATA_SA300, "ICH8M" },
1834 { ATA_I82801HBM_S2, 0, AHCI, 0x00, ATA_SA300, "ICH8M" },
1835 { ATA_I82801HBM_S3, 0, AHCI, 0x00, ATA_SA300, "ICH8M" },
1836 { ATA_I82801IB_S1, 0, AHCI, 0x00, ATA_SA300, "ICH9" },
1837 { ATA_I82801IB_S2, 0, AHCI, 0x00, ATA_SA300, "ICH9" },
1838 { ATA_I82801IB_AH2, 0, AHCI, 0x00, ATA_SA300, "ICH9" },
1839 { ATA_I82801IB_AH4, 0, AHCI, 0x00, ATA_SA300, "ICH9" },
1840 { ATA_I82801IB_AH6, 0, AHCI, 0x00, ATA_SA300, "ICH9" },
1841 { ATA_I31244, 0, 0, 0x00, ATA_SA150, "31244" },
1842 { 0, 0, 0, 0, 0, 0}};
1843 char buffer[64];
1844
1845 if (!(idx = ata_match_chip(dev, ids)))
1846 return ENXIO;
1847
1848 ksprintf(buffer, "Intel %s %s controller",
1849 idx->text, ata_mode2str(idx->max_dma));
1850 device_set_desc_copy(dev, buffer);
1851 ctlr->chip = idx;
1852 ctlr->chipinit = ata_intel_chipinit;
1853 return 0;
1854 }
1855
1856 static int
1857 ata_intel_chipinit(device_t dev)
1858 {
1859 struct ata_pci_controller *ctlr = device_get_softc(dev);
1860
1861 if (ata_setup_interrupt(dev))
1862 return ENXIO;
1863
1864 /* good old PIIX needs special treatment (not implemented) */
1865 if (ctlr->chip->chipid == ATA_I82371FB) {
1866 ctlr->setmode = ata_intel_old_setmode;
1867 }
1868
1869 /* the intel 31244 needs special care if in DPA mode */
1870 else if (ctlr->chip->chipid == ATA_I31244) {
1871 if (pci_get_subclass(dev) != PCIS_STORAGE_IDE) {
1872 ctlr->r_type2 = SYS_RES_MEMORY;
1873 ctlr->r_rid2 = PCIR_BAR(0);
1874 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
1875 &ctlr->r_rid2,
1876 RF_ACTIVE)))
1877 return ENXIO;
1878 ctlr->channels = 4;
1879 ctlr->allocate = ata_intel_31244_allocate;
1880 ctlr->reset = ata_intel_31244_reset;
1881 }
1882 ctlr->setmode = ata_sata_setmode;
1883 }
1884
1885 /* non SATA intel chips goes here */
1886 else if (ctlr->chip->max_dma < ATA_SA150) {
1887 ctlr->allocate = ata_intel_allocate;
1888 ctlr->setmode = ata_intel_new_setmode;
1889 }
1890
1891 /* SATA parts can be either compat or AHCI */
1892 else {
1893 /* force all ports active "the legacy way" */
1894 pci_write_config(dev, 0x92, pci_read_config(dev, 0x92, 2) | 0x0f,2);
1895
1896 ctlr->allocate = ata_intel_allocate;
1897 ctlr->reset = ata_intel_reset;
1898
1899 /*
1900 * if we have AHCI capability and BAR(5) as a memory resource
1901 * and AHCI or RAID mode enabled in BIOS we go for AHCI mode
1902 */
1903 if ((ctlr->chip->cfg1 == AHCI) &&
1904 (pci_read_config(dev, 0x90, 1) & 0xc0) &&
1905 (ata_ahci_chipinit(dev) != ENXIO))
1906 return 0;
1907
1908 ctlr->setmode = ata_sata_setmode;
1909
1910 /* enable PCI interrupt */
1911 pci_write_config(dev, PCIR_COMMAND,
1912 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400, 2);
1913 }
1914 return 0;
1915 }
1916
1917 static int
1918 ata_intel_allocate(device_t dev)
1919 {
1920 struct ata_channel *ch = device_get_softc(dev);
1921
1922 /* setup the usual register normal pci style */
1923 if (ata_pci_allocate(dev))
1924 return ENXIO;
1925
1926 ch->flags |= ATA_ALWAYS_DMASTAT;
1927 return 0;
1928 }
1929
1930 static void
1931 ata_intel_reset(device_t dev)
1932 {
1933 device_t parent = device_get_parent(dev);
1934 struct ata_pci_controller *ctlr = device_get_softc(parent);
1935 struct ata_channel *ch = device_get_softc(dev);
1936 int mask, timeout;
1937
1938 /* ICH6 & ICH7 in compat mode has 4 SATA ports as master/slave on 2 ch's */
1939 if (ctlr->chip->cfg1) {
1940 mask = (0x0005 << ch->unit);
1941 }
1942 else {
1943 /* ICH5 in compat mode has SATA ports as master/slave on 1 channel */
1944 if (pci_read_config(parent, 0x90, 1) & 0x04)
1945 mask = 0x0003;
1946 else {
1947 mask = (0x0001 << ch->unit);
1948 /* XXX SOS should be in intel_allocate if we grow it */
1949 ch->flags |= ATA_NO_SLAVE;
1950 }
1951 }
1952 pci_write_config(parent, 0x92, pci_read_config(parent, 0x92, 2) & ~mask, 2);
1953 DELAY(10);
1954 pci_write_config(parent, 0x92, pci_read_config(parent, 0x92, 2) | mask, 2);
1955
1956 /* wait up to 1 sec for "connect well" */
1957 for (timeout = 0; timeout < 100 ; timeout++) {
1958 if (((pci_read_config(parent, 0x92, 2) & (mask << 4)) == (mask << 4)) &&
1959 (ATA_IDX_INB(ch, ATA_STATUS) != 0xff))
1960 break;
1961 ata_udelay(10000);
1962 }
1963 ata_generic_reset(dev);
1964 }
1965
1966 static void
1967 ata_intel_old_setmode(device_t dev, int mode)
1968 {
1969 /* NOT YET */
1970 }
1971
1972 static void
1973 ata_intel_new_setmode(device_t dev, int mode)
1974 {
1975 device_t gparent = GRANDPARENT(dev);
1976 struct ata_pci_controller *ctlr = device_get_softc(gparent);
1977 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
1978 struct ata_device *atadev = device_get_softc(dev);
1979 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
1980 u_int32_t reg40 = pci_read_config(gparent, 0x40, 4);
1981 u_int8_t reg44 = pci_read_config(gparent, 0x44, 1);
1982 u_int8_t reg48 = pci_read_config(gparent, 0x48, 1);
1983 u_int16_t reg4a = pci_read_config(gparent, 0x4a, 2);
1984 u_int16_t reg54 = pci_read_config(gparent, 0x54, 2);
1985 u_int32_t mask40 = 0, new40 = 0;
1986 u_int8_t mask44 = 0, new44 = 0;
1987 int error;
1988 u_int8_t timings[] = { 0x00, 0x00, 0x10, 0x21, 0x23, 0x10, 0x21, 0x23,
1989 0x23, 0x23, 0x23, 0x23, 0x23, 0x23, 0x23 };
1990 /* PIO0 PIO1 PIO2 PIO3 PIO4 WDMA0 WDMA1 WDMA2 */
1991 /* UDMA0 UDMA1 UDMA2 UDMA3 UDMA4 UDMA5 UDMA6 */
1992
1993 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma);
1994
1995 if ( mode > ATA_UDMA2 && !(reg54 & (0x10 << devno))) {
1996 ata_print_cable(dev, "controller");
1997 mode = ATA_UDMA2;
1998 }
1999
2000 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
2001
2002 if (bootverbose)
2003 device_printf(dev, "%ssetting %s on %s chip\n",
2004 (error) ? "FAILURE " : "",
2005 ata_mode2str(mode), ctlr->chip->text);
2006 if (error)
2007 return;
2008
2009 /*
2010 * reg48: 1 bit per (primary drive 0, primary drive 1, secondary
2011 * drive 0, secondary drive 1)
2012 *
2013 * 0 Disable Ultra DMA mode
2014 * 1 Enable Ultra DMA mode
2015 *
2016 * reg4a: 4 bits per (primary drive 0, primary drive 1, secondary
2017 * drive 0, secondary drive 1).
2018 * 0000 UDMA mode 0
2019 * 0001 UDMA mode 1, 3, 5
2020 * 0010 UDMA mode 2, 4, reserved
2021 * 0011 reserved
2022 * (top two bits for each drive reserved)
2023 */
2024 #if 0
2025 device_printf(dev,
2026 "regs before 40=%08x 44=%02x 48=%02x 4a=%04x 54=%04x\n",
2027 reg40, reg44, reg48 ,reg4a, reg54);
2028 #endif
2029 reg48 &= ~(0x0001 << devno);
2030 reg4a &= ~(0x3 << (devno << 2));
2031 if (mode >= ATA_UDMA0) {
2032 reg48 |= 0x0001 << devno;
2033 if (mode > ATA_UDMA0)
2034 reg4a |= (1 + !(mode & 0x01)) << (devno << 2);
2035 }
2036 pci_write_config(gparent, 0x48, reg48, 2);
2037 pci_write_config(gparent, 0x4a, reg4a, 2);
2038
2039 /*
2040 * reg54:
2041 *
2042 * 32:20 reserved
2043 * 19:18 Secondary ATA signal mode
2044 * 17:16 Primary ATA signal mode
2045 * 00 = Normal (enabled)
2046 * 01 = Tri-state (disabled)
2047 * 10 = Drive Low (disabled)
2048 * 11 = Reserved
2049 *
2050 * 15 Secondary drive 1 - Base Clock
2051 * 14 Secondary drive 0 - Base Clock
2052 * 13 Primary drive 1 - Base Clock
2053 * 12 Primary drive 0 - Base Clock
2054 * 0 = Select 33 MHz clock
2055 * 1 = Select 100 Mhz clock
2056 *
2057 * 11 Reserved
2058 * 10 Vendor specific (set by BIOS?)
2059 * 09:08 Reserved
2060 *
2061 * 07 Secondary drive 1 - Cable Type
2062 * 06 Secondary drive 0 - Cable Type
2063 * 05 Primary drive 1 - Cable Type
2064 * 04 Primary drive 0 - Cable Type
2065 * 0 = 40 Conductor
2066 * 1 = 80 Conductor (or high speed cable)
2067 *
2068 * 03 Secondary drive 1 - Select 33/66 clock
2069 * 02 Secondary drive 0 - Select 33/66 clock
2070 * 01 Primary drive 1 - Select 33/66 clock
2071 * 00 Primary drive 0 - Select 33/66 clock
2072 * 0 = Select 33 MHz
2073 * 1 = Select 66 MHz
2074 *
2075 * It is unclear what this should be set to when operating
2076 * in 100MHz mode.
2077 *
2078 * NOTE: UDMA2 = 33 MHz
2079 * UDMA3 = 40 MHz (?) - unsupported
2080 * UDMA4 = 66 MHz
2081 * UDMA5 = 100 MHz
2082 * UDMA6 = 133 Mhz
2083 */
2084 reg54 |= 0x0400; /* set vendor specific bit */
2085 reg54 &= ~((0x1 << devno) | (0x1000 << devno));
2086
2087 if (mode >= ATA_UDMA5)
2088 reg54 |= (0x1000 << devno);
2089 else if (mode >= ATA_UDMA3) /* XXX should this be ATA_UDMA3 or 4? */
2090 reg54 |= (0x1 << devno);
2091
2092 pci_write_config(gparent, 0x54, reg54, 2);
2093
2094 /*
2095 * Reg40 (32 bits... well, actually two 16 bit registers)
2096 *
2097 * Primary channel bits 15:00, Secondary channel bits 31:00. Note
2098 * that slave timings are handled in register 44.
2099 *
2100 * 15 ATA Decode Enable (R/W) 1 = enable decoding of I/O ranges
2101 *
2102 * 14 Slave ATA Timing Register Enable (R/W)
2103 *
2104 * 13:12 IORDY Sample Mode
2105 * 00 PIO-0
2106 * 01 PIO-2, SW-2
2107 * 10 PIO-3, PIO-4, MW-1, MW-2
2108 * 11 Reserved
2109 *
2110 * 11:10 Reserved
2111 *
2112 * 09:08 Recovery Mode
2113 * 00 PIO-0, PIO-2, SW-2
2114 * 01 PIO-3, MW-1
2115 * 10 Reserved
2116 * 11 PIO-4, MW-2
2117 *
2118 * 07:04 Secondary Device Control Bits
2119 * 03:00 Primary Device Control Bits
2120 *
2121 * bit 3 DMA Timing Enable
2122 *
2123 * bit 2 Indicate Presence of ATA(1) or ATAPI(0) device
2124 *
2125 * bit 1 Enable IORDY sample point capability for PIO
2126 * xfers. Always enabled for PIO4 and PIO3, enabled
2127 * for PIO2 if indicated by the device, and otherwise
2128 * probably should be 0.
2129 *
2130 * bit 0 Fast Drive Timing Enable. Enables faster then PIO-0
2131 * timing modes.
2132 */
2133
2134 /*
2135 * Modify reg40 according to the table
2136 */
2137 if (atadev->unit == ATA_MASTER) {
2138 mask40 = 0x3300;
2139 new40 = timings[ata_mode2idx(mode)] << 8;
2140 }
2141 else {
2142 mask44 = 0x0f;
2143 new44 = ((timings[ata_mode2idx(mode)] & 0x30) >> 2) |
2144 (timings[ata_mode2idx(mode)] & 0x03);
2145 }
2146
2147 /*
2148 * Slave ATA timing register enable
2149 */
2150 mask40 |= 0x4000;
2151 new40 |= 0x4000;
2152
2153 /*
2154 * Device control bits 3:0 for master, 7:4 for slave.
2155 *
2156 * bit3 DMA Timing enable.
2157 * bit2 Indicate presence of ATA(1) or ATAPI(0) device, set accordingly
2158 * bit1 Enable IORDY sample point capability for PIO xfers. Always
2159 * enabled for PIO4 and PIO3, enabled for PIO2 if indicated by
2160 * the device, and otherwise should be 0.
2161 * bit0 Fast Drive Timing Enable. Enable faster then PIO-0 timing modes.
2162 *
2163 * Set to: 0 x 1 1
2164 */
2165
2166 if (atadev->unit == ATA_MASTER) {
2167 mask40 |= 0x0F;
2168 new40 |= 0x03;
2169 if (!ata_atapi(dev))
2170 new40 |= 0x04;
2171 } else {
2172 mask40 |= 0xF0;
2173 new40 |= 0x30;
2174 if (!ata_atapi(dev))
2175 new40 |= 0x40;
2176 }
2177 /*
2178 reg40 &= ~0x00ff00ff;
2179 reg40 |= 0x40774077;
2180 */
2181
2182 /*
2183 * Primary or Secondary controller
2184 */
2185 if (ch->unit) {
2186 mask40 <<= 16;
2187 new40 <<= 16;
2188 mask44 <<= 4;
2189 new44 <<= 4;
2190 }
2191 pci_write_config(gparent, 0x40, (reg40 & ~mask40) | new40, 4);
2192 pci_write_config(gparent, 0x44, (reg44 & ~mask44) | new44, 1);
2193
2194 #if 0
2195 reg40 = pci_read_config(gparent, 0x40, 4);
2196 reg44 = pci_read_config(gparent, 0x44, 1);
2197 reg48 = pci_read_config(gparent, 0x48, 1);
2198 reg4a = pci_read_config(gparent, 0x4a, 2);
2199 reg54 = pci_read_config(gparent, 0x54, 2);
2200 device_printf(dev,
2201 "regs after 40=%08x 44=%02x 48=%02x 4a=%04x 54=%04x\n",
2202 reg40, reg44, reg48 ,reg4a, reg54);
2203 #endif
2204
2205 atadev->mode = mode;
2206 }
2207
2208 static int
2209 ata_intel_31244_allocate(device_t dev)
2210 {
2211 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
2212 struct ata_channel *ch = device_get_softc(dev);
2213 int i;
2214 int ch_offset;
2215
2216 ch_offset = 0x200 + ch->unit * 0x200;
2217
2218 for (i = ATA_DATA; i < ATA_MAX_RES; i++)
2219 ch->r_io[i].res = ctlr->r_res2;
2220
2221 /* setup ATA registers */
2222 ch->r_io[ATA_DATA].offset = ch_offset + 0x00;
2223 ch->r_io[ATA_FEATURE].offset = ch_offset + 0x06;
2224 ch->r_io[ATA_COUNT].offset = ch_offset + 0x08;
2225 ch->r_io[ATA_SECTOR].offset = ch_offset + 0x0c;
2226 ch->r_io[ATA_CYL_LSB].offset = ch_offset + 0x10;
2227 ch->r_io[ATA_CYL_MSB].offset = ch_offset + 0x14;
2228 ch->r_io[ATA_DRIVE].offset = ch_offset + 0x18;
2229 ch->r_io[ATA_COMMAND].offset = ch_offset + 0x1d;
2230 ch->r_io[ATA_ERROR].offset = ch_offset + 0x04;
2231 ch->r_io[ATA_STATUS].offset = ch_offset + 0x1c;
2232 ch->r_io[ATA_ALTSTAT].offset = ch_offset + 0x28;
2233 ch->r_io[ATA_CONTROL].offset = ch_offset + 0x29;
2234
2235 /* setup DMA registers */
2236 ch->r_io[ATA_SSTATUS].offset = ch_offset + 0x100;
2237 ch->r_io[ATA_SERROR].offset = ch_offset + 0x104;
2238 ch->r_io[ATA_SCONTROL].offset = ch_offset + 0x108;
2239
2240 /* setup SATA registers */
2241 ch->r_io[ATA_BMCMD_PORT].offset = ch_offset + 0x70;
2242 ch->r_io[ATA_BMSTAT_PORT].offset = ch_offset + 0x72;
2243 ch->r_io[ATA_BMDTP_PORT].offset = ch_offset + 0x74;
2244
2245 ch->flags |= ATA_NO_SLAVE;
2246 ata_pci_hw(dev);
2247 ch->hw.status = ata_intel_31244_status;
2248 ch->hw.command = ata_intel_31244_command;
2249
2250 /* enable PHY state change interrupt */
2251 ATA_OUTL(ctlr->r_res2, 0x4,
2252 ATA_INL(ctlr->r_res2, 0x04) | (0x01 << (ch->unit << 3)));
2253 return 0;
2254 }
2255
2256 static int
2257 ata_intel_31244_status(device_t dev)
2258 {
2259 /* do we have any PHY events ? */
2260 ata_sata_phy_check_events(dev);
2261
2262 /* any drive action to take care of ? */
2263 return ata_pci_status(dev);
2264 }
2265
2266 static int
2267 ata_intel_31244_command(struct ata_request *request)
2268 {
2269 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev));
2270 struct ata_device *atadev = device_get_softc(request->dev);
2271 u_int64_t lba;
2272
2273 if (!(atadev->flags & ATA_D_48BIT_ACTIVE))
2274 return (ata_generic_command(request));
2275
2276 lba = request->u.ata.lba;
2277 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_D_LBA | atadev->unit);
2278 /* enable interrupt */
2279 ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_4BIT);
2280 ATA_IDX_OUTW(ch, ATA_FEATURE, request->u.ata.feature);
2281 ATA_IDX_OUTW(ch, ATA_COUNT, request->u.ata.count);
2282 ATA_IDX_OUTW(ch, ATA_SECTOR, ((lba >> 16) & 0xff00) | (lba & 0x00ff));
2283 ATA_IDX_OUTW(ch, ATA_CYL_LSB, ((lba >> 24) & 0xff00) |
2284 ((lba >> 8) & 0x00ff));
2285 ATA_IDX_OUTW(ch, ATA_CYL_MSB, ((lba >> 32) & 0xff00) |
2286 ((lba >> 16) & 0x00ff));
2287
2288 /* issue command to controller */
2289 ATA_IDX_OUTB(ch, ATA_COMMAND, request->u.ata.command);
2290
2291 return 0;
2292 }
2293
2294 static void
2295 ata_intel_31244_reset(device_t dev)
2296 {
2297 if (ata_sata_phy_reset(dev))
2298 ata_generic_reset(dev);
2299 }
2300
2301
2302 /*
2303 * Integrated Technology Express Inc. (ITE) chipset support functions
2304 */
2305 int
2306 ata_ite_ident(device_t dev)
2307 {
2308 struct ata_pci_controller *ctlr = device_get_softc(dev);
2309 struct ata_chip_id *idx;
2310 static struct ata_chip_id ids[] =
2311 {{ ATA_IT8212F, 0x00, 0x00, 0x00, ATA_UDMA6, "IT8212F" },
2312 { ATA_IT8211F, 0x00, 0x00, 0x00, ATA_UDMA6, "IT8211F" },
2313 { 0, 0, 0, 0, 0, 0}};
2314 char buffer[64];
2315
2316 if (!(idx = ata_match_chip(dev, ids)))
2317 return ENXIO;
2318
2319 ksprintf(buffer, "ITE %s %s controller",
2320 idx->text, ata_mode2str(idx->max_dma));
2321 device_set_desc_copy(dev, buffer);
2322 ctlr->chip = idx;
2323 ctlr->chipinit = ata_ite_chipinit;
2324 return 0;
2325 }
2326
2327 static int
2328 ata_ite_chipinit(device_t dev)
2329 {
2330 struct ata_pci_controller *ctlr = device_get_softc(dev);
2331
2332 if (ata_setup_interrupt(dev))
2333 return ENXIO;
2334
2335 ctlr->setmode = ata_ite_setmode;
2336
2337 /* set PCI mode and 66Mhz reference clock */
2338 pci_write_config(dev, 0x50, pci_read_config(dev, 0x50, 1) & ~0x83, 1);
2339
2340 /* set default active & recover timings */
2341 pci_write_config(dev, 0x54, 0x31, 1);
2342 pci_write_config(dev, 0x56, 0x31, 1);
2343 return 0;
2344 }
2345
2346 static void
2347 ata_ite_setmode(device_t dev, int mode)
2348 {
2349 device_t gparent = GRANDPARENT(dev);
2350 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
2351 struct ata_device *atadev = device_get_softc(dev);
2352 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
2353 int error;
2354
2355 /* correct the mode for what the HW supports */
2356 mode = ata_limit_mode(dev, mode, ATA_UDMA6);
2357
2358 /* check the CBLID bits for 80 conductor cable detection */
2359 if (mode > ATA_UDMA2 && (pci_read_config(gparent, 0x40, 2) &
2360 (ch->unit ? (1<<3) : (1<<2)))) {
2361 ata_print_cable(dev, "controller");
2362 mode = ATA_UDMA2;
2363 }
2364
2365 /* set the wanted mode on the device */
2366 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
2367
2368 if (bootverbose)
2369 device_printf(dev, "%s setting %s on ITE8212F chip\n",
2370 (error) ? "failed" : "success", ata_mode2str(mode));
2371
2372 /* if the device accepted the mode change, setup the HW accordingly */
2373 if (!error) {
2374 if (mode >= ATA_UDMA0) {
2375 u_int8_t udmatiming[] =
2376 { 0x44, 0x42, 0x31, 0x21, 0x11, 0xa2, 0x91 };
2377
2378 /* enable UDMA mode */
2379 pci_write_config(gparent, 0x50,
2380 pci_read_config(gparent, 0x50, 1) &
2381 ~(1 << (devno + 3)), 1);
2382
2383 /* set UDMA timing */
2384 pci_write_config(gparent,
2385 0x56 + (ch->unit << 2) + ATA_DEV(atadev->unit),
2386 udmatiming[mode & ATA_MODE_MASK], 1);
2387 }
2388 else {
2389 u_int8_t chtiming[] =
2390 { 0xaa, 0xa3, 0xa1, 0x33, 0x31, 0x88, 0x32, 0x31 };
2391
2392 /* disable UDMA mode */
2393 pci_write_config(gparent, 0x50,
2394 pci_read_config(gparent, 0x50, 1) |
2395 (1 << (devno + 3)), 1);
2396
2397 /* set active and recover timing (shared between master & slave) */
2398 if (pci_read_config(gparent, 0x54 + (ch->unit << 2), 1) <
2399 chtiming[ata_mode2idx(mode)])
2400 pci_write_config(gparent, 0x54 + (ch->unit << 2),
2401 chtiming[ata_mode2idx(mode)], 1);
2402 }
2403 atadev->mode = mode;
2404 }
2405 }
2406
2407
2408 /*
2409 * JMicron chipset support functions
2410 */
2411 int
2412 ata_jmicron_ident(device_t dev)
2413 {
2414 struct ata_pci_controller *ctlr = device_get_softc(dev);
2415 struct ata_chip_id *idx;
2416 static struct ata_chip_id ids[] =
2417 {{ ATA_JMB360, 0, 1, 0, ATA_SA300, "JMB360" },
2418 { ATA_JMB361, 0, 1, 1, ATA_SA300, "JMB361" },
2419 { ATA_JMB363, 0, 2, 1, ATA_SA300, "JMB363" },
2420 { ATA_JMB365, 0, 1, 2, ATA_SA300, "JMB365" },
2421 { ATA_JMB366, 0, 2, 2, ATA_SA300, "JMB366" },
2422 { ATA_JMB368, 0, 0, 1, ATA_UDMA6, "JMB368" },
2423 { 0, 0, 0, 0, 0, 0}};
2424 char buffer[64];
2425
2426 if (!(idx = ata_match_chip(dev, ids)))
2427 return ENXIO;
2428
2429 if ((pci_read_config(dev, 0xdf, 1) & 0x40) &&
2430 (pci_get_function(dev) == (pci_read_config(dev, 0x40, 1) & 0x02 >> 1)))
2431 ksnprintf(buffer, sizeof(buffer), "JMicron %s %s controller",
2432 idx->text, ata_mode2str(ATA_UDMA6));
2433 else
2434 ksnprintf(buffer, sizeof(buffer), "JMicron %s %s controller",
2435 idx->text, ata_mode2str(idx->max_dma));
2436 device_set_desc_copy(dev, buffer);
2437 ctlr->chip = idx;
2438 ctlr->chipinit = ata_jmicron_chipinit;
2439 return 0;
2440 }
2441
2442 static int
2443 ata_jmicron_chipinit(device_t dev)
2444 {
2445 struct ata_pci_controller *ctlr = device_get_softc(dev);
2446 int error;
2447
2448 if (ata_setup_interrupt(dev))
2449 return ENXIO;
2450
2451 /* do we have multiple PCI functions ? */
2452 if (pci_read_config(dev, 0xdf, 1) & 0x40) {
2453 /* are we on the AHCI part ? */
2454 if (ata_ahci_chipinit(dev) != ENXIO)
2455 return 0;
2456
2457 /* otherwise we are on the PATA part */
2458 ctlr->allocate = ata_pci_allocate;
2459 ctlr->reset = ata_generic_reset;
2460 ctlr->dmainit = ata_pci_dmainit;
2461 ctlr->setmode = ata_jmicron_setmode;
2462 ctlr->channels = ctlr->chip->cfg2;
2463 }
2464 else {
2465 /* set controller configuration to a combined setup we support */
2466 pci_write_config(dev, 0x40, 0x80c0a131, 4);
2467 pci_write_config(dev, 0x80, 0x01200000, 4);
2468
2469 if ((error = ata_ahci_chipinit(dev)))
2470 return error;
2471
2472 ctlr->allocate = ata_jmicron_allocate;
2473 ctlr->reset = ata_jmicron_reset;
2474 ctlr->dmainit = ata_jmicron_dmainit;
2475 ctlr->setmode = ata_jmicron_setmode;
2476
2477 /* set the number of HW channels */
2478 ctlr->channels = ctlr->chip->cfg1 + ctlr->chip->cfg2;
2479 }
2480 return 0;
2481 }
2482
2483 static int
2484 ata_jmicron_allocate(device_t dev)
2485 {
2486 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
2487 struct ata_channel *ch = device_get_softc(dev);
2488 int error;
2489
2490 if (ch->unit >= ctlr->chip->cfg1) {
2491 ch->unit -= ctlr->chip->cfg1;
2492 error = ata_pci_allocate(dev);
2493 ch->unit += ctlr->chip->cfg1;
2494 }
2495 else
2496 error = ata_ahci_allocate(dev);
2497 return error;
2498 }
2499
2500 static void
2501 ata_jmicron_reset(device_t dev)
2502 {
2503 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
2504 struct ata_channel *ch = device_get_softc(dev);
2505
2506 if (ch->unit >= ctlr->chip->cfg1)
2507 ata_generic_reset(dev);
2508 else
2509 ata_ahci_reset(dev);
2510 }
2511
2512 static void
2513 ata_jmicron_dmainit(device_t dev)
2514 {
2515 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
2516 struct ata_channel *ch = device_get_softc(dev);
2517
2518 if (ch->unit >= ctlr->chip->cfg1)
2519 ata_pci_dmainit(dev);
2520 else
2521 ata_ahci_dmainit(dev);
2522 }
2523
2524 static void
2525 ata_jmicron_setmode(device_t dev, int mode)
2526 {
2527 struct ata_pci_controller *ctlr = device_get_softc(GRANDPARENT(dev));
2528 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
2529
2530 if (pci_read_config(dev, 0xdf, 1) & 0x40 || ch->unit >= ctlr->chip->cfg1) {
2531 struct ata_device *atadev = device_get_softc(dev);
2532
2533 /* check for 80pin cable present */
2534 if (pci_read_config(dev, 0x40, 1) & 0x08)
2535 mode = ata_limit_mode(dev, mode, ATA_UDMA2);
2536 else
2537 mode = ata_limit_mode(dev, mode, ATA_UDMA6);
2538
2539 if (!ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode))
2540 atadev->mode = mode;
2541 }
2542 else
2543 ata_sata_setmode(dev, mode);
2544 }
2545
2546
2547 /*
2548 * Marvell chipset support functions
2549 */
2550 #define ATA_MV_HOST_BASE(ch) \
2551 ((ch->unit & 3) * 0x0100) + (ch->unit > 3 ? 0x30000 : 0x20000)
2552 #define ATA_MV_EDMA_BASE(ch) \
2553 ((ch->unit & 3) * 0x2000) + (ch->unit > 3 ? 0x30000 : 0x20000)
2554
2555 struct ata_marvell_response {
2556 u_int16_t tag;
2557 u_int8_t edma_status;
2558 u_int8_t dev_status;
2559 u_int32_t timestamp;
2560 };
2561
2562 struct ata_marvell_dma_prdentry {
2563 u_int32_t addrlo;
2564 u_int32_t count;
2565 u_int32_t addrhi;
2566 u_int32_t reserved;
2567 };
2568
2569 int
2570 ata_marvell_ident(device_t dev)
2571 {
2572 struct ata_pci_controller *ctlr = device_get_softc(dev);
2573 struct ata_chip_id *idx;
2574 static struct ata_chip_id ids[] =
2575 {{ ATA_M88SX5040, 0, 4, MV50XX, ATA_SA150, "88SX5040" },
2576 { ATA_M88SX5041, 0, 4, MV50XX, ATA_SA150, "88SX5041" },
2577 { ATA_M88SX5080, 0, 8, MV50XX, ATA_SA150, "88SX5080" },
2578 { ATA_M88SX5081, 0, 8, MV50XX, ATA_SA150, "88SX5081" },
2579 { ATA_M88SX6041, 0, 4, MV60XX, ATA_SA300, "88SX6041" },
2580 { ATA_M88SX6081, 0, 8, MV60XX, ATA_SA300, "88SX6081" },
2581 { ATA_M88SX6101, 0, 1, MV61XX, ATA_UDMA6, "88SX6101" },
2582 { ATA_M88SX6145, 0, 2, MV61XX, ATA_UDMA6, "88SX6145" },
2583 { 0, 0, 0, 0, 0, 0}};
2584 char buffer[64];
2585
2586 if (!(idx = ata_match_chip(dev, ids)))
2587 return ENXIO;
2588
2589 ksprintf(buffer, "Marvell %s %s controller",
2590 idx->text, ata_mode2str(idx->max_dma));
2591 device_set_desc_copy(dev, buffer);
2592 ctlr->chip = idx;
2593 switch (ctlr->chip->cfg2) {
2594 case MV50XX:
2595 case MV60XX:
2596 ctlr->chipinit = ata_marvell_edma_chipinit;
2597 break;
2598 case MV61XX:
2599 ctlr->chipinit = ata_marvell_pata_chipinit;
2600 break;
2601 }
2602 return 0;
2603 }
2604
2605 static int
2606 ata_marvell_pata_chipinit(device_t dev)
2607 {
2608 struct ata_pci_controller *ctlr = device_get_softc(dev);
2609
2610 if (ata_setup_interrupt(dev))
2611 return ENXIO;
2612
2613 ctlr->allocate = ata_marvell_pata_allocate;
2614 ctlr->setmode = ata_marvell_pata_setmode;
2615 ctlr->channels = ctlr->chip->cfg1;
2616 return 0;
2617 }
2618
2619 static int
2620 ata_marvell_pata_allocate(device_t dev)
2621 {
2622 struct ata_channel *ch = device_get_softc(dev);
2623
2624 /* setup the usual register normal pci style */
2625 if (ata_pci_allocate(dev))
2626 return ENXIO;
2627
2628 /* dont use 32 bit PIO transfers */
2629 ch->flags |= ATA_USE_16BIT;
2630
2631 return 0;
2632 }
2633
2634 static void
2635 ata_marvell_pata_setmode(device_t dev, int mode)
2636 {
2637 device_t gparent = GRANDPARENT(dev);
2638 struct ata_pci_controller *ctlr = device_get_softc(gparent);
2639 struct ata_device *atadev = device_get_softc(dev);
2640
2641 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma);
2642 mode = ata_check_80pin(dev, mode);
2643 if (!ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode))
2644 atadev->mode = mode;
2645 }
2646
2647 static int
2648 ata_marvell_edma_chipinit(device_t dev)
2649 {
2650 struct ata_pci_controller *ctlr = device_get_softc(dev);
2651
2652 if (ata_setup_interrupt(dev))
2653 return ENXIO;
2654
2655 ctlr->r_type1 = SYS_RES_MEMORY;
2656 ctlr->r_rid1 = PCIR_BAR(0);
2657 if (!(ctlr->r_res1 = bus_alloc_resource_any(dev, ctlr->r_type1,
2658 &ctlr->r_rid1, RF_ACTIVE)))
2659 return ENXIO;
2660
2661 /* mask all host controller interrupts */
2662 ATA_OUTL(ctlr->r_res1, 0x01d64, 0x00000000);
2663
2664 /* mask all PCI interrupts */
2665 ATA_OUTL(ctlr->r_res1, 0x01d5c, 0x00000000);
2666
2667 ctlr->allocate = ata_marvell_edma_allocate;
2668 ctlr->reset = ata_marvell_edma_reset;
2669 ctlr->dmainit = ata_marvell_edma_dmainit;
2670 ctlr->setmode = ata_sata_setmode;
2671 ctlr->channels = ctlr->chip->cfg1;
2672
2673 /* clear host controller interrupts */
2674 ATA_OUTL(ctlr->r_res1, 0x20014, 0x00000000);
2675 if (ctlr->chip->cfg1 > 4)
2676 ATA_OUTL(ctlr->r_res1, 0x30014, 0x00000000);
2677
2678 /* clear PCI interrupts */
2679 ATA_OUTL(ctlr->r_res1, 0x01d58, 0x00000000);
2680
2681 /* unmask PCI interrupts we want */
2682 ATA_OUTL(ctlr->r_res1, 0x01d5c, 0x007fffff);
2683
2684 /* unmask host controller interrupts we want */
2685 ATA_OUTL(ctlr->r_res1, 0x01d64, 0x000000ff/*HC0*/ | 0x0001fe00/*HC1*/ |
2686 /*(1<<19) | (1<<20) | (1<<21) |*/(1<<22) | (1<<24) | (0x7f << 25));
2687
2688 /* enable PCI interrupt */
2689 pci_write_config(dev, PCIR_COMMAND,
2690 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400, 2);
2691 return 0;
2692 }
2693
2694 static int
2695 ata_marvell_edma_allocate(device_t dev)
2696 {
2697 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
2698 struct ata_channel *ch = device_get_softc(dev);
2699 u_int64_t work = ch->dma->work_bus;
2700 int i;
2701
2702 /* clear work area */
2703 bzero(ch->dma->work, 1024+256);
2704
2705 /* set legacy ATA resources */
2706 for (i = ATA_DATA; i <= ATA_COMMAND; i++) {
2707 ch->r_io[i].res = ctlr->r_res1;
2708 ch->r_io[i].offset = 0x02100 + (i << 2) + ATA_MV_EDMA_BASE(ch);
2709 }
2710 ch->r_io[ATA_CONTROL].res = ctlr->r_res1;
2711 ch->r_io[ATA_CONTROL].offset = 0x02120 + ATA_MV_EDMA_BASE(ch);
2712 ch->r_io[ATA_IDX_ADDR].res = ctlr->r_res1;
2713 ata_default_registers(dev);
2714
2715 /* set SATA resources */
2716 switch (ctlr->chip->cfg2) {
2717 case MV50XX:
2718 ch->r_io[ATA_SSTATUS].res = ctlr->r_res1;
2719 ch->r_io[ATA_SSTATUS].offset = 0x00100 + ATA_MV_HOST_BASE(ch);
2720 ch->r_io[ATA_SERROR].res = ctlr->r_res1;
2721 ch->r_io[ATA_SERROR].offset = 0x00104 + ATA_MV_HOST_BASE(ch);
2722 ch->r_io[ATA_SCONTROL].res = ctlr->r_res1;
2723 ch->r_io[ATA_SCONTROL].offset = 0x00108 + ATA_MV_HOST_BASE(ch);
2724 break;
2725 case MV60XX:
2726 ch->r_io[ATA_SSTATUS].res = ctlr->r_res1;
2727 ch->r_io[ATA_SSTATUS].offset = 0x02300 + ATA_MV_EDMA_BASE(ch);
2728 ch->r_io[ATA_SERROR].res = ctlr->r_res1;
2729 ch->r_io[ATA_SERROR].offset = 0x02304 + ATA_MV_EDMA_BASE(ch);
2730 ch->r_io[ATA_SCONTROL].res = ctlr->r_res1;
2731 ch->r_io[ATA_SCONTROL].offset = 0x02308 + ATA_MV_EDMA_BASE(ch);
2732 ch->r_io[ATA_SACTIVE].res = ctlr->r_res1;
2733 ch->r_io[ATA_SACTIVE].offset = 0x02350 + ATA_MV_EDMA_BASE(ch);
2734 break;
2735 }
2736
2737 ch->flags |= ATA_NO_SLAVE;
2738 ch->flags |= ATA_USE_16BIT; /* XXX SOS needed ? */
2739 ata_generic_hw(dev);
2740 ch->hw.begin_transaction = ata_marvell_edma_begin_transaction;
2741 ch->hw.end_transaction = ata_marvell_edma_end_transaction;
2742 ch->hw.status = ata_marvell_edma_status;
2743
2744 /* disable the EDMA machinery */
2745 ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000002);
2746 DELAY(100000); /* SOS should poll for disabled */
2747
2748 /* set configuration to non-queued 128b read transfers stop on error */
2749 ATA_OUTL(ctlr->r_res1, 0x02000 + ATA_MV_EDMA_BASE(ch), (1<<11) | (1<<13));
2750
2751 /* request queue base high */
2752 ATA_OUTL(ctlr->r_res1, 0x02010 + ATA_MV_EDMA_BASE(ch), work >> 32);
2753
2754 /* request queue in ptr */
2755 ATA_OUTL(ctlr->r_res1, 0x02014 + ATA_MV_EDMA_BASE(ch), work & 0xffffffff);
2756
2757 /* request queue out ptr */
2758 ATA_OUTL(ctlr->r_res1, 0x02018 + ATA_MV_EDMA_BASE(ch), 0x0);
2759
2760 /* response queue base high */
2761 work += 1024;
2762 ATA_OUTL(ctlr->r_res1, 0x0201c + ATA_MV_EDMA_BASE(ch), work >> 32);
2763
2764 /* response queue in ptr */
2765 ATA_OUTL(ctlr->r_res1, 0x02020 + ATA_MV_EDMA_BASE(ch), 0x0);
2766
2767 /* response queue out ptr */
2768 ATA_OUTL(ctlr->r_res1, 0x02024 + ATA_MV_EDMA_BASE(ch), work & 0xffffffff);
2769
2770 /* clear SATA error register */
2771 ATA_IDX_OUTL(ch, ATA_SERROR, ATA_IDX_INL(ch, ATA_SERROR));
2772
2773 /* clear any outstanding error interrupts */
2774 ATA_OUTL(ctlr->r_res1, 0x02008 + ATA_MV_EDMA_BASE(ch), 0x0);
2775
2776 /* unmask all error interrupts */
2777 ATA_OUTL(ctlr->r_res1, 0x0200c + ATA_MV_EDMA_BASE(ch), ~0x0);
2778
2779 /* enable EDMA machinery */
2780 ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000001);
2781 return 0;
2782 }
2783
2784 static int
2785 ata_marvell_edma_status(device_t dev)
2786 {
2787 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
2788 struct ata_channel *ch = device_get_softc(dev);
2789 u_int32_t cause = ATA_INL(ctlr->r_res1, 0x01d60);
2790 int shift = (ch->unit << 1) + (ch->unit > 3);
2791
2792 if (cause & (1 << shift)) {
2793
2794 /* clear interrupt(s) */
2795 ATA_OUTL(ctlr->r_res1, 0x02008 + ATA_MV_EDMA_BASE(ch), 0x0);
2796
2797 /* do we have any PHY events ? */
2798 ata_sata_phy_check_events(dev);
2799 }
2800
2801 /* do we have any device action ? */
2802 return (cause & (2 << shift));
2803 }
2804
2805 /* must be called with ATA channel locked and state_mtx held */
2806 static int
2807 ata_marvell_edma_begin_transaction(struct ata_request *request)
2808 {
2809 struct ata_pci_controller *ctlr=device_get_softc(GRANDPARENT(request->dev));
2810 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev));
2811 u_int32_t req_in;
2812 u_int8_t *bytep;
2813 u_int16_t *wordp;
2814 u_int32_t *quadp;
2815 int i, tag = 0x07;
2816 int dummy, error, slot;
2817
2818 /* only DMA R/W goes through the EMDA machine */
2819 if (request->u.ata.command != ATA_READ_DMA &&
2820 request->u.ata.command != ATA_WRITE_DMA) {
2821
2822 /* disable the EDMA machinery */
2823 if (ATA_INL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch)) & 0x00000001)
2824 ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000002);
2825 return ata_begin_transaction(request);
2826 }
2827
2828 /* check for 48 bit access and convert if needed */
2829 ata_modify_if_48bit(request);
2830
2831 /* check sanity, setup SG list and DMA engine */
2832 if ((error = ch->dma->load(ch->dev, request->data, request->bytecount,
2833 request->flags & ATA_R_READ, ch->dma->sg,
2834 &dummy))) {
2835 device_printf(request->dev, "setting up DMA failed\n");
2836 request->result = error;
2837 return ATA_OP_FINISHED;
2838 }
2839
2840 /* get next free request queue slot */
2841 req_in = ATA_INL(ctlr->r_res1, 0x02014 + ATA_MV_EDMA_BASE(ch));
2842 slot = (((req_in & ~0xfffffc00) >> 5) + 0) & 0x1f;
2843 bytep = (u_int8_t *)(ch->dma->work);
2844 bytep += (slot << 5);
2845 wordp = (u_int16_t *)bytep;
2846 quadp = (u_int32_t *)bytep;
2847
2848 /* fill in this request */
2849 quadp[0] = (long)ch->dma->sg_bus & 0xffffffff;
2850 quadp[1] = (u_int64_t)ch->dma->sg_bus >> 32;
2851 wordp[4] = (request->flags & ATA_R_READ ? 0x01 : 0x00) | (tag<<1);
2852
2853 i = 10;
2854 bytep[i++] = (request->u.ata.count >> 8) & 0xff;
2855 bytep[i++] = 0x10 | ATA_COUNT;
2856 bytep[i++] = request->u.ata.count & 0xff;
2857 bytep[i++] = 0x10 | ATA_COUNT;
2858
2859 bytep[i++] = (request->u.ata.lba >> 24) & 0xff;
2860 bytep[i++] = 0x10 | ATA_SECTOR;
2861 bytep[i++] = request->u.ata.lba & 0xff;
2862 bytep[i++] = 0x10 | ATA_SECTOR;
2863
2864 bytep[i++] = (request->u.ata.lba >> 32) & 0xff;
2865 bytep[i++] = 0x10 | ATA_CYL_LSB;
2866 bytep[i++] = (request->u.ata.lba >> 8) & 0xff;
2867 bytep[i++] = 0x10 | ATA_CYL_LSB;
2868
2869 bytep[i++] = (request->u.ata.lba >> 40) & 0xff;
2870 bytep[i++] = 0x10 | ATA_CYL_MSB;
2871 bytep[i++] = (request->u.ata.lba >> 16) & 0xff;
2872 bytep[i++] = 0x10 | ATA_CYL_MSB;
2873
2874 bytep[i++] = ATA_D_LBA | ATA_D_IBM | ((request->u.ata.lba >> 24) & 0xf);
2875 bytep[i++] = 0x10 | ATA_DRIVE;
2876
2877 bytep[i++] = request->u.ata.command;
2878 bytep[i++] = 0x90 | ATA_COMMAND;
2879
2880 /* enable EDMA machinery if needed */
2881 if (!(ATA_INL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch)) & 0x00000001)) {
2882 ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000001);
2883 while (!(ATA_INL(ctlr->r_res1,
2884 0x02028 + ATA_MV_EDMA_BASE(ch)) & 0x00000001))
2885 DELAY(10);
2886 }
2887
2888 /* tell EDMA it has a new request */
2889 slot = (((req_in & ~0xfffffc00) >> 5) + 1) & 0x1f;
2890 req_in &= 0xfffffc00;
2891 req_in += (slot << 5);
2892 ATA_OUTL(ctlr->r_res1, 0x02014 + ATA_MV_EDMA_BASE(ch), req_in);
2893
2894 return ATA_OP_CONTINUES;
2895 }
2896
2897 /* must be called with ATA channel locked and state_mtx held */
2898 static int
2899 ata_marvell_edma_end_transaction(struct ata_request *request)
2900 {
2901 struct ata_pci_controller *ctlr=device_get_softc(GRANDPARENT(request->dev));
2902 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev));
2903 int offset = (ch->unit > 3 ? 0x30014 : 0x20014);
2904 u_int32_t icr = ATA_INL(ctlr->r_res1, offset);
2905 int res;
2906
2907 /* EDMA interrupt */
2908 if ((icr & (0x0001 << (ch->unit & 3)))) {
2909 struct ata_marvell_response *response;
2910 u_int32_t rsp_in, rsp_out;
2911 int slot;
2912
2913 /* stop timeout */
2914 callout_stop(&request->callout);
2915
2916 /* get response ptr's */
2917 rsp_in = ATA_INL(ctlr->r_res1, 0x02020 + ATA_MV_EDMA_BASE(ch));
2918 rsp_out = ATA_INL(ctlr->r_res1, 0x02024 + ATA_MV_EDMA_BASE(ch));
2919 slot = (((rsp_in & ~0xffffff00) >> 3)) & 0x1f;
2920 rsp_out &= 0xffffff00;
2921 rsp_out += (slot << 3);
2922 response = (struct ata_marvell_response *)
2923 (ch->dma->work + 1024 + (slot << 3));
2924
2925 /* record status for this request */
2926 request->status = response->dev_status;
2927 request->error = 0;
2928
2929 /* ack response */
2930 ATA_OUTL(ctlr->r_res1, 0x02024 + ATA_MV_EDMA_BASE(ch), rsp_out);
2931
2932 /* update progress */
2933 if (!(request->status & ATA_S_ERROR) &&
2934 !(request->flags & ATA_R_TIMEOUT))
2935 request->donecount = request->bytecount;
2936
2937 /* unload SG list */
2938 ch->dma->unload(ch->dev);
2939
2940 res = ATA_OP_FINISHED;
2941 }
2942
2943 /* legacy ATA interrupt */
2944 else {
2945 res = ata_end_transaction(request);
2946 }
2947
2948 /* ack interrupt */
2949 ATA_OUTL(ctlr->r_res1, offset, ~(icr & (0x0101 << (ch->unit & 3))));
2950 return res;
2951 }
2952
2953 static void
2954 ata_marvell_edma_reset(device_t dev)
2955 {
2956 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
2957 struct ata_channel *ch = device_get_softc(dev);
2958
2959 /* disable the EDMA machinery */
2960 ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000002);
2961 while ((ATA_INL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch)) & 0x00000001))
2962 DELAY(10);
2963
2964 /* clear SATA error register */
2965 ATA_IDX_OUTL(ch, ATA_SERROR, ATA_IDX_INL(ch, ATA_SERROR));
2966
2967 /* clear any outstanding error interrupts */
2968 ATA_OUTL(ctlr->r_res1, 0x02008 + ATA_MV_EDMA_BASE(ch), 0x0);
2969
2970 /* unmask all error interrupts */
2971 ATA_OUTL(ctlr->r_res1, 0x0200c + ATA_MV_EDMA_BASE(ch), ~0x0);
2972
2973 /* enable channel and test for devices */
2974 if (ata_sata_phy_reset(dev))
2975 ata_generic_reset(dev);
2976
2977 /* enable EDMA machinery */
2978 ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000001);
2979 }
2980
2981 static void
2982 ata_marvell_edma_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs,
2983 int error)
2984 {
2985 struct ata_dmasetprd_args *args = xsc;
2986 struct ata_marvell_dma_prdentry *prd = args->dmatab;
2987 int i;
2988
2989 if ((args->error = error))
2990 return;
2991
2992 for (i = 0; i < nsegs; i++) {
2993 prd[i].addrlo = htole32(segs[i].ds_addr);
2994 prd[i].count = htole32(segs[i].ds_len);
2995 prd[i].addrhi = htole32((u_int64_t)segs[i].ds_addr >> 32);
2996 }
2997 prd[i - 1].count |= htole32(ATA_DMA_EOT);
2998 }
2999
3000 static void
3001 ata_marvell_edma_dmainit(device_t dev)
3002 {
3003 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
3004 struct ata_channel *ch = device_get_softc(dev);
3005
3006 ata_dmainit(dev);
3007 if (ch->dma) {
3008 /* note start and stop are not used here */
3009 ch->dma->setprd = ata_marvell_edma_dmasetprd;
3010
3011 if (ATA_INL(ctlr->r_res1, 0x00d00) & 0x00000004)
3012 ch->dma->max_address = BUS_SPACE_MAXADDR;
3013
3014 /* chip does not reliably do 64K DMA transfers */
3015 ch->dma->max_iosize = 126 * DEV_BSIZE;
3016 }
3017 }
3018
3019
3020 /*
3021 * National chipset support functions
3022 */
3023 int
3024 ata_national_ident(device_t dev)
3025 {
3026 struct ata_pci_controller *ctlr = device_get_softc(dev);
3027
3028 /* this chip is a clone of the Cyrix chip, bugs and all */
3029 if (pci_get_devid(dev) == ATA_SC1100) {
3030 device_set_desc(dev, "National Geode SC1100 ATA33 controller");
3031 ctlr->chipinit = ata_national_chipinit;
3032 return 0;
3033 }
3034 return ENXIO;
3035 }
3036
3037 static int
3038 ata_national_chipinit(device_t dev)
3039 {
3040 struct ata_pci_controller *ctlr = device_get_softc(dev);
3041
3042 if (ata_setup_interrupt(dev))
3043 return ENXIO;
3044
3045 ctlr->setmode = ata_national_setmode;
3046 return 0;
3047 }
3048
3049 static void
3050 ata_national_setmode(device_t dev, int mode)
3051 {
3052 device_t gparent = GRANDPARENT(dev);
3053 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
3054 struct ata_device *atadev = device_get_softc(dev);
3055 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
3056 u_int32_t piotiming[] =
3057 { 0x9172d132, 0x21717121, 0x00803020, 0x20102010, 0x00100010,
3058 0x00803020, 0x20102010, 0x00100010,
3059 0x00100010, 0x00100010, 0x00100010 };
3060 u_int32_t dmatiming[] = { 0x80077771, 0x80012121, 0x80002020 };
3061 u_int32_t udmatiming[] = { 0x80921250, 0x80911140, 0x80911030 };
3062 int error;
3063
3064 ch->dma->alignment = 16;
3065 ch->dma->max_iosize = 126 * DEV_BSIZE;
3066
3067 mode = ata_limit_mode(dev, mode, ATA_UDMA2);
3068
3069 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
3070
3071 if (bootverbose)
3072 device_printf(dev, "%s setting %s on National chip\n",
3073 (error) ? "failed" : "success", ata_mode2str(mode));
3074 if (!error) {
3075 if (mode >= ATA_UDMA0) {
3076 pci_write_config(gparent, 0x44 + (devno << 3),
3077 udmatiming[mode & ATA_MODE_MASK], 4);
3078 }
3079 else if (mode >= ATA_WDMA0) {
3080 pci_write_config(gparent, 0x44 + (devno << 3),
3081 dmatiming[mode & ATA_MODE_MASK], 4);
3082 }
3083 else {
3084 pci_write_config(gparent, 0x44 + (devno << 3),
3085 pci_read_config(gparent, 0x44 + (devno << 3), 4) |
3086 0x80000000, 4);
3087 }
3088 pci_write_config(gparent, 0x40 + (devno << 3),
3089 piotiming[ata_mode2idx(mode)], 4);
3090 atadev->mode = mode;
3091 }
3092 }
3093
3094 /*
3095 * NetCell chipset support functions
3096 */
3097 int
3098 ata_netcell_ident(device_t dev)
3099 {
3100 struct ata_pci_controller *ctlr = device_get_softc(dev);
3101
3102 if (pci_get_devid(dev) == ATA_NETCELL_SR) {
3103 device_set_desc(dev, "Netcell SyncRAID SR3000/5000 RAID Controller");
3104 ctlr->chipinit = ata_netcell_chipinit;
3105 return 0;
3106 }
3107 return ENXIO;
3108 }
3109
3110 static int
3111 ata_netcell_chipinit(device_t dev)
3112 {
3113 struct ata_pci_controller *ctlr = device_get_softc(dev);
3114
3115 if (ata_generic_chipinit(dev))
3116 return ENXIO;
3117
3118 ctlr->allocate = ata_netcell_allocate;
3119 return 0;
3120 }
3121
3122 static int
3123 ata_netcell_allocate(device_t dev)
3124 {
3125 struct ata_channel *ch = device_get_softc(dev);
3126
3127 /* setup the usual register normal pci style */
3128 if (ata_pci_allocate(dev))
3129 return ENXIO;
3130
3131 /* the NetCell only supports 16 bit PIO transfers */
3132 ch->flags |= ATA_USE_16BIT;
3133
3134 return 0;
3135 }
3136
3137
3138 /*
3139 * nVidia chipset support functions
3140 */
3141 int
3142 ata_nvidia_ident(device_t dev)
3143 {
3144 struct ata_pci_controller *ctlr = device_get_softc(dev);
3145 struct ata_chip_id *idx;
3146 static struct ata_chip_id ids[] =
3147 {{ ATA_NFORCE1, 0, AMDNVIDIA, NVIDIA, ATA_UDMA5, "nForce" },
3148 { ATA_NFORCE2, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce2" },
3149 { ATA_NFORCE2_PRO, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce2 Pro" },
3150 { ATA_NFORCE2_PRO_S1, 0, 0, 0, ATA_SA150, "nForce2 Pro" },
3151 { ATA_NFORCE3, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce3" },
3152 { ATA_NFORCE3_PRO, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce3 Pro" },
3153 { ATA_NFORCE3_PRO_S1, 0, 0, 0, ATA_SA150, "nForce3 Pro" },
3154 { ATA_NFORCE3_PRO_S2, 0, 0, 0, ATA_SA150, "nForce3 Pro" },
3155 { ATA_NFORCE_MCP04, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce MCP" },
3156 { ATA_NFORCE_MCP04_S1, 0, 0, NV4, ATA_SA150, "nForce MCP" },
3157 { ATA_NFORCE_MCP04_S2, 0, 0, NV4, ATA_SA150, "nForce MCP" },
3158 { ATA_NFORCE_CK804, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce CK804" },
3159 { ATA_NFORCE_CK804_S1, 0, 0, NV4, ATA_SA300, "nForce CK804" },
3160 { ATA_NFORCE_CK804_S2, 0, 0, NV4, ATA_SA300, "nForce CK804" },
3161 { ATA_NFORCE_MCP51, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce MCP51" },
3162 { ATA_NFORCE_MCP51_S1, 0, 0, NV4|NVQ, ATA_SA300, "nForce MCP51" },
3163 { ATA_NFORCE_MCP51_S2, 0, 0, NV4|NVQ, ATA_SA300, "nForce MCP51" },
3164 { ATA_NFORCE_MCP55, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce MCP55" },
3165 { ATA_NFORCE_MCP55_S1, 0, 0, NV4|NVQ, ATA_SA300, "nForce MCP55" },
3166 { ATA_NFORCE_MCP55_S2, 0, 0, NV4|NVQ, ATA_SA300, "nForce MCP55" },
3167 { ATA_NFORCE_MCP61, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce MCP61" },
3168 { ATA_NFORCE_MCP61_S1, 0, 0, NV4|NVQ, ATA_SA300, "nForce MCP61" },
3169 { ATA_NFORCE_MCP61_S2, 0, 0, NV4|NVQ, ATA_SA300, "nForce MCP61" },
3170 { ATA_NFORCE_MCP61_S3, 0, 0, NV4|NVQ, ATA_SA300, "nForce MCP61" },
3171 { ATA_NFORCE_MCP65, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce MCP65" },
3172 { ATA_NFORCE_MCP67, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce MCP67" },
3173 { ATA_NFORCE_MCP67_S2, 0, 0, NV4|NVQ, ATA_SA300, "nForce MCP67" },
3174 { ATA_NFORCE_MCP73, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce MCP73" },
3175 { ATA_NFORCE_MCP77, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce MCP77" },
3176 { 0, 0, 0, 0, 0, 0}} ;
3177 char buffer[64] ;
3178
3179 if (!(idx = ata_match_chip(dev, ids)))
3180 return ENXIO;
3181
3182 ksprintf(buffer, "nVidia %s %s controller",
3183 idx->text, ata_mode2str(idx->max_dma));
3184 device_set_desc_copy(dev, buffer);
3185 ctlr->chip = idx;
3186 ctlr->chipinit = ata_nvidia_chipinit;
3187 return 0;
3188 }
3189
3190 static int
3191 ata_nvidia_chipinit(device_t dev)
3192 {
3193 struct ata_pci_controller *ctlr = device_get_softc(dev);
3194
3195 if (ata_setup_interrupt(dev))
3196 return ENXIO;
3197
3198 if (ctlr->chip->max_dma >= ATA_SA150) {
3199 if (pci_read_config(dev, PCIR_BAR(5), 1) & 1)
3200 ctlr->r_type2 = SYS_RES_IOPORT;
3201 else
3202 ctlr->r_type2 = SYS_RES_MEMORY;
3203 ctlr->r_rid2 = PCIR_BAR(5);
3204 if ((ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
3205 &ctlr->r_rid2, RF_ACTIVE))) {
3206 int offset = ctlr->chip->cfg2 & NV4 ? 0x0440 : 0x0010;
3207
3208 ctlr->allocate = ata_nvidia_allocate;
3209 ctlr->reset = ata_nvidia_reset;
3210
3211 /* enable control access */
3212 pci_write_config(dev, 0x50, pci_read_config(dev, 0x50, 1) | 0x04,1);
3213
3214 if (ctlr->chip->cfg2 & NVQ) {
3215 /* clear interrupt status */
3216 ATA_OUTL(ctlr->r_res2, offset, 0x00ff00ff);
3217
3218 /* enable device and PHY state change interrupts */
3219 ATA_OUTL(ctlr->r_res2, offset + 4, 0x000d000d);
3220
3221 /* disable NCQ support */
3222 ATA_OUTL(ctlr->r_res2, 0x0400,
3223 ATA_INL(ctlr->r_res2, 0x0400) & 0xfffffff9);
3224 }
3225 else {
3226 /* clear interrupt status */
3227 ATA_OUTB(ctlr->r_res2, offset, 0xff);
3228
3229 /* enable device and PHY state change interrupts */
3230 ATA_OUTB(ctlr->r_res2, offset + 1, 0xdd);
3231 }
3232
3233 /* enable PCI interrupt */
3234 pci_write_config(dev, PCIR_COMMAND,
3235 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400,2);
3236
3237 }
3238 ctlr->setmode = ata_sata_setmode;
3239 }
3240 else {
3241 /* disable prefetch, postwrite */
3242 pci_write_config(dev, 0x51, pci_read_config(dev, 0x51, 1) & 0x0f, 1);
3243 ctlr->setmode = ata_via_family_setmode;
3244 }
3245 return 0;
3246 }
3247
3248 static int
3249 ata_nvidia_allocate(device_t dev)
3250 {
3251 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
3252 struct ata_channel *ch = device_get_softc(dev);
3253
3254 /* setup the usual register normal pci style */
3255 if (ata_pci_allocate(dev))
3256 return ENXIO;
3257
3258 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2;
3259 ch->r_io[ATA_SSTATUS].offset = (ch->unit << 6);
3260 ch->r_io[ATA_SERROR].res = ctlr->r_res2;
3261 ch->r_io[ATA_SERROR].offset = 0x04 + (ch->unit << 6);
3262 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2;
3263 ch->r_io[ATA_SCONTROL].offset = 0x08 + (ch->unit << 6);
3264
3265 ch->hw.status = ata_nvidia_status;
3266 ch->flags |= ATA_NO_SLAVE;
3267
3268 return 0;
3269 }
3270
3271 static int
3272 ata_nvidia_status(device_t dev)
3273 {
3274 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
3275 struct ata_channel *ch = device_get_softc(dev);
3276 int offset = ctlr->chip->cfg2 & NV4 ? 0x0440 : 0x0010;
3277 int shift = ch->unit << (ctlr->chip->cfg2 & NVQ ? 4 : 2);
3278 u_int32_t istatus;
3279
3280 /* get interrupt status */
3281 if (ctlr->chip->cfg2 & NVQ)
3282 istatus = ATA_INL(ctlr->r_res2, offset);
3283 else
3284 istatus = ATA_INB(ctlr->r_res2, offset);
3285
3286 /* do we have any PHY events ? */
3287 if (istatus & (0x0c << shift))
3288 ata_sata_phy_check_events(dev);
3289
3290 /* clear interrupt(s) */
3291 if (ctlr->chip->cfg2 & NVQ)
3292 ATA_OUTL(ctlr->r_res2, offset, (0x0f << shift) | 0x00f000f0);
3293 else
3294 ATA_OUTB(ctlr->r_res2, offset, (0x0f << shift));
3295
3296 /* do we have any device action ? */
3297 return (istatus & (0x01 << shift));
3298 }
3299
3300 static void
3301 ata_nvidia_reset(device_t dev)
3302 {
3303 if (ata_sata_phy_reset(dev))
3304 ata_generic_reset(dev);
3305 }
3306
3307
3308 /*
3309 * Promise chipset support functions
3310 */
3311 #define ATA_PDC_APKT_OFFSET 0x00000010
3312 #define ATA_PDC_HPKT_OFFSET 0x00000040
3313 #define ATA_PDC_ASG_OFFSET 0x00000080
3314 #define ATA_PDC_LSG_OFFSET 0x000000c0
3315 #define ATA_PDC_HSG_OFFSET 0x00000100
3316 #define ATA_PDC_CHN_OFFSET 0x00000400
3317 #define ATA_PDC_BUF_BASE 0x00400000
3318 #define ATA_PDC_BUF_OFFSET 0x00100000
3319 #define ATA_PDC_MAX_HPKT 8
3320 #define ATA_PDC_WRITE_REG 0x00
3321 #define ATA_PDC_WRITE_CTL 0x0e
3322 #define ATA_PDC_WRITE_END 0x08
3323 #define ATA_PDC_WAIT_NBUSY 0x10
3324 #define ATA_PDC_WAIT_READY 0x18
3325 #define ATA_PDC_1B 0x20
3326 #define ATA_PDC_2B 0x40
3327
3328 struct host_packet {
3329 u_int32_t addr;
3330 TAILQ_ENTRY(host_packet) chain;
3331 };
3332
3333 struct ata_promise_sx4 {
3334 struct spinlock mtx;
3335 TAILQ_HEAD(, host_packet) queue;
3336 int busy;
3337 };
3338
3339 int
3340 ata_promise_ident(device_t dev)
3341 {
3342 struct ata_pci_controller *ctlr = device_get_softc(dev);
3343 struct ata_chip_id *idx;
3344 static struct ata_chip_id ids[] =
3345 {{ ATA_PDC20246, 0, PROLD, 0x00, ATA_UDMA2, "PDC20246" },
3346 { ATA_PDC20262, 0, PRNEW, 0x00, ATA_UDMA4, "PDC20262" },
3347 { ATA_PDC20263, 0, PRNEW, 0x00, ATA_UDMA4, "PDC20263" },
3348 { ATA_PDC20265, 0, PRNEW, 0x00, ATA_UDMA5, "PDC20265" },
3349 { ATA_PDC20267, 0, PRNEW, 0x00, ATA_UDMA5, "PDC20267" },
3350 { ATA_PDC20268, 0, PRTX, PRTX4, ATA_UDMA5, "PDC20268" },
3351 { ATA_PDC20269, 0, PRTX, 0x00, ATA_UDMA6, "PDC20269" },
3352 { ATA_PDC20270, 0, PRTX, PRTX4, ATA_UDMA5, "PDC20270" },
3353 { ATA_PDC20271, 0, PRTX, 0x00, ATA_UDMA6, "PDC20271" },
3354 { ATA_PDC20275, 0, PRTX, 0x00, ATA_UDMA6, "PDC20275" },
3355 { ATA_PDC20276, 0, PRTX, PRSX6K, ATA_UDMA6, "PDC20276" },
3356 { ATA_PDC20277, 0, PRTX, 0x00, ATA_UDMA6, "PDC20277" },
3357 { ATA_PDC20318, 0, PRMIO, PRSATA, ATA_SA150, "PDC20318" },
3358 { ATA_PDC20319, 0, PRMIO, PRSATA, ATA_SA150, "PDC20319" },
3359 { ATA_PDC20371, 0, PRMIO, PRCMBO, ATA_SA150, "PDC20371" },
3360 { ATA_PDC20375, 0, PRMIO, PRCMBO, ATA_SA150, "PDC20375" },
3361 { ATA_PDC20376, 0, PRMIO, PRCMBO, ATA_SA150, "PDC20376" },
3362 { ATA_PDC20377, 0, PRMIO, PRCMBO, ATA_SA150, "PDC20377" },
3363 { ATA_PDC20378, 0, PRMIO, PRCMBO, ATA_SA150, "PDC20378" },
3364 { ATA_PDC20379, 0, PRMIO, PRCMBO, ATA_SA150, "PDC20379" },
3365 { ATA_PDC20571, 0, PRMIO, PRCMBO2, ATA_SA150, "PDC20571" },
3366 { ATA_PDC20575, 0, PRMIO, PRCMBO2, ATA_SA150, "PDC20575" },
3367 { ATA_PDC20579, 0, PRMIO, PRCMBO2, ATA_SA150, "PDC20579" },
3368 { ATA_PDC20771, 0, PRMIO, PRCMBO2, ATA_SA300, "PDC20771" },
3369 { ATA_PDC40775, 0, PRMIO, PRCMBO2, ATA_SA300, "PDC40775" },
3370 { ATA_PDC20617, 0, PRMIO, PRPATA, ATA_UDMA6, "PDC20617" },
3371 { ATA_PDC20618, 0, PRMIO, PRPATA, ATA_UDMA6, "PDC20618" },
3372 { ATA_PDC20619, 0, PRMIO, PRPATA, ATA_UDMA6, "PDC20619" },
3373 { ATA_PDC20620, 0, PRMIO, PRPATA, ATA_UDMA6, "PDC20620" },
3374 { ATA_PDC20621, 0, PRMIO, PRSX4X, ATA_UDMA5, "PDC20621" },
3375 { ATA_PDC20622, 0, PRMIO, PRSX4X, ATA_SA150, "PDC20622" },
3376 { ATA_PDC40518, 0, PRMIO, PRSATA2, ATA_SA150, "PDC40518" },
3377 { ATA_PDC40519, 0, PRMIO, PRSATA2, ATA_SA150, "PDC40519" },
3378 { ATA_PDC40718, 0, PRMIO, PRSATA2, ATA_SA300, "PDC40718" },
3379 { ATA_PDC40719, 0, PRMIO, PRSATA2, ATA_SA300, "PDC40719" },
3380 { ATA_PDC40779, 0, PRMIO, PRSATA2, ATA_SA300, "PDC40779" },
3381 { 0, 0, 0, 0, 0, 0}};
3382 char buffer[64];
3383 uintptr_t devid = 0;
3384
3385 if (!(idx = ata_match_chip(dev, ids)))
3386 return ENXIO;
3387
3388 /* if we are on a SuperTrak SX6000 dont attach */
3389 if ((idx->cfg2 & PRSX6K) && pci_get_class(GRANDPARENT(dev))==PCIC_BRIDGE &&
3390 !BUS_READ_IVAR(device_get_parent(GRANDPARENT(dev)),
3391 GRANDPARENT(dev), PCI_IVAR_DEVID, &devid) &&
3392 devid == ATA_I960RM)
3393 return ENXIO;
3394
3395 strcpy(buffer, "Promise ");
3396 strcat(buffer, idx->text);
3397
3398 /* if we are on a FastTrak TX4, adjust the interrupt resource */
3399 if ((idx->cfg2 & PRTX4) && pci_get_class(GRANDPARENT(dev))==PCIC_BRIDGE &&
3400 !BUS_READ_IVAR(device_get_parent(GRANDPARENT(dev)),
3401 GRANDPARENT(dev), PCI_IVAR_DEVID, &devid) &&
3402 ((devid == ATA_DEC_21150) || (devid == ATA_DEC_21150_1))) {
3403 static long start = 0, end = 0;
3404
3405 if (pci_get_slot(dev) == 1) {
3406 bus_get_resource(dev, SYS_RES_IRQ, 0, &start, &end);
3407 strcat(buffer, " (channel 0+1)");
3408 }
3409 else if (pci_get_slot(dev) == 2 && start && end) {
3410 bus_set_resource(dev, SYS_RES_IRQ, 0, start, end);
3411 strcat(buffer, " (channel 2+3)");
3412 }
3413 else {
3414 start = end = 0;
3415 }
3416 }
3417 ksprintf(buffer, "%s %s controller", buffer, ata_mode2str(idx->max_dma));
3418 device_set_desc_copy(dev, buffer);
3419 ctlr->chip = idx;
3420 ctlr->chipinit = ata_promise_chipinit;
3421 return 0;
3422 }
3423
3424 static int
3425 ata_promise_chipinit(device_t dev)
3426 {
3427 struct ata_pci_controller *ctlr = device_get_softc(dev);
3428 int fake_reg, stat_reg;
3429
3430 if (ata_setup_interrupt(dev))
3431 return ENXIO;
3432
3433 switch (ctlr->chip->cfg1) {
3434 case PRNEW:
3435 /* setup clocks */
3436 ATA_OUTB(ctlr->r_res1, 0x11, ATA_INB(ctlr->r_res1, 0x11) | 0x0a);
3437
3438 ctlr->dmainit = ata_promise_dmainit;
3439 /* FALLTHROUGH */
3440
3441 case PROLD:
3442 /* enable burst mode */
3443 ATA_OUTB(ctlr->r_res1, 0x1f, ATA_INB(ctlr->r_res1, 0x1f) | 0x01);
3444 ctlr->allocate = ata_promise_allocate;
3445 ctlr->setmode = ata_promise_setmode;
3446 return 0;
3447
3448 case PRTX:
3449 ctlr->allocate = ata_promise_tx2_allocate;
3450 ctlr->setmode = ata_promise_setmode;
3451 return 0;
3452
3453 case PRMIO:
3454 ctlr->r_type1 = SYS_RES_MEMORY;
3455 ctlr->r_rid1 = PCIR_BAR(4);
3456 if (!(ctlr->r_res1 = bus_alloc_resource_any(dev, ctlr->r_type1,
3457 &ctlr->r_rid1, RF_ACTIVE)))
3458 goto failnfree;
3459
3460 ctlr->r_type2 = SYS_RES_MEMORY;
3461 ctlr->r_rid2 = PCIR_BAR(3);
3462 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
3463 &ctlr->r_rid2, RF_ACTIVE)))
3464 goto failnfree;
3465
3466 if (ctlr->chip->cfg2 == PRSX4X) {
3467 struct ata_promise_sx4 *hpkt;
3468 u_int32_t dimm = ATA_INL(ctlr->r_res2, 0x000c0080);
3469
3470 if (bus_teardown_intr(dev, ctlr->r_irq, ctlr->handle) ||
3471 bus_setup_intr(dev, ctlr->r_irq, ATA_INTR_FLAGS,
3472 ata_promise_sx4_intr, ctlr, &ctlr->handle, NULL)) {
3473 device_printf(dev, "unable to setup interrupt\n");
3474 goto failnfree;
3475 }
3476
3477 /* print info about cache memory */
3478 device_printf(dev, "DIMM size %dMB @ 0x%08x%s\n",
3479 (((dimm >> 16) & 0xff)-((dimm >> 24) & 0xff)+1) << 4,
3480 ((dimm >> 24) & 0xff),
3481 ATA_INL(ctlr->r_res2, 0x000c0088) & (1<<16) ?
3482 " ECC enabled" : "" );
3483
3484 /* adjust cache memory parameters */
3485 ATA_OUTL(ctlr->r_res2, 0x000c000c,
3486 (ATA_INL(ctlr->r_res2, 0x000c000c) & 0xffff0000));
3487
3488 /* setup host packet controls */
3489 hpkt = kmalloc(sizeof(struct ata_promise_sx4),
3490 M_TEMP, M_INTWAIT | M_ZERO);
3491 spin_init(&hpkt->mtx);
3492 TAILQ_INIT(&hpkt->queue);
3493 hpkt->busy = 0;
3494 device_set_ivars(dev, hpkt);
3495 ctlr->allocate = ata_promise_mio_allocate;
3496 ctlr->reset = ata_promise_mio_reset;
3497 ctlr->dmainit = ata_promise_mio_dmainit;
3498 ctlr->setmode = ata_promise_setmode;
3499 ctlr->channels = 4;
3500 return 0;
3501 }
3502
3503 /* mio type controllers need an interrupt intercept */
3504 if (bus_teardown_intr(dev, ctlr->r_irq, ctlr->handle) ||
3505 bus_setup_intr(dev, ctlr->r_irq, ATA_INTR_FLAGS,
3506 ata_promise_mio_intr, ctlr, &ctlr->handle, NULL)) {
3507 device_printf(dev, "unable to setup interrupt\n");
3508 goto failnfree;
3509 }
3510
3511 switch (ctlr->chip->cfg2) {
3512 case PRPATA:
3513 ctlr->channels = ((ATA_INL(ctlr->r_res2, 0x48) & 0x01) > 0) +
3514 ((ATA_INL(ctlr->r_res2, 0x48) & 0x02) > 0) + 2;
3515 goto sata150;
3516 case PRCMBO:
3517 ctlr->channels = 3;
3518 goto sata150;
3519 case PRSATA:
3520 ctlr->channels = 4;
3521 sata150:
3522 fake_reg = 0x60;
3523 stat_reg = 0x6c;
3524 break;
3525
3526 case PRCMBO2:
3527 ctlr->channels = 3;
3528 goto sataii;
3529 case PRSATA2:
3530 default:
3531 ctlr->channels = 4;
3532 sataii:
3533 fake_reg = 0x54;
3534 stat_reg = 0x60;
3535 break;
3536 }
3537
3538 /* prime fake interrupt register */
3539 ATA_OUTL(ctlr->r_res2, fake_reg, 0xffffffff);
3540
3541 /* clear SATA status */
3542 ATA_OUTL(ctlr->r_res2, stat_reg, 0x000000ff);
3543
3544 ctlr->allocate = ata_promise_mio_allocate;
3545 ctlr->reset = ata_promise_mio_reset;
3546 ctlr->dmainit = ata_promise_mio_dmainit;
3547 ctlr->setmode = ata_promise_mio_setmode;
3548
3549 return 0;
3550 }
3551
3552 failnfree:
3553 if (ctlr->r_res2)
3554 bus_release_resource(dev, ctlr->r_type2, ctlr->r_rid2, ctlr->r_res2);
3555 if (ctlr->r_res1)
3556 bus_release_resource(dev, ctlr->r_type1, ctlr->r_rid1, ctlr->r_res1);
3557 return ENXIO;
3558 }
3559
3560 static int
3561 ata_promise_allocate(device_t dev)
3562 {
3563 struct ata_channel *ch = device_get_softc(dev);
3564
3565 if (ata_pci_allocate(dev))
3566 return ENXIO;
3567
3568 ch->hw.status = ata_promise_status;
3569 return 0;
3570 }
3571
3572 static int
3573 ata_promise_status(device_t dev)
3574 {
3575 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
3576 struct ata_channel *ch = device_get_softc(dev);
3577
3578 if (ATA_INL(ctlr->r_res1, 0x1c) & (ch->unit ? 0x00004000 : 0x00000400)) {
3579 return ata_pci_status(dev);
3580 }
3581 return 0;
3582 }
3583
3584 static int
3585 ata_promise_dmastart(device_t dev)
3586 {
3587 struct ata_pci_controller *ctlr = device_get_softc(GRANDPARENT(dev));
3588 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
3589 struct ata_device *atadev = device_get_softc(dev);
3590
3591 if (atadev->flags & ATA_D_48BIT_ACTIVE) {
3592 ATA_OUTB(ctlr->r_res1, 0x11,
3593 ATA_INB(ctlr->r_res1, 0x11) | (ch->unit ? 0x08 : 0x02));
3594 ATA_OUTL(ctlr->r_res1, ch->unit ? 0x24 : 0x20,
3595 ((ch->dma->flags & ATA_DMA_READ) ? 0x05000000 : 0x06000000) |
3596 (ch->dma->cur_iosize >> 1));
3597 }
3598 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, (ATA_IDX_INB(ch, ATA_BMSTAT_PORT) |
3599 (ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR)));
3600 ATA_IDX_OUTL(ch, ATA_BMDTP_PORT, ch->dma->sg_bus);
3601 ATA_IDX_OUTB(ch, ATA_BMCMD_PORT,
3602 ((ch->dma->flags & ATA_DMA_READ) ? ATA_BMCMD_WRITE_READ : 0) |
3603 ATA_BMCMD_START_STOP);
3604 ch->flags |= ATA_DMA_ACTIVE;
3605 return 0;
3606 }
3607
3608 static int
3609 ata_promise_dmastop(device_t dev)
3610 {
3611 struct ata_pci_controller *ctlr = device_get_softc(GRANDPARENT(dev));
3612 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
3613 struct ata_device *atadev = device_get_softc(dev);
3614 int error;
3615
3616 if (atadev->flags & ATA_D_48BIT_ACTIVE) {
3617 ATA_OUTB(ctlr->r_res1, 0x11,
3618 ATA_INB(ctlr->r_res1, 0x11) & ~(ch->unit ? 0x08 : 0x02));
3619 ATA_OUTL(ctlr->r_res1, ch->unit ? 0x24 : 0x20, 0);
3620 }
3621 error = ATA_IDX_INB(ch, ATA_BMSTAT_PORT);
3622 ATA_IDX_OUTB(ch, ATA_BMCMD_PORT,
3623 ATA_IDX_INB(ch, ATA_BMCMD_PORT) & ~ATA_BMCMD_START_STOP);
3624 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR);
3625 ch->flags &= ~ATA_DMA_ACTIVE;
3626 return error;
3627 }
3628
3629 static void
3630 ata_promise_dmareset(device_t dev)
3631 {
3632 struct ata_channel *ch = device_get_softc(dev);
3633
3634 ATA_IDX_OUTB(ch, ATA_BMCMD_PORT,
3635 ATA_IDX_INB(ch, ATA_BMCMD_PORT) & ~ATA_BMCMD_START_STOP);
3636 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR);
3637 ch->flags &= ~ATA_DMA_ACTIVE;
3638 }
3639
3640 static void
3641 ata_promise_dmainit(device_t dev)
3642 {
3643 struct ata_channel *ch = device_get_softc(dev);
3644
3645 ata_dmainit(dev);
3646 if (ch->dma) {
3647 ch->dma->start = ata_promise_dmastart;
3648 ch->dma->stop = ata_promise_dmastop;
3649 ch->dma->reset = ata_promise_dmareset;
3650 }
3651 }
3652
3653 static void
3654 ata_promise_setmode(device_t dev, int mode)
3655 {
3656 device_t gparent = GRANDPARENT(dev);
3657 struct ata_pci_controller *ctlr = device_get_softc(gparent);
3658 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
3659 struct ata_device *atadev = device_get_softc(dev);
3660 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
3661 int error;
3662 u_int32_t timings[][2] = {
3663 /* PROLD PRNEW mode */
3664 { 0x004ff329, 0x004fff2f }, /* PIO 0 */
3665 { 0x004fec25, 0x004ff82a }, /* PIO 1 */
3666 { 0x004fe823, 0x004ff026 }, /* PIO 2 */
3667 { 0x004fe622, 0x004fec24 }, /* PIO 3 */
3668 { 0x004fe421, 0x004fe822 }, /* PIO 4 */
3669 { 0x004567f3, 0x004acef6 }, /* MWDMA 0 */
3670 { 0x004467f3, 0x0048cef6 }, /* MWDMA 1 */
3671 { 0x004367f3, 0x0046cef6 }, /* MWDMA 2 */
3672 { 0x004367f3, 0x0046cef6 }, /* UDMA 0 */
3673 { 0x004247f3, 0x00448ef6 }, /* UDMA 1 */
3674 { 0x004127f3, 0x00436ef6 }, /* UDMA 2 */
3675 { 0, 0x00424ef6 }, /* UDMA 3 */
3676 { 0, 0x004127f3 }, /* UDMA 4 */
3677 { 0, 0x004127f3 } /* UDMA 5 */
3678 };
3679
3680 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma);
3681
3682 switch (ctlr->chip->cfg1) {
3683 case PROLD:
3684 case PRNEW:
3685 if (mode > ATA_UDMA2 && (pci_read_config(gparent, 0x50, 2) &
3686 (ch->unit ? 1 << 11 : 1 << 10))) {
3687 ata_print_cable(dev, "controller");
3688 mode = ATA_UDMA2;
3689 }
3690 if (ata_atapi(dev) && mode > ATA_PIO_MAX)
3691 mode = ata_limit_mode(dev, mode, ATA_PIO_MAX);
3692 break;
3693
3694 case PRTX:
3695 ATA_IDX_OUTB(ch, ATA_BMDEVSPEC_0, 0x0b);
3696 if (mode > ATA_UDMA2 &&
3697 ATA_IDX_INB(ch, ATA_BMDEVSPEC_1) & 0x04) {
3698 ata_print_cable(dev, "controller");
3699 mode = ATA_UDMA2;
3700 }
3701 break;
3702
3703 case PRMIO:
3704 if (mode > ATA_UDMA2 &&
3705 (ATA_INL(ctlr->r_res2,
3706 (ctlr->chip->cfg2 & PRSX4X ? 0x000c0260 : 0x0260) +
3707 (ch->unit << 7)) & 0x01000000)) {
3708 ata_print_cable(dev, "controller");
3709 mode = ATA_UDMA2;
3710 }
3711 break;
3712 }
3713
3714 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
3715
3716 if (bootverbose)
3717 device_printf(dev, "%ssetting %s on %s chip\n",
3718 (error) ? "FAILURE " : "",
3719 ata_mode2str(mode), ctlr->chip->text);
3720 if (!error) {
3721 if (ctlr->chip->cfg1 < PRTX)
3722 pci_write_config(gparent, 0x60 + (devno << 2),
3723 timings[ata_mode2idx(mode)][ctlr->chip->cfg1], 4);
3724 atadev->mode = mode;
3725 }
3726 return;
3727 }
3728
3729 static int
3730 ata_promise_tx2_allocate(device_t dev)
3731 {
3732 struct ata_channel *ch = device_get_softc(dev);
3733
3734 if (ata_pci_allocate(dev))
3735 return ENXIO;
3736
3737 ch->hw.status = ata_promise_tx2_status;
3738 return 0;
3739 }
3740
3741 static int
3742 ata_promise_tx2_status(device_t dev)
3743 {
3744 struct ata_channel *ch = device_get_softc(dev);
3745
3746 ATA_IDX_OUTB(ch, ATA_BMDEVSPEC_0, 0x0b);
3747 if (ATA_IDX_INB(ch, ATA_BMDEVSPEC_1) & 0x20) {
3748 return ata_pci_status(dev);
3749 }
3750 return 0;
3751 }
3752
3753 static int
3754 ata_promise_mio_allocate(device_t dev)
3755 {
3756 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
3757 struct ata_channel *ch = device_get_softc(dev);
3758 int offset = (ctlr->chip->cfg2 & PRSX4X) ? 0x000c0000 : 0;
3759 int i;
3760
3761 for (i = ATA_DATA; i <= ATA_COMMAND; i++) {
3762 ch->r_io[i].res = ctlr->r_res2;
3763 ch->r_io[i].offset = offset + 0x0200 + (i << 2) + (ch->unit << 7);
3764 }
3765 ch->r_io[ATA_CONTROL].res = ctlr->r_res2;
3766 ch->r_io[ATA_CONTROL].offset = offset + 0x0238 + (ch->unit << 7);
3767 ch->r_io[ATA_IDX_ADDR].res = ctlr->r_res2;
3768 ata_default_registers(dev);
3769 if ((ctlr->chip->cfg2 & (PRSATA | PRSATA2)) ||
3770 ((ctlr->chip->cfg2 & (PRCMBO | PRCMBO2)) && ch->unit < 2)) {
3771 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2;
3772 ch->r_io[ATA_SSTATUS].offset = 0x400 + (ch->unit << 8);
3773 ch->r_io[ATA_SERROR].res = ctlr->r_res2;
3774 ch->r_io[ATA_SERROR].offset = 0x404 + (ch->unit << 8);
3775 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2;
3776 ch->r_io[ATA_SCONTROL].offset = 0x408 + (ch->unit << 8);
3777 ch->flags |= ATA_NO_SLAVE;
3778 }
3779 ch->flags |= ATA_USE_16BIT;
3780
3781 ata_generic_hw(dev);
3782 if (ctlr->chip->cfg2 & PRSX4X) {
3783 ch->hw.command = ata_promise_sx4_command;
3784 }
3785 else {
3786 ch->hw.command = ata_promise_mio_command;
3787 ch->hw.status = ata_promise_mio_status;
3788 }
3789 return 0;
3790 }
3791
3792 static void
3793 ata_promise_mio_intr(void *data)
3794 {
3795 struct ata_pci_controller *ctlr = data;
3796 struct ata_channel *ch;
3797 u_int32_t vector;
3798 int unit, fake_reg;
3799
3800 switch (ctlr->chip->cfg2) {
3801 case PRPATA:
3802 case PRCMBO:
3803 case PRSATA:
3804 fake_reg = 0x60;
3805 break;
3806 case PRCMBO2:
3807 case PRSATA2:
3808 default:
3809 fake_reg = 0x54;
3810 break;
3811 }
3812
3813 /*
3814 * since reading interrupt status register on early "mio" chips
3815 * clears the status bits we cannot read it for each channel later on
3816 * in the generic interrupt routine.
3817 * store the bits in an unused register in the chip so we can read
3818 * it from there safely to get around this "feature".
3819 */
3820 vector = ATA_INL(ctlr->r_res2, 0x040);
3821 ATA_OUTL(ctlr->r_res2, 0x040, vector);
3822 ATA_OUTL(ctlr->r_res2, fake_reg, vector);
3823
3824 for (unit = 0; unit < ctlr->channels; unit++) {
3825 if ((ch = ctlr->interrupt[unit].argument))
3826 ctlr->interrupt[unit].function(ch);
3827 }
3828
3829 ATA_OUTL(ctlr->r_res2, fake_reg, 0xffffffff);
3830 }
3831
3832 static int
3833 ata_promise_mio_status(device_t dev)
3834 {
3835 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
3836 struct ata_channel *ch = device_get_softc(dev);
3837 struct ata_connect_task *tp;
3838 u_int32_t fake_reg, stat_reg, vector, status;
3839
3840 switch (ctlr->chip->cfg2) {
3841 case PRPATA:
3842 case PRCMBO:
3843 case PRSATA:
3844 fake_reg = 0x60;
3845 stat_reg = 0x6c;
3846 break;
3847 case PRCMBO2:
3848 case PRSATA2:
3849 default:
3850 fake_reg = 0x54;
3851 stat_reg = 0x60;
3852 break;
3853 }
3854
3855 /* read and acknowledge interrupt */
3856 vector = ATA_INL(ctlr->r_res2, fake_reg);
3857
3858 /* read and clear interface status */
3859 status = ATA_INL(ctlr->r_res2, stat_reg);
3860 ATA_OUTL(ctlr->r_res2, stat_reg, status & (0x00000011 << ch->unit));
3861
3862 /* check for and handle disconnect events */
3863 if ((status & (0x00000001 << ch->unit)) &&
3864 (tp = (struct ata_connect_task *)
3865 kmalloc(sizeof(struct ata_connect_task),
3866 M_ATA, M_INTWAIT | M_ZERO))) {
3867
3868 if (bootverbose)
3869 device_printf(ch->dev, "DISCONNECT requested\n");
3870 tp->action = ATA_C_DETACH;
3871 tp->dev = ch->dev;
3872 TASK_INIT(&tp->task, 0, ata_sata_phy_event, tp);
3873 taskqueue_enqueue(taskqueue_thread[mycpuid], &tp->task);
3874 }
3875
3876 /* check for and handle connect events */
3877 if ((status & (0x00000010 << ch->unit)) &&
3878 (tp = (struct ata_connect_task *)
3879 kmalloc(sizeof(struct ata_connect_task),
3880 M_ATA, M_INTWAIT | M_ZERO))) {
3881
3882 if (bootverbose)
3883 device_printf(ch->dev, "CONNECT requested\n");
3884 tp->action = ATA_C_ATTACH;
3885 tp->dev = ch->dev;
3886 TASK_INIT(&tp->task, 0, ata_sata_phy_event, tp);
3887 taskqueue_enqueue(taskqueue_thread[mycpuid], &tp->task);
3888 }
3889
3890 /* do we have any device action ? */
3891 return (vector & (1 << (ch->unit + 1)));
3892 }
3893
3894 static int
3895 ata_promise_mio_command(struct ata_request *request)
3896 {
3897 struct ata_pci_controller *ctlr=device_get_softc(GRANDPARENT(request->dev));
3898 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev));
3899 u_int32_t *wordp = (u_int32_t *)ch->dma->work;
3900
3901 ATA_OUTL(ctlr->r_res2, (ch->unit + 1) << 2, 0x00000001);
3902
3903 /* XXX SOS add ATAPI commands support later */
3904 switch (request->u.ata.command) {
3905 default:
3906 return ata_generic_command(request);
3907
3908 case ATA_READ_DMA:
3909 case ATA_READ_DMA48:
3910 wordp[0] = htole32(0x04 | ((ch->unit + 1) << 16) | (0x00 << 24));
3911 break;
3912
3913 case ATA_WRITE_DMA:
3914 case ATA_WRITE_DMA48:
3915 wordp[0] = htole32(0x00 | ((ch->unit + 1) << 16) | (0x00 << 24));
3916 break;
3917 }
3918 wordp[1] = htole32(ch->dma->sg_bus);
3919 wordp[2] = 0;
3920 ata_promise_apkt((u_int8_t*)wordp, request);
3921
3922 ATA_OUTL(ctlr->r_res2, 0x0240 + (ch->unit << 7), ch->dma->work_bus);
3923 return 0;
3924 }
3925
3926 static void
3927 ata_promise_mio_reset(device_t dev)
3928 {
3929 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
3930 struct ata_channel *ch = device_get_softc(dev);
3931 struct ata_promise_sx4 *hpktp;
3932
3933 switch (ctlr->chip->cfg2) {
3934 case PRSX4X:
3935
3936 /* softreset channel ATA module */
3937 hpktp = device_get_ivars(ctlr->dev);
3938 ATA_OUTL(ctlr->r_res2, 0xc0260 + (ch->unit << 7), ch->unit + 1);
3939 ata_udelay(1000);
3940 ATA_OUTL(ctlr->r_res2, 0xc0260 + (ch->unit << 7),
3941 (ATA_INL(ctlr->r_res2, 0xc0260 + (ch->unit << 7)) &
3942 ~0x00003f9f) | (ch->unit + 1));
3943
3944 /* softreset HOST module */ /* XXX SOS what about other outstandings */
3945 spin_lock_wr(&hpktp->mtx);
3946 ATA_OUTL(ctlr->r_res2, 0xc012c,
3947 (ATA_INL(ctlr->r_res2, 0xc012c) & ~0x00000f9f) | (1 << 11));
3948 DELAY(10);
3949 ATA_OUTL(ctlr->r_res2, 0xc012c,
3950 (ATA_INL(ctlr->r_res2, 0xc012c) & ~0x00000f9f));
3951 hpktp->busy = 0;
3952 spin_unlock_wr(&hpktp->mtx);
3953 ata_generic_reset(dev);
3954 break;
3955
3956 case PRPATA:
3957 case PRCMBO:
3958 case PRSATA:
3959 if ((ctlr->chip->cfg2 == PRSATA) ||
3960 ((ctlr->chip->cfg2 == PRCMBO) && (ch->unit < 2))) {
3961
3962 /* mask plug/unplug intr */
3963 ATA_OUTL(ctlr->r_res2, 0x06c, (0x00110000 << ch->unit));
3964 }
3965
3966 /* softreset channels ATA module */
3967 ATA_OUTL(ctlr->r_res2, 0x0260 + (ch->unit << 7), (1 << 11));
3968 ata_udelay(10000);
3969 ATA_OUTL(ctlr->r_res2, 0x0260 + (ch->unit << 7),
3970 (ATA_INL(ctlr->r_res2, 0x0260 + (ch->unit << 7)) &
3971 ~0x00003f9f) | (ch->unit + 1));
3972
3973 if ((ctlr->chip->cfg2 == PRSATA) ||
3974 ((ctlr->chip->cfg2 == PRCMBO) && (ch->unit < 2))) {
3975
3976 if (ata_sata_phy_reset(dev))
3977 ata_generic_reset(dev);
3978
3979 /* reset and enable plug/unplug intr */
3980 ATA_OUTL(ctlr->r_res2, 0x06c, (0x00000011 << ch->unit));
3981 }
3982 else
3983 ata_generic_reset(dev);
3984 break;
3985
3986 case PRCMBO2:
3987 case PRSATA2:
3988 if ((ctlr->chip->cfg2 == PRSATA2) ||
3989 ((ctlr->chip->cfg2 == PRCMBO2) && (ch->unit < 2))) {
3990 /* set portmultiplier port */
3991 ATA_OUTL(ctlr->r_res2, 0x4e8 + (ch->unit << 8), 0x0f);
3992
3993 /* mask plug/unplug intr */
3994 ATA_OUTL(ctlr->r_res2, 0x060, (0x00110000 << ch->unit));
3995 }
3996
3997 /* softreset channels ATA module */
3998 ATA_OUTL(ctlr->r_res2, 0x0260 + (ch->unit << 7), (1 << 11));
3999 ata_udelay(10000);
4000 ATA_OUTL(ctlr->r_res2, 0x0260 + (ch->unit << 7),
4001 (ATA_INL(ctlr->r_res2, 0x0260 + (ch->unit << 7)) &
4002 ~0x00003f9f) | (ch->unit + 1));
4003
4004 if ((ctlr->chip->cfg2 == PRSATA2) ||
4005 ((ctlr->chip->cfg2 == PRCMBO2) && (ch->unit < 2))) {
4006
4007 /* set PHY mode to "improved" */
4008 ATA_OUTL(ctlr->r_res2, 0x414 + (ch->unit << 8),
4009 (ATA_INL(ctlr->r_res2, 0x414 + (ch->unit << 8)) &
4010 ~0x00000003) | 0x00000001);
4011
4012 if (ata_sata_phy_reset(dev))
4013 ata_generic_reset(dev);
4014
4015 /* reset and enable plug/unplug intr */
4016 ATA_OUTL(ctlr->r_res2, 0x060, (0x00000011 << ch->unit));
4017
4018 /* set portmultiplier port */
4019 ATA_OUTL(ctlr->r_res2, 0x4e8 + (ch->unit << 8), 0x00);
4020 }
4021 else
4022 ata_generic_reset(dev);
4023 break;
4024
4025 }
4026 }
4027
4028 static void
4029 ata_promise_mio_dmainit(device_t dev)
4030 {
4031 /* note start and stop are not used here */
4032 ata_dmainit(dev);
4033 }
4034
4035 static void
4036 ata_promise_mio_setmode(device_t dev, int mode)
4037 {
4038 device_t gparent = GRANDPARENT(dev);
4039 struct ata_pci_controller *ctlr = device_get_softc(gparent);
4040 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
4041
4042 if ( (ctlr->chip->cfg2 == PRSATA) ||
4043 ((ctlr->chip->cfg2 == PRCMBO) && (ch->unit < 2)) ||
4044 (ctlr->chip->cfg2 == PRSATA2) ||
4045 ((ctlr->chip->cfg2 == PRCMBO2) && (ch->unit < 2)))
4046 ata_sata_setmode(dev, mode);
4047 else
4048 ata_promise_setmode(dev, mode);
4049 }
4050
4051 static void
4052 ata_promise_sx4_intr(void *data)
4053 {
4054 struct ata_pci_controller *ctlr = data;
4055 struct ata_channel *ch;
4056 u_int32_t vector = ATA_INL(ctlr->r_res2, 0x000c0480);
4057 int unit;
4058
4059 for (unit = 0; unit < ctlr->channels; unit++) {
4060 if (vector & (1 << (unit + 1)))
4061 if ((ch = ctlr->interrupt[unit].argument))
4062 ctlr->interrupt[unit].function(ch);
4063 if (vector & (1 << (unit + 5)))
4064 if ((ch = ctlr->interrupt[unit].argument))
4065 ata_promise_queue_hpkt(ctlr,
4066 htole32((ch->unit * ATA_PDC_CHN_OFFSET) +
4067 ATA_PDC_HPKT_OFFSET));
4068 if (vector & (1 << (unit + 9))) {
4069 ata_promise_next_hpkt(ctlr);
4070 if ((ch = ctlr->interrupt[unit].argument))
4071 ctlr->interrupt[unit].function(ch);
4072 }
4073 if (vector & (1 << (unit + 13))) {
4074 ata_promise_next_hpkt(ctlr);
4075 if ((ch = ctlr->interrupt[unit].argument))
4076 ATA_OUTL(ctlr->r_res2, 0x000c0240 + (ch->unit << 7),
4077 htole32((ch->unit * ATA_PDC_CHN_OFFSET) +
4078 ATA_PDC_APKT_OFFSET));
4079 }
4080 }
4081 }
4082
4083 static int
4084 ata_promise_sx4_command(struct ata_request *request)
4085 {
4086 device_t gparent = GRANDPARENT(request->dev);
4087 struct ata_pci_controller *ctlr = device_get_softc(gparent);
4088 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev));
4089 struct ata_dma_prdentry *prd = ch->dma->sg;
4090 caddr_t window = rman_get_virtual(ctlr->r_res1);
4091 u_int32_t *wordp;
4092 int i, idx, length = 0;
4093
4094 /* XXX SOS add ATAPI commands support later */
4095 switch (request->u.ata.command) {
4096
4097 default:
4098 return -1;
4099
4100 case ATA_ATA_IDENTIFY:
4101 case ATA_READ:
4102 case ATA_READ48:
4103 case ATA_READ_MUL:
4104 case ATA_READ_MUL48:
4105 case ATA_WRITE:
4106 case ATA_WRITE48:
4107 case ATA_WRITE_MUL:
4108 case ATA_WRITE_MUL48:
4109 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit + 1) << 2), 0x00000001);
4110 return ata_generic_command(request);
4111
4112 case ATA_SETFEATURES:
4113 case ATA_FLUSHCACHE:
4114 case ATA_FLUSHCACHE48:
4115 case ATA_SLEEP:
4116 case ATA_SET_MULTI:
4117 wordp = (u_int32_t *)
4118 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_APKT_OFFSET);
4119 wordp[0] = htole32(0x08 | ((ch->unit + 1)<<16) | (0x00 << 24));
4120 wordp[1] = 0;
4121 wordp[2] = 0;
4122 ata_promise_apkt((u_int8_t *)wordp, request);
4123 ATA_OUTL(ctlr->r_res2, 0x000c0484, 0x00000001);
4124 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit + 1) << 2), 0x00000001);
4125 ATA_OUTL(ctlr->r_res2, 0x000c0240 + (ch->unit << 7),
4126 htole32((ch->unit * ATA_PDC_CHN_OFFSET)+ATA_PDC_APKT_OFFSET));
4127 return 0;
4128
4129 case ATA_READ_DMA:
4130 case ATA_READ_DMA48:
4131 case ATA_WRITE_DMA:
4132 case ATA_WRITE_DMA48:
4133 wordp = (u_int32_t *)
4134 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_HSG_OFFSET);
4135 i = idx = 0;
4136 do {
4137 wordp[idx++] = prd[i].addr;
4138 wordp[idx++] = prd[i].count;
4139 length += (prd[i].count & ~ATA_DMA_EOT);
4140 } while (!(prd[i++].count & ATA_DMA_EOT));
4141
4142 wordp = (u_int32_t *)
4143 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_LSG_OFFSET);
4144 wordp[0] = htole32((ch->unit * ATA_PDC_BUF_OFFSET) + ATA_PDC_BUF_BASE);
4145 wordp[1] = htole32(request->bytecount | ATA_DMA_EOT);
4146
4147 wordp = (u_int32_t *)
4148 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_ASG_OFFSET);
4149 wordp[0] = htole32((ch->unit * ATA_PDC_BUF_OFFSET) + ATA_PDC_BUF_BASE);
4150 wordp[1] = htole32(request->bytecount | ATA_DMA_EOT);
4151
4152 wordp = (u_int32_t *)
4153 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_HPKT_OFFSET);
4154 if (request->flags & ATA_R_READ)
4155 wordp[0] = htole32(0x14 | ((ch->unit+9)<<16) | ((ch->unit+5)<<24));
4156 if (request->flags & ATA_R_WRITE)
4157 wordp[0] = htole32(0x00 | ((ch->unit+13)<<16) | (0x00<<24));
4158 wordp[1] = htole32((ch->unit * ATA_PDC_CHN_OFFSET)+ATA_PDC_HSG_OFFSET);
4159 wordp[2] = htole32((ch->unit * ATA_PDC_CHN_OFFSET)+ATA_PDC_LSG_OFFSET);
4160 wordp[3] = 0;
4161
4162 wordp = (u_int32_t *)
4163 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_APKT_OFFSET);
4164 if (request->flags & ATA_R_READ)
4165 wordp[0] = htole32(0x04 | ((ch->unit+5)<<16) | (0x00<<24));
4166 if (request->flags & ATA_R_WRITE)
4167 wordp[0] = htole32(0x10 | ((ch->unit+1)<<16) | ((ch->unit+13)<<24));
4168 wordp[1] = htole32((ch->unit * ATA_PDC_CHN_OFFSET)+ATA_PDC_ASG_OFFSET);
4169 wordp[2] = 0;
4170 ata_promise_apkt((u_int8_t *)wordp, request);
4171 ATA_OUTL(ctlr->r_res2, 0x000c0484, 0x00000001);
4172
4173 if (request->flags & ATA_R_READ) {
4174 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit+5)<<2), 0x00000001);
4175 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit+9)<<2), 0x00000001);
4176 ATA_OUTL(ctlr->r_res2, 0x000c0240 + (ch->unit << 7),
4177 htole32((ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_APKT_OFFSET));
4178 }
4179 if (request->flags & ATA_R_WRITE) {
4180 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit+1)<<2), 0x00000001);
4181 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit+13)<<2), 0x00000001);
4182 ata_promise_queue_hpkt(ctlr,
4183 htole32((ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_HPKT_OFFSET));
4184 }
4185 return 0;
4186 }
4187 }
4188
4189 static int
4190 ata_promise_apkt(u_int8_t *bytep, struct ata_request *request)
4191 {
4192 struct ata_device *atadev = device_get_softc(request->dev);
4193 int i = 12;
4194
4195 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_PDC_WAIT_NBUSY|ATA_DRIVE;
4196 bytep[i++] = ATA_D_IBM | ATA_D_LBA | atadev->unit;
4197 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_CTL;
4198 bytep[i++] = ATA_A_4BIT;
4199
4200 if (atadev->flags & ATA_D_48BIT_ACTIVE) {
4201 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_FEATURE;
4202 bytep[i++] = request->u.ata.feature >> 8;
4203 bytep[i++] = request->u.ata.feature;
4204 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_COUNT;
4205 bytep[i++] = request->u.ata.count >> 8;
4206 bytep[i++] = request->u.ata.count;
4207 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_SECTOR;
4208 bytep[i++] = request->u.ata.lba >> 24;
4209 bytep[i++] = request->u.ata.lba;
4210 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_CYL_LSB;
4211 bytep[i++] = request->u.ata.lba >> 32;
4212 bytep[i++] = request->u.ata.lba >> 8;
4213 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_CYL_MSB;
4214 bytep[i++] = request->u.ata.lba >> 40;
4215 bytep[i++] = request->u.ata.lba >> 16;
4216 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_DRIVE;
4217 bytep[i++] = ATA_D_LBA | atadev->unit;
4218 }
4219 else {
4220 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_FEATURE;
4221 bytep[i++] = request->u.ata.feature;
4222 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_COUNT;
4223 bytep[i++] = request->u.ata.count;
4224 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_SECTOR;
4225 bytep[i++] = request->u.ata.lba;
4226 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_CYL_LSB;
4227 bytep[i++] = request->u.ata.lba >> 8;
4228 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_CYL_MSB;
4229 bytep[i++] = request->u.ata.lba >> 16;
4230 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_DRIVE;
4231 bytep[i++] = (atadev->flags & ATA_D_USE_CHS ? 0 : ATA_D_LBA) |
4232 ATA_D_IBM | atadev->unit | ((request->u.ata.lba >> 24)&0xf);
4233 }
4234 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_END | ATA_COMMAND;
4235 bytep[i++] = request->u.ata.command;
4236 return i;
4237 }
4238
4239 static void
4240 ata_promise_queue_hpkt(struct ata_pci_controller *ctlr, u_int32_t hpkt)
4241 {
4242 struct ata_promise_sx4 *hpktp = device_get_ivars(ctlr->dev);
4243
4244 spin_lock_wr(&hpktp->mtx);
4245 if (hpktp->busy) {
4246 struct host_packet *hp =
4247 kmalloc(sizeof(struct host_packet), M_TEMP, M_INTWAIT | M_ZERO);
4248 hp->addr = hpkt;
4249 TAILQ_INSERT_TAIL(&hpktp->queue, hp, chain);
4250 }
4251 else {
4252 hpktp->busy = 1;
4253 ATA_OUTL(ctlr->r_res2, 0x000c0100, hpkt);
4254 }
4255 spin_unlock_wr(&hpktp->mtx);
4256 }
4257
4258 static void
4259 ata_promise_next_hpkt(struct ata_pci_controller *ctlr)
4260 {
4261 struct ata_promise_sx4 *hpktp = device_get_ivars(ctlr->dev);
4262 struct host_packet *hp;
4263
4264 spin_lock_wr(&hpktp->mtx);
4265 if ((hp = TAILQ_FIRST(&hpktp->queue))) {
4266 TAILQ_REMOVE(&hpktp->queue, hp, chain);
4267 ATA_OUTL(ctlr->r_res2, 0x000c0100, hp->addr);
4268 kfree(hp, M_TEMP);
4269 }
4270 else
4271 hpktp->busy = 0;
4272 spin_unlock_wr(&hpktp->mtx);
4273 }
4274
4275
4276 /*
4277 * ServerWorks chipset support functions
4278 */
4279 int
4280 ata_serverworks_ident(device_t dev)
4281 {
4282 struct ata_pci_controller *ctlr = device_get_softc(dev);
4283 struct ata_chip_id *idx;
4284 static struct ata_chip_id ids[] =
4285 {{ ATA_ROSB4, 0x00, SWKS33, 0, ATA_UDMA2, "ROSB4" },
4286 { ATA_CSB5, 0x92, SWKS100, 0, ATA_UDMA5, "CSB5" },
4287 { ATA_CSB5, 0x00, SWKS66, 0, ATA_UDMA4, "CSB5" },
4288 { ATA_CSB6, 0x00, SWKS100, 0, ATA_UDMA5, "CSB6" },
4289 { ATA_CSB6_1, 0x00, SWKS66, 0, ATA_UDMA4, "CSB6" },
4290 { ATA_HT1000, 0x00, SWKS100, 0, ATA_UDMA5, "HT1000" },
4291 { ATA_HT1000_S1, 0x00, SWKS100, 4, ATA_SA150, "HT1000" },
4292 { ATA_HT1000_S2, 0x00, SWKSMIO, 4, ATA_SA150, "HT1000" },
4293 { ATA_K2, 0x00, SWKSMIO, 4, ATA_SA150, "K2" },
4294 { ATA_FRODO4, 0x00, SWKSMIO, 4, ATA_SA150, "Frodo4" },
4295 { ATA_FRODO8, 0x00, SWKSMIO, 8, ATA_SA150, "Frodo8" },
4296 { 0, 0, 0, 0, 0, 0}};
4297 char buffer[64];
4298
4299 if (!(idx = ata_match_chip(dev, ids)))
4300 return ENXIO;
4301
4302 ksprintf(buffer, "ServerWorks %s %s controller",
4303 idx->text, ata_mode2str(idx->max_dma));
4304 device_set_desc_copy(dev, buffer);
4305 ctlr->chip = idx;
4306 ctlr->chipinit = ata_serverworks_chipinit;
4307 return 0;
4308 }
4309
4310 static int
4311 ata_serverworks_chipinit(device_t dev)
4312 {
4313 struct ata_pci_controller *ctlr = device_get_softc(dev);
4314
4315 if (ata_setup_interrupt(dev))
4316 return ENXIO;
4317
4318 if (ctlr->chip->cfg1 == SWKSMIO) {
4319 ctlr->r_type2 = SYS_RES_MEMORY;
4320 ctlr->r_rid2 = PCIR_BAR(5);
4321 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
4322 &ctlr->r_rid2, RF_ACTIVE)))
4323 return ENXIO;
4324
4325 ctlr->channels = ctlr->chip->cfg2;
4326 ctlr->allocate = ata_serverworks_allocate;
4327 ctlr->setmode = ata_sata_setmode;
4328 return 0;
4329 }
4330 else if (ctlr->chip->cfg1 == SWKS33) {
4331 device_t *children;
4332 int nchildren, i;
4333
4334 /* locate the ISA part in the southbridge and enable UDMA33 */
4335 if (!device_get_children(device_get_parent(dev), &children,&nchildren)){
4336 for (i = 0; i < nchildren; i++) {
4337 if (pci_get_devid(children[i]) == ATA_ROSB4_ISA) {
4338 pci_write_config(children[i], 0x64,
4339 (pci_read_config(children[i], 0x64, 4) &
4340 ~0x00002000) | 0x00004000, 4);
4341 break;
4342 }
4343 }
4344 kfree(children, M_TEMP);
4345 }
4346 }
4347 else {
4348 pci_write_config(dev, 0x5a,
4349 (pci_read_config(dev, 0x5a, 1) & ~0x40) |
4350 (ctlr->chip->cfg1 == SWKS100) ? 0x03 : 0x02, 1);
4351 }
4352 ctlr->setmode = ata_serverworks_setmode;
4353 return 0;
4354 }
4355
4356 static int
4357 ata_serverworks_allocate(device_t dev)
4358 {
4359 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
4360 struct ata_channel *ch = device_get_softc(dev);
4361 int ch_offset;
4362 int i;
4363
4364 ch_offset = ch->unit * 0x100;
4365
4366 for (i = ATA_DATA; i < ATA_MAX_RES; i++)
4367 ch->r_io[i].res = ctlr->r_res2;
4368
4369 /* setup ATA registers */
4370 ch->r_io[ATA_DATA].offset = ch_offset + 0x00;
4371 ch->r_io[ATA_FEATURE].offset = ch_offset + 0x04;
4372 ch->r_io[ATA_COUNT].offset = ch_offset + 0x08;
4373 ch->r_io[ATA_SECTOR].offset = ch_offset + 0x0c;
4374 ch->r_io[ATA_CYL_LSB].offset = ch_offset + 0x10;
4375 ch->r_io[ATA_CYL_MSB].offset = ch_offset + 0x14;
4376 ch->r_io[ATA_DRIVE].offset = ch_offset + 0x18;
4377 ch->r_io[ATA_COMMAND].offset = ch_offset + 0x1c;
4378 ch->r_io[ATA_CONTROL].offset = ch_offset + 0x20;
4379 ata_default_registers(dev);
4380
4381 /* setup DMA registers */
4382 ch->r_io[ATA_BMCMD_PORT].offset = ch_offset + 0x30;
4383 ch->r_io[ATA_BMSTAT_PORT].offset = ch_offset + 0x32;
4384 ch->r_io[ATA_BMDTP_PORT].offset = ch_offset + 0x34;
4385
4386 /* setup SATA registers */
4387 ch->r_io[ATA_SSTATUS].offset = ch_offset + 0x40;
4388 ch->r_io[ATA_SERROR].offset = ch_offset + 0x44;
4389 ch->r_io[ATA_SCONTROL].offset = ch_offset + 0x48;
4390
4391 ch->flags |= ATA_NO_SLAVE;
4392 ata_pci_hw(dev);
4393
4394 /* chip does not reliably do 64K DMA transfers */
4395 if (ch->dma)
4396 ch->dma->max_iosize = 126 * DEV_BSIZE;
4397
4398 return 0;
4399 }
4400
4401 static void
4402 ata_serverworks_setmode(device_t dev, int mode)
4403 {
4404 device_t gparent = GRANDPARENT(dev);
4405 struct ata_pci_controller *ctlr = device_get_softc(gparent);
4406 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
4407 struct ata_device *atadev = device_get_softc(dev);
4408 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
4409 int offset = (devno ^ 0x01) << 3;
4410 int error;
4411 u_int8_t piotimings[] = { 0x5d, 0x47, 0x34, 0x22, 0x20, 0x34, 0x22, 0x20,
4412 0x20, 0x20, 0x20, 0x20, 0x20, 0x20 };
4413 u_int8_t dmatimings[] = { 0x77, 0x21, 0x20 };
4414
4415 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma);
4416
4417 mode = ata_check_80pin(dev, mode);
4418
4419 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
4420
4421 if (bootverbose)
4422 device_printf(dev, "%ssetting %s on %s chip\n",
4423 (error) ? "FAILURE " : "",
4424 ata_mode2str(mode), ctlr->chip->text);
4425 if (!error) {
4426 if (mode >= ATA_UDMA0) {
4427 pci_write_config(gparent, 0x56,
4428 (pci_read_config(gparent, 0x56, 2) &
4429 ~(0xf << (devno << 2))) |
4430 ((mode & ATA_MODE_MASK) << (devno << 2)), 2);
4431 pci_write_config(gparent, 0x54,
4432 pci_read_config(gparent, 0x54, 1) |
4433 (0x01 << devno), 1);
4434 pci_write_config(gparent, 0x44,
4435 (pci_read_config(gparent, 0x44, 4) &
4436 ~(0xff << offset)) |
4437 (dmatimings[2] << offset), 4);
4438 }
4439 else if (mode >= ATA_WDMA0) {
4440 pci_write_config(gparent, 0x54,
4441 pci_read_config(gparent, 0x54, 1) &
4442 ~(0x01 << devno), 1);
4443 pci_write_config(gparent, 0x44,
4444 (pci_read_config(gparent, 0x44, 4) &
4445 ~(0xff << offset)) |
4446 (dmatimings[mode & ATA_MODE_MASK] << offset), 4);
4447 }
4448 else
4449 pci_write_config(gparent, 0x54,
4450 pci_read_config(gparent, 0x54, 1) &
4451 ~(0x01 << devno), 1);
4452
4453 pci_write_config(gparent, 0x40,
4454 (pci_read_config(gparent, 0x40, 4) &
4455 ~(0xff << offset)) |
4456 (piotimings[ata_mode2idx(mode)] << offset), 4);
4457 atadev->mode = mode;
4458 }
4459 }
4460
4461
4462 /*
4463 * Silicon Image Inc. (SiI) (former CMD) chipset support functions
4464 */
4465 int
4466 ata_sii_ident(device_t dev)
4467 {
4468 struct ata_pci_controller *ctlr = device_get_softc(dev);
4469 struct ata_chip_id *idx;
4470 static struct ata_chip_id ids[] =
4471 {{ ATA_SII3114, 0x00, SIIMEMIO, SII4CH, ATA_SA150, "SiI 3114" },
4472 { ATA_SII3512, 0x02, SIIMEMIO, 0, ATA_SA150, "SiI 3512" },
4473 { ATA_SII3112, 0x02, SIIMEMIO, 0, ATA_SA150, "SiI 3112" },
4474 { ATA_SII3112_1, 0x02, SIIMEMIO, 0, ATA_SA150, "SiI 3112" },
4475 { ATA_SII3512, 0x00, SIIMEMIO, SIIBUG, ATA_SA150, "SiI 3512" },
4476 { ATA_SII3112, 0x00, SIIMEMIO, SIIBUG, ATA_SA150, "SiI 3112" },
4477 { ATA_SII3112_1, 0x00, SIIMEMIO, SIIBUG, ATA_SA150, "SiI 3112" },
4478 { ATA_SII3124, 0x00, SIIPRBIO, SII4CH, ATA_SA300, "SiI 3124" },
4479 { ATA_SII3132, 0x00, SIIPRBIO, 0, ATA_SA300, "SiI 3132" },
4480 { ATA_SII0680, 0x00, SIIMEMIO, SIISETCLK, ATA_UDMA6, "SiI 0680" },
4481 { ATA_CMD649, 0x00, 0, SIIINTR, ATA_UDMA5, "CMD 649" },
4482 { ATA_CMD648, 0x00, 0, SIIINTR, ATA_UDMA4, "CMD 648" },
4483 { ATA_CMD646, 0x07, 0, 0, ATA_UDMA2, "CMD 646U2" },
4484 { ATA_CMD646, 0x00, 0, 0, ATA_WDMA2, "CMD 646" },
4485 { 0, 0, 0, 0, 0, 0}};
4486 char buffer[64];
4487
4488 if (!(idx = ata_match_chip(dev, ids)))
4489 return ENXIO;
4490
4491 ksprintf(buffer, "%s %s controller", idx->text, ata_mode2str(idx->max_dma));
4492 device_set_desc_copy(dev, buffer);
4493 ctlr->chip = idx;
4494 ctlr->chipinit = ata_sii_chipinit;
4495 return 0;
4496 }
4497
4498 static int
4499 ata_sii_chipinit(device_t dev)
4500 {
4501 struct ata_pci_controller *ctlr = device_get_softc(dev);
4502
4503 if (ata_setup_interrupt(dev))
4504 return ENXIO;
4505
4506 switch (ctlr->chip->cfg1) {
4507 case SIIPRBIO:
4508 ctlr->r_type1 = SYS_RES_MEMORY;
4509 ctlr->r_rid1 = PCIR_BAR(0);
4510 if (!(ctlr->r_res1 = bus_alloc_resource_any(dev, ctlr->r_type1,
4511 &ctlr->r_rid1, RF_ACTIVE)))
4512 return ENXIO;
4513
4514 ctlr->r_rid2 = PCIR_BAR(2);
4515 ctlr->r_type2 = SYS_RES_MEMORY;
4516 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
4517 &ctlr->r_rid2, RF_ACTIVE))){
4518 bus_release_resource(dev, ctlr->r_type1, ctlr->r_rid1,ctlr->r_res1);
4519 return ENXIO;
4520 }
4521 ctlr->allocate = ata_siiprb_allocate;
4522 ctlr->reset = ata_siiprb_reset;
4523 ctlr->dmainit = ata_siiprb_dmainit;
4524 ctlr->setmode = ata_sata_setmode;
4525 ctlr->channels = (ctlr->chip->cfg2 == SII4CH) ? 4 : 2;
4526
4527 /* reset controller */
4528 ATA_OUTL(ctlr->r_res1, 0x0040, 0x80000000);
4529 DELAY(10000);
4530 ATA_OUTL(ctlr->r_res1, 0x0040, 0x0000000f);
4531
4532 /* enable PCI interrupt */
4533 pci_write_config(dev, PCIR_COMMAND,
4534 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400, 2);
4535 break;
4536
4537 case SIIMEMIO:
4538 ctlr->r_type2 = SYS_RES_MEMORY;
4539 ctlr->r_rid2 = PCIR_BAR(5);
4540 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
4541 &ctlr->r_rid2, RF_ACTIVE)))
4542 return ENXIO;
4543
4544 if (ctlr->chip->cfg2 & SIISETCLK) {
4545 if ((pci_read_config(dev, 0x8a, 1) & 0x30) != 0x10)
4546 pci_write_config(dev, 0x8a,
4547 (pci_read_config(dev, 0x8a, 1) & 0xcf)|0x10,1);
4548 if ((pci_read_config(dev, 0x8a, 1) & 0x30) != 0x10)
4549 device_printf(dev, "%s could not set ATA133 clock\n",
4550 ctlr->chip->text);
4551 }
4552
4553 /* if we have 4 channels enable the second set */
4554 if (ctlr->chip->cfg2 & SII4CH) {
4555 ATA_OUTL(ctlr->r_res2, 0x0200, 0x00000002);
4556 ctlr->channels = 4;
4557 }
4558
4559 /* dont block interrupts from any channel */
4560 pci_write_config(dev, 0x48,
4561 (pci_read_config(dev, 0x48, 4) & ~0x03c00000), 4);
4562
4563 /* enable PCI interrupt as BIOS might not */
4564 pci_write_config(dev, 0x8a, (pci_read_config(dev, 0x8a, 1) & 0x3f), 1);
4565
4566 ctlr->allocate = ata_sii_allocate;
4567 if (ctlr->chip->max_dma >= ATA_SA150) {
4568 ctlr->reset = ata_sii_reset;
4569 ctlr->setmode = ata_sata_setmode;
4570 }
4571 else
4572 ctlr->setmode = ata_sii_setmode;
4573 break;
4574
4575 default:
4576 if ((pci_read_config(dev, 0x51, 1) & 0x08) != 0x08) {
4577 device_printf(dev, "HW has secondary channel disabled\n");
4578 ctlr->channels = 1;
4579 }
4580
4581 /* enable interrupt as BIOS might not */
4582 pci_write_config(dev, 0x71, 0x01, 1);
4583
4584 ctlr->allocate = ata_cmd_allocate;
4585 ctlr->setmode = ata_cmd_setmode;
4586 break;
4587 }
4588 return 0;
4589 }
4590
4591 static int
4592 ata_cmd_allocate(device_t dev)
4593 {
4594 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
4595 struct ata_channel *ch = device_get_softc(dev);
4596
4597 /* setup the usual register normal pci style */
4598 if (ata_pci_allocate(dev))
4599 return ENXIO;
4600
4601 if (ctlr->chip->cfg2 & SIIINTR)
4602 ch->hw.status = ata_cmd_status;
4603
4604 return 0;
4605 }
4606
4607 static int
4608 ata_cmd_status(device_t dev)
4609 {
4610 struct ata_channel *ch = device_get_softc(dev);
4611 u_int8_t reg71;
4612
4613 if (((reg71 = pci_read_config(device_get_parent(ch->dev), 0x71, 1)) &
4614 (ch->unit ? 0x08 : 0x04))) {
4615 pci_write_config(device_get_parent(ch->dev), 0x71,
4616 reg71 & ~(ch->unit ? 0x04 : 0x08), 1);
4617 return ata_pci_status(dev);
4618 }
4619 return 0;
4620 }
4621
4622 static void
4623 ata_cmd_setmode(device_t dev, int mode)
4624 {
4625 device_t gparent = GRANDPARENT(dev);
4626 struct ata_pci_controller *ctlr = device_get_softc(gparent);
4627 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
4628 struct ata_device *atadev = device_get_softc(dev);
4629 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
4630 int error;
4631
4632 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma);
4633
4634 mode = ata_check_80pin(dev, mode);
4635
4636 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
4637
4638 if (bootverbose)
4639 device_printf(dev, "%ssetting %s on %s chip\n",
4640 (error) ? "FAILURE " : "",
4641 ata_mode2str(mode), ctlr->chip->text);
4642 if (!error) {
4643 int treg = 0x54 + ((devno < 3) ? (devno << 1) : 7);
4644 int ureg = ch->unit ? 0x7b : 0x73;
4645
4646 if (mode >= ATA_UDMA0) {
4647 int udmatimings[][2] = { { 0x31, 0xc2 }, { 0x21, 0x82 },
4648 { 0x11, 0x42 }, { 0x25, 0x8a },
4649 { 0x15, 0x4a }, { 0x05, 0x0a } };
4650
4651 u_int8_t umode = pci_read_config(gparent, ureg, 1);
4652
4653 umode &= ~(atadev->unit == ATA_MASTER ? 0x35 : 0xca);
4654 umode |= udmatimings[mode & ATA_MODE_MASK][ATA_DEV(atadev->unit)];
4655 pci_write_config(gparent, ureg, umode, 1);
4656 }
4657 else if (mode >= ATA_WDMA0) {
4658 int dmatimings[] = { 0x87, 0x32, 0x3f };
4659
4660 pci_write_config(gparent, treg, dmatimings[mode & ATA_MODE_MASK],1);
4661 pci_write_config(gparent, ureg,
4662 pci_read_config(gparent, ureg, 1) &
4663 ~(atadev->unit == ATA_MASTER ? 0x35 : 0xca), 1);
4664 }
4665 else {
4666 int piotimings[] = { 0xa9, 0x57, 0x44, 0x32, 0x3f };
4667 pci_write_config(gparent, treg,
4668 piotimings[(mode & ATA_MODE_MASK) - ATA_PIO0], 1);
4669 pci_write_config(gparent, ureg,
4670 pci_read_config(gparent, ureg, 1) &
4671 ~(atadev->unit == ATA_MASTER ? 0x35 : 0xca), 1);
4672 }
4673 atadev->mode = mode;
4674 }
4675 }
4676
4677 static int
4678 ata_sii_allocate(device_t dev)
4679 {
4680 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
4681 struct ata_channel *ch = device_get_softc(dev);
4682 int unit01 = (ch->unit & 1), unit10 = (ch->unit & 2);
4683 int i;
4684
4685 for (i = ATA_DATA; i <= ATA_COMMAND; i++) {
4686 ch->r_io[i].res = ctlr->r_res2;
4687 ch->r_io[i].offset = 0x80 + i + (unit01 << 6) + (unit10 << 8);
4688 }
4689 ch->r_io[ATA_CONTROL].res = ctlr->r_res2;
4690 ch->r_io[ATA_CONTROL].offset = 0x8a + (unit01 << 6) + (unit10 << 8);
4691 ch->r_io[ATA_IDX_ADDR].res = ctlr->r_res2;
4692 ata_default_registers(dev);
4693
4694 ch->r_io[ATA_BMCMD_PORT].res = ctlr->r_res2;
4695 ch->r_io[ATA_BMCMD_PORT].offset = 0x00 + (unit01 << 3) + (unit10 << 8);
4696 ch->r_io[ATA_BMSTAT_PORT].res = ctlr->r_res2;
4697 ch->r_io[ATA_BMSTAT_PORT].offset = 0x02 + (unit01 << 3) + (unit10 << 8);
4698 ch->r_io[ATA_BMDTP_PORT].res = ctlr->r_res2;
4699 ch->r_io[ATA_BMDTP_PORT].offset = 0x04 + (unit01 << 3) + (unit10 << 8);
4700
4701 if (ctlr->chip->max_dma >= ATA_SA150) {
4702 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2;
4703 ch->r_io[ATA_SSTATUS].offset = 0x104 + (unit01 << 7) + (unit10 << 8);
4704 ch->r_io[ATA_SERROR].res = ctlr->r_res2;
4705 ch->r_io[ATA_SERROR].offset = 0x108 + (unit01 << 7) + (unit10 << 8);
4706 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2;
4707 ch->r_io[ATA_SCONTROL].offset = 0x100 + (unit01 << 7) + (unit10 << 8);
4708 ch->flags |= ATA_NO_SLAVE;
4709
4710 /* enable PHY state change interrupt */
4711 ATA_OUTL(ctlr->r_res2, 0x148 + (unit01 << 7) + (unit10 << 8),(1 << 16));
4712 }
4713
4714 if ((ctlr->chip->cfg2 & SIIBUG) && ch->dma) {
4715 /* work around errata in early chips */
4716 ch->dma->boundary = 16 * DEV_BSIZE;
4717 ch->dma->segsize = 15 * DEV_BSIZE;
4718 }
4719
4720 ata_pci_hw(dev);
4721 ch->hw.status = ata_sii_status;
4722 return 0;
4723 }
4724
4725 static int
4726 ata_sii_status(device_t dev)
4727 {
4728 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
4729 struct ata_channel *ch = device_get_softc(dev);
4730 int offset0 = ((ch->unit & 1) << 3) + ((ch->unit & 2) << 8);
4731 int offset1 = ((ch->unit & 1) << 6) + ((ch->unit & 2) << 8);
4732
4733 /* do we have any PHY events ? */
4734 if (ctlr->chip->max_dma >= ATA_SA150 &&
4735 (ATA_INL(ctlr->r_res2, 0x10 + offset0) & 0x00000010))
4736 ata_sata_phy_check_events(dev);
4737
4738 if (ATA_INL(ctlr->r_res2, 0xa0 + offset1) & 0x00000800)
4739 return ata_pci_status(dev);
4740 else
4741 return 0;
4742 }
4743
4744 static void
4745 ata_sii_reset(device_t dev)
4746 {
4747 if (ata_sata_phy_reset(dev))
4748 ata_generic_reset(dev);
4749 }
4750
4751 static void
4752 ata_sii_setmode(device_t dev, int mode)
4753 {
4754 device_t gparent = GRANDPARENT(dev);
4755 struct ata_pci_controller *ctlr = device_get_softc(gparent);
4756 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
4757 struct ata_device *atadev = device_get_softc(dev);
4758 int rego = (ch->unit << 4) + (ATA_DEV(atadev->unit) << 1);
4759 int mreg = ch->unit ? 0x84 : 0x80;
4760 int mask = 0x03 << (ATA_DEV(atadev->unit) << 2);
4761 int mval = pci_read_config(gparent, mreg, 1) & ~mask;
4762 int error;
4763
4764 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma);
4765
4766 if (ctlr->chip->cfg2 & SIISETCLK) {
4767 if (mode > ATA_UDMA2 && (pci_read_config(gparent, 0x79, 1) &
4768 (ch->unit ? 0x02 : 0x01))) {
4769 ata_print_cable(dev, "controller");
4770 mode = ATA_UDMA2;
4771 }
4772 }
4773 else
4774 mode = ata_check_80pin(dev, mode);
4775
4776 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
4777
4778 if (bootverbose)
4779 device_printf(dev, "%ssetting %s on %s chip\n",
4780 (error) ? "FAILURE " : "",
4781 ata_mode2str(mode), ctlr->chip->text);
4782 if (error)
4783 return;
4784
4785 if (mode >= ATA_UDMA0) {
4786 u_int8_t udmatimings[] = { 0xf, 0xb, 0x7, 0x5, 0x3, 0x2, 0x1 };
4787 u_int8_t ureg = 0xac + rego;
4788
4789 pci_write_config(gparent, mreg,
4790 mval | (0x03 << (ATA_DEV(atadev->unit) << 2)), 1);
4791 pci_write_config(gparent, ureg,
4792 (pci_read_config(gparent, ureg, 1) & ~0x3f) |
4793 udmatimings[mode & ATA_MODE_MASK], 1);
4794
4795 }
4796 else if (mode >= ATA_WDMA0) {
4797 u_int8_t dreg = 0xa8 + rego;
4798 u_int16_t dmatimings[] = { 0x2208, 0x10c2, 0x10c1 };
4799
4800 pci_write_config(gparent, mreg,
4801 mval | (0x02 << (ATA_DEV(atadev->unit) << 2)), 1);
4802 pci_write_config(gparent, dreg, dmatimings[mode & ATA_MODE_MASK], 2);
4803
4804 }
4805 else {
4806 u_int8_t preg = 0xa4 + rego;
4807 u_int16_t piotimings[] = { 0x328a, 0x2283, 0x1104, 0x10c3, 0x10c1 };
4808
4809 pci_write_config(gparent, mreg,
4810 mval | (0x01 << (ATA_DEV(atadev->unit) << 2)), 1);
4811 pci_write_config(gparent, preg, piotimings[mode & ATA_MODE_MASK], 2);
4812 }
4813 atadev->mode = mode;
4814 }
4815
4816 struct ata_siiprb_dma_prdentry {
4817 u_int64_t addr;
4818 u_int32_t count;
4819 u_int32_t control;
4820 } __packed;
4821
4822 struct ata_siiprb_ata_command {
4823 u_int32_t reserved0;
4824 struct ata_siiprb_dma_prdentry prd[126];
4825 } __packed;
4826
4827 struct ata_siiprb_atapi_command {
4828 u_int8_t cdb[16];
4829 struct ata_siiprb_dma_prdentry prd[125];
4830 } __packed;
4831
4832 struct ata_siiprb_command {
4833 u_int16_t control;
4834 u_int16_t protocol_override;
4835 u_int32_t transfer_count;
4836 u_int8_t fis[20];
4837 union {
4838 struct ata_siiprb_ata_command ata;
4839 struct ata_siiprb_atapi_command atapi;
4840 } u;
4841 } __packed;
4842
4843 static int
4844 ata_siiprb_allocate(device_t dev)
4845 {
4846 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
4847 struct ata_channel *ch = device_get_softc(dev);
4848 int offset = ch->unit * 0x2000;
4849
4850 /* set the SATA resources */
4851 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2;
4852 ch->r_io[ATA_SSTATUS].offset = 0x1f04 + offset;
4853 ch->r_io[ATA_SERROR].res = ctlr->r_res2;
4854 ch->r_io[ATA_SERROR].offset = 0x1f08 + offset;
4855 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2;
4856 ch->r_io[ATA_SCONTROL].offset = 0x1f00 + offset;
4857 ch->r_io[ATA_SACTIVE].res = ctlr->r_res2;
4858 ch->r_io[ATA_SACTIVE].offset = 0x1f0c + offset;
4859
4860 ch->hw.begin_transaction = ata_siiprb_begin_transaction;
4861 ch->hw.end_transaction = ata_siiprb_end_transaction;
4862 ch->hw.status = ata_siiprb_status;
4863 ch->hw.command = NULL; /* not used here */
4864 return 0;
4865 }
4866
4867 static int
4868 ata_siiprb_status(device_t dev)
4869 {
4870 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
4871 struct ata_channel *ch = device_get_softc(dev);
4872 int offset = ch->unit * 0x2000;
4873
4874 if ((ATA_INL(ctlr->r_res1, 0x0044) & (1 << ch->unit))) {
4875 u_int32_t istatus = ATA_INL(ctlr->r_res2, 0x1008 + offset);
4876
4877 /* do we have any PHY events ? */
4878 ata_sata_phy_check_events(dev);
4879
4880 /* clear interrupt(s) */
4881 ATA_OUTL(ctlr->r_res2, 0x1008 + offset, istatus);
4882
4883 /* do we have any device action ? */
4884 return (istatus & 0x00000001);
4885 }
4886 return 0;
4887 }
4888
4889 static int
4890 ata_siiprb_begin_transaction(struct ata_request *request)
4891 {
4892 struct ata_pci_controller *ctlr=device_get_softc(GRANDPARENT(request->dev));
4893 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev));
4894 struct ata_siiprb_command *prb;
4895 int offset = ch->unit * 0x2000;
4896 u_int64_t prb_bus;
4897 int tag = 0, dummy;
4898
4899 /* check for 48 bit access and convert if needed */
4900 ata_modify_if_48bit(request);
4901
4902 /* get a piece of the workspace for this request */
4903 prb = (struct ata_siiprb_command *)
4904 (ch->dma->work + (sizeof(struct ata_siiprb_command) * tag));
4905
4906 /* set basic prd options ata/atapi etc etc */
4907 bzero(prb, sizeof(struct ata_siiprb_command));
4908
4909 /* setup the FIS for this request */
4910 if (!ata_request2fis_h2d(request, &prb->fis[0])) {
4911 device_printf(request->dev, "setting up SATA FIS failed\n");
4912 request->result = EIO;
4913 return ATA_OP_FINISHED;
4914 }
4915
4916 /* if request moves data setup and load SG list */
4917 if (request->flags & (ATA_R_READ | ATA_R_WRITE)) {
4918 struct ata_siiprb_dma_prdentry *prd;
4919
4920 if (request->flags & ATA_R_ATAPI)
4921 prd = &prb->u.atapi.prd[0];
4922 else
4923 prd = &prb->u.ata.prd[0];
4924 if (ch->dma->load(ch->dev, request->data, request->bytecount,
4925 request->flags & ATA_R_READ, prd, &dummy)) {
4926 device_printf(request->dev, "setting up DMA failed\n");
4927 request->result = EIO;
4928 return ATA_OP_FINISHED;
4929 }
4930 }
4931
4932 /* activate the prb */
4933 prb_bus = ch->dma->work_bus + (sizeof(struct ata_siiprb_command) * tag);
4934 ATA_OUTL(ctlr->r_res2,
4935 0x1c00 + offset + (tag * sizeof(u_int64_t)), prb_bus);
4936 ATA_OUTL(ctlr->r_res2,
4937 0x1c04 + offset + (tag * sizeof(u_int64_t)), prb_bus>>32);
4938
4939 /* start the timeout */
4940 callout_reset(&request->callout, request->timeout * hz,
4941 (timeout_t*)ata_timeout, request);
4942 return ATA_OP_CONTINUES;
4943 }
4944
4945 static int
4946 ata_siiprb_end_transaction(struct ata_request *request)
4947 {
4948 struct ata_pci_controller *ctlr=device_get_softc(GRANDPARENT(request->dev));
4949 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev));
4950 struct ata_siiprb_command *prb;
4951 int offset = ch->unit * 0x2000;
4952 int error, tag = 0;
4953
4954 /* kill the timeout */
4955 callout_stop(&request->callout);
4956
4957 prb = (struct ata_siiprb_command *)
4958 ((u_int8_t *)rman_get_virtual(ctlr->r_res2) + (tag << 7) + offset);
4959
4960 /* if error status get details */
4961 request->status = prb->fis[2];
4962 if (request->status & ATA_S_ERROR)
4963 request->error = prb->fis[3];
4964
4965 /* update progress */
4966 if (!(request->status & ATA_S_ERROR) && !(request->flags & ATA_R_TIMEOUT)) {
4967 if (request->flags & ATA_R_READ)
4968 request->donecount = prb->transfer_count;
4969 else
4970 request->donecount = request->bytecount;
4971 }
4972
4973 /* any controller errors flagged ? */
4974 if ((error = ATA_INL(ctlr->r_res2, 0x1024 + offset))) {
4975 kprintf("ata_siiprb_end_transaction %s error=%08x\n",
4976 ata_cmd2str(request), error);
4977 }
4978
4979 /* release SG list etc */
4980 ch->dma->unload(ch->dev);
4981
4982 return ATA_OP_FINISHED;
4983 }
4984
4985 static void
4986 ata_siiprb_reset(device_t dev)
4987 {
4988 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
4989 struct ata_channel *ch = device_get_softc(dev);
4990 int offset = ch->unit * 0x2000;
4991 struct ata_siiprb_command *prb;
4992 u_int64_t prb_bus;
4993 u_int32_t status, signature;
4994 int timeout, tag = 0;
4995
4996 /* reset channel HW */
4997 ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x00000001);
4998 DELAY(1000);
4999 ATA_OUTL(ctlr->r_res2, 0x1004 + offset, 0x00000001);
5000 DELAY(10000);
5001
5002 /* poll for channel ready */
5003 for (timeout = 0; timeout < 1000; timeout++) {
5004 if ((status = ATA_INL(ctlr->r_res2, 0x1000 + offset)) & 0x00040000)
5005 break;
5006 DELAY(1000);
5007 }
5008 if (timeout >= 1000) {
5009 device_printf(ch->dev, "channel HW reset timeout reset failure\n");
5010 ch->devices = 0;
5011 goto finish;
5012 }
5013 if (bootverbose)
5014 device_printf(ch->dev, "channel HW reset time=%dms\n", timeout * 1);
5015
5016 /* reset phy */
5017 if (!ata_sata_phy_reset(dev)) {
5018 if (bootverbose)
5019 device_printf(ch->dev, "phy reset found no device\n");
5020 ch->devices = 0;
5021 goto finish;
5022 }
5023
5024 /* get a piece of the workspace for a soft reset request */
5025 prb = (struct ata_siiprb_command *)
5026 (ch->dma->work + (sizeof(struct ata_siiprb_command) * tag));
5027 bzero(prb, sizeof(struct ata_siiprb_command));
5028 prb->control = htole16(0x0080);
5029
5030 /* activate the soft reset prb */
5031 prb_bus = ch->dma->work_bus + (sizeof(struct ata_siiprb_command) * tag);
5032 ATA_OUTL(ctlr->r_res2,
5033 0x1c00 + offset + (tag * sizeof(u_int64_t)), prb_bus);
5034 ATA_OUTL(ctlr->r_res2,
5035 0x1c04 + offset + (tag * sizeof(u_int64_t)), prb_bus>>32);
5036
5037 /* poll for channel ready */
5038 for (timeout = 0; timeout < 1000; timeout++) {
5039 DELAY(1000);
5040 if ((status = ATA_INL(ctlr->r_res2, 0x1008 + offset)) & 0x00010000)
5041 break;
5042 }
5043 if (timeout >= 1000) {
5044 device_printf(ch->dev, "reset timeout - no device found\n");
5045 ch->devices = 0;
5046 goto finish;
5047 }
5048 if (bootverbose)
5049 device_printf(ch->dev, "soft reset exec time=%dms status=%08x\n",
5050 timeout, status);
5051
5052 /* find out whats there */
5053 prb = (struct ata_siiprb_command *)
5054 ((u_int8_t *)rman_get_virtual(ctlr->r_res2) + (tag << 7) + offset);
5055 signature =
5056 prb->fis[12]|(prb->fis[4]<<8)|(prb->fis[5]<<16)|(prb->fis[6]<<24);
5057 if (bootverbose)
5058 device_printf(ch->dev, "signature=%08x\n", signature);
5059 switch (signature) {
5060 case 0xeb140101:
5061 ch->devices = ATA_ATAPI_MASTER;
5062 device_printf(ch->dev, "SATA ATAPI devices not supported yet\n");
5063 ch->devices = 0;
5064 break;
5065 case 0x96690101:
5066 ch->devices = ATA_PORTMULTIPLIER;
5067 device_printf(ch->dev, "Portmultipliers not supported yet\n");
5068 ch->devices = 0;
5069 break;
5070 case 0x00000101:
5071 ch->devices = ATA_ATA_MASTER;
5072 break;
5073 default:
5074 ch->devices = 0;
5075 }
5076
5077 finish:
5078 /* clear interrupt(s) */
5079 ATA_OUTL(ctlr->r_res2, 0x1008 + offset, 0x000008ff);
5080
5081 /* require explicit interrupt ack */
5082 ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x00000008);
5083
5084 /* 64bit mode */
5085 ATA_OUTL(ctlr->r_res2, 0x1004 + offset, 0x00000400);
5086
5087 /* enable interrupts wanted */
5088 ATA_OUTL(ctlr->r_res2, 0x1010 + offset, 0x000000ff);
5089 }
5090
5091 static void
5092 ata_siiprb_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error)
5093 {
5094 struct ata_dmasetprd_args *args = xsc;
5095 struct ata_siiprb_dma_prdentry *prd = args->dmatab;
5096 int i;
5097
5098 if ((args->error = error))
5099 return;
5100
5101 for (i = 0; i < nsegs; i++) {
5102 prd[i].addr = htole64(segs[i].ds_addr);
5103 prd[i].count = htole32(segs[i].ds_len);
5104 }
5105 prd[i - 1].control = htole32(ATA_DMA_EOT);
5106 }
5107
5108 static void
5109 ata_siiprb_dmainit(device_t dev)
5110 {
5111 struct ata_channel *ch = device_get_softc(dev);
5112
5113 ata_dmainit(dev);
5114 if (ch->dma) {
5115 /* note start and stop are not used here */
5116 ch->dma->setprd = ata_siiprb_dmasetprd;
5117 ch->dma->max_address = BUS_SPACE_MAXADDR;
5118 }
5119 }
5120
5121
5122 /*
5123 * Silicon Integrated Systems Corp. (SiS) chipset support functions
5124 */
5125 int
5126 ata_sis_ident(device_t dev)
5127 {
5128 struct ata_pci_controller *ctlr = device_get_softc(dev);
5129 struct ata_chip_id *idx;
5130 static struct ata_chip_id ids[] =
5131 {{ ATA_SIS182, 0x00, SISSATA, 0, ATA_SA150, "182" }, /* south */
5132 { ATA_SIS181, 0x00, SISSATA, 0, ATA_SA150, "181" }, /* south */
5133 { ATA_SIS180, 0x00, SISSATA, 0, ATA_SA150, "180" }, /* south */
5134 { ATA_SIS965, 0x00, SIS133NEW, 0, ATA_UDMA6, "965" }, /* south */
5135 { ATA_SIS964, 0x00, SIS133NEW, 0, ATA_UDMA6, "964" }, /* south */
5136 { ATA_SIS963, 0x00, SIS133NEW, 0, ATA_UDMA6, "963" }, /* south */
5137 { ATA_SIS962, 0x00, SIS133NEW, 0, ATA_UDMA6, "962" }, /* south */
5138
5139 { ATA_SIS745, 0x00, SIS100NEW, 0, ATA_UDMA5, "745" }, /* 1chip */
5140 { ATA_SIS735, 0x00, SIS100NEW, 0, ATA_UDMA5, "735" }, /* 1chip */
5141 { ATA_SIS733, 0x00, SIS100NEW, 0, ATA_UDMA5, "733" }, /* 1chip */
5142 { ATA_SIS730, 0x00, SIS100OLD, 0, ATA_UDMA5, "730" }, /* 1chip */
5143
5144 { ATA_SIS635, 0x00, SIS100NEW, 0, ATA_UDMA5, "635" }, /* 1chip */
5145 { ATA_SIS633, 0x00, SIS100NEW, 0, ATA_UDMA5, "633" }, /* unknown */
5146 { ATA_SIS630, 0x30, SIS100OLD, 0, ATA_UDMA5, "630S"}, /* 1chip */
5147 { ATA_SIS630, 0x00, SIS66, 0, ATA_UDMA4, "630" }, /* 1chip */
5148 { ATA_SIS620, 0x00, SIS66, 0, ATA_UDMA4, "620" }, /* 1chip */
5149
5150 { ATA_SIS550, 0x00, SIS66, 0, ATA_UDMA5, "550" },
5151 { ATA_SIS540, 0x00, SIS66, 0, ATA_UDMA4, "540" },
5152 { ATA_SIS530, 0x00, SIS66, 0, ATA_UDMA4, "530" },
5153
5154 { ATA_SIS5513, 0xc2, SIS33, 1, ATA_UDMA2, "5513" },
5155 { ATA_SIS5513, 0x00, SIS33, 1, ATA_WDMA2, "5513" },
5156 { 0, 0, 0, 0, 0, 0 }};
5157 char buffer[64];
5158 int found = 0;
5159
5160 if (!(idx = ata_find_chip(dev, ids, -pci_get_slot(dev))))
5161 return ENXIO;
5162
5163 if (idx->cfg2 && !found) {
5164 u_int8_t reg57 = pci_read_config(dev, 0x57, 1);
5165
5166 pci_write_config(dev, 0x57, (reg57 & 0x7f), 1);
5167 if (pci_read_config(dev, PCIR_DEVVENDOR, 4) == ATA_SIS5518) {
5168 found = 1;
5169 idx->cfg1 = SIS133NEW;
5170 idx->max_dma = ATA_UDMA6;
5171 ksprintf(buffer, "SiS 962/963 %s controller",
5172 ata_mode2str(idx->max_dma));
5173 }
5174 pci_write_config(dev, 0x57, reg57, 1);
5175 }
5176 if (idx->cfg2 && !found) {
5177 u_int8_t reg4a = pci_read_config(dev, 0x4a, 1);
5178
5179 pci_write_config(dev, 0x4a, (reg4a | 0x10), 1);
5180 if (pci_read_config(dev, PCIR_DEVVENDOR, 4) == ATA_SIS5517) {
5181 struct ata_chip_id id[] =
5182 {{ ATA_SISSOUTH, 0x10, 0, 0, 0, "" }, { 0, 0, 0, 0, 0, 0 }};
5183
5184 found = 1;
5185 if (ata_find_chip(dev, id, pci_get_slot(dev))) {
5186 idx->cfg1 = SIS133OLD;
5187 idx->max_dma = ATA_UDMA6;
5188 }
5189 else {
5190 idx->cfg1 = SIS100NEW;
5191 idx->max_dma = ATA_UDMA5;
5192 }
5193 ksprintf(buffer, "SiS 961 %s controller",ata_mode2str(idx->max_dma));
5194 }
5195 pci_write_config(dev, 0x4a, reg4a, 1);
5196 }
5197 if (!found)
5198 ksprintf(buffer,"SiS %s %s controller",
5199 idx->text, ata_mode2str(idx->max_dma));
5200
5201 device_set_desc_copy(dev, buffer);
5202 ctlr->chip = idx;
5203 ctlr->chipinit = ata_sis_chipinit;
5204 return 0;
5205 }
5206
5207 static int
5208 ata_sis_chipinit(device_t dev)
5209 {
5210 struct ata_pci_controller *ctlr = device_get_softc(dev);
5211
5212 if (ata_setup_interrupt(dev))
5213 return ENXIO;
5214
5215 switch (ctlr->chip->cfg1) {
5216 case SIS33:
5217 break;
5218 case SIS66:
5219 case SIS100OLD:
5220 pci_write_config(dev, 0x52, pci_read_config(dev, 0x52, 1) & ~0x04, 1);
5221 break;
5222 case SIS100NEW:
5223 case SIS133OLD:
5224 pci_write_config(dev, 0x49, pci_read_config(dev, 0x49, 1) & ~0x01, 1);
5225 break;
5226 case SIS133NEW:
5227 pci_write_config(dev, 0x50, pci_read_config(dev, 0x50, 2) | 0x0008, 2);
5228 pci_write_config(dev, 0x52, pci_read_config(dev, 0x52, 2) | 0x0008, 2);
5229 break;
5230 case SISSATA:
5231 ctlr->r_type2 = SYS_RES_IOPORT;
5232 ctlr->r_rid2 = PCIR_BAR(5);
5233 if ((ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
5234 &ctlr->r_rid2, RF_ACTIVE))) {
5235 ctlr->allocate = ata_sis_allocate;
5236 ctlr->reset = ata_sis_reset;
5237
5238 /* enable PCI interrupt */
5239 pci_write_config(dev, PCIR_COMMAND,
5240 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400,2);
5241 }
5242 ctlr->setmode = ata_sata_setmode;
5243 return 0;
5244 default:
5245 return ENXIO;
5246 }
5247 ctlr->setmode = ata_sis_setmode;
5248 return 0;
5249 }
5250
5251 static int
5252 ata_sis_allocate(device_t dev)
5253 {
5254 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
5255 struct ata_channel *ch = device_get_softc(dev);
5256 int offset = ch->unit << ((ctlr->chip->chipid == ATA_SIS182) ? 5 : 6);
5257
5258 /* setup the usual register normal pci style */
5259 if (ata_pci_allocate(dev))
5260 return ENXIO;
5261
5262 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2;
5263 ch->r_io[ATA_SSTATUS].offset = 0x00 + offset;
5264 ch->r_io[ATA_SERROR].res = ctlr->r_res2;
5265 ch->r_io[ATA_SERROR].offset = 0x04 + offset;
5266 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2;
5267 ch->r_io[ATA_SCONTROL].offset = 0x08 + offset;
5268 ch->flags |= ATA_NO_SLAVE;
5269
5270 /* XXX SOS PHY hotplug handling missing in SiS chip ?? */
5271 /* XXX SOS unknown how to enable PHY state change interrupt */
5272 return 0;
5273 }
5274
5275 static void
5276 ata_sis_reset(device_t dev)
5277 {
5278 if (ata_sata_phy_reset(dev))
5279 ata_generic_reset(dev);
5280 }
5281
5282 static void
5283 ata_sis_setmode(device_t dev, int mode)
5284 {
5285 device_t gparent = GRANDPARENT(dev);
5286 struct ata_pci_controller *ctlr = device_get_softc(gparent);
5287 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
5288 struct ata_device *atadev = device_get_softc(dev);
5289 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
5290 int error;
5291
5292 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma);
5293
5294 if (ctlr->chip->cfg1 == SIS133NEW) {
5295 if (mode > ATA_UDMA2 &&
5296 pci_read_config(gparent, ch->unit ? 0x52 : 0x50,2) & 0x8000) {
5297 ata_print_cable(dev, "controller");
5298 mode = ATA_UDMA2;
5299 }
5300 }
5301 else {
5302 if (mode > ATA_UDMA2 &&
5303 pci_read_config(gparent, 0x48, 1)&(ch->unit ? 0x20 : 0x10)) {
5304 ata_print_cable(dev, "controller");
5305 mode = ATA_UDMA2;
5306 }
5307 }
5308
5309 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
5310
5311 if (bootverbose)
5312 device_printf(dev, "%ssetting %s on %s chip\n",
5313 (error) ? "FAILURE " : "",
5314 ata_mode2str(mode), ctlr->chip->text);
5315 if (!error) {
5316 switch (ctlr->chip->cfg1) {
5317 case SIS133NEW: {
5318 u_int32_t timings[] =
5319 { 0x28269008, 0x0c266008, 0x04263008, 0x0c0a3008, 0x05093008,
5320 0x22196008, 0x0c0a3008, 0x05093008, 0x050939fc, 0x050936ac,
5321 0x0509347c, 0x0509325c, 0x0509323c, 0x0509322c, 0x0509321c};
5322 u_int32_t reg;
5323
5324 reg = (pci_read_config(gparent, 0x57, 1)&0x40?0x70:0x40)+(devno<<2);
5325 pci_write_config(gparent, reg, timings[ata_mode2idx(mode)], 4);
5326 break;
5327 }
5328 case SIS133OLD: {
5329 u_int16_t timings[] =
5330 { 0x00cb, 0x0067, 0x0044, 0x0033, 0x0031, 0x0044, 0x0033, 0x0031,
5331 0x8f31, 0x8a31, 0x8731, 0x8531, 0x8331, 0x8231, 0x8131 };
5332
5333 u_int16_t reg = 0x40 + (devno << 1);
5334
5335 pci_write_config(gparent, reg, timings[ata_mode2idx(mode)], 2);
5336 break;
5337 }
5338 case SIS100NEW: {
5339 u_int16_t timings[] =
5340 { 0x00cb, 0x0067, 0x0044, 0x0033, 0x0031, 0x0044, 0x0033,
5341 0x0031, 0x8b31, 0x8731, 0x8531, 0x8431, 0x8231, 0x8131 };
5342 u_int16_t reg = 0x40 + (devno << 1);
5343
5344 pci_write_config(gparent, reg, timings[ata_mode2idx(mode)], 2);
5345 break;
5346 }
5347 case SIS100OLD:
5348 case SIS66:
5349 case SIS33: {
5350 u_int16_t timings[] =
5351 { 0x0c0b, 0x0607, 0x0404, 0x0303, 0x0301, 0x0404, 0x0303,
5352 0x0301, 0xf301, 0xd301, 0xb301, 0xa301, 0x9301, 0x8301 };
5353 u_int16_t reg = 0x40 + (devno << 1);
5354
5355 pci_write_config(gparent, reg, timings[ata_mode2idx(mode)], 2);
5356 break;
5357 }
5358 }
5359 atadev->mode = mode;
5360 }
5361 }
5362
5363
5364 /* VIA Technologies Inc. chipset support functions */
5365 int
5366 ata_via_ident(device_t dev)
5367 {
5368 struct ata_pci_controller *ctlr = device_get_softc(dev);
5369 struct ata_chip_id *idx;
5370 static struct ata_chip_id ids[] =
5371 {{ ATA_VIA82C586, 0x02, VIA33, 0x00, ATA_UDMA2, "82C586B" },
5372 { ATA_VIA82C586, 0x00, VIA33, 0x00, ATA_WDMA2, "82C586" },
5373 { ATA_VIA82C596, 0x12, VIA66, VIACLK, ATA_UDMA4, "82C596B" },
5374 { ATA_VIA82C596, 0x00, VIA33, 0x00, ATA_UDMA2, "82C596" },
5375 { ATA_VIA82C686, 0x40, VIA100, VIABUG, ATA_UDMA5, "82C686B"},
5376 { ATA_VIA82C686, 0x10, VIA66, VIACLK, ATA_UDMA4, "82C686A" },
5377 { ATA_VIA82C686, 0x00, VIA33, 0x00, ATA_UDMA2, "82C686" },
5378 { ATA_VIA8231, 0x00, VIA100, VIABUG, ATA_UDMA5, "8231" },
5379 { ATA_VIA8233, 0x00, VIA100, 0x00, ATA_UDMA5, "8233" },
5380 { ATA_VIA8233C, 0x00, VIA100, 0x00, ATA_UDMA5, "8233C" },
5381 { ATA_VIA8233A, 0x00, VIA133, 0x00, ATA_UDMA6, "8233A" },
5382 { ATA_VIA8235, 0x00, VIA133, 0x00, ATA_UDMA6, "8235" },
5383 { ATA_VIA8237, 0x00, VIA133, 0x00, ATA_UDMA6, "8237" },
5384 { ATA_VIA8237A, 0x00, VIA133, 0x00, ATA_UDMA6, "8237A" },
5385 { ATA_VIA8251, 0x00, VIA133, 0x00, ATA_UDMA6, "8251" },
5386 { 0, 0, 0, 0, 0, 0 }};
5387 static struct ata_chip_id new_ids[] =
5388 {{ ATA_VIA6410, 0x00, 0, 0x00, ATA_UDMA6, "6410" },
5389 { ATA_VIA6420, 0x00, 7, 0x00, ATA_SA150, "6420" },
5390 { ATA_VIA6421, 0x00, 6, VIABAR, ATA_SA150, "6421" },
5391 { ATA_VIA8237A, 0x00, 7, 0x00, ATA_SA150, "8237A" },
5392 { ATA_VIA8237S, 0x00, 7, 0x00, ATA_SA150, "8237S" },
5393 { ATA_VIA8251, 0x00, 0, VIAAHCI, ATA_SA300, "8251" },
5394 { 0, 0, 0, 0, 0, 0 }};
5395 char buffer[64];
5396
5397 if (pci_get_devid(dev) == ATA_VIA82C571) {
5398 if (!(idx = ata_find_chip(dev, ids, -99)))
5399 return ENXIO;
5400 }
5401 else {
5402 if (!(idx = ata_match_chip(dev, new_ids)))
5403 return ENXIO;
5404 }
5405
5406 ksprintf(buffer, "VIA %s %s controller",
5407 idx->text, ata_mode2str(idx->max_dma));
5408 device_set_desc_copy(dev, buffer);
5409 ctlr->chip = idx;
5410 ctlr->chipinit = ata_via_chipinit;
5411 return 0;
5412 }
5413
5414 static int
5415 ata_via_chipinit(device_t dev)
5416 {
5417 struct ata_pci_controller *ctlr = device_get_softc(dev);
5418
5419 if (ata_setup_interrupt(dev))
5420 return ENXIO;
5421
5422 if (ctlr->chip->max_dma >= ATA_SA150) {
5423 /* do we have AHCI capability ? */
5424 if ((ctlr->chip->cfg2 == VIAAHCI) && ata_ahci_chipinit(dev) != ENXIO)
5425 return 0;
5426
5427 ctlr->r_type2 = SYS_RES_IOPORT;
5428 ctlr->r_rid2 = PCIR_BAR(5);
5429 if ((ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
5430 &ctlr->r_rid2, RF_ACTIVE))) {
5431 ctlr->allocate = ata_via_allocate;
5432 ctlr->reset = ata_via_reset;
5433
5434 /* enable PCI interrupt */
5435 pci_write_config(dev, PCIR_COMMAND,
5436 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400,2);
5437 }
5438
5439 if (ctlr->chip->cfg2 & VIABAR) {
5440 ctlr->channels = 3;
5441 ctlr->setmode = ata_via_setmode;
5442 }
5443 else
5444 ctlr->setmode = ata_sata_setmode;
5445 return 0;
5446 }
5447
5448 /* prepare for ATA-66 on the 82C686a and 82C596b */
5449 if (ctlr->chip->cfg2 & VIACLK)
5450 pci_write_config(dev, 0x50, 0x030b030b, 4);
5451
5452 /* the southbridge might need the data corruption fix */
5453 if (ctlr->chip->cfg2 & VIABUG)
5454 ata_via_southbridge_fixup(dev);
5455
5456 /* set fifo configuration half'n'half */
5457 pci_write_config(dev, 0x43,
5458 (pci_read_config(dev, 0x43, 1) & 0x90) | 0x2a, 1);
5459
5460 /* set status register read retry */
5461 pci_write_config(dev, 0x44, pci_read_config(dev, 0x44, 1) | 0x08, 1);
5462
5463 /* set DMA read & end-of-sector fifo flush */
5464 pci_write_config(dev, 0x46,
5465 (pci_read_config(dev, 0x46, 1) & 0x0c) | 0xf0, 1);
5466
5467 /* set sector size */
5468 pci_write_config(dev, 0x60, DEV_BSIZE, 2);
5469 pci_write_config(dev, 0x68, DEV_BSIZE, 2);
5470
5471 ctlr->setmode = ata_via_family_setmode;
5472 return 0;
5473 }
5474
5475 static int
5476 ata_via_allocate(device_t dev)
5477 {
5478 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
5479 struct ata_channel *ch = device_get_softc(dev);
5480
5481 /* newer SATA chips has resources in one BAR for each channel */
5482 if (ctlr->chip->cfg2 & VIABAR) {
5483 struct resource *r_io;
5484 int i, rid;
5485
5486 rid = PCIR_BAR(ch->unit);
5487 if (!(r_io = bus_alloc_resource_any(device_get_parent(dev),
5488 SYS_RES_IOPORT,
5489 &rid, RF_ACTIVE)))
5490 return ENXIO;
5491
5492 for (i = ATA_DATA; i <= ATA_COMMAND; i ++) {
5493 ch->r_io[i].res = r_io;
5494 ch->r_io[i].offset = i;
5495 }
5496 ch->r_io[ATA_CONTROL].res = r_io;
5497 ch->r_io[ATA_CONTROL].offset = 2 + ATA_IOSIZE;
5498 ch->r_io[ATA_IDX_ADDR].res = r_io;
5499 ata_default_registers(dev);
5500 for (i = ATA_BMCMD_PORT; i <= ATA_BMDTP_PORT; i++) {
5501 ch->r_io[i].res = ctlr->r_res1;
5502 ch->r_io[i].offset = (i - ATA_BMCMD_PORT)+(ch->unit * ATA_BMIOSIZE);
5503 }
5504 ata_pci_hw(dev);
5505 if (ch->unit >= 2)
5506 return 0;
5507 }
5508 else {
5509 /* setup the usual register normal pci style */
5510 if (ata_pci_allocate(dev))
5511 return ENXIO;
5512 }
5513
5514 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2;
5515 ch->r_io[ATA_SSTATUS].offset = (ch->unit << ctlr->chip->cfg1);
5516 ch->r_io[ATA_SERROR].res = ctlr->r_res2;
5517 ch->r_io[ATA_SERROR].offset = 0x04 + (ch->unit << ctlr->chip->cfg1);
5518 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2;
5519 ch->r_io[ATA_SCONTROL].offset = 0x08 + (ch->unit << ctlr->chip->cfg1);
5520 ch->flags |= ATA_NO_SLAVE;
5521
5522 /* XXX SOS PHY hotplug handling missing in VIA chip ?? */
5523 /* XXX SOS unknown how to enable PHY state change interrupt */
5524 return 0;
5525 }
5526
5527 static void
5528 ata_via_reset(device_t dev)
5529 {
5530 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
5531 struct ata_channel *ch = device_get_softc(dev);
5532
5533 if ((ctlr->chip->cfg2 & VIABAR) && (ch->unit > 1))
5534 ata_generic_reset(dev);
5535 else
5536 if (ata_sata_phy_reset(dev))
5537 ata_generic_reset(dev);
5538 }
5539
5540 static void
5541 ata_via_setmode(device_t dev, int mode)
5542 {
5543 device_t gparent = GRANDPARENT(dev);
5544 struct ata_pci_controller *ctlr = device_get_softc(gparent);
5545 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
5546 struct ata_device *atadev = device_get_softc(dev);
5547 int error;
5548
5549 if ((ctlr->chip->cfg2 & VIABAR) && (ch->unit > 1)) {
5550 u_int8_t pio_timings[] = { 0xa8, 0x65, 0x65, 0x32, 0x20,
5551 0x65, 0x32, 0x20,
5552 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20 };
5553 u_int8_t dma_timings[] = { 0xee, 0xe8, 0xe6, 0xe4, 0xe2, 0xe1, 0xe0 };
5554
5555 mode = ata_check_80pin(dev, ata_limit_mode(dev, mode, ATA_UDMA6));
5556 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
5557 if (bootverbose)
5558 device_printf(dev, "%ssetting %s on %s chip\n",
5559 (error) ? "FAILURE " : "", ata_mode2str(mode),
5560 ctlr->chip->text);
5561 if (!error) {
5562 pci_write_config(gparent, 0xab, pio_timings[ata_mode2idx(mode)], 1);
5563 if (mode >= ATA_UDMA0)
5564 pci_write_config(gparent, 0xb3,
5565 dma_timings[mode & ATA_MODE_MASK], 1);
5566 atadev->mode = mode;
5567 }
5568 }
5569 else
5570 ata_sata_setmode(dev, mode);
5571 }
5572
5573 static void
5574 ata_via_southbridge_fixup(device_t dev)
5575 {
5576 device_t *children;
5577 int nchildren, i;
5578
5579 if (device_get_children(device_get_parent(dev), &children, &nchildren))
5580 return;
5581
5582 for (i = 0; i < nchildren; i++) {
5583 if (pci_get_devid(children[i]) == ATA_VIA8363 ||
5584 pci_get_devid(children[i]) == ATA_VIA8371 ||
5585 pci_get_devid(children[i]) == ATA_VIA8662 ||
5586 pci_get_devid(children[i]) == ATA_VIA8361) {
5587 u_int8_t reg76 = pci_read_config(children[i], 0x76, 1);
5588
5589 if ((reg76 & 0xf0) != 0xd0) {
5590 device_printf(dev,
5591 "Correcting VIA config for southbridge data corruption bug\n");
5592 pci_write_config(children[i], 0x75, 0x80, 1);
5593 pci_write_config(children[i], 0x76, (reg76 & 0x0f) | 0xd0, 1);
5594 }
5595 break;
5596 }
5597 }
5598 kfree(children, M_TEMP);
5599 }
5600
5601
5602 /* common code for VIA, AMD & nVidia */
5603 static void
5604 ata_via_family_setmode(device_t dev, int mode)
5605 {
5606 device_t gparent = GRANDPARENT(dev);
5607 struct ata_pci_controller *ctlr = device_get_softc(gparent);
5608 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
5609 struct ata_device *atadev = device_get_softc(dev);
5610 u_int8_t timings[] = { 0xa8, 0x65, 0x42, 0x22, 0x20, 0x42, 0x22, 0x20,
5611 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20 };
5612 int modes[][7] = {
5613 { 0xc2, 0xc1, 0xc0, 0x00, 0x00, 0x00, 0x00 }, /* VIA ATA33 */
5614 { 0xee, 0xec, 0xea, 0xe9, 0xe8, 0x00, 0x00 }, /* VIA ATA66 */
5615 { 0xf7, 0xf6, 0xf4, 0xf2, 0xf1, 0xf0, 0x00 }, /* VIA ATA100 */
5616 { 0xf7, 0xf7, 0xf6, 0xf4, 0xf2, 0xf1, 0xf0 }, /* VIA ATA133 */
5617 { 0xc2, 0xc1, 0xc0, 0xc4, 0xc5, 0xc6, 0xc7 }}; /* AMD/nVIDIA */
5618 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
5619 int reg = 0x53 - devno;
5620 int error;
5621
5622 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma);
5623
5624 if (ctlr->chip->cfg2 & AMDCABLE) {
5625 if (mode > ATA_UDMA2 &&
5626 !(pci_read_config(gparent, 0x42, 1) & (1 << devno))) {
5627 ata_print_cable(dev, "controller");
5628 mode = ATA_UDMA2;
5629 }
5630 }
5631 else
5632 mode = ata_check_80pin(dev, mode);
5633
5634 if (ctlr->chip->cfg2 & NVIDIA)
5635 reg += 0x10;
5636
5637 if (ctlr->chip->cfg1 != VIA133)
5638 pci_write_config(gparent, reg - 0x08, timings[ata_mode2idx(mode)], 1);
5639
5640 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
5641
5642 if (bootverbose)
5643 device_printf(dev, "%ssetting %s on %s chip\n",
5644 (error) ? "FAILURE " : "", ata_mode2str(mode),
5645 ctlr->chip->text);
5646 if (!error) {
5647 if (mode >= ATA_UDMA0)
5648 pci_write_config(gparent, reg,
5649 modes[ctlr->chip->cfg1][mode & ATA_MODE_MASK], 1);
5650 else
5651 pci_write_config(gparent, reg, 0x8b, 1);
5652 atadev->mode = mode;
5653 }
5654 }
5655
5656
5657 /* misc functions */
5658 static struct ata_chip_id *
5659 ata_match_chip(device_t dev, struct ata_chip_id *index)
5660 {
5661 while (index->chipid != 0) {
5662 if (pci_get_devid(dev) == index->chipid &&
5663 pci_get_revid(dev) >= index->chiprev)
5664 return index;
5665 index++;
5666 }
5667 return NULL;
5668 }
5669
5670 static struct ata_chip_id *
5671 ata_find_chip(device_t dev, struct ata_chip_id *index, int slot)
5672 {
5673 device_t *children;
5674 int nchildren, i;
5675
5676 if (device_get_children(device_get_parent(dev), &children, &nchildren))
5677 return 0;
5678
5679 while (index->chipid != 0) {
5680 for (i = 0; i < nchildren; i++) {
5681 if (((slot >= 0 && pci_get_slot(children[i]) == slot) ||
5682 (slot < 0 && pci_get_slot(children[i]) <= -slot)) &&
5683 pci_get_devid(children[i]) == index->chipid &&
5684 pci_get_revid(children[i]) >= index->chiprev) {
5685 kfree(children, M_TEMP);
5686 return index;
5687 }
5688 }
5689 index++;
5690 }
5691 kfree(children, M_TEMP);
5692 return NULL;
5693 }
5694
5695 static int
5696 ata_setup_interrupt(device_t dev)
5697 {
5698 struct ata_pci_controller *ctlr = device_get_softc(dev);
5699 int rid = ATA_IRQ_RID;
5700
5701 if (!ata_legacy(dev)) {
5702 if (!(ctlr->r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
5703 RF_SHAREABLE | RF_ACTIVE))) {
5704 device_printf(dev, "unable to map interrupt\n");
5705 return ENXIO;
5706 }
5707 if ((bus_setup_intr(dev, ctlr->r_irq, ATA_INTR_FLAGS,
5708 ata_generic_intr, ctlr, &ctlr->handle, NULL))) {
5709 device_printf(dev, "unable to setup interrupt\n");
5710 return ENXIO;
5711 }
5712 }
5713 return 0;
5714 }
5715
5716 struct ata_serialize {
5717 struct spinlock locked_mtx;
5718 int locked_ch;
5719 int restart_ch;
5720 };
5721
5722 static int
5723 ata_serialize(device_t dev, int flags)
5724 {
5725 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
5726 struct ata_channel *ch = device_get_softc(dev);
5727 struct ata_serialize *serial;
5728 static int inited = 0;
5729 int res;
5730
5731 if (!inited) {
5732 serial = kmalloc(sizeof(struct ata_serialize),
5733 M_TEMP, M_INTWAIT | M_ZERO);
5734 spin_init(&serial->locked_mtx);
5735 serial->locked_ch = -1;
5736 serial->restart_ch = -1;
5737 device_set_ivars(ctlr->dev, serial);
5738 inited = 1;
5739 }
5740 else
5741 serial = device_get_ivars(ctlr->dev);
5742
5743 spin_lock_wr(&serial->locked_mtx);
5744 switch (flags) {
5745 case ATA_LF_LOCK:
5746 if (serial->locked_ch == -1)
5747 serial->locked_ch = ch->unit;
5748 if (serial->locked_ch != ch->unit)
5749 serial->restart_ch = ch->unit;
5750 break;
5751
5752 case ATA_LF_UNLOCK:
5753 if (serial->locked_ch == ch->unit) {
5754 serial->locked_ch = -1;
5755 if (serial->restart_ch != -1) {
5756 if ((ch = ctlr->interrupt[serial->restart_ch].argument)) {
5757 serial->restart_ch = -1;
5758 spin_unlock_wr(&serial->locked_mtx);
5759 ata_start(ch->dev);
5760 return -1;
5761 }
5762 }
5763 }
5764 break;
5765
5766 case ATA_LF_WHICH:
5767 break;
5768 }
5769 res = serial->locked_ch;
5770 spin_unlock_wr(&serial->locked_mtx);
5771 return res;
5772 }
5773
5774 static void
5775 ata_print_cable(device_t dev, u_int8_t *who)
5776 {
5777 device_printf(dev,
5778 "DMA limited to UDMA33, %s found non-ATA66 cable\n", who);
5779 }
5780
5781 static int
5782 ata_atapi(device_t dev)
5783 {
5784 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
5785 struct ata_device *atadev = device_get_softc(dev);
5786
5787 return ((atadev->unit == ATA_MASTER && ch->devices & ATA_ATAPI_MASTER) ||
5788 (atadev->unit == ATA_SLAVE && ch->devices & ATA_ATAPI_SLAVE));
5789 }
5790
5791 static int
5792 ata_check_80pin(device_t dev, int mode)
5793 {
5794 struct ata_device *atadev = device_get_softc(dev);
5795
5796 if (mode > ATA_UDMA2 && !(atadev->param.hwres & ATA_CABLE_ID)) {
5797 ata_print_cable(dev, "device");
5798 mode = ATA_UDMA2;
5799 }
5800 return mode;
5801 }
5802
5803 static int
5804 ata_mode2idx(int mode)
5805 {
5806 if ((mode & ATA_DMA_MASK) == ATA_UDMA0)
5807 return (mode & ATA_MODE_MASK) + 8;
5808 if ((mode & ATA_DMA_MASK) == ATA_WDMA0)
5809 return (mode & ATA_MODE_MASK) + 5;
5810 return (mode & ATA_MODE_MASK) - ATA_PIO0;
5811 }
DragonFly BSD