?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
fix typo in previous commit
[dragonfly.git] / sys / platform / pc64 / isa / npx.c
blob666b495bc65366429d25c32ccb597646caefda32
1 /*-
2 * Copyright (c) 1990 William Jolitz.
3 * Copyright (c) 1991 The Regents of the University of California.
4 * Copyright (c) 2008 The DragonFly Project.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. All advertising materials mentioning features or use of this software
16 * must display the following acknowledgement:
17 * This product includes software developed by the University of
18 * California, Berkeley and its contributors.
19 * 4. Neither the name of the University nor the names of its contributors
20 * may be used to endorse or promote products derived from this software
21 * without specific prior written permission.
22 *
23 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
26 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
27 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
29 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33 * SUCH DAMAGE.
34 *
35 * from: @(#)npx.c 7.2 (Berkeley) 5/12/91
36 * $FreeBSD: src/sys/i386/isa/npx.c,v 1.80.2.3 2001/10/20 19:04:38 tegge Exp $
37 * $DragonFly: src/sys/platform/pc64/isa/npx.c,v 1.1 2008/08/29 17:07:19 dillon Exp $
38 */
39
40 #include "opt_cpu.h"
41 #include "opt_debug_npx.h"
42 #include "opt_math_emulate.h"
43
44 #include <sys/param.h>
45 #include <sys/systm.h>
46 #include <sys/bus.h>
47 #include <sys/kernel.h>
48 #include <sys/malloc.h>
49 #include <sys/module.h>
50 #include <sys/sysctl.h>
51 #include <sys/proc.h>
52 #include <sys/rman.h>
53 #ifdef NPX_DEBUG
54 #include <sys/syslog.h>
55 #endif
56 #include <sys/signalvar.h>
57
58 #include <sys/thread2.h>
59 #include <sys/mplock2.h>
60
61 #ifndef SMP
62 #include <machine/asmacros.h>
63 #endif
64 #include <machine/cputypes.h>
65 #include <machine/frame.h>
66 #include <machine/ipl.h>
67 #include <machine/md_var.h>
68 #include <machine/pcb.h>
69 #include <machine/psl.h>
70 #ifndef SMP
71 #include <machine/clock.h>
72 #endif
73 #include <machine/specialreg.h>
74 #include <machine/segments.h>
75 #include <machine/globaldata.h>
76
77 #ifndef SMP
78 #include <machine_base/icu/icu.h>
79 #include <machine_base/isa/intr_machdep.h>
80 #include <bus/isa/isa.h>
81 #endif
82
83 /*
84 * 387 and 287 Numeric Coprocessor Extension (NPX) Driver.
85 */
86
87 /* Configuration flags. */
88 #define NPX_DISABLE_I586_OPTIMIZED_BCOPY (1 << 0)
89 #define NPX_DISABLE_I586_OPTIMIZED_BZERO (1 << 1)
90 #define NPX_DISABLE_I586_OPTIMIZED_COPYIO (1 << 2)
91 #define NPX_PREFER_EMULATOR (1 << 3)
92
93 #ifdef __GNUC__
94
95 #define fldcw(addr) __asm("fldcw %0" : : "m" (*(addr)))
96 #define fnclex() __asm("fnclex")
97 #define fninit() __asm("fninit")
98 #define fnop() __asm("fnop")
99 #define fnsave(addr) __asm __volatile("fnsave %0" : "=m" (*(addr)))
100 #define fnstcw(addr) __asm __volatile("fnstcw %0" : "=m" (*(addr)))
101 #define fnstsw(addr) __asm __volatile("fnstsw %0" : "=m" (*(addr)))
102 #define fp_divide_by_0() __asm("fldz; fld1; fdiv %st,%st(1); fnop")
103 #define frstor(addr) __asm("frstor %0" : : "m" (*(addr)))
104 #ifndef CPU_DISABLE_SSE
105 #define fxrstor(addr) __asm("fxrstor %0" : : "m" (*(addr)))
106 #define fxsave(addr) __asm __volatile("fxsave %0" : "=m" (*(addr)))
107 #endif
108 #define start_emulating() __asm("smsw %%ax; orb %0,%%al; lmsw %%ax" \
109 : : "n" (CR0_TS) : "ax")
110 #define stop_emulating() __asm("clts")
111
112 #else /* not __GNUC__ */
113
114 void fldcw (caddr_t addr);
115 void fnclex (void);
116 void fninit (void);
117 void fnop (void);
118 void fnsave (caddr_t addr);
119 void fnstcw (caddr_t addr);
120 void fnstsw (caddr_t addr);
121 void fp_divide_by_0 (void);
122 void frstor (caddr_t addr);
123 #ifndef CPU_DISABLE_SSE
124 void fxsave (caddr_t addr);
125 void fxrstor (caddr_t addr);
126 #endif
127 void start_emulating (void);
128 void stop_emulating (void);
129
130 #endif /* __GNUC__ */
131
132 #ifndef CPU_DISABLE_SSE
133 #define GET_FPU_EXSW_PTR(td) \
134 (cpu_fxsr ? \
135 &(td)->td_savefpu->sv_xmm.sv_ex_sw : \
136 &(td)->td_savefpu->sv_87.sv_ex_sw)
137 #else /* CPU_DISABLE_SSE */
138 #define GET_FPU_EXSW_PTR(td) \
139 (&(td)->td_savefpu->sv_87.sv_ex_sw)
140 #endif /* CPU_DISABLE_SSE */
141
142 typedef u_char bool_t;
143 #ifndef CPU_DISABLE_SSE
144 static void fpu_clean_state(void);
145 #endif
146
147
148 static int npx_attach (device_t dev);
149 void npx_intr (void *);
150 static int npx_probe (device_t dev);
151 static int npx_probe1 (device_t dev);
152 static void fpusave (union savefpu *);
153 static void fpurstor (union savefpu *);
154
155 int hw_float; /* XXX currently just alias for npx_exists */
156
157 extern int bzeront_avail;
158
159 SYSCTL_INT(_hw,HW_FLOATINGPT, floatingpoint,
160 CTLFLAG_RD, &hw_float, 0,
161 "Floatingpoint instructions executed in hardware");
162 #if (defined(I586_CPU) || defined(I686_CPU)) && !defined(CPU_DISABLE_SSE)
163 int mmxopt = 1;
164 SYSCTL_INT(_kern, OID_AUTO, mmxopt, CTLFLAG_RD, &mmxopt, 0,
165 "MMX/XMM optimized bcopy/copyin/copyout support");
166 #endif
167
168 #ifndef SMP
169 static u_int npx0_imask;
170 static struct gate_descriptor npx_idt_probeintr;
171 static int npx_intrno;
172 static volatile u_int npx_intrs_while_probing;
173 static volatile u_int npx_traps_while_probing;
174 #endif
175
176 static bool_t npx_ex16;
177 static bool_t npx_exists;
178 static bool_t npx_irq13;
179 static int npx_irq; /* irq number */
180
181 #ifndef SMP
182 /*
183 * Special interrupt handlers. Someday intr0-intr15 will be used to count
184 * interrupts. We'll still need a special exception 16 handler. The busy
185 * latch stuff in probeintr() can be moved to npxprobe().
186 */
187 inthand_t probeintr;
188 __asm(" \n\
189 .text \n\
190 .p2align 2,0x90 \n\
191 .type " __XSTRING(CNAME(probeintr)) ",@function \n\
192 " __XSTRING(CNAME(probeintr)) ": \n\
193 ss \n\
194 incl " __XSTRING(CNAME(npx_intrs_while_probing)) " \n\
195 pushl %eax \n\
196 movb $0x20,%al # EOI (asm in strings loses cpp features) \n\
197 outb %al,$0xa0 # IO_ICU2 \n\
198 outb %al,$0x20 # IO_ICU1 \n\
199 movb $0,%al \n\
200 outb %al,$0xf0 # clear BUSY# latch \n\
201 popl %eax \n\
202 iret \n\
203 ");
204
205 inthand_t probetrap;
206 __asm(" \n\
207 .text \n\
208 .p2align 2,0x90 \n\
209 .type " __XSTRING(CNAME(probetrap)) ",@function \n\
210 " __XSTRING(CNAME(probetrap)) ": \n\
211 ss \n\
212 incl " __XSTRING(CNAME(npx_traps_while_probing)) " \n\
213 fnclex \n\
214 iret \n\
215 ");
216 #endif /* SMP */
217
218 static struct krate badfprate = { 1 };
219
220 /*
221 * Probe routine. Initialize cr0 to give correct behaviour for [f]wait
222 * whether the device exists or not (XXX should be elsewhere). Set flags
223 * to tell npxattach() what to do. Modify device struct if npx doesn't
224 * need to use interrupts. Return 1 if device exists.
225 */
226 static int
227 npx_probe(device_t dev)
228 {
229 #ifdef SMP
230
231 if (resource_int_value("npx", 0, "irq", &npx_irq) != 0)
232 npx_irq = 13;
233 return npx_probe1(dev);
234
235 #else /* SMP */
236
237 int result;
238 u_long save_eflags;
239 u_char save_icu1_mask;
240 u_char save_icu2_mask;
241 struct gate_descriptor save_idt_npxintr;
242 struct gate_descriptor save_idt_npxtrap;
243 /*
244 * This routine is now just a wrapper for npxprobe1(), to install
245 * special npx interrupt and trap handlers, to enable npx interrupts
246 * and to disable other interrupts. Someday isa_configure() will
247 * install suitable handlers and run with interrupts enabled so we
248 * won't need to do so much here.
249 */
250 if (resource_int_value("npx", 0, "irq", &npx_irq) != 0)
251 npx_irq = 13;
252 npx_intrno = IDT_OFFSET + npx_irq;
253 save_eflags = read_eflags();
254 cpu_disable_intr();
255 save_icu1_mask = inb(IO_ICU1 + 1);
256 save_icu2_mask = inb(IO_ICU2 + 1);
257 save_idt_npxintr = idt[npx_intrno];
258 save_idt_npxtrap = idt[16];
259 outb(IO_ICU1 + 1, ~(1 << ICU_IRQ_SLAVE));
260 outb(IO_ICU2 + 1, ~(1 << (npx_irq - 8)));
261 setidt(16, probetrap, SDT_SYS386TGT, SEL_KPL, 0);
262 setidt(npx_intrno, probeintr, SDT_SYS386IGT, SEL_KPL, 0);
263 npx_idt_probeintr = idt[npx_intrno];
264 cpu_enable_intr();
265 result = npx_probe1(dev);
266 cpu_disable_intr();
267 outb(IO_ICU1 + 1, save_icu1_mask);
268 outb(IO_ICU2 + 1, save_icu2_mask);
269 idt[npx_intrno] = save_idt_npxintr;
270 idt[16] = save_idt_npxtrap;
271 write_eflags(save_eflags);
272 return (result);
273
274 #endif /* SMP */
275 }
276
277 static int
278 npx_probe1(device_t dev)
279 {
280 #ifndef SMP
281 u_short control;
282 u_short status;
283 #endif
284
285 /*
286 * Partially reset the coprocessor, if any. Some BIOS's don't reset
287 * it after a warm boot.
288 */
289 outb(0xf1, 0); /* full reset on some systems, NOP on others */
290 outb(0xf0, 0); /* clear BUSY# latch */
291 /*
292 * Prepare to trap all ESC (i.e., NPX) instructions and all WAIT
293 * instructions. We must set the CR0_MP bit and use the CR0_TS
294 * bit to control the trap, because setting the CR0_EM bit does
295 * not cause WAIT instructions to trap. It's important to trap
296 * WAIT instructions - otherwise the "wait" variants of no-wait
297 * control instructions would degenerate to the "no-wait" variants
298 * after FP context switches but work correctly otherwise. It's
299 * particularly important to trap WAITs when there is no NPX -
300 * otherwise the "wait" variants would always degenerate.
301 *
302 * Try setting CR0_NE to get correct error reporting on 486DX's.
303 * Setting it should fail or do nothing on lesser processors.
304 */
305 load_cr0(rcr0() | CR0_MP | CR0_NE);
306 /*
307 * But don't trap while we're probing.
308 */
309 stop_emulating();
310 /*
311 * Finish resetting the coprocessor, if any. If there is an error
312 * pending, then we may get a bogus IRQ13, but probeintr() will handle
313 * it OK. Bogus halts have never been observed, but we enabled
314 * IRQ13 and cleared the BUSY# latch early to handle them anyway.
315 */
316 fninit();
317
318 #ifdef SMP
319 /*
320 * Exception 16 MUST work for SMP.
321 */
322 npx_irq13 = 0;
323 npx_ex16 = hw_float = npx_exists = 1;
324 device_set_desc(dev, "math processor");
325 return (0);
326
327 #else /* !SMP */
328 device_set_desc(dev, "math processor");
329
330 /*
331 * Don't use fwait here because it might hang.
332 * Don't use fnop here because it usually hangs if there is no FPU.
333 */
334 DELAY(1000); /* wait for any IRQ13 */
335 #ifdef DIAGNOSTIC
336 if (npx_intrs_while_probing != 0)
337 kprintf("fninit caused %u bogus npx interrupt(s)\n",
338 npx_intrs_while_probing);
339 if (npx_traps_while_probing != 0)
340 kprintf("fninit caused %u bogus npx trap(s)\n",
341 npx_traps_while_probing);
342 #endif
343 /*
344 * Check for a status of mostly zero.
345 */
346 status = 0x5a5a;
347 fnstsw(&status);
348 if ((status & 0xb8ff) == 0) {
349 /*
350 * Good, now check for a proper control word.
351 */
352 control = 0x5a5a;
353 fnstcw(&control);
354 if ((control & 0x1f3f) == 0x033f) {
355 hw_float = npx_exists = 1;
356 /*
357 * We have an npx, now divide by 0 to see if exception
358 * 16 works.
359 */
360 control &= ~(1 << 2); /* enable divide by 0 trap */
361 fldcw(&control);
362 npx_traps_while_probing = npx_intrs_while_probing = 0;
363 fp_divide_by_0();
364 if (npx_traps_while_probing != 0) {
365 /*
366 * Good, exception 16 works.
367 */
368 npx_ex16 = 1;
369 return (0);
370 }
371 if (npx_intrs_while_probing != 0) {
372 int rid;
373 struct resource *r;
374 void *intr;
375 /*
376 * Bad, we are stuck with IRQ13.
377 */
378 npx_irq13 = 1;
379 /*
380 * npxattach would be too late to set npx0_imask
381 */
382 npx0_imask |= (1 << npx_irq);
383
384 /*
385 * We allocate these resources permanently,
386 * so there is no need to keep track of them.
387 */
388 rid = 0;
389 r = bus_alloc_resource(dev, SYS_RES_IOPORT,
390 &rid, IO_NPX, IO_NPX,
391 IO_NPXSIZE, RF_ACTIVE);
392 if (r == 0)
393 panic("npx: can't get ports");
394 rid = 0;
395 r = bus_alloc_resource(dev, SYS_RES_IRQ,
396 &rid, npx_irq, npx_irq,
397 1, RF_ACTIVE);
398 if (r == 0)
399 panic("npx: can't get IRQ");
400 BUS_SETUP_INTR(device_get_parent(dev),
401 dev, r, 0,
402 npx_intr, 0, &intr, NULL);
403 if (intr == 0)
404 panic("npx: can't create intr");
405
406 return (0);
407 }
408 /*
409 * Worse, even IRQ13 is broken. Use emulator.
410 */
411 }
412 }
413 /*
414 * Probe failed, but we want to get to npxattach to initialize the
415 * emulator and say that it has been installed. XXX handle devices
416 * that aren't really devices better.
417 */
418 return (0);
419 #endif /* SMP */
420 }
421
422 /*
423 * Attach routine - announce which it is, and wire into system
424 */
425 int
426 npx_attach(device_t dev)
427 {
428 int flags;
429
430 if (resource_int_value("npx", 0, "flags", &flags) != 0)
431 flags = 0;
432
433 if (flags)
434 device_printf(dev, "flags 0x%x ", flags);
435 if (npx_irq13) {
436 device_printf(dev, "using IRQ 13 interface\n");
437 } else {
438 #if defined(MATH_EMULATE)
439 if (npx_ex16) {
440 if (!(flags & NPX_PREFER_EMULATOR))
441 device_printf(dev, "INT 16 interface\n");
442 else {
443 device_printf(dev, "FPU exists, but flags request "
444 "emulator\n");
445 hw_float = npx_exists = 0;
446 }
447 } else if (npx_exists) {
448 device_printf(dev, "error reporting broken; using 387 emulator\n");
449 hw_float = npx_exists = 0;
450 } else
451 device_printf(dev, "387 emulator\n");
452 #else
453 if (npx_ex16) {
454 device_printf(dev, "INT 16 interface\n");
455 if (flags & NPX_PREFER_EMULATOR) {
456 device_printf(dev, "emulator requested, but none compiled "
457 "into kernel, using FPU\n");
458 }
459 } else
460 device_printf(dev, "no 387 emulator in kernel and no FPU!\n");
461 #endif
462 }
463 npxinit(__INITIAL_NPXCW__);
464
465 #if (defined(I586_CPU) || defined(I686_CPU)) && !defined(CPU_DISABLE_SSE)
466 /*
467 * The asm_mmx_*() routines actually use XMM as well, so only
468 * enable them if we have SSE2 and are using FXSR (fxsave/fxrstore).
469 */
470 TUNABLE_INT_FETCH("kern.mmxopt", &mmxopt);
471 if ((cpu_feature & CPUID_MMX) && (cpu_feature & CPUID_SSE) &&
472 (cpu_feature & CPUID_SSE2) &&
473 npx_ex16 && npx_exists && mmxopt && cpu_fxsr
474 ) {
475 if ((flags & NPX_DISABLE_I586_OPTIMIZED_BCOPY) == 0) {
476 bcopy_vector = (void **)asm_xmm_bcopy;
477 ovbcopy_vector = (void **)asm_xmm_bcopy;
478 memcpy_vector = (void **)asm_xmm_memcpy;
479 kprintf("Using XMM optimized bcopy/copyin/copyout\n");
480 }
481 if ((flags & NPX_DISABLE_I586_OPTIMIZED_BZERO) == 0) {
482 /* XXX */
483 }
484 } else if ((cpu_feature & CPUID_MMX) && (cpu_feature & CPUID_SSE) &&
485 npx_ex16 && npx_exists && mmxopt && cpu_fxsr
486 ) {
487 if ((flags & NPX_DISABLE_I586_OPTIMIZED_BCOPY) == 0) {
488 bcopy_vector = (void **)asm_mmx_bcopy;
489 ovbcopy_vector = (void **)asm_mmx_bcopy;
490 memcpy_vector = (void **)asm_mmx_memcpy;
491 kprintf("Using MMX optimized bcopy/copyin/copyout\n");
492 }
493 if ((flags & NPX_DISABLE_I586_OPTIMIZED_BZERO) == 0) {
494 /* XXX */
495 }
496 }
497
498 if ((cpu_feature & CPUID_MMX) && (cpu_feature & CPUID_SSE) && mmxopt)
499 bzeront_avail = 1;
500 #endif
501 #if 0
502 if (cpu_class == CPUCLASS_586 && npx_ex16 && npx_exists &&
503 timezero("i586_bzero()", i586_bzero) <
504 timezero("bzero()", bzero) * 4 / 5) {
505 if (!(flags & NPX_DISABLE_I586_OPTIMIZED_BCOPY)) {
506 bcopy_vector = i586_bcopy;
507 ovbcopy_vector = i586_bcopy;
508 }
509 if (!(flags & NPX_DISABLE_I586_OPTIMIZED_BZERO))
510 bzero_vector = i586_bzero;
511 if (!(flags & NPX_DISABLE_I586_OPTIMIZED_COPYIO)) {
512 copyin_vector = i586_copyin;
513 copyout_vector = i586_copyout;
514 }
515 }
516 #endif
517 return (0); /* XXX unused */
518 }
519
520 /*
521 * Initialize the floating point unit.
522 */
523 void
524 npxinit(u_short control)
525 {
526 static union savefpu dummy __aligned(16);
527
528 if (!npx_exists)
529 return;
530 /*
531 * fninit has the same h/w bugs as fnsave. Use the detoxified
532 * fnsave to throw away any junk in the fpu. npxsave() initializes
533 * the fpu and sets npxthread = NULL as important side effects.
534 */
535 npxsave(&dummy);
536 crit_enter();
537 stop_emulating();
538 fldcw(&control);
539 fpusave(curthread->td_savefpu);
540 mdcpu->gd_npxthread = NULL;
541 start_emulating();
542 crit_exit();
543 }
544
545 /*
546 * Free coprocessor (if we have it).
547 */
548 void
549 npxexit(void)
550 {
551 if (curthread == mdcpu->gd_npxthread)
552 npxsave(curthread->td_savefpu);
553 #ifdef NPX_DEBUG
554 if (npx_exists) {
555 u_int masked_exceptions;
556
557 masked_exceptions =
558 curthread->td_savefpu->sv_87.sv_env.en_cw
559 & curthread->td_savefpu->sv_87.sv_env.en_sw & 0x7f;
560 /*
561 * Log exceptions that would have trapped with the old
562 * control word (overflow, divide by 0, and invalid operand).
563 */
564 if (masked_exceptions & 0x0d)
565 log(LOG_ERR,
566 "pid %d (%s) exited with masked floating point exceptions 0x%02x\n",
567 curproc->p_pid, curproc->p_comm, masked_exceptions);
568 }
569 #endif
570 }
571
572 /*
573 * The following mechanism is used to ensure that the FPE_... value
574 * that is passed as a trapcode to the signal handler of the user
575 * process does not have more than one bit set.
576 *
577 * Multiple bits may be set if the user process modifies the control
578 * word while a status word bit is already set. While this is a sign
579 * of bad coding, we have no choise than to narrow them down to one
580 * bit, since we must not send a trapcode that is not exactly one of
581 * the FPE_ macros.
582 *
583 * The mechanism has a static table with 127 entries. Each combination
584 * of the 7 FPU status word exception bits directly translates to a
585 * position in this table, where a single FPE_... value is stored.
586 * This FPE_... value stored there is considered the "most important"
587 * of the exception bits and will be sent as the signal code. The
588 * precedence of the bits is based upon Intel Document "Numerical
589 * Applications", Chapter "Special Computational Situations".
590 *
591 * The macro to choose one of these values does these steps: 1) Throw
592 * away status word bits that cannot be masked. 2) Throw away the bits
593 * currently masked in the control word, assuming the user isn't
594 * interested in them anymore. 3) Reinsert status word bit 7 (stack
595 * fault) if it is set, which cannot be masked but must be presered.
596 * 4) Use the remaining bits to point into the trapcode table.
597 *
598 * The 6 maskable bits in order of their preference, as stated in the
599 * above referenced Intel manual:
600 * 1 Invalid operation (FP_X_INV)
601 * 1a Stack underflow
602 * 1b Stack overflow
603 * 1c Operand of unsupported format
604 * 1d SNaN operand.
605 * 2 QNaN operand (not an exception, irrelavant here)
606 * 3 Any other invalid-operation not mentioned above or zero divide
607 * (FP_X_INV, FP_X_DZ)
608 * 4 Denormal operand (FP_X_DNML)
609 * 5 Numeric over/underflow (FP_X_OFL, FP_X_UFL)
610 * 6 Inexact result (FP_X_IMP)
611 */
612 static char fpetable[128] = {
613 0,
614 FPE_FLTINV, /* 1 - INV */
615 FPE_FLTUND, /* 2 - DNML */
616 FPE_FLTINV, /* 3 - INV | DNML */
617 FPE_FLTDIV, /* 4 - DZ */
618 FPE_FLTINV, /* 5 - INV | DZ */
619 FPE_FLTDIV, /* 6 - DNML | DZ */
620 FPE_FLTINV, /* 7 - INV | DNML | DZ */
621 FPE_FLTOVF, /* 8 - OFL */
622 FPE_FLTINV, /* 9 - INV | OFL */
623 FPE_FLTUND, /* A - DNML | OFL */
624 FPE_FLTINV, /* B - INV | DNML | OFL */
625 FPE_FLTDIV, /* C - DZ | OFL */
626 FPE_FLTINV, /* D - INV | DZ | OFL */
627 FPE_FLTDIV, /* E - DNML | DZ | OFL */
628 FPE_FLTINV, /* F - INV | DNML | DZ | OFL */
629 FPE_FLTUND, /* 10 - UFL */
630 FPE_FLTINV, /* 11 - INV | UFL */
631 FPE_FLTUND, /* 12 - DNML | UFL */
632 FPE_FLTINV, /* 13 - INV | DNML | UFL */
633 FPE_FLTDIV, /* 14 - DZ | UFL */
634 FPE_FLTINV, /* 15 - INV | DZ | UFL */
635 FPE_FLTDIV, /* 16 - DNML | DZ | UFL */
636 FPE_FLTINV, /* 17 - INV | DNML | DZ | UFL */
637 FPE_FLTOVF, /* 18 - OFL | UFL */
638 FPE_FLTINV, /* 19 - INV | OFL | UFL */
639 FPE_FLTUND, /* 1A - DNML | OFL | UFL */
640 FPE_FLTINV, /* 1B - INV | DNML | OFL | UFL */
641 FPE_FLTDIV, /* 1C - DZ | OFL | UFL */
642 FPE_FLTINV, /* 1D - INV | DZ | OFL | UFL */
643 FPE_FLTDIV, /* 1E - DNML | DZ | OFL | UFL */
644 FPE_FLTINV, /* 1F - INV | DNML | DZ | OFL | UFL */
645 FPE_FLTRES, /* 20 - IMP */
646 FPE_FLTINV, /* 21 - INV | IMP */
647 FPE_FLTUND, /* 22 - DNML | IMP */
648 FPE_FLTINV, /* 23 - INV | DNML | IMP */
649 FPE_FLTDIV, /* 24 - DZ | IMP */
650 FPE_FLTINV, /* 25 - INV | DZ | IMP */
651 FPE_FLTDIV, /* 26 - DNML | DZ | IMP */
652 FPE_FLTINV, /* 27 - INV | DNML | DZ | IMP */
653 FPE_FLTOVF, /* 28 - OFL | IMP */
654 FPE_FLTINV, /* 29 - INV | OFL | IMP */
655 FPE_FLTUND, /* 2A - DNML | OFL | IMP */
656 FPE_FLTINV, /* 2B - INV | DNML | OFL | IMP */
657 FPE_FLTDIV, /* 2C - DZ | OFL | IMP */
658 FPE_FLTINV, /* 2D - INV | DZ | OFL | IMP */
659 FPE_FLTDIV, /* 2E - DNML | DZ | OFL | IMP */
660 FPE_FLTINV, /* 2F - INV | DNML | DZ | OFL | IMP */
661 FPE_FLTUND, /* 30 - UFL | IMP */
662 FPE_FLTINV, /* 31 - INV | UFL | IMP */
663 FPE_FLTUND, /* 32 - DNML | UFL | IMP */
664 FPE_FLTINV, /* 33 - INV | DNML | UFL | IMP */
665 FPE_FLTDIV, /* 34 - DZ | UFL | IMP */
666 FPE_FLTINV, /* 35 - INV | DZ | UFL | IMP */
667 FPE_FLTDIV, /* 36 - DNML | DZ | UFL | IMP */
668 FPE_FLTINV, /* 37 - INV | DNML | DZ | UFL | IMP */
669 FPE_FLTOVF, /* 38 - OFL | UFL | IMP */
670 FPE_FLTINV, /* 39 - INV | OFL | UFL | IMP */
671 FPE_FLTUND, /* 3A - DNML | OFL | UFL | IMP */
672 FPE_FLTINV, /* 3B - INV | DNML | OFL | UFL | IMP */
673 FPE_FLTDIV, /* 3C - DZ | OFL | UFL | IMP */
674 FPE_FLTINV, /* 3D - INV | DZ | OFL | UFL | IMP */
675 FPE_FLTDIV, /* 3E - DNML | DZ | OFL | UFL | IMP */
676 FPE_FLTINV, /* 3F - INV | DNML | DZ | OFL | UFL | IMP */
677 FPE_FLTSUB, /* 40 - STK */
678 FPE_FLTSUB, /* 41 - INV | STK */
679 FPE_FLTUND, /* 42 - DNML | STK */
680 FPE_FLTSUB, /* 43 - INV | DNML | STK */
681 FPE_FLTDIV, /* 44 - DZ | STK */
682 FPE_FLTSUB, /* 45 - INV | DZ | STK */
683 FPE_FLTDIV, /* 46 - DNML | DZ | STK */
684 FPE_FLTSUB, /* 47 - INV | DNML | DZ | STK */
685 FPE_FLTOVF, /* 48 - OFL | STK */
686 FPE_FLTSUB, /* 49 - INV | OFL | STK */
687 FPE_FLTUND, /* 4A - DNML | OFL | STK */
688 FPE_FLTSUB, /* 4B - INV | DNML | OFL | STK */
689 FPE_FLTDIV, /* 4C - DZ | OFL | STK */
690 FPE_FLTSUB, /* 4D - INV | DZ | OFL | STK */
691 FPE_FLTDIV, /* 4E - DNML | DZ | OFL | STK */
692 FPE_FLTSUB, /* 4F - INV | DNML | DZ | OFL | STK */
693 FPE_FLTUND, /* 50 - UFL | STK */
694 FPE_FLTSUB, /* 51 - INV | UFL | STK */
695 FPE_FLTUND, /* 52 - DNML | UFL | STK */
696 FPE_FLTSUB, /* 53 - INV | DNML | UFL | STK */
697 FPE_FLTDIV, /* 54 - DZ | UFL | STK */
698 FPE_FLTSUB, /* 55 - INV | DZ | UFL | STK */
699 FPE_FLTDIV, /* 56 - DNML | DZ | UFL | STK */
700 FPE_FLTSUB, /* 57 - INV | DNML | DZ | UFL | STK */
701 FPE_FLTOVF, /* 58 - OFL | UFL | STK */
702 FPE_FLTSUB, /* 59 - INV | OFL | UFL | STK */
703 FPE_FLTUND, /* 5A - DNML | OFL | UFL | STK */
704 FPE_FLTSUB, /* 5B - INV | DNML | OFL | UFL | STK */
705 FPE_FLTDIV, /* 5C - DZ | OFL | UFL | STK */
706 FPE_FLTSUB, /* 5D - INV | DZ | OFL | UFL | STK */
707 FPE_FLTDIV, /* 5E - DNML | DZ | OFL | UFL | STK */
708 FPE_FLTSUB, /* 5F - INV | DNML | DZ | OFL | UFL | STK */
709 FPE_FLTRES, /* 60 - IMP | STK */
710 FPE_FLTSUB, /* 61 - INV | IMP | STK */
711 FPE_FLTUND, /* 62 - DNML | IMP | STK */
712 FPE_FLTSUB, /* 63 - INV | DNML | IMP | STK */
713 FPE_FLTDIV, /* 64 - DZ | IMP | STK */
714 FPE_FLTSUB, /* 65 - INV | DZ | IMP | STK */
715 FPE_FLTDIV, /* 66 - DNML | DZ | IMP | STK */
716 FPE_FLTSUB, /* 67 - INV | DNML | DZ | IMP | STK */
717 FPE_FLTOVF, /* 68 - OFL | IMP | STK */
718 FPE_FLTSUB, /* 69 - INV | OFL | IMP | STK */
719 FPE_FLTUND, /* 6A - DNML | OFL | IMP | STK */
720 FPE_FLTSUB, /* 6B - INV | DNML | OFL | IMP | STK */
721 FPE_FLTDIV, /* 6C - DZ | OFL | IMP | STK */
722 FPE_FLTSUB, /* 6D - INV | DZ | OFL | IMP | STK */
723 FPE_FLTDIV, /* 6E - DNML | DZ | OFL | IMP | STK */
724 FPE_FLTSUB, /* 6F - INV | DNML | DZ | OFL | IMP | STK */
725 FPE_FLTUND, /* 70 - UFL | IMP | STK */
726 FPE_FLTSUB, /* 71 - INV | UFL | IMP | STK */
727 FPE_FLTUND, /* 72 - DNML | UFL | IMP | STK */
728 FPE_FLTSUB, /* 73 - INV | DNML | UFL | IMP | STK */
729 FPE_FLTDIV, /* 74 - DZ | UFL | IMP | STK */
730 FPE_FLTSUB, /* 75 - INV | DZ | UFL | IMP | STK */
731 FPE_FLTDIV, /* 76 - DNML | DZ | UFL | IMP | STK */
732 FPE_FLTSUB, /* 77 - INV | DNML | DZ | UFL | IMP | STK */
733 FPE_FLTOVF, /* 78 - OFL | UFL | IMP | STK */
734 FPE_FLTSUB, /* 79 - INV | OFL | UFL | IMP | STK */
735 FPE_FLTUND, /* 7A - DNML | OFL | UFL | IMP | STK */
736 FPE_FLTSUB, /* 7B - INV | DNML | OFL | UFL | IMP | STK */
737 FPE_FLTDIV, /* 7C - DZ | OFL | UFL | IMP | STK */
738 FPE_FLTSUB, /* 7D - INV | DZ | OFL | UFL | IMP | STK */
739 FPE_FLTDIV, /* 7E - DNML | DZ | OFL | UFL | IMP | STK */
740 FPE_FLTSUB, /* 7F - INV | DNML | DZ | OFL | UFL | IMP | STK */
741 };
742
743 /*
744 * Preserve the FP status word, clear FP exceptions, then generate a SIGFPE.
745 *
746 * Clearing exceptions is necessary mainly to avoid IRQ13 bugs. We now
747 * depend on longjmp() restoring a usable state. Restoring the state
748 * or examining it might fail if we didn't clear exceptions.
749 *
750 * The error code chosen will be one of the FPE_... macros. It will be
751 * sent as the second argument to old BSD-style signal handlers and as
752 * "siginfo_t->si_code" (second argument) to SA_SIGINFO signal handlers.
753 *
754 * XXX the FP state is not preserved across signal handlers. So signal
755 * handlers cannot afford to do FP unless they preserve the state or
756 * longjmp() out. Both preserving the state and longjmp()ing may be
757 * destroyed by IRQ13 bugs. Clearing FP exceptions is not an acceptable
758 * solution for signals other than SIGFPE.
759 *
760 * The MP lock is not held on entry (see i386/i386/exception.s) and
761 * should not be held on exit. Interrupts are enabled. We must enter
762 * a critical section to stabilize the FP system and prevent an interrupt
763 * or preemption from changing the FP state out from under us.
764 */
765 void
766 npx_intr(void *dummy)
767 {
768 int code;
769 u_short control;
770 struct intrframe *frame;
771 u_long *exstat;
772
773 crit_enter();
774
775 /*
776 * This exception can only occur with CR0_TS clear, otherwise we
777 * would get a DNA exception. However, since interrupts were
778 * enabled a preemption could have sneaked in and used the FP system
779 * before we entered our critical section. If that occured, the
780 * TS bit will be set and npxthread will be NULL.
781 */
782 if (npx_exists && (rcr0() & CR0_TS)) {
783 KASSERT(mdcpu->gd_npxthread == NULL, ("gd_npxthread was %p with TS set!", mdcpu->gd_npxthread));
784 npxdna();
785 crit_exit();
786 return;
787 }
788 if (mdcpu->gd_npxthread == NULL || !npx_exists) {
789 get_mplock();
790 kprintf("npxintr: npxthread = %p, curthread = %p, npx_exists = %d\n",
791 mdcpu->gd_npxthread, curthread, npx_exists);
792 panic("npxintr from nowhere");
793 }
794 if (mdcpu->gd_npxthread != curthread) {
795 get_mplock();
796 kprintf("npxintr: npxthread = %p, curthread = %p, npx_exists = %d\n",
797 mdcpu->gd_npxthread, curthread, npx_exists);
798 panic("npxintr from non-current process");
799 }
800
801 exstat = GET_FPU_EXSW_PTR(curthread);
802 outb(0xf0, 0);
803 fnstsw(exstat);
804 fnstcw(&control);
805 fnclex();
806
807 get_mplock();
808
809 /*
810 * Pass exception to process.
811 */
812 frame = (struct intrframe *)&dummy; /* XXX */
813 if ((ISPL(frame->if_cs) == SEL_UPL) || (frame->if_eflags & PSL_VM)) {
814 /*
815 * Interrupt is essentially a trap, so we can afford to call
816 * the SIGFPE handler (if any) as soon as the interrupt
817 * returns.
818 *
819 * XXX little or nothing is gained from this, and plenty is
820 * lost - the interrupt frame has to contain the trap frame
821 * (this is otherwise only necessary for the rescheduling trap
822 * in doreti, and the frame for that could easily be set up
823 * just before it is used).
824 */
825 curthread->td_lwp->lwp_md.md_regs = INTR_TO_TRAPFRAME(frame);
826 /*
827 * Encode the appropriate code for detailed information on
828 * this exception.
829 */
830 code =
831 fpetable[(*exstat & ~control & 0x3f) | (*exstat & 0x40)];
832 trapsignal(curthread->td_lwp, SIGFPE, code);
833 } else {
834 /*
835 * Nested interrupt. These losers occur when:
836 * o an IRQ13 is bogusly generated at a bogus time, e.g.:
837 * o immediately after an fnsave or frstor of an
838 * error state.
839 * o a couple of 386 instructions after
840 * "fstpl _memvar" causes a stack overflow.
841 * These are especially nasty when combined with a
842 * trace trap.
843 * o an IRQ13 occurs at the same time as another higher-
844 * priority interrupt.
845 *
846 * Treat them like a true async interrupt.
847 */
848 lwpsignal(curproc, curthread->td_lwp, SIGFPE);
849 }
850 rel_mplock();
851 crit_exit();
852 }
853
854 /*
855 * Implement the device not available (DNA) exception. gd_npxthread had
856 * better be NULL. Restore the current thread's FP state and set gd_npxthread
857 * to curthread.
858 *
859 * Interrupts are enabled and preemption can occur. Enter a critical
860 * section to stabilize the FP state.
861 */
862 int
863 npxdna(void)
864 {
865 thread_t td = curthread;
866 u_long *exstat;
867 int didinit = 0;
868
869 if (!npx_exists)
870 return (0);
871 if (mdcpu->gd_npxthread != NULL) {
872 kprintf("npxdna: npxthread = %p, curthread = %p\n",
873 mdcpu->gd_npxthread, td);
874 panic("npxdna");
875 }
876
877 /*
878 * Setup the initial saved state if the thread has never before
879 * used the FP unit. This also occurs when a thread pushes a
880 * signal handler and uses FP in the handler.
881 */
882 if ((td->td_flags & (TDF_USINGFP | TDF_KERNELFP)) == 0) {
883 td->td_flags |= TDF_USINGFP;
884 npxinit(__INITIAL_NPXCW__);
885 didinit = 1;
886 }
887
888 /*
889 * The setting of gd_npxthread and the call to fpurstor() must not
890 * be preempted by an interrupt thread or we will take an npxdna
891 * trap and potentially save our current fpstate (which is garbage)
892 * and then restore the garbage rather then the originally saved
893 * fpstate.
894 */
895 crit_enter();
896 stop_emulating();
897 /*
898 * Record new context early in case frstor causes an IRQ13.
899 */
900 mdcpu->gd_npxthread = td;
901 exstat = GET_FPU_EXSW_PTR(td);
902 *exstat = 0;
903 /*
904 * The following frstor may cause an IRQ13 when the state being
905 * restored has a pending error. The error will appear to have been
906 * triggered by the current (npx) user instruction even when that
907 * instruction is a no-wait instruction that should not trigger an
908 * error (e.g., fnclex). On at least one 486 system all of the
909 * no-wait instructions are broken the same as frstor, so our
910 * treatment does not amplify the breakage. On at least one
911 * 386/Cyrix 387 system, fnclex works correctly while frstor and
912 * fnsave are broken, so our treatment breaks fnclex if it is the
913 * first FPU instruction after a context switch.
914 */
915 if ((td->td_savefpu->sv_xmm.sv_env.en_mxcsr & ~0xFFBF)
916 #ifndef CPU_DISABLE_SSE
917 && cpu_fxsr
918 #endif
919 ) {
920 krateprintf(&badfprate,
921 "FXRSTR: illegal FP MXCSR %08x didinit = %d\n",
922 td->td_savefpu->sv_xmm.sv_env.en_mxcsr, didinit);
923 td->td_savefpu->sv_xmm.sv_env.en_mxcsr &= 0xFFBF;
924 lwpsignal(curproc, curthread->td_lwp, SIGFPE);
925 }
926 fpurstor(td->td_savefpu);
927 crit_exit();
928
929 return (1);
930 }
931
932 /*
933 * Wrapper for the fnsave instruction to handle h/w bugs. If there is an error
934 * pending, then fnsave generates a bogus IRQ13 on some systems. Force
935 * any IRQ13 to be handled immediately, and then ignore it. This routine is
936 * often called at splhigh so it must not use many system services. In
937 * particular, it's much easier to install a special handler than to
938 * guarantee that it's safe to use npxintr() and its supporting code.
939 *
940 * WARNING! This call is made during a switch and the MP lock will be
941 * setup for the new target thread rather then the current thread, so we
942 * cannot do anything here that depends on the *_mplock() functions as
943 * we may trip over their assertions.
944 *
945 * WARNING! When using fxsave we MUST fninit after saving the FP state. The
946 * kernel will always assume that the FP state is 'safe' (will not cause
947 * exceptions) for mmx/xmm use if npxthread is NULL. The kernel must still
948 * setup a custom save area before actually using the FP unit, but it will
949 * not bother calling fninit. This greatly improves kernel performance when
950 * it wishes to use the FP unit.
951 */
952 void
953 npxsave(union savefpu *addr)
954 {
955 #if defined(SMP) || !defined(CPU_DISABLE_SSE)
956
957 crit_enter();
958 stop_emulating();
959 fpusave(addr);
960 mdcpu->gd_npxthread = NULL;
961 fninit();
962 start_emulating();
963 crit_exit();
964
965 #else /* !SMP and CPU_DISABLE_SSE */
966
967 u_char icu1_mask;
968 u_char icu2_mask;
969 u_char old_icu1_mask;
970 u_char old_icu2_mask;
971 struct gate_descriptor save_idt_npxintr;
972 u_long save_eflags;
973
974 save_eflags = read_eflags();
975 cpu_disable_intr();
976 old_icu1_mask = inb(IO_ICU1 + 1);
977 old_icu2_mask = inb(IO_ICU2 + 1);
978 save_idt_npxintr = idt[npx_intrno];
979 outb(IO_ICU1 + 1, old_icu1_mask & ~((1 << ICU_IRQ_SLAVE) | npx0_imask));
980 outb(IO_ICU2 + 1, old_icu2_mask & ~(npx0_imask >> 8));
981 idt[npx_intrno] = npx_idt_probeintr;
982 cpu_enable_intr();
983 stop_emulating();
984 fnsave(addr);
985 fnop();
986 cpu_disable_intr();
987 mdcpu->gd_npxthread = NULL;
988 start_emulating();
989 icu1_mask = inb(IO_ICU1 + 1); /* masks may have changed */
990 icu2_mask = inb(IO_ICU2 + 1);
991 outb(IO_ICU1 + 1,
992 (icu1_mask & ~npx0_imask) | (old_icu1_mask & npx0_imask));
993 outb(IO_ICU2 + 1,
994 (icu2_mask & ~(npx0_imask >> 8))
995 | (old_icu2_mask & (npx0_imask >> 8)));
996 idt[npx_intrno] = save_idt_npxintr;
997 write_eflags(save_eflags); /* back to usual state */
998
999 #endif /* SMP */
1000 }
1001
1002 static void
1003 fpusave(union savefpu *addr)
1004 {
1005 #ifndef CPU_DISABLE_SSE
1006 if (cpu_fxsr)
1007 fxsave(addr);
1008 else
1009 #endif
1010 fnsave(addr);
1011 }
1012
1013 /*
1014 * Save the FP state to the mcontext structure.
1015 *
1016 * WARNING: If you want to try to npxsave() directly to mctx->mc_fpregs,
1017 * then it MUST be 16-byte aligned. Currently this is not guarenteed.
1018 */
1019 void
1020 npxpush(mcontext_t *mctx)
1021 {
1022 thread_t td = curthread;
1023
1024 KKASSERT((td->td_flags & TDF_KERNELFP) == 0);
1025
1026 if (td->td_flags & TDF_USINGFP) {
1027 if (mdcpu->gd_npxthread == td) {
1028 /*
1029 * XXX Note: This is a bit inefficient if the signal
1030 * handler uses floating point, extra faults will
1031 * occur.
1032 */
1033 mctx->mc_ownedfp = _MC_FPOWNED_FPU;
1034 npxsave(td->td_savefpu);
1035 } else {
1036 mctx->mc_ownedfp = _MC_FPOWNED_PCB;
1037 }
1038 bcopy(td->td_savefpu, mctx->mc_fpregs, sizeof(mctx->mc_fpregs));
1039 td->td_flags &= ~TDF_USINGFP;
1040 mctx->mc_fpformat =
1041 #ifndef CPU_DISABLE_SSE
1042 (cpu_fxsr) ? _MC_FPFMT_XMM :
1043 #endif
1044 _MC_FPFMT_387;
1045 } else {
1046 mctx->mc_ownedfp = _MC_FPOWNED_NONE;
1047 mctx->mc_fpformat = _MC_FPFMT_NODEV;
1048 }
1049 }
1050
1051 /*
1052 * Restore the FP state from the mcontext structure.
1053 */
1054 void
1055 npxpop(mcontext_t *mctx)
1056 {
1057 thread_t td = curthread;
1058
1059 KKASSERT((td->td_flags & TDF_KERNELFP) == 0);
1060
1061 switch(mctx->mc_ownedfp) {
1062 case _MC_FPOWNED_NONE:
1063 /*
1064 * If the signal handler used the FP unit but the interrupted
1065 * code did not, release the FP unit. Clear TDF_USINGFP will
1066 * force the FP unit to reinit so the interrupted code sees
1067 * a clean slate.
1068 */
1069 if (td->td_flags & TDF_USINGFP) {
1070 if (td == mdcpu->gd_npxthread)
1071 npxsave(td->td_savefpu);
1072 td->td_flags &= ~TDF_USINGFP;
1073 }
1074 break;
1075 case _MC_FPOWNED_FPU:
1076 case _MC_FPOWNED_PCB:
1077 /*
1078 * Clear ownership of the FP unit and restore our saved state.
1079 *
1080 * NOTE: The signal handler may have set-up some FP state and
1081 * enabled the FP unit, so we have to restore no matter what.
1082 *
1083 * XXX: This is bit inefficient, if the code being returned
1084 * to is actively using the FP this results in multiple
1085 * kernel faults.
1086 *
1087 * WARNING: The saved state was exposed to userland and may
1088 * have to be sanitized to avoid a GP fault in the kernel.
1089 */
1090 if (td == mdcpu->gd_npxthread)
1091 npxsave(td->td_savefpu);
1092 bcopy(mctx->mc_fpregs, td->td_savefpu, sizeof(*td->td_savefpu));
1093 if ((td->td_savefpu->sv_xmm.sv_env.en_mxcsr & ~0xFFBF)
1094 #ifndef CPU_DISABLE_SSE
1095 && cpu_fxsr
1096 #endif
1097 ) {
1098 krateprintf(&badfprate,
1099 "pid %d (%s) signal return from user: "
1100 "illegal FP MXCSR %08x\n",
1101 td->td_proc->p_pid,
1102 td->td_proc->p_comm,
1103 td->td_savefpu->sv_xmm.sv_env.en_mxcsr);
1104 td->td_savefpu->sv_xmm.sv_env.en_mxcsr &= 0xFFBF;
1105 }
1106 td->td_flags |= TDF_USINGFP;
1107 break;
1108 }
1109 }
1110
1111 #ifndef CPU_DISABLE_SSE
1112 /*
1113 * On AuthenticAMD processors, the fxrstor instruction does not restore
1114 * the x87's stored last instruction pointer, last data pointer, and last
1115 * opcode values, except in the rare case in which the exception summary
1116 * (ES) bit in the x87 status word is set to 1.
1117 *
1118 * In order to avoid leaking this information across processes, we clean
1119 * these values by performing a dummy load before executing fxrstor().
1120 */
1121 static double dummy_variable = 0.0;
1122 static void
1123 fpu_clean_state(void)
1124 {
1125 u_short status;
1126
1127 /*
1128 * Clear the ES bit in the x87 status word if it is currently
1129 * set, in order to avoid causing a fault in the upcoming load.
1130 */
1131 fnstsw(&status);
1132 if (status & 0x80)
1133 fnclex();
1134
1135 /*
1136 * Load the dummy variable into the x87 stack. This mangles
1137 * the x87 stack, but we don't care since we're about to call
1138 * fxrstor() anyway.
1139 */
1140 __asm __volatile("ffree %%st(7); fld %0" : : "m" (dummy_variable));
1141 }
1142 #endif /* CPU_DISABLE_SSE */
1143
1144 static void
1145 fpurstor(union savefpu *addr)
1146 {
1147 #ifndef CPU_DISABLE_SSE
1148 if (cpu_fxsr) {
1149 fpu_clean_state();
1150 fxrstor(addr);
1151 } else {
1152 frstor(addr);
1153 }
1154 #else
1155 frstor(addr);
1156 #endif
1157 }
1158
1159 /*
1160 * Because npx is a static device that always exists under nexus,
1161 * and is not scanned by the nexus device, we need an identify
1162 * function to install the device.
1163 */
1164 static device_method_t npx_methods[] = {
1165 /* Device interface */
1166 DEVMETHOD(device_identify, bus_generic_identify),
1167 DEVMETHOD(device_probe, npx_probe),
1168 DEVMETHOD(device_attach, npx_attach),
1169 DEVMETHOD(device_detach, bus_generic_detach),
1170 DEVMETHOD(device_shutdown, bus_generic_shutdown),
1171 DEVMETHOD(device_suspend, bus_generic_suspend),
1172 DEVMETHOD(device_resume, bus_generic_resume),
1173
1174 { 0, 0 }
1175 };
1176
1177 static driver_t npx_driver = {
1178 "npx",
1179 npx_methods,
1180 1, /* no softc */
1181 };
1182
1183 static devclass_t npx_devclass;
1184
1185 /*
1186 * We prefer to attach to the root nexus so that the usual case (exception 16)
1187 * doesn't describe the processor as being `on isa'.
1188 */
1189 DRIVER_MODULE(npx, nexus, npx_driver, npx_devclass, 0, 0);
DragonFly BSD