2 * CAM SCSI interface for the the Advanced Systems Inc.
3 * Second Generation SCSI controllers.
5 * Product specific probe and attach routines can be found in:
7 * adw_pci.c ABP[3]940UW, ABP950UW, ABP3940U2W
9 * Copyright (c) 1998, 1999, 2000 Justin Gibbs.
10 * All rights reserved.
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions, and the following disclaimer,
17 * without modification.
18 * 2. The name of the author may not be used to endorse or promote products
19 * derived from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
25 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33 * $FreeBSD: src/sys/dev/advansys/adwcam.c,v 1.7.2.2 2001/03/05 13:08:55 obrien Exp $
34 * $DragonFly: src/sys/dev/disk/advansys/adwcam.c,v 1.19 2008/05/18 20:30:20 pavalos Exp $
38 * advansys.c - Linux Host Driver for AdvanSys SCSI Adapters
40 * Copyright (c) 1995-1998 Advanced System Products, Inc.
41 * All Rights Reserved.
43 * Redistribution and use in source and binary forms, with or without
44 * modification, are permitted provided that redistributions of source
45 * code retain the above copyright notice and this comment without
49 #include <sys/param.h>
50 #include <sys/systm.h>
51 #include <sys/kernel.h>
52 #include <sys/malloc.h>
54 #include <sys/thread2.h>
56 #include <machine/clock.h>
60 #include <bus/cam/cam.h>
61 #include <bus/cam/cam_ccb.h>
62 #include <bus/cam/cam_sim.h>
63 #include <bus/cam/cam_xpt_sim.h>
64 #include <bus/cam/cam_debug.h>
66 #include <bus/cam/scsi/scsi_message.h>
70 /* Definitions for our use of the SIM private CCB area */
71 #define ccb_acb_ptr spriv_ptr0
72 #define ccb_adw_ptr spriv_ptr1
76 static __inline cam_status
adwccbstatus(union ccb
*);
77 static __inline
struct acb
* adwgetacb(struct adw_softc
*adw
);
78 static __inline
void adwfreeacb(struct adw_softc
*adw
,
81 static void adwmapmem(void *arg
, bus_dma_segment_t
*segs
,
83 static struct sg_map_node
*
84 adwallocsgmap(struct adw_softc
*adw
);
85 static int adwallocacbs(struct adw_softc
*adw
);
87 static void adwexecuteacb(void *arg
, bus_dma_segment_t
*dm_segs
,
89 static void adw_action(struct cam_sim
*sim
, union ccb
*ccb
);
90 static void adw_poll(struct cam_sim
*sim
);
91 static void adw_async(void *callback_arg
, u_int32_t code
,
92 struct cam_path
*path
, void *arg
);
93 static void adwprocesserror(struct adw_softc
*adw
, struct acb
*acb
);
94 static void adwtimeout(void *arg
);
95 static void adw_handle_device_reset(struct adw_softc
*adw
,
97 static void adw_handle_bus_reset(struct adw_softc
*adw
,
100 static __inline cam_status
101 adwccbstatus(union ccb
* ccb
)
103 return (ccb
->ccb_h
.status
& CAM_STATUS_MASK
);
106 static __inline
struct acb
*
107 adwgetacb(struct adw_softc
*adw
)
112 if ((acb
= SLIST_FIRST(&adw
->free_acb_list
)) != NULL
) {
113 SLIST_REMOVE_HEAD(&adw
->free_acb_list
, links
);
114 } else if (adw
->num_acbs
< adw
->max_acbs
) {
116 acb
= SLIST_FIRST(&adw
->free_acb_list
);
118 kprintf("%s: Can't malloc ACB\n", adw_name(adw
));
120 SLIST_REMOVE_HEAD(&adw
->free_acb_list
, links
);
129 adwfreeacb(struct adw_softc
*adw
, struct acb
*acb
)
132 if ((acb
->state
& ACB_ACTIVE
) != 0)
133 LIST_REMOVE(&acb
->ccb
->ccb_h
, sim_links
.le
);
134 if ((acb
->state
& ACB_RELEASE_SIMQ
) != 0)
135 acb
->ccb
->ccb_h
.status
|= CAM_RELEASE_SIMQ
;
136 else if ((adw
->state
& ADW_RESOURCE_SHORTAGE
) != 0
137 && (acb
->ccb
->ccb_h
.status
& CAM_RELEASE_SIMQ
) == 0) {
138 acb
->ccb
->ccb_h
.status
|= CAM_RELEASE_SIMQ
;
139 adw
->state
&= ~ADW_RESOURCE_SHORTAGE
;
141 acb
->state
= ACB_FREE
;
142 SLIST_INSERT_HEAD(&adw
->free_acb_list
, acb
, links
);
147 adwmapmem(void *arg
, bus_dma_segment_t
*segs
, int nseg
, int error
)
149 bus_addr_t
*busaddrp
;
151 busaddrp
= (bus_addr_t
*)arg
;
152 *busaddrp
= segs
->ds_addr
;
155 static struct sg_map_node
*
156 adwallocsgmap(struct adw_softc
*adw
)
158 struct sg_map_node
*sg_map
;
160 sg_map
= kmalloc(sizeof(*sg_map
), M_DEVBUF
, M_INTWAIT
);
162 /* Allocate S/G space for the next batch of ACBS */
163 if (bus_dmamem_alloc(adw
->sg_dmat
, (void **)&sg_map
->sg_vaddr
,
164 BUS_DMA_NOWAIT
, &sg_map
->sg_dmamap
) != 0) {
165 kfree(sg_map
, M_DEVBUF
);
169 SLIST_INSERT_HEAD(&adw
->sg_maps
, sg_map
, links
);
171 bus_dmamap_load(adw
->sg_dmat
, sg_map
->sg_dmamap
, sg_map
->sg_vaddr
,
172 PAGE_SIZE
, adwmapmem
, &sg_map
->sg_physaddr
, /*flags*/0);
174 bzero(sg_map
->sg_vaddr
, PAGE_SIZE
);
179 * Allocate another chunk of CCB's. Return count of entries added.
180 * Assumed to be called under crit_enter().
183 adwallocacbs(struct adw_softc
*adw
)
185 struct acb
*next_acb
;
186 struct sg_map_node
*sg_map
;
188 struct adw_sg_block
*blocks
;
192 next_acb
= &adw
->acbs
[adw
->num_acbs
];
193 sg_map
= adwallocsgmap(adw
);
198 blocks
= sg_map
->sg_vaddr
;
199 busaddr
= sg_map
->sg_physaddr
;
201 newcount
= (PAGE_SIZE
/ (ADW_SG_BLOCKCNT
* sizeof(*blocks
)));
202 for (i
= 0; adw
->num_acbs
< adw
->max_acbs
&& i
< newcount
; i
++) {
205 error
= bus_dmamap_create(adw
->buffer_dmat
, /*flags*/0,
209 next_acb
->queue
.scsi_req_baddr
= acbvtob(adw
, next_acb
);
210 next_acb
->queue
.scsi_req_bo
= acbvtobo(adw
, next_acb
);
211 next_acb
->queue
.sense_baddr
=
212 acbvtob(adw
, next_acb
) + offsetof(struct acb
, sense_data
);
213 next_acb
->sg_blocks
= blocks
;
214 next_acb
->sg_busaddr
= busaddr
;
215 next_acb
->state
= ACB_FREE
;
216 SLIST_INSERT_HEAD(&adw
->free_acb_list
, next_acb
, links
);
217 blocks
+= ADW_SG_BLOCKCNT
;
218 busaddr
+= ADW_SG_BLOCKCNT
* sizeof(*blocks
);
226 adwexecuteacb(void *arg
, bus_dma_segment_t
*dm_segs
, int nseg
, int error
)
230 struct adw_softc
*adw
;
232 acb
= (struct acb
*)arg
;
234 adw
= (struct adw_softc
*)ccb
->ccb_h
.ccb_adw_ptr
;
238 kprintf("%s: Unexpected error 0x%x returned from "
239 "bus_dmamap_load\n", adw_name(adw
), error
);
240 if (ccb
->ccb_h
.status
== CAM_REQ_INPROG
) {
241 xpt_freeze_devq(ccb
->ccb_h
.path
, /*count*/1);
242 ccb
->ccb_h
.status
= CAM_REQ_TOO_BIG
|CAM_DEV_QFRZN
;
244 adwfreeacb(adw
, acb
);
252 acb
->queue
.data_addr
= dm_segs
[0].ds_addr
;
253 acb
->queue
.data_cnt
= ccb
->csio
.dxfer_len
;
255 struct adw_sg_block
*sg_block
;
256 struct adw_sg_elm
*sg
;
257 bus_addr_t sg_busaddr
;
259 bus_dma_segment_t
*end_seg
;
261 end_seg
= dm_segs
+ nseg
;
263 sg_busaddr
= acb
->sg_busaddr
;
265 /* Copy the segments into our SG list */
266 for (sg_block
= acb
->sg_blocks
;; sg_block
++) {
269 sg
= sg_block
->sg_list
;
270 for (i
= 0; i
< ADW_NO_OF_SG_PER_BLOCK
; i
++) {
271 if (dm_segs
>= end_seg
)
274 sg
->sg_addr
= dm_segs
->ds_addr
;
275 sg
->sg_count
= dm_segs
->ds_len
;
279 sg_block
->sg_cnt
= i
;
281 if (dm_segs
== end_seg
) {
282 sg_block
->sg_busaddr_next
= 0;
286 sizeof(struct adw_sg_block
);
287 sg_block
->sg_busaddr_next
= sg_busaddr
;
290 acb
->queue
.sg_real_addr
= acb
->sg_busaddr
;
292 acb
->queue
.sg_real_addr
= 0;
295 if ((ccb
->ccb_h
.flags
& CAM_DIR_MASK
) == CAM_DIR_IN
)
296 op
= BUS_DMASYNC_PREREAD
;
298 op
= BUS_DMASYNC_PREWRITE
;
300 bus_dmamap_sync(adw
->buffer_dmat
, acb
->dmamap
, op
);
303 acb
->queue
.data_addr
= 0;
304 acb
->queue
.data_cnt
= 0;
305 acb
->queue
.sg_real_addr
= 0;
311 * Last time we need to check if this CCB needs to
314 if (ccb
->ccb_h
.status
!= CAM_REQ_INPROG
) {
316 bus_dmamap_unload(adw
->buffer_dmat
, acb
->dmamap
);
317 adwfreeacb(adw
, acb
);
323 acb
->state
|= ACB_ACTIVE
;
324 ccb
->ccb_h
.status
|= CAM_SIM_QUEUED
;
325 LIST_INSERT_HEAD(&adw
->pending_ccbs
, &ccb
->ccb_h
, sim_links
.le
);
326 callout_reset(&ccb
->ccb_h
.timeout_ch
, (ccb
->ccb_h
.timeout
* hz
) / 1000,
329 adw_send_acb(adw
, acb
, acbvtob(adw
, acb
));
335 adw_action(struct cam_sim
*sim
, union ccb
*ccb
)
337 struct adw_softc
*adw
;
339 CAM_DEBUG(ccb
->ccb_h
.path
, CAM_DEBUG_TRACE
, ("adw_action\n"));
341 adw
= (struct adw_softc
*)cam_sim_softc(sim
);
343 switch (ccb
->ccb_h
.func_code
) {
344 /* Common cases first */
345 case XPT_SCSI_IO
: /* Execute the requested I/O operation */
347 struct ccb_scsiio
*csio
;
348 struct ccb_hdr
*ccbh
;
354 /* Max supported CDB length is 12 bytes */
355 if (csio
->cdb_len
> 12) {
356 ccb
->ccb_h
.status
= CAM_REQ_INVALID
;
361 if ((acb
= adwgetacb(adw
)) == NULL
) {
363 adw
->state
|= ADW_RESOURCE_SHORTAGE
;
365 xpt_freeze_simq(sim
, /*count*/1);
366 ccb
->ccb_h
.status
= CAM_REQUEUE_REQ
;
371 /* Link acb and ccb so we can find one from the other */
373 ccb
->ccb_h
.ccb_acb_ptr
= acb
;
374 ccb
->ccb_h
.ccb_adw_ptr
= adw
;
377 acb
->queue
.target_cmd
= 0;
378 acb
->queue
.target_id
= ccb
->ccb_h
.target_id
;
379 acb
->queue
.target_lun
= ccb
->ccb_h
.target_lun
;
381 acb
->queue
.mflag
= 0;
382 acb
->queue
.sense_len
=
383 MIN(csio
->sense_len
, sizeof(acb
->sense_data
));
384 acb
->queue
.cdb_len
= csio
->cdb_len
;
385 if ((ccb
->ccb_h
.flags
& CAM_TAG_ACTION_VALID
) != 0) {
386 switch (csio
->tag_action
) {
387 case MSG_SIMPLE_Q_TAG
:
388 acb
->queue
.scsi_cntl
= ADW_QSC_SIMPLE_Q_TAG
;
390 case MSG_HEAD_OF_Q_TAG
:
391 acb
->queue
.scsi_cntl
= ADW_QSC_HEAD_OF_Q_TAG
;
393 case MSG_ORDERED_Q_TAG
:
394 acb
->queue
.scsi_cntl
= ADW_QSC_ORDERED_Q_TAG
;
397 acb
->queue
.scsi_cntl
= ADW_QSC_NO_TAGMSG
;
401 acb
->queue
.scsi_cntl
= ADW_QSC_NO_TAGMSG
;
403 if ((ccb
->ccb_h
.flags
& CAM_DIS_DISCONNECT
) != 0)
404 acb
->queue
.scsi_cntl
|= ADW_QSC_NO_DISC
;
406 acb
->queue
.done_status
= 0;
407 acb
->queue
.scsi_status
= 0;
408 acb
->queue
.host_status
= 0;
409 acb
->queue
.sg_wk_ix
= 0;
410 if ((ccb
->ccb_h
.flags
& CAM_CDB_POINTER
) != 0) {
411 if ((ccb
->ccb_h
.flags
& CAM_CDB_PHYS
) == 0) {
412 bcopy(csio
->cdb_io
.cdb_ptr
,
413 acb
->queue
.cdb
, csio
->cdb_len
);
415 /* I guess I could map it in... */
416 ccb
->ccb_h
.status
= CAM_REQ_INVALID
;
417 adwfreeacb(adw
, acb
);
422 bcopy(csio
->cdb_io
.cdb_bytes
,
423 acb
->queue
.cdb
, csio
->cdb_len
);
427 * If we have any data to send with this command,
428 * map it into bus space.
430 if ((ccbh
->flags
& CAM_DIR_MASK
) != CAM_DIR_NONE
) {
431 if ((ccbh
->flags
& CAM_SCATTER_VALID
) == 0) {
433 * We've been given a pointer
434 * to a single buffer.
436 if ((ccbh
->flags
& CAM_DATA_PHYS
) == 0) {
441 bus_dmamap_load(adw
->buffer_dmat
,
447 if (error
== EINPROGRESS
) {
449 * So as to maintain ordering,
450 * freeze the controller queue
451 * until our mapping is
454 xpt_freeze_simq(sim
, 1);
455 acb
->state
|= CAM_RELEASE_SIMQ
;
459 struct bus_dma_segment seg
;
461 /* Pointer to physical buffer */
463 (bus_addr_t
)csio
->data_ptr
;
464 seg
.ds_len
= csio
->dxfer_len
;
465 adwexecuteacb(acb
, &seg
, 1, 0);
468 struct bus_dma_segment
*segs
;
470 if ((ccbh
->flags
& CAM_DATA_PHYS
) != 0)
471 panic("adw_action - Physical "
475 if ((ccbh
->flags
&CAM_SG_LIST_PHYS
)==0)
476 panic("adw_action - Virtual "
480 /* Just use the segments provided */
481 segs
= (struct bus_dma_segment
*)csio
->data_ptr
;
482 adwexecuteacb(acb
, segs
, csio
->sglist_cnt
,
483 (csio
->sglist_cnt
< ADW_SGSIZE
)
487 adwexecuteacb(acb
, NULL
, 0, 0);
491 case XPT_RESET_DEV
: /* Bus Device Reset the specified SCSI device */
493 adw_idle_cmd_status_t status
;
495 status
= adw_idle_cmd_send(adw
, ADW_IDLE_CMD_DEVICE_RESET
,
496 ccb
->ccb_h
.target_id
);
497 if (status
== ADW_IDLE_CMD_SUCCESS
) {
498 ccb
->ccb_h
.status
= CAM_REQ_CMP
;
500 xpt_print_path(ccb
->ccb_h
.path
);
501 kprintf("BDR Delivered\n");
504 ccb
->ccb_h
.status
= CAM_REQ_CMP_ERR
;
508 case XPT_ABORT
: /* Abort the specified CCB */
510 ccb
->ccb_h
.status
= CAM_REQ_INVALID
;
513 case XPT_SET_TRAN_SETTINGS
:
515 struct ccb_trans_settings_scsi
*scsi
;
516 struct ccb_trans_settings_spi
*spi
;
517 struct ccb_trans_settings
*cts
;
521 target_mask
= 0x01 << ccb
->ccb_h
.target_id
;
524 scsi
= &cts
->proto_specific
.scsi
;
525 spi
= &cts
->xport_specific
.spi
;
526 if (cts
->type
== CTS_TYPE_CURRENT_SETTINGS
) {
529 sdtrdone
= adw_lram_read_16(adw
, ADW_MC_SDTR_DONE
);
530 if ((spi
->valid
& CTS_SPI_VALID_DISC
) != 0) {
534 adw_lram_read_16(adw
, ADW_MC_DISC_ENABLE
);
536 if ((spi
->flags
& CTS_SPI_FLAGS_DISC_ENB
) != 0)
537 discenb
|= target_mask
;
539 discenb
&= ~target_mask
;
541 adw_lram_write_16(adw
, ADW_MC_DISC_ENABLE
,
545 if ((scsi
->valid
& CTS_SCSI_VALID_TQ
) != 0) {
547 if ((scsi
->flags
& CTS_SCSI_FLAGS_TAG_ENB
) != 0)
548 adw
->tagenb
|= target_mask
;
550 adw
->tagenb
&= ~target_mask
;
553 if ((spi
->valid
& CTS_SPI_VALID_BUS_WIDTH
) != 0) {
559 adw_lram_read_16(adw
, ADW_MC_WDTR_ABLE
);
560 wdtrenb
= wdtrenb_orig
;
561 wdtrdone
= adw_lram_read_16(adw
,
563 switch (spi
->bus_width
) {
564 case MSG_EXT_WDTR_BUS_32_BIT
:
565 case MSG_EXT_WDTR_BUS_16_BIT
:
566 wdtrenb
|= target_mask
;
568 case MSG_EXT_WDTR_BUS_8_BIT
:
570 wdtrenb
&= ~target_mask
;
573 if (wdtrenb
!= wdtrenb_orig
) {
574 adw_lram_write_16(adw
,
577 wdtrdone
&= ~target_mask
;
578 adw_lram_write_16(adw
,
581 /* Wide negotiation forces async */
582 sdtrdone
&= ~target_mask
;
583 adw_lram_write_16(adw
,
589 if (((spi
->valid
& CTS_SPI_VALID_SYNC_RATE
) != 0)
590 || ((spi
->valid
& CTS_SPI_VALID_SYNC_OFFSET
) != 0)) {
596 sdtr
= adw_get_chip_sdtr(adw
,
597 ccb
->ccb_h
.target_id
);
599 sdtrable
= adw_lram_read_16(adw
,
601 sdtrable_orig
= sdtrable
;
604 & CTS_SPI_VALID_SYNC_RATE
) != 0) {
612 & CTS_SPI_VALID_SYNC_OFFSET
) != 0) {
613 if (spi
->sync_offset
== 0)
614 sdtr
= ADW_MC_SDTR_ASYNC
;
617 if (sdtr
== ADW_MC_SDTR_ASYNC
)
618 sdtrable
&= ~target_mask
;
620 sdtrable
|= target_mask
;
621 if (sdtr
!= sdtr_orig
622 || sdtrable
!= sdtrable_orig
) {
623 adw_set_chip_sdtr(adw
,
624 ccb
->ccb_h
.target_id
,
626 sdtrdone
&= ~target_mask
;
627 adw_lram_write_16(adw
, ADW_MC_SDTR_ABLE
,
629 adw_lram_write_16(adw
, ADW_MC_SDTR_DONE
,
636 ccb
->ccb_h
.status
= CAM_REQ_CMP
;
640 case XPT_GET_TRAN_SETTINGS
:
641 /* Get default/user set transfer settings for the target */
643 struct ccb_trans_settings_scsi
*scsi
;
644 struct ccb_trans_settings_spi
*spi
;
645 struct ccb_trans_settings
*cts
;
649 target_mask
= 0x01 << ccb
->ccb_h
.target_id
;
650 cts
->protocol
= PROTO_SCSI
;
651 cts
->protocol_version
= SCSI_REV_2
;
652 cts
->transport
= XPORT_SPI
;
653 cts
->transport_version
= 2;
655 scsi
= &cts
->proto_specific
.scsi
;
656 spi
= &cts
->xport_specific
.spi
;
657 if (cts
->type
== CTS_TYPE_CURRENT_SETTINGS
) {
661 if ((adw
->user_discenb
& target_mask
) != 0)
662 spi
->flags
|= CTS_SPI_FLAGS_DISC_ENB
;
664 if ((adw
->user_tagenb
& target_mask
) != 0)
665 scsi
->flags
|= CTS_SCSI_FLAGS_TAG_ENB
;
667 if ((adw
->user_wdtr
& target_mask
) != 0)
668 spi
->bus_width
= MSG_EXT_WDTR_BUS_16_BIT
;
670 spi
->bus_width
= MSG_EXT_WDTR_BUS_8_BIT
;
672 mc_sdtr
= adw_get_user_sdtr(adw
, ccb
->ccb_h
.target_id
);
673 spi
->sync_period
= adw_find_period(adw
, mc_sdtr
);
674 if (spi
->sync_period
!= 0)
675 spi
->sync_offset
= 15; /* XXX ??? */
677 spi
->sync_offset
= 0;
684 if ((adw_lram_read_16(adw
, ADW_MC_DISC_ENABLE
)
686 spi
->flags
|= CTS_SPI_FLAGS_DISC_ENB
;
688 if ((adw
->tagenb
& target_mask
) != 0)
689 scsi
->flags
|= CTS_SCSI_FLAGS_TAG_ENB
;
692 adw_lram_read_16(adw
,
693 ADW_MC_DEVICE_HSHK_CFG_TABLE
694 + (2 * ccb
->ccb_h
.target_id
));
696 if ((targ_tinfo
& ADW_HSHK_CFG_WIDE_XFR
) != 0)
697 spi
->bus_width
= MSG_EXT_WDTR_BUS_16_BIT
;
699 spi
->bus_width
= MSG_EXT_WDTR_BUS_8_BIT
;
702 adw_hshk_cfg_period_factor(targ_tinfo
);
704 spi
->sync_offset
= targ_tinfo
& ADW_HSHK_CFG_OFFSET
;
705 if (spi
->sync_period
== 0)
706 spi
->sync_offset
= 0;
708 if (spi
->sync_offset
== 0)
709 spi
->sync_period
= 0;
712 spi
->valid
= CTS_SPI_VALID_SYNC_RATE
713 | CTS_SPI_VALID_SYNC_OFFSET
714 | CTS_SPI_VALID_BUS_WIDTH
715 | CTS_SPI_VALID_DISC
;
716 scsi
->valid
= CTS_SCSI_VALID_TQ
;
717 ccb
->ccb_h
.status
= CAM_REQ_CMP
;
721 case XPT_CALC_GEOMETRY
:
723 struct ccb_calc_geometry
*ccg
;
725 u_int32_t secs_per_cylinder
;
729 * XXX Use Adaptec translation until I find out how to
730 * get this information from the card.
733 size_mb
= ccg
->volume_size
734 / ((1024L * 1024L) / ccg
->block_size
);
737 if (size_mb
> 1024 && extended
) {
739 ccg
->secs_per_track
= 63;
742 ccg
->secs_per_track
= 32;
744 secs_per_cylinder
= ccg
->heads
* ccg
->secs_per_track
;
745 ccg
->cylinders
= ccg
->volume_size
/ secs_per_cylinder
;
746 ccb
->ccb_h
.status
= CAM_REQ_CMP
;
750 case XPT_RESET_BUS
: /* Reset the specified SCSI bus */
754 failure
= adw_reset_bus(adw
);
756 ccb
->ccb_h
.status
= CAM_REQ_CMP_ERR
;
759 xpt_print_path(adw
->path
);
760 kprintf("Bus Reset Delivered\n");
762 ccb
->ccb_h
.status
= CAM_REQ_CMP
;
767 case XPT_TERM_IO
: /* Terminate the I/O process */
769 ccb
->ccb_h
.status
= CAM_REQ_INVALID
;
772 case XPT_PATH_INQ
: /* Path routing inquiry */
774 struct ccb_pathinq
*cpi
= &ccb
->cpi
;
776 cpi
->version_num
= 1;
777 cpi
->hba_inquiry
= PI_WIDE_16
|PI_SDTR_ABLE
|PI_TAG_ABLE
;
778 cpi
->target_sprt
= 0;
780 cpi
->hba_eng_cnt
= 0;
781 cpi
->max_target
= ADW_MAX_TID
;
782 cpi
->max_lun
= ADW_MAX_LUN
;
783 cpi
->initiator_id
= adw
->initiator_id
;
784 cpi
->bus_id
= cam_sim_bus(sim
);
785 cpi
->base_transfer_speed
= 3300;
786 strncpy(cpi
->sim_vid
, "FreeBSD", SIM_IDLEN
);
787 strncpy(cpi
->hba_vid
, "AdvanSys", HBA_IDLEN
);
788 strncpy(cpi
->dev_name
, cam_sim_name(sim
), DEV_IDLEN
);
789 cpi
->unit_number
= cam_sim_unit(sim
);
790 cpi
->transport
= XPORT_SPI
;
791 cpi
->transport_version
= 2;
792 cpi
->protocol
= PROTO_SCSI
;
793 cpi
->protocol_version
= SCSI_REV_2
;
794 cpi
->ccb_h
.status
= CAM_REQ_CMP
;
799 ccb
->ccb_h
.status
= CAM_REQ_INVALID
;
806 adw_poll(struct cam_sim
*sim
)
808 adw_intr(cam_sim_softc(sim
));
812 adw_async(void *callback_arg
, u_int32_t code
, struct cam_path
*path
, void *arg
)
817 adw_alloc(device_t dev
, struct resource
*regs
, int regs_type
, int regs_id
)
819 struct adw_softc
*adw
;
823 * Allocate a storage area for us
825 adw
= kmalloc(sizeof(struct adw_softc
), M_DEVBUF
, M_INTWAIT
| M_ZERO
);
826 LIST_INIT(&adw
->pending_ccbs
);
827 SLIST_INIT(&adw
->sg_maps
);
829 adw
->unit
= device_get_unit(dev
);
830 adw
->regs_res_type
= regs_type
;
831 adw
->regs_res_id
= regs_id
;
833 adw
->tag
= rman_get_bustag(regs
);
834 adw
->bsh
= rman_get_bushandle(regs
);
835 KKASSERT(adw
->unit
>= 0 && adw
->unit
< 100);
837 adw
->name
= kmalloc(sizeof("adw") + i
+ 1, M_DEVBUF
, M_INTWAIT
);
838 ksprintf(adw
->name
, "adw%d", adw
->unit
);
843 adw_free(struct adw_softc
*adw
)
845 switch (adw
->init_level
) {
848 struct sg_map_node
*sg_map
;
850 while ((sg_map
= SLIST_FIRST(&adw
->sg_maps
)) != NULL
) {
851 SLIST_REMOVE_HEAD(&adw
->sg_maps
, links
);
852 bus_dmamap_unload(adw
->sg_dmat
,
854 bus_dmamem_free(adw
->sg_dmat
, sg_map
->sg_vaddr
,
856 kfree(sg_map
, M_DEVBUF
);
858 bus_dma_tag_destroy(adw
->sg_dmat
);
861 bus_dmamap_unload(adw
->acb_dmat
, adw
->acb_dmamap
);
863 bus_dmamem_free(adw
->acb_dmat
, adw
->acbs
,
865 bus_dmamap_destroy(adw
->acb_dmat
, adw
->acb_dmamap
);
867 bus_dma_tag_destroy(adw
->acb_dmat
);
869 bus_dmamap_unload(adw
->carrier_dmat
, adw
->carrier_dmamap
);
871 bus_dmamem_free(adw
->carrier_dmat
, adw
->carriers
,
872 adw
->carrier_dmamap
);
873 bus_dmamap_destroy(adw
->carrier_dmat
, adw
->carrier_dmamap
);
875 bus_dma_tag_destroy(adw
->carrier_dmat
);
877 bus_dma_tag_destroy(adw
->buffer_dmat
);
879 bus_dma_tag_destroy(adw
->parent_dmat
);
883 kfree(adw
->name
, M_DEVBUF
);
884 kfree(adw
, M_DEVBUF
);
888 adw_init(struct adw_softc
*adw
)
890 struct adw_eeprom eep_config
;
896 checksum
= adw_eeprom_read(adw
, &eep_config
);
897 bcopy(eep_config
.serial_number
, adw
->serial_number
,
898 sizeof(adw
->serial_number
));
899 if (checksum
!= eep_config
.checksum
) {
900 u_int16_t serial_number
[3];
902 adw
->flags
|= ADW_EEPROM_FAILED
;
903 kprintf("%s: EEPROM checksum failed. Restoring Defaults\n",
907 * Restore the default EEPROM settings.
908 * Assume the 6 byte board serial number that was read
909 * from EEPROM is correct even if the EEPROM checksum
912 bcopy(adw
->default_eeprom
, &eep_config
, sizeof(eep_config
));
913 bcopy(adw
->serial_number
, eep_config
.serial_number
,
914 sizeof(serial_number
));
915 adw_eeprom_write(adw
, &eep_config
);
918 /* Pull eeprom information into our softc. */
919 adw
->bios_ctrl
= eep_config
.bios_ctrl
;
920 adw
->user_wdtr
= eep_config
.wdtr_able
;
921 for (tid
= 0; tid
< ADW_MAX_TID
; tid
++) {
925 tid_mask
= 0x1 << tid
;
926 if ((adw
->features
& ADW_ULTRA
) != 0) {
928 * Ultra chips store sdtr and ultraenb
929 * bits in their seeprom, so we must
930 * construct valid mc_sdtr entries for
933 if (eep_config
.sync1
.sync_enable
& tid_mask
) {
934 if (eep_config
.sync2
.ultra_enable
& tid_mask
)
935 mc_sdtr
= ADW_MC_SDTR_20
;
937 mc_sdtr
= ADW_MC_SDTR_10
;
939 mc_sdtr
= ADW_MC_SDTR_ASYNC
;
941 switch (ADW_TARGET_GROUP(tid
)) {
943 mc_sdtr
= eep_config
.sync4
.sdtr4
;
946 mc_sdtr
= eep_config
.sync3
.sdtr3
;
949 mc_sdtr
= eep_config
.sync2
.sdtr2
;
951 default: /* Shut up compiler */
953 mc_sdtr
= eep_config
.sync1
.sdtr1
;
956 mc_sdtr
>>= ADW_TARGET_GROUP_SHIFT(tid
);
959 adw_set_user_sdtr(adw
, tid
, mc_sdtr
);
961 adw
->user_tagenb
= eep_config
.tagqng_able
;
962 adw
->user_discenb
= eep_config
.disc_enable
;
963 adw
->max_acbs
= eep_config
.max_host_qng
;
964 adw
->initiator_id
= (eep_config
.adapter_scsi_id
& ADW_MAX_TID
);
967 * Sanity check the number of host openings.
969 if (adw
->max_acbs
> ADW_DEF_MAX_HOST_QNG
)
970 adw
->max_acbs
= ADW_DEF_MAX_HOST_QNG
;
971 else if (adw
->max_acbs
< ADW_DEF_MIN_HOST_QNG
) {
972 /* If the value is zero, assume it is uninitialized. */
973 if (adw
->max_acbs
== 0)
974 adw
->max_acbs
= ADW_DEF_MAX_HOST_QNG
;
976 adw
->max_acbs
= ADW_DEF_MIN_HOST_QNG
;
980 if ((adw
->features
& ADW_ULTRA2
) != 0) {
981 switch (eep_config
.termination_lvd
) {
983 kprintf("%s: Invalid EEPROM LVD Termination Settings.\n",
985 kprintf("%s: Reverting to Automatic LVD Termination\n",
988 case ADW_EEPROM_TERM_AUTO
:
990 case ADW_EEPROM_TERM_BOTH_ON
:
991 scsicfg1
|= ADW2_SCSI_CFG1_TERM_LVD_LO
;
993 case ADW_EEPROM_TERM_HIGH_ON
:
994 scsicfg1
|= ADW2_SCSI_CFG1_TERM_LVD_HI
;
996 case ADW_EEPROM_TERM_OFF
:
997 scsicfg1
|= ADW2_SCSI_CFG1_DIS_TERM_DRV
;
1002 switch (eep_config
.termination_se
) {
1004 kprintf("%s: Invalid SE EEPROM Termination Settings.\n",
1006 kprintf("%s: Reverting to Automatic SE Termination\n",
1009 case ADW_EEPROM_TERM_AUTO
:
1011 case ADW_EEPROM_TERM_BOTH_ON
:
1012 scsicfg1
|= ADW_SCSI_CFG1_TERM_CTL_L
;
1014 case ADW_EEPROM_TERM_HIGH_ON
:
1015 scsicfg1
|= ADW_SCSI_CFG1_TERM_CTL_H
;
1017 case ADW_EEPROM_TERM_OFF
:
1018 scsicfg1
|= ADW_SCSI_CFG1_TERM_CTL_MANUAL
;
1021 kprintf("%s: SCSI ID %d, ", adw_name(adw
), adw
->initiator_id
);
1023 /* DMA tag for mapping buffers into device visible space. */
1024 if (bus_dma_tag_create(adw
->parent_dmat
, /*alignment*/1, /*boundary*/0,
1025 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT
,
1026 /*highaddr*/BUS_SPACE_MAXADDR
,
1027 /*filter*/NULL
, /*filterarg*/NULL
,
1028 /*maxsize*/MAXBSIZE
, /*nsegments*/ADW_SGSIZE
,
1029 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT
,
1030 /*flags*/BUS_DMA_ALLOCNOW
,
1031 &adw
->buffer_dmat
) != 0) {
1037 /* DMA tag for our ccb carrier structures */
1038 if (bus_dma_tag_create(adw
->parent_dmat
, /*alignment*/0x10,
1040 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT
,
1041 /*highaddr*/BUS_SPACE_MAXADDR
,
1042 /*filter*/NULL
, /*filterarg*/NULL
,
1043 (adw
->max_acbs
+ ADW_NUM_CARRIER_QUEUES
+ 1)
1044 * sizeof(struct adw_carrier
),
1046 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT
,
1047 /*flags*/0, &adw
->carrier_dmat
) != 0) {
1053 /* Allocation for our ccb carrier structures */
1054 if (bus_dmamem_alloc(adw
->carrier_dmat
, (void **)&adw
->carriers
,
1055 BUS_DMA_NOWAIT
, &adw
->carrier_dmamap
) != 0) {
1061 /* And permanently map them */
1062 bus_dmamap_load(adw
->carrier_dmat
, adw
->carrier_dmamap
,
1064 (adw
->max_acbs
+ ADW_NUM_CARRIER_QUEUES
+ 1)
1065 * sizeof(struct adw_carrier
),
1066 adwmapmem
, &adw
->carrier_busbase
, /*flags*/0);
1068 /* Clear them out. */
1069 bzero(adw
->carriers
, (adw
->max_acbs
+ ADW_NUM_CARRIER_QUEUES
+ 1)
1070 * sizeof(struct adw_carrier
));
1072 /* Setup our free carrier list */
1073 adw
->free_carriers
= adw
->carriers
;
1074 for (i
= 0; i
< adw
->max_acbs
+ ADW_NUM_CARRIER_QUEUES
; i
++) {
1075 adw
->carriers
[i
].carr_offset
=
1076 carriervtobo(adw
, &adw
->carriers
[i
]);
1077 adw
->carriers
[i
].carr_ba
=
1078 carriervtob(adw
, &adw
->carriers
[i
]);
1079 adw
->carriers
[i
].areq_ba
= 0;
1080 adw
->carriers
[i
].next_ba
=
1081 carriervtobo(adw
, &adw
->carriers
[i
+1]);
1083 /* Terminal carrier. Never leaves the freelist */
1084 adw
->carriers
[i
].carr_offset
=
1085 carriervtobo(adw
, &adw
->carriers
[i
]);
1086 adw
->carriers
[i
].carr_ba
=
1087 carriervtob(adw
, &adw
->carriers
[i
]);
1088 adw
->carriers
[i
].areq_ba
= 0;
1089 adw
->carriers
[i
].next_ba
= ~0;
1093 /* DMA tag for our acb structures */
1094 if (bus_dma_tag_create(adw
->parent_dmat
, /*alignment*/1, /*boundary*/0,
1095 /*lowaddr*/BUS_SPACE_MAXADDR
,
1096 /*highaddr*/BUS_SPACE_MAXADDR
,
1097 /*filter*/NULL
, /*filterarg*/NULL
,
1098 adw
->max_acbs
* sizeof(struct acb
),
1100 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT
,
1101 /*flags*/0, &adw
->acb_dmat
) != 0) {
1107 /* Allocation for our ccbs */
1108 if (bus_dmamem_alloc(adw
->acb_dmat
, (void **)&adw
->acbs
,
1109 BUS_DMA_NOWAIT
, &adw
->acb_dmamap
) != 0)
1114 /* And permanently map them */
1115 bus_dmamap_load(adw
->acb_dmat
, adw
->acb_dmamap
,
1117 adw
->max_acbs
* sizeof(struct acb
),
1118 adwmapmem
, &adw
->acb_busbase
, /*flags*/0);
1120 /* Clear them out. */
1121 bzero(adw
->acbs
, adw
->max_acbs
* sizeof(struct acb
));
1123 /* DMA tag for our S/G structures. We allocate in page sized chunks */
1124 if (bus_dma_tag_create(adw
->parent_dmat
, /*alignment*/1, /*boundary*/0,
1125 /*lowaddr*/BUS_SPACE_MAXADDR
,
1126 /*highaddr*/BUS_SPACE_MAXADDR
,
1127 /*filter*/NULL
, /*filterarg*/NULL
,
1128 PAGE_SIZE
, /*nsegments*/1,
1129 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT
,
1130 /*flags*/0, &adw
->sg_dmat
) != 0) {
1136 /* Allocate our first batch of ccbs */
1137 if (adwallocacbs(adw
) == 0)
1140 if (adw_init_chip(adw
, scsicfg1
) != 0)
1143 kprintf("Queue Depth %d\n", adw
->max_acbs
);
1149 * Attach all the sub-devices we can find
1152 adw_attach(struct adw_softc
*adw
)
1154 struct ccb_setasync csa
;
1159 /* Hook up our interrupt handler */
1160 if ((error
= bus_setup_intr(adw
->device
, adw
->irq
, 0,
1161 adw_intr
, adw
, &adw
->ih
, NULL
)) != 0) {
1162 device_printf(adw
->device
, "bus_setup_intr() failed: %d\n",
1167 /* Start the Risc processor now that we are fully configured. */
1168 adw_outw(adw
, ADW_RISC_CSR
, ADW_RISC_CSR_RUN
);
1171 * Construct our SIM entry.
1173 adw
->sim
= cam_sim_alloc(adw_action
, adw_poll
, "adw", adw
, adw
->unit
,
1174 &sim_mplock
, 1, adw
->max_acbs
, NULL
);
1175 if (adw
->sim
== NULL
) {
1183 if (xpt_bus_register(adw
->sim
, 0) != CAM_SUCCESS
) {
1184 cam_sim_free(adw
->sim
);
1189 if (xpt_create_path(&adw
->path
, /*periph*/NULL
, cam_sim_path(adw
->sim
),
1190 CAM_TARGET_WILDCARD
, CAM_LUN_WILDCARD
)
1192 xpt_setup_ccb(&csa
.ccb_h
, adw
->path
, /*priority*/5);
1193 csa
.ccb_h
.func_code
= XPT_SASYNC_CB
;
1194 csa
.event_enable
= AC_LOST_DEVICE
;
1195 csa
.callback
= adw_async
;
1196 csa
.callback_arg
= adw
;
1197 xpt_action((union ccb
*)&csa
);
1208 struct adw_softc
*adw
;
1211 adw
= (struct adw_softc
*)arg
;
1212 if ((adw_inw(adw
, ADW_CTRL_REG
) & ADW_CTRL_REG_HOST_INTR
) == 0)
1215 /* Reading the register clears the interrupt. */
1216 int_stat
= adw_inb(adw
, ADW_INTR_STATUS_REG
);
1218 if ((int_stat
& ADW_INTR_STATUS_INTRB
) != 0) {
1221 /* Async Microcode Event */
1222 intrb_code
= adw_lram_read_8(adw
, ADW_MC_INTRB_CODE
);
1223 switch (intrb_code
) {
1224 case ADW_ASYNC_CARRIER_READY_FAILURE
:
1226 * The RISC missed our update of
1229 if (LIST_FIRST(&adw
->pending_ccbs
) != NULL
)
1230 adw_tickle_risc(adw
, ADW_TICKLE_A
);
1232 case ADW_ASYNC_SCSI_BUS_RESET_DET
:
1234 * The firmware detected a SCSI Bus reset.
1236 kprintf("Someone Reset the Bus\n");
1237 adw_handle_bus_reset(adw
, /*initiated*/FALSE
);
1239 case ADW_ASYNC_RDMA_FAILURE
:
1241 * Handle RDMA failure by resetting the
1242 * SCSI Bus and chip.
1245 AdvResetChipAndSB(adv_dvc_varp
);
1249 case ADW_ASYNC_HOST_SCSI_BUS_RESET
:
1251 * Host generated SCSI bus reset occurred.
1253 adw_handle_bus_reset(adw
, /*initiated*/TRUE
);
1256 kprintf("adw_intr: unknown async code 0x%x\n",
1263 * Run down the RequestQ.
1265 while ((adw
->responseq
->next_ba
& ADW_RQ_DONE
) != 0) {
1266 struct adw_carrier
*free_carrier
;
1271 kprintf("0x%x, 0x%x, 0x%x, 0x%x\n",
1272 adw
->responseq
->carr_offset
,
1273 adw
->responseq
->carr_ba
,
1274 adw
->responseq
->areq_ba
,
1275 adw
->responseq
->next_ba
);
1278 * The firmware copies the adw_scsi_req_q.acb_baddr
1279 * field into the areq_ba field of the carrier.
1281 acb
= acbbotov(adw
, adw
->responseq
->areq_ba
);
1284 * The least significant four bits of the next_ba
1285 * field are used as flags. Mask them out and then
1286 * advance through the list.
1288 free_carrier
= adw
->responseq
;
1290 carrierbotov(adw
, free_carrier
->next_ba
& ADW_NEXT_BA_MASK
);
1291 free_carrier
->next_ba
= adw
->free_carriers
->carr_offset
;
1292 adw
->free_carriers
= free_carrier
;
1296 callout_stop(&ccb
->ccb_h
.timeout_ch
);
1297 if ((ccb
->ccb_h
.flags
& CAM_DIR_MASK
) != CAM_DIR_NONE
) {
1298 bus_dmasync_op_t op
;
1300 if ((ccb
->ccb_h
.flags
& CAM_DIR_MASK
) == CAM_DIR_IN
)
1301 op
= BUS_DMASYNC_POSTREAD
;
1303 op
= BUS_DMASYNC_POSTWRITE
;
1304 bus_dmamap_sync(adw
->buffer_dmat
, acb
->dmamap
, op
);
1305 bus_dmamap_unload(adw
->buffer_dmat
, acb
->dmamap
);
1306 ccb
->csio
.resid
= acb
->queue
.data_cnt
;
1308 ccb
->csio
.resid
= 0;
1310 /* Common Cases inline... */
1311 if (acb
->queue
.host_status
== QHSTA_NO_ERROR
1312 && (acb
->queue
.done_status
== QD_NO_ERROR
1313 || acb
->queue
.done_status
== QD_WITH_ERROR
)) {
1314 ccb
->csio
.scsi_status
= acb
->queue
.scsi_status
;
1315 ccb
->ccb_h
.status
= 0;
1316 switch (ccb
->csio
.scsi_status
) {
1317 case SCSI_STATUS_OK
:
1318 ccb
->ccb_h
.status
|= CAM_REQ_CMP
;
1320 case SCSI_STATUS_CHECK_COND
:
1321 case SCSI_STATUS_CMD_TERMINATED
:
1322 bcopy(&acb
->sense_data
, &ccb
->csio
.sense_data
,
1323 ccb
->csio
.sense_len
);
1324 ccb
->ccb_h
.status
|= CAM_AUTOSNS_VALID
;
1325 ccb
->csio
.sense_resid
= acb
->queue
.sense_len
;
1328 ccb
->ccb_h
.status
|= CAM_SCSI_STATUS_ERROR
1330 xpt_freeze_devq(ccb
->ccb_h
.path
, /*count*/1);
1333 adwfreeacb(adw
, acb
);
1336 adwprocesserror(adw
, acb
);
1342 adwprocesserror(struct adw_softc
*adw
, struct acb
*acb
)
1347 if (acb
->queue
.done_status
== QD_ABORTED_BY_HOST
) {
1348 ccb
->ccb_h
.status
= CAM_REQ_ABORTED
;
1351 switch (acb
->queue
.host_status
) {
1352 case QHSTA_M_SEL_TIMEOUT
:
1353 ccb
->ccb_h
.status
= CAM_SEL_TIMEOUT
;
1355 case QHSTA_M_SXFR_OFF_UFLW
:
1356 case QHSTA_M_SXFR_OFF_OFLW
:
1357 case QHSTA_M_DATA_OVER_RUN
:
1358 ccb
->ccb_h
.status
= CAM_DATA_RUN_ERR
;
1360 case QHSTA_M_SXFR_DESELECTED
:
1361 case QHSTA_M_UNEXPECTED_BUS_FREE
:
1362 ccb
->ccb_h
.status
= CAM_UNEXP_BUSFREE
;
1364 case QHSTA_M_SCSI_BUS_RESET
:
1365 case QHSTA_M_SCSI_BUS_RESET_UNSOL
:
1366 ccb
->ccb_h
.status
= CAM_SCSI_BUS_RESET
;
1368 case QHSTA_M_BUS_DEVICE_RESET
:
1369 ccb
->ccb_h
.status
= CAM_BDR_SENT
;
1371 case QHSTA_M_QUEUE_ABORTED
:
1372 /* BDR or Bus Reset */
1373 kprintf("Saw Queue Aborted\n");
1374 ccb
->ccb_h
.status
= adw
->last_reset
;
1376 case QHSTA_M_SXFR_SDMA_ERR
:
1377 case QHSTA_M_SXFR_SXFR_PERR
:
1378 case QHSTA_M_RDMA_PERR
:
1379 ccb
->ccb_h
.status
= CAM_UNCOR_PARITY
;
1381 case QHSTA_M_WTM_TIMEOUT
:
1382 case QHSTA_M_SXFR_WD_TMO
:
1384 /* The SCSI bus hung in a phase */
1385 xpt_print_path(adw
->path
);
1386 kprintf("Watch Dog timer expired. Reseting bus\n");
1390 case QHSTA_M_SXFR_XFR_PH_ERR
:
1391 ccb
->ccb_h
.status
= CAM_SEQUENCE_FAIL
;
1393 case QHSTA_M_SXFR_UNKNOWN_ERROR
:
1395 case QHSTA_M_BAD_CMPL_STATUS_IN
:
1396 /* No command complete after a status message */
1397 ccb
->ccb_h
.status
= CAM_SEQUENCE_FAIL
;
1399 case QHSTA_M_AUTO_REQ_SENSE_FAIL
:
1400 ccb
->ccb_h
.status
= CAM_AUTOSENSE_FAIL
;
1402 case QHSTA_M_INVALID_DEVICE
:
1403 ccb
->ccb_h
.status
= CAM_PATH_INVALID
;
1405 case QHSTA_M_NO_AUTO_REQ_SENSE
:
1407 * User didn't request sense, but we got a
1410 ccb
->csio
.scsi_status
= acb
->queue
.scsi_status
;
1411 ccb
->ccb_h
.status
= CAM_SCSI_STATUS_ERROR
;
1414 panic("%s: Unhandled Host status error %x",
1415 adw_name(adw
), acb
->queue
.host_status
);
1419 if ((acb
->state
& ACB_RECOVERY_ACB
) != 0) {
1420 if (ccb
->ccb_h
.status
== CAM_SCSI_BUS_RESET
1421 || ccb
->ccb_h
.status
== CAM_BDR_SENT
)
1422 ccb
->ccb_h
.status
= CAM_CMD_TIMEOUT
;
1424 if (ccb
->ccb_h
.status
!= CAM_REQ_CMP
) {
1425 xpt_freeze_devq(ccb
->ccb_h
.path
, /*count*/1);
1426 ccb
->ccb_h
.status
|= CAM_DEV_QFRZN
;
1428 adwfreeacb(adw
, acb
);
1433 adwtimeout(void *arg
)
1437 struct adw_softc
*adw
;
1438 adw_idle_cmd_status_t status
;
1441 acb
= (struct acb
*)arg
;
1443 adw
= (struct adw_softc
*)ccb
->ccb_h
.ccb_adw_ptr
;
1444 xpt_print_path(ccb
->ccb_h
.path
);
1445 kprintf("ACB %p - timed out\n", (void *)acb
);
1449 if ((acb
->state
& ACB_ACTIVE
) == 0) {
1450 xpt_print_path(ccb
->ccb_h
.path
);
1451 kprintf("ACB %p - timed out CCB already completed\n",
1457 acb
->state
|= ACB_RECOVERY_ACB
;
1458 target_id
= ccb
->ccb_h
.target_id
;
1460 /* Attempt a BDR first */
1461 status
= adw_idle_cmd_send(adw
, ADW_IDLE_CMD_DEVICE_RESET
,
1462 ccb
->ccb_h
.target_id
);
1464 if (status
== ADW_IDLE_CMD_SUCCESS
) {
1465 kprintf("%s: BDR Delivered. No longer in timeout\n",
1467 adw_handle_device_reset(adw
, target_id
);
1470 xpt_print_path(adw
->path
);
1471 kprintf("Bus Reset Delivered. No longer in timeout\n");
1476 adw_handle_device_reset(struct adw_softc
*adw
, u_int target
)
1478 struct cam_path
*path
;
1481 error
= xpt_create_path(&path
, /*periph*/NULL
, cam_sim_path(adw
->sim
),
1482 target
, CAM_LUN_WILDCARD
);
1484 if (error
== CAM_REQ_CMP
) {
1485 xpt_async(AC_SENT_BDR
, path
, NULL
);
1486 xpt_free_path(path
);
1488 adw
->last_reset
= CAM_BDR_SENT
;
1492 adw_handle_bus_reset(struct adw_softc
*adw
, int initiated
)
1496 * The microcode currently sets the SCSI Bus Reset signal
1497 * while handling the AscSendIdleCmd() IDLE_CMD_SCSI_RESET
1498 * command above. But the SCSI Bus Reset Hold Time in the
1499 * microcode is not deterministic (it may in fact be for less
1500 * than the SCSI Spec. minimum of 25 us). Therefore on return
1501 * the Adv Library sets the SCSI Bus Reset signal for
1502 * ADW_SCSI_RESET_HOLD_TIME_US, which is defined to be greater
1507 scsi_ctrl
= adw_inw(adw
, ADW_SCSI_CTRL
) & ~ADW_SCSI_CTRL_RSTOUT
;
1508 adw_outw(adw
, ADW_SCSI_CTRL
, scsi_ctrl
| ADW_SCSI_CTRL_RSTOUT
);
1509 DELAY(ADW_SCSI_RESET_HOLD_TIME_US
);
1510 adw_outw(adw
, ADW_SCSI_CTRL
, scsi_ctrl
);
1513 * We will perform the async notification when the
1514 * SCSI Reset interrupt occurs.
1517 xpt_async(AC_BUS_RESET
, adw
->path
, NULL
);
1518 adw
->last_reset
= CAM_SCSI_BUS_RESET
;