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Remove empty DragonFly CVS IDs.
[dragonfly.git] / sys / dev / netif / ath / hal / ath_hal / ar5212 / ar5212.h
blobea5d2dba12f47f7e8397c3eaba597d139a35dced
1 /*
2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
3 * Copyright (c) 2002-2008 Atheros Communications, Inc.
4 *
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
8 *
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16 *
17 * $FreeBSD: head/sys/dev/ath/ath_hal/ar5212/ar5212.h 188979 2009-02-24 01:07:06Z sam $
18 */
19 #ifndef _ATH_AR5212_H_
20 #define _ATH_AR5212_H_
21
22 #include "ah_eeprom.h"
23
24 #define AR5212_MAGIC 0x19541014
25
26 /* DCU Transmit Filter macros */
27 #define CALC_MMR(dcu, idx) \
28 ( (4 * dcu) + (idx < 32 ? 0 : (idx < 64 ? 1 : (idx < 96 ? 2 : 3))) )
29 #define TXBLK_FROM_MMR(mmr) \
30 (AR_D_TXBLK_BASE + ((mmr & 0x1f) << 6) + ((mmr & 0x20) >> 3))
31 #define CALC_TXBLK_ADDR(dcu, idx) (TXBLK_FROM_MMR(CALC_MMR(dcu, idx)))
32 #define CALC_TXBLK_VALUE(idx) (1 << (idx & 0x1f))
33
34 /* MAC register values */
35
36 #define INIT_INTERRUPT_MASK \
37 ( AR_IMR_TXERR | AR_IMR_TXOK | AR_IMR_RXORN | \
38 AR_IMR_RXERR | AR_IMR_RXOK | AR_IMR_TXURN | \
39 AR_IMR_HIUERR )
40 #define INIT_BEACON_CONTROL \
41 ((INIT_RESET_TSF << 24) | (INIT_BEACON_EN << 23) | \
42 (INIT_TIM_OFFSET << 16) | INIT_BEACON_PERIOD)
43
44 #define INIT_CONFIG_STATUS 0x00000000
45 #define INIT_RSSI_THR 0x00000781 /* Missed beacon counter initialized to 0x7 (max is 0xff) */
46 #define INIT_IQCAL_LOG_COUNT_MAX 0xF
47 #define INIT_BCON_CNTRL_REG 0x00000000
48
49 #define INIT_USEC 40
50 #define HALF_RATE_USEC 19 /* ((40 / 2) - 1 ) */
51 #define QUARTER_RATE_USEC 9 /* ((40 / 4) - 1 ) */
52
53 #define RX_NON_FULL_RATE_LATENCY 63
54 #define TX_HALF_RATE_LATENCY 108
55 #define TX_QUARTER_RATE_LATENCY 216
56
57 #define IFS_SLOT_FULL_RATE 0x168 /* 9 us half, 40 MHz core clock (9*40) */
58 #define IFS_SLOT_HALF_RATE 0x104 /* 13 us half, 20 MHz core clock (13*20) */
59 #define IFS_SLOT_QUARTER_RATE 0xD2 /* 21 us quarter, 10 MHz core clock (21*10) */
60 #define IFS_EIFS_FULL_RATE 0xE60 /* (74 + (2 * 9)) * 40MHz core clock */
61 #define IFS_EIFS_HALF_RATE 0xDAC /* (149 + (2 * 13)) * 20MHz core clock */
62 #define IFS_EIFS_QUARTER_RATE 0xD48 /* (298 + (2 * 21)) * 10MHz core clock */
63
64 #define ACK_CTS_TIMEOUT_11A 0x3E8 /* ACK timeout in 11a core clocks */
65
66 /* Tx frame start to tx data start delay */
67 #define TX_FRAME_D_START_HALF_RATE 0xc
68 #define TX_FRAME_D_START_QUARTER_RATE 0xd
69
70 /*
71 * Various fifo fill before Tx start, in 64-byte units
72 * i.e. put the frame in the air while still DMAing
73 */
74 #define MIN_TX_FIFO_THRESHOLD 0x1
75 #define MAX_TX_FIFO_THRESHOLD ((IEEE80211_MAX_LEN / 64) + 1)
76 #define INIT_TX_FIFO_THRESHOLD MIN_TX_FIFO_THRESHOLD
77
78 #define HAL_DECOMP_MASK_SIZE 128 /* 1 byte per key */
79
80 /*
81 * Gain support.
82 */
83 #define NUM_CORNER_FIX_BITS 4
84 #define NUM_CORNER_FIX_BITS_5112 7
85 #define DYN_ADJ_UP_MARGIN 15
86 #define DYN_ADJ_LO_MARGIN 20
87 #define PHY_PROBE_CCK_CORRECTION 5
88 #define CCK_OFDM_GAIN_DELTA 15
89
90 enum GAIN_PARAMS {
91 GP_TXCLIP,
92 GP_PD90,
93 GP_PD84,
94 GP_GSEL,
95 };
96
97 enum GAIN_PARAMS_5112 {
98 GP_MIXGAIN_OVR,
99 GP_PWD_138,
100 GP_PWD_137,
101 GP_PWD_136,
102 GP_PWD_132,
103 GP_PWD_131,
104 GP_PWD_130,
105 };
106
107 typedef struct _gainOptStep {
108 int16_t paramVal[NUM_CORNER_FIX_BITS_5112];
109 int32_t stepGain;
110 int8_t stepName[16];
111 } GAIN_OPTIMIZATION_STEP;
112
113 typedef struct {
114 uint32_t numStepsInLadder;
115 uint32_t defaultStepNum;
116 GAIN_OPTIMIZATION_STEP optStep[10];
117 } GAIN_OPTIMIZATION_LADDER;
118
119 typedef struct {
120 uint32_t currStepNum;
121 uint32_t currGain;
122 uint32_t targetGain;
123 uint32_t loTrig;
124 uint32_t hiTrig;
125 uint32_t active;
126 const GAIN_OPTIMIZATION_STEP *currStep;
127 } GAIN_VALUES;
128
129 /* RF HAL structures */
130 typedef struct RfHalFuncs {
131 void *priv; /* private state */
132
133 void (*rfDetach)(struct ath_hal *ah);
134 void (*writeRegs)(struct ath_hal *,
135 u_int modeIndex, u_int freqIndex, int regWrites);
136 uint32_t *(*getRfBank)(struct ath_hal *ah, int bank);
137 HAL_BOOL (*setChannel)(struct ath_hal *,
138 const struct ieee80211_channel *);
139 HAL_BOOL (*setRfRegs)(struct ath_hal *,
140 const struct ieee80211_channel *, uint16_t modesIndex,
141 uint16_t *rfXpdGain);
142 HAL_BOOL (*setPowerTable)(struct ath_hal *ah,
143 int16_t *minPower, int16_t *maxPower,
144 const struct ieee80211_channel *, uint16_t *rfXpdGain);
145 HAL_BOOL (*getChannelMaxMinPower)(struct ath_hal *ah,
146 const const struct ieee80211_channel *,
147 int16_t *maxPow, int16_t *minPow);
148 int16_t (*getNfAdjust)(struct ath_hal *, const HAL_CHANNEL_INTERNAL*);
149 } RF_HAL_FUNCS;
150
151 struct ar5212AniParams {
152 int maxNoiseImmunityLevel; /* [0..4] */
153 int totalSizeDesired[5];
154 int coarseHigh[5];
155 int coarseLow[5];
156 int firpwr[5];
157
158 int maxSpurImmunityLevel; /* [0..7] */
159 int cycPwrThr1[8];
160
161 int maxFirstepLevel; /* [0..2] */
162 int firstep[3];
163
164 uint32_t ofdmTrigHigh;
165 uint32_t ofdmTrigLow;
166 uint32_t cckTrigHigh;
167 uint32_t cckTrigLow;
168 int32_t rssiThrLow;
169 uint32_t rssiThrHigh;
170
171 int period; /* update listen period */
172
173 /* NB: intentionally ordered so data exported to user space is first */
174 uint32_t ofdmPhyErrBase; /* Base value for ofdm err counter */
175 uint32_t cckPhyErrBase; /* Base value for cck err counters */
176 };
177
178 /*
179 * Per-channel ANI state private to the driver.
180 */
181 struct ar5212AniState {
182 uint8_t noiseImmunityLevel;
183 uint8_t spurImmunityLevel;
184 uint8_t firstepLevel;
185 uint8_t ofdmWeakSigDetectOff;
186 uint8_t cckWeakSigThreshold;
187 uint32_t listenTime;
188
189 /* NB: intentionally ordered so data exported to user space is first */
190 uint32_t txFrameCount; /* Last txFrameCount */
191 uint32_t rxFrameCount; /* Last rx Frame count */
192 uint32_t cycleCount; /* Last cycleCount
193 (to detect wrap-around) */
194 uint32_t ofdmPhyErrCount;/* OFDM err count since last reset */
195 uint32_t cckPhyErrCount; /* CCK err count since last reset */
196
197 const struct ar5212AniParams *params;
198 };
199
200 #define HAL_ANI_ENA 0x00000001 /* ANI operation enabled */
201 #define HAL_RSSI_ANI_ENA 0x00000002 /* rssi-based processing ena'd*/
202
203 struct ar5212Stats {
204 uint32_t ast_ani_niup; /* ANI increased noise immunity */
205 uint32_t ast_ani_nidown; /* ANI decreased noise immunity */
206 uint32_t ast_ani_spurup; /* ANI increased spur immunity */
207 uint32_t ast_ani_spurdown;/* ANI descreased spur immunity */
208 uint32_t ast_ani_ofdmon; /* ANI OFDM weak signal detect on */
209 uint32_t ast_ani_ofdmoff;/* ANI OFDM weak signal detect off */
210 uint32_t ast_ani_cckhigh;/* ANI CCK weak signal threshold high */
211 uint32_t ast_ani_ccklow; /* ANI CCK weak signal threshold low */
212 uint32_t ast_ani_stepup; /* ANI increased first step level */
213 uint32_t ast_ani_stepdown;/* ANI decreased first step level */
214 uint32_t ast_ani_ofdmerrs;/* ANI cumulative ofdm phy err count */
215 uint32_t ast_ani_cckerrs;/* ANI cumulative cck phy err count */
216 uint32_t ast_ani_reset; /* ANI parameters zero'd for non-STA */
217 uint32_t ast_ani_lzero; /* ANI listen time forced to zero */
218 uint32_t ast_ani_lneg; /* ANI listen time calculated < 0 */
219 HAL_MIB_STATS ast_mibstats; /* MIB counter stats */
220 HAL_NODE_STATS ast_nodestats; /* Latest rssi stats from driver */
221 };
222
223 /*
224 * NF Cal history buffer
225 */
226 #define AR5212_CCA_MAX_GOOD_VALUE -95
227 #define AR5212_CCA_MAX_HIGH_VALUE -62
228 #define AR5212_CCA_MIN_BAD_VALUE -125
229
230 #define AR512_NF_CAL_HIST_MAX 5
231
232 struct ar5212NfCalHist {
233 int16_t nfCalBuffer[AR512_NF_CAL_HIST_MAX];
234 int16_t privNF;
235 uint8_t currIndex;
236 uint8_t first_run;
237 uint8_t invalidNFcount;
238 };
239
240 struct ath_hal_5212 {
241 struct ath_hal_private ah_priv; /* base class */
242
243 /*
244 * Per-chip common Initialization data.
245 * NB: RF backends have their own ini data.
246 */
247 HAL_INI_ARRAY ah_ini_modes;
248 HAL_INI_ARRAY ah_ini_common;
249
250 GAIN_VALUES ah_gainValues;
251
252 uint8_t ah_macaddr[IEEE80211_ADDR_LEN];
253 uint8_t ah_bssid[IEEE80211_ADDR_LEN];
254 uint8_t ah_bssidmask[IEEE80211_ADDR_LEN];
255
256 /*
257 * Runtime state.
258 */
259 uint32_t ah_maskReg; /* copy of AR_IMR */
260 struct ar5212Stats ah_stats; /* various statistics */
261 RF_HAL_FUNCS *ah_rfHal;
262 uint32_t ah_txDescMask; /* mask for TXDESC */
263 uint32_t ah_txOkInterruptMask;
264 uint32_t ah_txErrInterruptMask;
265 uint32_t ah_txDescInterruptMask;
266 uint32_t ah_txEolInterruptMask;
267 uint32_t ah_txUrnInterruptMask;
268 HAL_TX_QUEUE_INFO ah_txq[HAL_NUM_TX_QUEUES];
269 uint32_t ah_intrTxqs; /* tx q interrupt state */
270 /* decomp mask array */
271 uint8_t ah_decompMask[HAL_DECOMP_MASK_SIZE];
272 HAL_POWER_MODE ah_powerMode;
273 HAL_ANT_SETTING ah_antControl; /* antenna setting */
274 HAL_BOOL ah_diversity; /* fast diversity setting */
275 enum {
276 IQ_CAL_INACTIVE,
277 IQ_CAL_RUNNING,
278 IQ_CAL_DONE
279 } ah_bIQCalibration; /* IQ calibrate state */
280 HAL_RFGAIN ah_rfgainState; /* RF gain calibrartion state */
281 uint32_t ah_tx6PowerInHalfDbm; /* power output for 6Mb tx */
282 uint32_t ah_staId1Defaults; /* STA_ID1 default settings */
283 uint32_t ah_miscMode; /* MISC_MODE settings */
284 uint32_t ah_rssiThr; /* RSSI_THR settings */
285 HAL_BOOL ah_cwCalRequire; /* for ap51 */
286 HAL_BOOL ah_tpcEnabled; /* per-packet tpc enabled */
287 HAL_BOOL ah_phyPowerOn; /* PHY power state */
288 HAL_BOOL ah_isHb63; /* cached HB63 check */
289 uint32_t ah_macTPC; /* tpc register */
290 uint32_t ah_beaconInterval; /* XXX */
291 enum {
292 AUTO_32KHZ, /* use it if 32kHz crystal present */
293 USE_32KHZ, /* do it regardless */
294 DONT_USE_32KHZ, /* don't use it regardless */
295 } ah_enable32kHzClock; /* whether to sleep at 32kHz */
296 uint32_t ah_ofdmTxPower;
297 int16_t ah_txPowerIndexOffset;
298 /*
299 * Noise floor cal histogram support.
300 */
301 struct ar5212NfCalHist ah_nfCalHist;
302
303 u_int ah_slottime; /* user-specified slot time */
304 u_int ah_acktimeout; /* user-specified ack timeout */
305 u_int ah_ctstimeout; /* user-specified cts timeout */
306 u_int ah_sifstime; /* user-specified sifs time */
307 /*
308 * RF Silent handling; setup according to the EEPROM.
309 */
310 uint32_t ah_gpioSelect; /* GPIO pin to use */
311 uint32_t ah_polarity; /* polarity to disable RF */
312 uint32_t ah_gpioBit; /* after init, prev value */
313 /*
314 * ANI support.
315 */
316 uint32_t ah_procPhyErr; /* Process Phy errs */
317 HAL_BOOL ah_hasHwPhyCounters; /* Hardware has phy counters */
318 struct ar5212AniParams ah_aniParams24; /* 2.4GHz parameters */
319 struct ar5212AniParams ah_aniParams5; /* 5GHz parameters */
320 struct ar5212AniState *ah_curani; /* cached last reference */
321 struct ar5212AniState ah_ani[AH_MAXCHAN]; /* per-channel state */
322
323 /*
324 * Transmit power state. Note these are maintained
325 * here so they can be retrieved by diagnostic tools.
326 */
327 uint16_t *ah_pcdacTable;
328 u_int ah_pcdacTableSize;
329 uint16_t ah_ratesArray[16];
330
331 uint8_t ah_txTrigLev; /* current Tx trigger level */
332 uint8_t ah_maxTxTrigLev; /* max tx trigger level */
333 };
334 #define AH5212(_ah) ((struct ath_hal_5212 *)(_ah))
335
336 /*
337 * IS_XXXX macros test the MAC version
338 * IS_RADXXX macros test the radio/RF version (matching both 2G-only and 2/5G)
339 *
340 * Some single chip radios have equivalent radio/RF (e.g. 5112)
341 * for those use IS_RADXXX_ANY macros.
342 */
343 #define IS_2317(ah) \
344 ((AH_PRIVATE(ah)->ah_devid == AR5212_AR2317_REV1) || \
345 (AH_PRIVATE(ah)->ah_devid == AR5212_AR2317_REV2))
346 #define IS_2316(ah) \
347 (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_2415)
348 #define IS_2413(ah) \
349 (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_2413 || IS_2316(ah))
350 #define IS_5424(ah) \
351 (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_5424 || \
352 (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_5413 && \
353 AH_PRIVATE(ah)->ah_macRev <= AR_SREV_D2PLUS_MS))
354 #define IS_5413(ah) \
355 (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_5413 || IS_5424(ah))
356 #define IS_2425(ah) \
357 (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_2425)
358 #define IS_2417(ah) \
359 ((AH_PRIVATE(ah)->ah_macVersion) == AR_SREV_2417)
360 #define IS_HB63(ah) (AH5212(ah)->ah_isHb63 == AH_TRUE)
361
362 #define AH_RADIO_MAJOR(ah) \
363 (AH_PRIVATE(ah)->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR)
364 #define AH_RADIO_MINOR(ah) \
365 (AH_PRIVATE(ah)->ah_analog5GhzRev & AR_RADIO_SREV_MINOR)
366 #define IS_RAD5111(ah) \
367 (AH_RADIO_MAJOR(ah) == AR_RAD5111_SREV_MAJOR || \
368 AH_RADIO_MAJOR(ah) == AR_RAD2111_SREV_MAJOR)
369 #define IS_RAD5112(ah) \
370 (AH_RADIO_MAJOR(ah) == AR_RAD5112_SREV_MAJOR || \
371 AH_RADIO_MAJOR(ah) == AR_RAD2112_SREV_MAJOR)
372 /* NB: does not include 5413 as Atheros' IS_5112 macro does */
373 #define IS_RAD5112_ANY(ah) \
374 (AR_RAD5112_SREV_MAJOR <= AH_RADIO_MAJOR(ah) && \
375 AH_RADIO_MAJOR(ah) <= AR_RAD2413_SREV_MAJOR)
376 #define IS_RAD5112_REV1(ah) \
377 (IS_RAD5112(ah) && \
378 AH_RADIO_MINOR(ah) < (AR_RAD5112_SREV_2_0 & AR_RADIO_SREV_MINOR))
379 #define IS_RADX112_REV2(ah) \
380 (AH_PRIVATE(ah)->ah_analog5GhzRev == AR_RAD5112_SREV_2_0 || \
381 AH_PRIVATE(ah)->ah_analog5GhzRev == AR_RAD2112_SREV_2_0 || \
382 AH_PRIVATE(ah)->ah_analog5GhzRev == AR_RAD2112_SREV_2_1 || \
383 AH_PRIVATE(ah)->ah_analog5GhzRev == AR_RAD5112_SREV_2_1)
384
385 #define ar5212RfDetach(ah) do { \
386 if (AH5212(ah)->ah_rfHal != AH_NULL) \
387 AH5212(ah)->ah_rfHal->rfDetach(ah); \
388 } while (0)
389 #define ar5212GetRfBank(ah, b) \
390 AH5212(ah)->ah_rfHal->getRfBank(ah, b)
391
392 /*
393 * Hack macros for Nala/San: 11b is handled
394 * using 11g; flip the channel flags to accomplish this.
395 */
396 #define SAVE_CCK(_ah, _chan, _flag) do { \
397 if ((IS_2425(_ah) || IS_2417(_ah)) && \
398 (((_chan)->ic_flags) & IEEE80211_CHAN_CCK)) { \
399 (_chan)->ic_flags &= ~IEEE80211_CHAN_CCK; \
400 (_chan)->ic_flags |= IEEE80211_CHAN_DYN; \
401 (_flag) = AH_TRUE; \
402 } else \
403 (_flag) = AH_FALSE; \
404 } while (0)
405 #define RESTORE_CCK(_ah, _chan, _flag) do { \
406 if ((_flag) && (IS_2425(_ah) || IS_2417(_ah))) { \
407 (_chan)->ic_flags &= ~IEEE80211_CHAN_DYN; \
408 (_chan)->ic_flags |= IEEE80211_CHAN_CCK; \
409 } \
410 } while (0)
411
412 struct ath_hal;
413
414 extern uint32_t ar5212GetRadioRev(struct ath_hal *ah);
415 extern void ar5212InitState(struct ath_hal_5212 *, uint16_t devid, HAL_SOFTC,
416 HAL_BUS_TAG st, HAL_BUS_HANDLE sh, HAL_STATUS *status);
417 extern void ar5212Detach(struct ath_hal *ah);
418 extern HAL_BOOL ar5212ChipTest(struct ath_hal *ah);
419 extern HAL_BOOL ar5212GetChannelEdges(struct ath_hal *ah,
420 uint16_t flags, uint16_t *low, uint16_t *high);
421 extern HAL_BOOL ar5212FillCapabilityInfo(struct ath_hal *ah);
422
423 extern void ar5212SetBeaconTimers(struct ath_hal *ah,
424 const HAL_BEACON_TIMERS *);
425 extern void ar5212BeaconInit(struct ath_hal *ah,
426 uint32_t next_beacon, uint32_t beacon_period);
427 extern void ar5212ResetStaBeaconTimers(struct ath_hal *ah);
428 extern void ar5212SetStaBeaconTimers(struct ath_hal *ah,
429 const HAL_BEACON_STATE *);
430
431 extern HAL_BOOL ar5212IsInterruptPending(struct ath_hal *ah);
432 extern HAL_BOOL ar5212GetPendingInterrupts(struct ath_hal *ah, HAL_INT *);
433 extern HAL_INT ar5212GetInterrupts(struct ath_hal *ah);
434 extern HAL_INT ar5212SetInterrupts(struct ath_hal *ah, HAL_INT ints);
435
436 extern uint32_t ar5212GetKeyCacheSize(struct ath_hal *);
437 extern HAL_BOOL ar5212IsKeyCacheEntryValid(struct ath_hal *, uint16_t entry);
438 extern HAL_BOOL ar5212ResetKeyCacheEntry(struct ath_hal *ah, uint16_t entry);
439 extern HAL_BOOL ar5212SetKeyCacheEntryMac(struct ath_hal *,
440 uint16_t entry, const uint8_t *mac);
441 extern HAL_BOOL ar5212SetKeyCacheEntry(struct ath_hal *ah, uint16_t entry,
442 const HAL_KEYVAL *k, const uint8_t *mac, int xorKey);
443
444 extern void ar5212GetMacAddress(struct ath_hal *ah, uint8_t *mac);
445 extern HAL_BOOL ar5212SetMacAddress(struct ath_hal *ah, const uint8_t *);
446 extern void ar5212GetBssIdMask(struct ath_hal *ah, uint8_t *mac);
447 extern HAL_BOOL ar5212SetBssIdMask(struct ath_hal *, const uint8_t *);
448 extern HAL_BOOL ar5212EepromRead(struct ath_hal *, u_int off, uint16_t *data);
449 extern HAL_BOOL ar5212EepromWrite(struct ath_hal *, u_int off, uint16_t data);
450 extern HAL_BOOL ar5212SetRegulatoryDomain(struct ath_hal *ah,
451 uint16_t regDomain, HAL_STATUS *stats);
452 extern u_int ar5212GetWirelessModes(struct ath_hal *ah);
453 extern void ar5212EnableRfKill(struct ath_hal *);
454 extern HAL_BOOL ar5212GpioCfgOutput(struct ath_hal *, uint32_t gpio,
455 HAL_GPIO_MUX_TYPE);
456 extern HAL_BOOL ar5212GpioCfgInput(struct ath_hal *, uint32_t gpio);
457 extern HAL_BOOL ar5212GpioSet(struct ath_hal *, uint32_t gpio, uint32_t val);
458 extern uint32_t ar5212GpioGet(struct ath_hal *ah, uint32_t gpio);
459 extern void ar5212GpioSetIntr(struct ath_hal *ah, u_int, uint32_t ilevel);
460 extern void ar5212SetLedState(struct ath_hal *ah, HAL_LED_STATE state);
461 extern void ar5212WriteAssocid(struct ath_hal *ah, const uint8_t *bssid,
462 uint16_t assocId);
463 extern uint32_t ar5212GetTsf32(struct ath_hal *ah);
464 extern uint64_t ar5212GetTsf64(struct ath_hal *ah);
465 extern void ar5212ResetTsf(struct ath_hal *ah);
466 extern void ar5212SetBasicRate(struct ath_hal *ah, HAL_RATE_SET *pSet);
467 extern uint32_t ar5212GetRandomSeed(struct ath_hal *ah);
468 extern HAL_BOOL ar5212DetectCardPresent(struct ath_hal *ah);
469 extern void ar5212EnableMibCounters(struct ath_hal *);
470 extern void ar5212DisableMibCounters(struct ath_hal *);
471 extern void ar5212UpdateMibCounters(struct ath_hal *ah, HAL_MIB_STATS* stats);
472 extern HAL_BOOL ar5212IsJapanChannelSpreadSupported(struct ath_hal *ah);
473 extern uint32_t ar5212GetCurRssi(struct ath_hal *ah);
474 extern u_int ar5212GetDefAntenna(struct ath_hal *ah);
475 extern void ar5212SetDefAntenna(struct ath_hal *ah, u_int antenna);
476 extern HAL_ANT_SETTING ar5212GetAntennaSwitch(struct ath_hal *);
477 extern HAL_BOOL ar5212SetAntennaSwitch(struct ath_hal *, HAL_ANT_SETTING);
478 extern HAL_BOOL ar5212IsSleepAfterBeaconBroken(struct ath_hal *ah);
479 extern HAL_BOOL ar5212SetSifsTime(struct ath_hal *, u_int);
480 extern u_int ar5212GetSifsTime(struct ath_hal *);
481 extern HAL_BOOL ar5212SetSlotTime(struct ath_hal *, u_int);
482 extern u_int ar5212GetSlotTime(struct ath_hal *);
483 extern HAL_BOOL ar5212SetAckTimeout(struct ath_hal *, u_int);
484 extern u_int ar5212GetAckTimeout(struct ath_hal *);
485 extern HAL_BOOL ar5212SetAckCTSRate(struct ath_hal *, u_int);
486 extern u_int ar5212GetAckCTSRate(struct ath_hal *);
487 extern HAL_BOOL ar5212SetCTSTimeout(struct ath_hal *, u_int);
488 extern u_int ar5212GetCTSTimeout(struct ath_hal *);
489 extern HAL_BOOL ar5212SetDecompMask(struct ath_hal *, uint16_t, int);
490 void ar5212SetCoverageClass(struct ath_hal *, uint8_t, int);
491 extern void ar5212SetPCUConfig(struct ath_hal *);
492 extern HAL_BOOL ar5212Use32KHzclock(struct ath_hal *ah, HAL_OPMODE opmode);
493 extern void ar5212SetupClock(struct ath_hal *ah, HAL_OPMODE opmode);
494 extern void ar5212RestoreClock(struct ath_hal *ah, HAL_OPMODE opmode);
495 extern int16_t ar5212GetNfAdjust(struct ath_hal *,
496 const HAL_CHANNEL_INTERNAL *);
497 extern void ar5212SetCompRegs(struct ath_hal *ah);
498 extern HAL_STATUS ar5212GetCapability(struct ath_hal *, HAL_CAPABILITY_TYPE,
499 uint32_t, uint32_t *);
500 extern HAL_BOOL ar5212SetCapability(struct ath_hal *, HAL_CAPABILITY_TYPE,
501 uint32_t, uint32_t, HAL_STATUS *);
502 extern HAL_BOOL ar5212GetDiagState(struct ath_hal *ah, int request,
503 const void *args, uint32_t argsize,
504 void **result, uint32_t *resultsize);
505
506 extern HAL_BOOL ar5212SetPowerMode(struct ath_hal *ah, HAL_POWER_MODE mode,
507 int setChip);
508 extern HAL_POWER_MODE ar5212GetPowerMode(struct ath_hal *ah);
509 extern HAL_BOOL ar5212GetPowerStatus(struct ath_hal *ah);
510
511 extern uint32_t ar5212GetRxDP(struct ath_hal *ath);
512 extern void ar5212SetRxDP(struct ath_hal *ah, uint32_t rxdp);
513 extern void ar5212EnableReceive(struct ath_hal *ah);
514 extern HAL_BOOL ar5212StopDmaReceive(struct ath_hal *ah);
515 extern void ar5212StartPcuReceive(struct ath_hal *ah);
516 extern void ar5212StopPcuReceive(struct ath_hal *ah);
517 extern void ar5212SetMulticastFilter(struct ath_hal *ah,
518 uint32_t filter0, uint32_t filter1);
519 extern HAL_BOOL ar5212ClrMulticastFilterIndex(struct ath_hal *, uint32_t ix);
520 extern HAL_BOOL ar5212SetMulticastFilterIndex(struct ath_hal *, uint32_t ix);
521 extern uint32_t ar5212GetRxFilter(struct ath_hal *ah);
522 extern void ar5212SetRxFilter(struct ath_hal *ah, uint32_t bits);
523 extern HAL_BOOL ar5212SetupRxDesc(struct ath_hal *,
524 struct ath_desc *, uint32_t size, u_int flags);
525 extern HAL_STATUS ar5212ProcRxDesc(struct ath_hal *ah, struct ath_desc *,
526 uint32_t, struct ath_desc *, uint64_t,
527 struct ath_rx_status *);
528
529 extern HAL_BOOL ar5212Reset(struct ath_hal *ah, HAL_OPMODE opmode,
530 struct ieee80211_channel *chan, HAL_BOOL bChannelChange,
531 HAL_STATUS *status);
532 extern HAL_BOOL ar5212SetChannel(struct ath_hal *,
533 const struct ieee80211_channel *);
534 extern void ar5212SetOperatingMode(struct ath_hal *ah, int opmode);
535 extern HAL_BOOL ar5212PhyDisable(struct ath_hal *ah);
536 extern HAL_BOOL ar5212Disable(struct ath_hal *ah);
537 extern HAL_BOOL ar5212ChipReset(struct ath_hal *ah,
538 const struct ieee80211_channel *);
539 extern HAL_BOOL ar5212PerCalibration(struct ath_hal *ah,
540 struct ieee80211_channel *chan, HAL_BOOL *isIQdone);
541 extern HAL_BOOL ar5212PerCalibrationN(struct ath_hal *ah,
542 struct ieee80211_channel *chan, u_int chainMask,
543 HAL_BOOL longCal, HAL_BOOL *isCalDone);
544 extern HAL_BOOL ar5212ResetCalValid(struct ath_hal *ah,
545 const struct ieee80211_channel *);
546 extern int16_t ar5212GetNoiseFloor(struct ath_hal *ah);
547 extern void ar5212InitNfCalHistBuffer(struct ath_hal *);
548 extern int16_t ar5212GetNfHistMid(const int16_t calData[]);
549 extern void ar5212SetSpurMitigation(struct ath_hal *,
550 const struct ieee80211_channel *);
551 extern HAL_BOOL ar5212SetAntennaSwitchInternal(struct ath_hal *ah,
552 HAL_ANT_SETTING settings, const struct ieee80211_channel *);
553 extern HAL_BOOL ar5212SetTxPowerLimit(struct ath_hal *ah, uint32_t limit);
554 extern HAL_BOOL ar5212GetChipPowerLimits(struct ath_hal *ah,
555 struct ieee80211_channel *chan);
556 extern void ar5212InitializeGainValues(struct ath_hal *);
557 extern HAL_RFGAIN ar5212GetRfgain(struct ath_hal *ah);
558 extern void ar5212RequestRfgain(struct ath_hal *);
559
560 extern HAL_BOOL ar5212UpdateTxTrigLevel(struct ath_hal *,
561 HAL_BOOL IncTrigLevel);
562 extern HAL_BOOL ar5212SetTxQueueProps(struct ath_hal *ah, int q,
563 const HAL_TXQ_INFO *qInfo);
564 extern HAL_BOOL ar5212GetTxQueueProps(struct ath_hal *ah, int q,
565 HAL_TXQ_INFO *qInfo);
566 extern int ar5212SetupTxQueue(struct ath_hal *ah, HAL_TX_QUEUE type,
567 const HAL_TXQ_INFO *qInfo);
568 extern HAL_BOOL ar5212ReleaseTxQueue(struct ath_hal *ah, u_int q);
569 extern HAL_BOOL ar5212ResetTxQueue(struct ath_hal *ah, u_int q);
570 extern uint32_t ar5212GetTxDP(struct ath_hal *ah, u_int q);
571 extern HAL_BOOL ar5212SetTxDP(struct ath_hal *ah, u_int q, uint32_t txdp);
572 extern HAL_BOOL ar5212StartTxDma(struct ath_hal *ah, u_int q);
573 extern uint32_t ar5212NumTxPending(struct ath_hal *ah, u_int q);
574 extern HAL_BOOL ar5212StopTxDma(struct ath_hal *ah, u_int q);
575 extern HAL_BOOL ar5212SetupTxDesc(struct ath_hal *ah, struct ath_desc *ds,
576 u_int pktLen, u_int hdrLen, HAL_PKT_TYPE type, u_int txPower,
577 u_int txRate0, u_int txTries0,
578 u_int keyIx, u_int antMode, u_int flags,
579 u_int rtsctsRate, u_int rtsctsDuration,
580 u_int compicvLen, u_int compivLen, u_int comp);
581 extern HAL_BOOL ar5212SetupXTxDesc(struct ath_hal *, struct ath_desc *,
582 u_int txRate1, u_int txRetries1,
583 u_int txRate2, u_int txRetries2,
584 u_int txRate3, u_int txRetries3);
585 extern HAL_BOOL ar5212FillTxDesc(struct ath_hal *ah, struct ath_desc *ds,
586 u_int segLen, HAL_BOOL firstSeg, HAL_BOOL lastSeg,
587 const struct ath_desc *ds0);
588 extern HAL_STATUS ar5212ProcTxDesc(struct ath_hal *ah,
589 struct ath_desc *, struct ath_tx_status *);
590 extern void ar5212GetTxIntrQueue(struct ath_hal *ah, uint32_t *);
591 extern void ar5212IntrReqTxDesc(struct ath_hal *ah, struct ath_desc *);
592
593 extern const HAL_RATE_TABLE *ar5212GetRateTable(struct ath_hal *, u_int mode);
594
595 extern void ar5212AniAttach(struct ath_hal *, const struct ar5212AniParams *,
596 const struct ar5212AniParams *, HAL_BOOL ena);
597 extern void ar5212AniDetach(struct ath_hal *);
598 extern struct ar5212AniState *ar5212AniGetCurrentState(struct ath_hal *);
599 extern struct ar5212Stats *ar5212AniGetCurrentStats(struct ath_hal *);
600 extern HAL_BOOL ar5212AniControl(struct ath_hal *, HAL_ANI_CMD cmd, int param);
601 extern HAL_BOOL ar5212AniSetParams(struct ath_hal *,
602 const struct ar5212AniParams *, const struct ar5212AniParams *);
603 struct ath_rx_status;
604 extern void ar5212AniPhyErrReport(struct ath_hal *ah,
605 const struct ath_rx_status *rs);
606 extern void ar5212ProcessMibIntr(struct ath_hal *, const HAL_NODE_STATS *);
607 extern void ar5212AniPoll(struct ath_hal *, const HAL_NODE_STATS *,
608 const struct ieee80211_channel *);
609 extern void ar5212AniReset(struct ath_hal *, const struct ieee80211_channel *,
610 HAL_OPMODE, int);
611
612 extern HAL_BOOL ar5212IsNFCalInProgress(struct ath_hal *ah);
613 extern HAL_BOOL ar5212WaitNFCalComplete(struct ath_hal *ah, int i);
614
615 #endif /* _ATH_AR5212_H_ */
DragonFly BSD