sys/dev/netif/ath/hal/ath_hal/ar5210/ar5210_interrupts.c

   1 /*
   2  * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
   3  * Copyright (c) 2002-2004 Atheros Communications, Inc.
   4  *
   5  * Permission to use, copy, modify, and/or distribute this software for any
   6  * purpose with or without fee is hereby granted, provided that the above
   7  * copyright notice and this permission notice appear in all copies.
   8  *
   9  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  10  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  11  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  12  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  13  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  14  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  15  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  16  *
  17  * $FreeBSD: head/sys/dev/ath/ath_hal/ar5210/ar5210_interrupts.c 192397 2009-05-19 17:35:15Z sam $
  18  */
  19 #include "opt_ah.h"
  20
  21 #include "ah.h"
  22 #include "ah_internal.h"
  23
  24 #include "ar5210/ar5210.h"
  25 #include "ar5210/ar5210reg.h"
  26
  27 /*
  28  * Return non-zero if an interrupt is pending.
  29  */
  30 HAL_BOOL
  31 ar5210IsInterruptPending(struct ath_hal *ah)
  32 {
  33         return (OS_REG_READ(ah, AR_INTPEND) ? AH_TRUE : AH_FALSE);
  34 }
  35
  36 /*
  37  * Read the Interrupt Status Register value and return
  38  * an abstracted bitmask of the data found in the ISR.
  39  * Note that reading the ISR clear pending interrupts.
  40  */
  41 HAL_BOOL
  42 ar5210GetPendingInterrupts(struct ath_hal *ah, HAL_INT *masked)
  43 {
  44 #define AR_FATAL_INT \
  45     (AR_ISR_MCABT_INT | AR_ISR_SSERR_INT | AR_ISR_DPERR_INT | AR_ISR_RXORN_INT)
  46         struct ath_hal_5210 *ahp = AH5210(ah);
  47         uint32_t isr;
  48
  49         isr = OS_REG_READ(ah, AR_ISR);
  50         if (isr == 0xffffffff) {
  51                 *masked = 0;
  52                 return AH_FALSE;
  53         }
  54
  55         /*
  56          * Mask interrupts that have no device-independent
  57          * representation; these are added back below.  We
  58          * also masked with the abstracted IMR to insure no
  59          * status bits leak through that weren't requested
  60          * (e.g. RXNOFRM) and that might confuse the caller.
  61          */
  62         *masked = (isr & (HAL_INT_COMMON - HAL_INT_BNR)) & ahp->ah_maskReg;
  63
  64         if (isr & AR_FATAL_INT)
  65                 *masked |= HAL_INT_FATAL;
  66         if (isr & (AR_ISR_RXOK_INT | AR_ISR_RXERR_INT))
  67                 *masked |= HAL_INT_RX;
  68         if (isr & (AR_ISR_TXOK_INT | AR_ISR_TXDESC_INT | AR_ISR_TXERR_INT | AR_ISR_TXEOL_INT))
  69                 *masked |= HAL_INT_TX;
  70
  71         /*
  72          * On fatal errors collect ISR state for debugging.
  73          */
  74         if (*masked & HAL_INT_FATAL) {
  75                 AH_PRIVATE(ah)->ah_fatalState[0] = isr;
  76         }
  77
  78         return AH_TRUE;
  79 #undef AR_FATAL_INT
  80 }
  81
  82 HAL_INT
  83 ar5210GetInterrupts(struct ath_hal *ah)
  84 {
  85         return AH5210(ah)->ah_maskReg;
  86 }
  87
  88 HAL_INT
  89 ar5210SetInterrupts(struct ath_hal *ah, HAL_INT ints)
  90 {
  91         struct ath_hal_5210 *ahp = AH5210(ah);
  92         uint32_t omask = ahp->ah_maskReg;
  93         uint32_t mask;
  94
  95         HALDEBUG(ah, HAL_DEBUG_INTERRUPT, "%s: 0x%x => 0x%x\n",
  96             __func__, omask, ints);
  97
  98         /*
  99          * Disable interrupts here before reading & modifying
 100          * the mask so that the ISR does not modify the mask
 101          * out from under us.
 102          */
 103         if (omask & HAL_INT_GLOBAL) {
 104                 HALDEBUG(ah, HAL_DEBUG_INTERRUPT, "%s: disable IER\n", __func__);
 105                 OS_REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
 106         }
 107
 108         mask = ints & (HAL_INT_COMMON - HAL_INT_BNR);
 109         if (ints & HAL_INT_RX)
 110                 mask |= AR_IMR_RXOK_INT | AR_IMR_RXERR_INT;
 111         if (ints & HAL_INT_TX) {
 112                 if (ahp->ah_txOkInterruptMask)
 113                         mask |= AR_IMR_TXOK_INT;
 114                 if (ahp->ah_txErrInterruptMask)
 115                         mask |= AR_IMR_TXERR_INT;
 116                 if (ahp->ah_txDescInterruptMask)
 117                         mask |= AR_IMR_TXDESC_INT;
 118                 if (ahp->ah_txEolInterruptMask)
 119                         mask |= AR_IMR_TXEOL_INT;
 120         }
 121
 122         /* Write the new IMR and store off our SW copy. */
 123         HALDEBUG(ah, HAL_DEBUG_INTERRUPT, "%s: new IMR 0x%x\n", __func__, mask);
 124         OS_REG_WRITE(ah, AR_IMR, mask);
 125         ahp->ah_maskReg = ints;
 126
 127         /* Re-enable interrupts as appropriate. */
 128         if (ints & HAL_INT_GLOBAL) {
 129                 HALDEBUG(ah, HAL_DEBUG_INTERRUPT, "%s: enable IER\n", __func__);
 130                 OS_REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
 131         }
 132
 133         return omask;
 134 }