sys/dev/sound/pci/vibes.h

   1 /*-
   2  * Copyright (c) 2001 Orion Hodson <O.Hodson@cs.ucl.ac.uk>
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  * 1. Redistributions of source code must retain the above copyright
   9  *    notice, this list of conditions and the following disclaimer.
  10  * 2. Redistributions in binary form must reproduce the above copyright
  11  *    notice, this list of conditions and the following disclaimer in the
  12  *    documentation and/or other materials provided with the distribution.
  13  *
  14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  15  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  16  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  17  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  18  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  19  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  20  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  21  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  22  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  23  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  24  * SUCH DAMAGE.
  25  *
  26  * $FreeBSD: src/sys/dev/sound/pci/vibes.h,v 1.2 2005/01/06 01:43:19 imp Exp $
  27  * $DragonFly: src/sys/dev/sound/pci/vibes.h,v 1.3 2007/01/04 21:47:02 corecode Exp $
  28  */
  29
  30 /* ------------------------------------------------------------------------- */
  31 /* PCI Configuration Register Offsets */
  32
  33 #define SV_PCI_COMPAT   0x10
  34 #define SV_PCI_ENHANCED 0x14
  35 #define SV_PCI_FMSYNTH  0x18
  36 #define SV_PCI_MIDI     0x1c
  37 #define SV_PCI_GAMES    0x20
  38 #define SV_PCI_DMAA     0x40
  39 #define SV_PCI_DMAC     0x48
  40
  41 #define SV_PCI_DMAA_SIZE        0x10
  42 #define SV_PCI_DMAA_ALIGN       0x10
  43 #define SV_PCI_DMAC_SIZE        0x10
  44 #define SV_PCI_DMAC_ALIGN       0x10
  45
  46 #define SV_PCI_ENHANCED_SIZE    0x08
  47
  48 #define SV_PCI_DMA_ENABLE       0x00000001
  49 #define SV_PCI_DMA_EXTENDED     0x00000008
  50
  51 /* ------------------------------------------------------------------------- */
  52 /* DMA Configuration Registers */
  53
  54 #define SV_DMA_ADDR     0x00
  55 #define SV_DMA_COUNT    0x04
  56
  57 #define SV_DMA_MODE     0x0B
  58 #define         SV_DMA_MODE_AUTO        0x10
  59 #define         SV_DMA_MODE_RD          0x04
  60 #define         SV_DMA_MODE_WR          0x08
  61
  62 /* ------------------------------------------------------------------------- */
  63 /* Enhanced Mode Configuration Registers */
  64
  65 #define SV_CM_CONTROL   0x00
  66 #define         SV_CM_CONTROL_ENHANCED  0x01
  67 #define         SV_CM_CONTROL_TEST      0x02
  68 #define         SV_CM_CONTROL_REVERB    0x04
  69 #define         SV_CM_CONTROL_PWS       0x08
  70 #define         SV_CM_CONTROL_INTA      0x20
  71 #define         SV_CM_CONTROL_RESET     0x80
  72
  73 #define SV_CM_IMR       0x01
  74 #define         SV_CM_IMR_AMSK          0x01
  75 #define         SV_CM_IMR_CMSK          0x04
  76 #define         SV_CM_IMR_SMSK          0x08
  77 #define         SV_CM_IMR_UDM           0x40
  78 #define         SV_CM_IMR_MIDM          0x80
  79
  80 #define SV_CM_STATUS    0x02
  81 #define         SV_CM_STATUS_AINT       0x01
  82 #define         SV_CM_STATUS_CINT       0x04
  83 #define         SV_CM_STATUS_SINT       0x08
  84 #define         SV_CM_STATUS_UDI        0x40
  85 #define         SV_CM_STATUS_MI         0x80
  86
  87 #define SV_CM_INDEX     0x04
  88 #define         SV_CM_INDEX_MASK        0x3f
  89 #define         SV_CM_INDEX_MCE         0x40
  90 #define         SV_CM_INDEX_TRD         0x80
  91
  92 #define SV_CM_DATA      0x05
  93
  94 /* ------------------------------------------------------------------------- */
  95 /* Indexed Codec/Mixer Registers (left channels were applicable) */
  96
  97 #define SV_REG_ADC_INPUT        0x00
  98 #define         SV_INPUT_GAIN_MASK      0x0f
  99 #define         SV_INPUT_MICGAIN        0x10
 100 #define         SV_INPUT_CD             0x20
 101 #define         SV_INPUT_DAC            0x40
 102 #define         SV_INPUT_AUX2           0x60
 103 #define         SV_INPUT_LINE           0x80
 104 #define         SV_INPUT_AUX1           0xa0
 105 #define         SV_INPUT_MIC            0xc0
 106 #define         SV_INPUT_MIXOUT         0xe0
 107
 108 #define SV_REG_AUX1             0x02
 109 #define SV_REG_CD               0x04
 110 #define SV_REG_LINE             0x06
 111 #define SV_REG_MIC              0x08
 112 #define SV_REG_SYNTH            0x0a
 113 #define SV_REG_AUX2             0x0c
 114 #define SV_REG_MIX              0x0e
 115 #define SV_REG_PCM              0x10
 116 #define         SV_DEFAULT_MAX          0x1f
 117 #define         SV_ADC_MAX              0x0f
 118 #define         SV_MIC_MAX              0x0f
 119 #define         SV_PCM_MAX              0x3f
 120 #define         SV_MUTE                 0x80
 121
 122 #define SV_REG_FORMAT           0x12
 123 #define         SV_AFMT_MONO    0x00
 124 #define         SV_AFMT_STEREO  0x01
 125 #define         SV_AFMT_S16     0x02
 126 #define         SV_AFMT_U8      0x00
 127 #define         SV_AFMT_DMAA(x)         (x)
 128 #define         SV_AFMT_DMAA_MSK        0x03
 129 #define         SV_AFMT_DMAC(x)         ((x) << 4)
 130 #define         SV_AFMT_DMAC_MSK        0x30
 131
 132 #define SV_REG_ENABLE           0x13
 133 #define         SV_PLAY_ENABLE          0x01
 134 #define         SV_RECORD_ENABLE        0x02
 135 #define         SV_PLAYBACK_PAUSE       0x04
 136
 137 #define SV_REG_REVISION 0x15
 138
 139 #define SV_REG_LOOPBACK 0x16
 140 #define         SV_LOOPBACK_ENABLE      0x01
 141 #define         SV_LOOPBACK_MAX         0x3f
 142 #define         SV_LOOPBACK_LEVEL(x)    ((x) << 2)
 143
 144 #define SV_REG_DMAA_COUNT_HI    0x18
 145 #define SV_REG_DMAA_COUNT_LO    0x19
 146 #define SV_REG_DMAC_COUNT_HI    0x1c
 147 #define SV_REG_DMAC_COUNT_LO    0x1d
 148
 149 #define SV_REG_PCM_SAMPLING_LO  0x1e
 150 #define SV_REG_PCM_SAMPLING_HI  0x1f
 151
 152 #define SV_REG_SYN_SAMPLING_LO  0x20
 153 #define SV_REG_SYN_SAMPLING_HI  0x21
 154
 155 #define SV_REG_CLOCK_SOURCE     0x22
 156 #define         SV_CLOCK_ALTERNATE      0x10
 157 #define SV_REG_ALT_RATE 0x23
 158
 159 #define SV_REG_ADC_PLLM 0x24
 160 #define SV_REG_ADC_PLLN 0x25
 161 #define         SV_ADC_PLLN(x)          ((x) & 0x1f)
 162 #define         SV_ADC_PLLR(x)          ((x) << 5)
 163
 164 #define SV_REG_SYNTH_PLLM       0x26
 165 #define SV_REG_SYNTH_PLLN       0x27
 166 #define         SV_SYNTH_PLLN(x)        ((x) & 0x1f)
 167 #define         SV_SYNTH_PLLR(x)        ((x) << 5)
 168
 169 #define SV_REG_SRS_SPACE        0x2c
 170 #define         SV_SRS_SPACE_100        0x00
 171 #define         SV_SRS_SPACE_75         0x01
 172 #define         SV_SRS_SPACE_50         0x02
 173 #define         SV_SRS_SPACE_25         0x03
 174 #define         SV_SRS_SPACE_0          0x04
 175 #define         SV_SRS_DISABLED         0x80
 176
 177 #define SV_REG_SRS_CENTER       0x2d
 178 #define         SV_SRS_CENTER_100       0x00
 179 #define         SV_SRS_CENTER_75        0x01
 180 #define         SV_SRS_CENTER_50        0x02
 181 #define         SV_SRS_CENTER_25        0x03
 182 #define         SV_SRS_CENTER_0         0x04
 183
 184 #define SV_REG_ANALOG_PWR       0x30
 185 #define         SV_ANALOG_OFF_DAC       0x01
 186 #define         SV_ANALOG_OFF_ADC       0x08
 187 #define         SV_ANALOG_OFF_MIX       0x10
 188 #define         SV_ANALOG_OFF_SRS       0x20
 189 #define         SV_ANALOG_OFF_SPLL      0x40
 190 #define         SV_ANALOG_OFF_APLL      0x80
 191 #define         SV_ANALOG_OFF           0xf9
 192
 193 #define SV_REG_DIGITAL_PWR      0x31
 194 #define         SV_DIGITAL_OFF_SYN      0x01
 195 #define         SV_DIGITAL_OFF_MU       0x02
 196 #define         SV_DIGITAL_OFF_GP       0x04
 197 #define         SV_DIGITAL_OFF_BI       0x08
 198 #define         SV_DIGITAL_OFF          0x0f
 199
 200 /* ------------------------------------------------------------------------- */
 201 /* ADC PLL constants */
 202
 203 #define         SV_F_SCALE              512
 204 #define         SV_F_REF                24576000