sys/bus/isa/isareg.h

   1 /*-
   2  * Copyright (c) 1990 The Regents of the University of California.
   3  * All rights reserved.
   4  *
   5  * This code is derived from software contributed to Berkeley by
   6  * William Jolitz.
   7  *
   8  * Redistribution and use in source and binary forms, with or without
   9  * modification, are permitted provided that the following conditions
  10  * are met:
  11  * 1. Redistributions of source code must retain the above copyright
  12  *    notice, this list of conditions and the following disclaimer.
  13  * 2. Redistributions in binary form must reproduce the above copyright
  14  *    notice, this list of conditions and the following disclaimer in the
  15  *    documentation and/or other materials provided with the distribution.
  16  * 3. Neither the name of the University nor the names of its contributors
  17  *    may be used to endorse or promote products derived from this software
  18  *    without specific prior written permission.
  19  *
  20  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
  21  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
  24  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  25  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  26  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  27  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  28  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  29  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  30  * SUCH DAMAGE.
  31  *
  32  *      from: @(#)isa.h 5.7 (Berkeley) 5/9/91
  33  * $FreeBSD: src/sys/isa/isareg.h,v 1.4.2.1 2000/07/18 20:39:05 dfr Exp $
  34  * $DragonFly: src/sys/bus/isa/isareg.h,v 1.4 2005/06/12 20:55:14 swildner Exp $
  35  */
  36
  37 #ifndef _ISA_ISA_H_
  38 #define _ISA_ISA_H_
  39
  40 /* BEWARE:  Included in both assembler and C code */
  41
  42 /*
  43  * ISA Bus conventions
  44  */
  45
  46 /*
  47  * Input / Output Port Assignments
  48  */
  49 #ifndef IO_ISABEGIN
  50 #define IO_ISABEGIN     0x000           /* 0x000 - Beginning of I/O Registers */
  51
  52                 /* CPU Board */
  53 #define IO_DMA1         0x000           /* 8237A DMA Controller #1 */
  54 #define IO_ICU1         0x020           /* 8259A Interrupt Controller #1 */
  55 #define IO_PMP1         0x026           /* 82347 Power Management Peripheral */
  56 #define IO_TIMER1       0x040           /* 8253 Timer #1 */
  57 #define IO_TIMER2       0x048           /* 8253 Timer #2 */
  58 #define IO_KBD          0x060           /* 8042 Keyboard */
  59 #define IO_PPI          0x061           /* Programmable Peripheral Interface */
  60 #define IO_RTC          0x070           /* RTC */
  61 #define IO_NMI          IO_RTC          /* NMI Control */
  62 #define IO_DMAPG        0x080           /* DMA Page Registers */
  63 #define IO_ICU2         0x0A0           /* 8259A Interrupt Controller #2 */
  64 #define IO_DMA2         0x0C0           /* 8237A DMA Controller #2 */
  65 #define IO_NPX          0x0F0           /* Numeric Coprocessor */
  66
  67                 /* Cards */
  68                                         /* 0x100 - 0x16F Open */
  69
  70 #define IO_WD2          0x170           /* Secondary Fixed Disk Controller */
  71
  72 #define IO_PMP2         0x178           /* 82347 Power Management Peripheral */
  73
  74                                         /* 0x17A - 0x1EF Open */
  75
  76 #define IO_WD1          0x1F0           /* Primary Fixed Disk Controller */
  77 #define IO_GAME         0x201           /* Game Controller */
  78
  79                                         /* 0x202 - 0x22A Open */
  80
  81 #define IO_ASC2         0x22B           /* AmiScan addr.grp. 2 */
  82
  83                                         /* 0x230 - 0x26A Open */
  84
  85 #define IO_ASC3         0x26B           /* AmiScan addr.grp. 3 */
  86 #define IO_GSC1         0x270 /* -- 0x27B! GeniScan GS-4500 addr.grp. 1 */
  87 #define IO_LPT2         0x278           /* Parallel Port #2 */
  88
  89                                         /* 0x280 - 0x2AA Open */
  90
  91 #define IO_ASC4         0x2AB           /* AmiScan addr.grp. 4 */
  92
  93                                         /* 0x2B0 - 0x2DF Open */
  94
  95 #define IO_GSC2         0x2E0           /* GeniScan GS-4500 addr.grp. 2 */
  96 #define IO_COM4         0x2E8           /* COM4 i/o address */
  97 #define IO_ASC5         0x2EB           /* AmiScan addr.grp. 5 */
  98
  99                                         /* 0x2F0 - 0x2F7 Open */
 100
 101 #define IO_COM2         0x2F8           /* COM2 i/o address */
 102
 103                                         /* 0x300 - 0x32A Open */
 104
 105 #define IO_ASC6         0x32B           /* AmiScan addr.grp. 6 */
 106 #define IO_AHA0         0x330           /* adaptec 1542 default addr. */
 107 #define IO_BT0          0x330           /* bustek 742a default addr. */
 108 #define IO_UHA0         0x330           /* ultrastore 14f default addr. */
 109 #define IO_AHA1         0x334           /* adaptec 1542 default addr. */
 110 #define IO_BT1          0x334           /* bustek 742a default addr. */
 111
 112                                         /* 0x340 - 0x36A Open */
 113
 114 #define IO_ASC7         0x36B           /* AmiScan addr.grp. 7 */
 115 #define IO_GSC3         0x370           /* GeniScan GS-4500 addr.grp. 3 */
 116 #define IO_FD2          0x370           /* secondary base i/o address */
 117 #define IO_LPT1         0x378           /* Parallel Port #1 */
 118
 119                                         /* 0x380 - 0x3AA Open */
 120
 121 #define IO_ASC8         0x3AB           /* AmiScan addr.grp. 8 */
 122 #define IO_MDA          0x3B0           /* Monochome Adapter */
 123 #define IO_LPT3         0x3BC           /* Monochome Adapter Printer Port */
 124 #define IO_VGA          0x3C0           /* E/VGA Ports */
 125 #define IO_CGA          0x3D0           /* CGA Ports */
 126 #define IO_GSC4         0x3E0           /* GeniScan GS-4500 addr.grp. 4 */
 127 #define IO_COM3         0x3E8           /* COM3 i/o address */
 128 #define IO_ASC1         0x3EB           /* AmiScan addr.grp. 1 */
 129 #define IO_FD1          0x3F0           /* primary base i/o address */
 130 #define IO_COM1         0x3F8           /* COM1 i/o address */
 131
 132 #define IO_ISAEND       0x3FF           /* End (actually Max) of I/O Regs */
 133 #endif /* !IO_ISABEGIN */
 134
 135 /*
 136  * Input / Output Port Sizes - these are from several sources, and tend
 137  * to be the larger of what was found.
 138  */
 139 #ifndef IO_ISASIZES
 140 #define IO_ISASIZES
 141
 142 #define IO_ASCSIZE      5               /* AmiScan GI1904-based hand scanner */
 143 #define IO_CGASIZE      12              /* CGA controllers */
 144 #define IO_COMSIZE      8               /* 8250, 16x50 com controllers */
 145 #define IO_DMASIZE      16              /* 8237 DMA controllers */
 146 #define IO_DPGSIZE      32              /* 74LS612 DMA page registers */
 147 #define IO_EISASIZE     256             /* EISA controllers */
 148 #define IO_FDCSIZE      8               /* Nec765 floppy controllers */
 149 #define IO_GAMSIZE      16              /* AT compatible game controllers */
 150 #define IO_GSCSIZE      8               /* GeniScan GS-4500G hand scanner */
 151 #define IO_ICUSIZE      16              /* 8259A interrupt controllers */
 152 #define IO_KBDSIZE      16              /* 8042 Keyboard controllers */
 153
 154 /* The following line was changed to support more architectures (simpler
 155    chipsets (like those for Alpha) only use 4, but more complex controllers
 156    can use an additional 4; the probe to see if the additional 4
 157    can be used by the specific chipset is now done in the ppc
 158    code by ppc_probe()... */
 159
 160 #define IO_LPTSIZE_EXTENDED     8       /* "Extended" LPT controllers */
 161 #define IO_LPTSIZE_NORMAL       4       /* "Normal" LPT controllers */
 162
 163 #define IO_MDASIZE      12              /* Monochrome display controllers */
 164 #define IO_NPXSIZE      16              /* 80387/80487 NPX registers */
 165 #define IO_PMPSIZE      2               /* 82347 power management peripheral */
 166 #define IO_PSMSIZE      5               /* 8042 Keyboard controllers */
 167 #define IO_RTCSIZE      16              /* CMOS real time clock, NMI control */
 168 #define IO_TMRSIZE      16              /* 8253 programmable timers */
 169 #define IO_VGASIZE      16              /* VGA controllers */
 170 #define IO_WDCSIZE      8               /* WD compatible disk controllers */
 171
 172 #endif /* !IO_ISASIZES */
 173
 174 /*
 175  * Input / Output Memory Physical Addresses
 176  */
 177 #ifndef IOM_BEGIN
 178 #define IOM_BEGIN       0x0A0000        /* Start of I/O Memory "hole" */
 179 #define IOM_END         0x100000        /* End of I/O Memory "hole" */
 180 #define IOM_SIZE        (IOM_END - IOM_BEGIN)
 181 #endif /* !IOM_BEGIN */
 182
 183 /*
 184  * RAM Physical Address Space (ignoring the above mentioned "hole")
 185  */
 186 #ifndef RAM_BEGIN
 187 #define RAM_BEGIN       0x0000000       /* Start of RAM Memory */
 188 #define RAM_END         0x1000000       /* End of RAM Memory */
 189 #define RAM_SIZE        (RAM_END - RAM_BEGIN)
 190 #endif /* !RAM_BEGIN */
 191
 192 /*
 193  * Oddball Physical Memory Addresses
 194  */
 195 #ifndef COMPAQ_RAMRELOC
 196 #define COMPAQ_RAMRELOC 0x80C00000      /* Compaq RAM relocation/diag */
 197 #define COMPAQ_RAMSETUP 0x80C00002      /* Compaq RAM setup */
 198 #define WEITEK_FPU      0xC0000000      /* WTL 2167 */
 199 #define CYRIX_EMC       0xC0000000      /* Cyrix EMC */
 200 #endif /* !COMPAQ_RAMRELOC */
 201
 202 #endif /* !_ISA_ISA_H_ */