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- Correct register name
[dragonfly.git] / sys / dev / netif / ral / rt2560reg.h
blob9e12a8fc443b4d043fa4ad17eba16a8ea72f5b46
1 /*
2 * Copyright (c) 2005, 2006
3 * Damien Bergamini <damien.bergamini@free.fr>
4 *
5 * Permission to use, copy, modify, and distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
8 *
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16 *
17 * $FreeBSD: src/sys/dev/ral/rt2560reg.h,v 1.1 2006/03/05 20:36:56 damien Exp $
18 * $DragonFly: src/sys/dev/netif/ral/rt2560reg.h,v 1.2 2006/11/16 12:24:35 sephe Exp $
19 */
20
21 #define RT2560_TX_RING_COUNT 48
22 #define RT2560_ATIM_RING_COUNT 4
23 #define RT2560_PRIO_RING_COUNT 16
24 #define RT2560_BEACON_RING_COUNT 1
25 #define RT2560_RX_RING_COUNT 32
26
27 #define RT2560_TX_DESC_SIZE (sizeof (struct rt2560_tx_desc))
28 #define RT2560_RX_DESC_SIZE (sizeof (struct rt2560_rx_desc))
29
30 #define RT2560_MAX_SCATTER 1
31
32 /*
33 * Control and status registers.
34 */
35 #define RT2560_CSR0 0x0000 /* ASIC version number */
36 #define RT2560_CSR1 0x0004 /* System control */
37 #define RT2560_CSR3 0x000c /* STA MAC address 0 */
38 #define RT2560_CSR4 0x0010 /* STA MAC address 1 */
39 #define RT2560_CSR5 0x0014 /* BSSID 0 */
40 #define RT2560_CSR6 0x0018 /* BSSID 1 */
41 #define RT2560_CSR7 0x001c /* Interrupt source */
42 #define RT2560_CSR8 0x0020 /* Interrupt mask */
43 #define RT2560_CSR9 0x0024 /* Maximum frame length */
44 #define RT2560_SECCSR0 0x0028 /* WEP control */
45 #define RT2560_CSR11 0x002c /* Back-off control */
46 #define RT2560_CSR12 0x0030 /* Synchronization configuration 0 */
47 #define RT2560_CSR13 0x0034 /* Synchronization configuration 1 */
48 #define RT2560_CSR14 0x0038 /* Synchronization control */
49 #define RT2560_CSR15 0x003c /* Synchronization status */
50 #define RT2560_CSR16 0x0040 /* TSF timer 0 */
51 #define RT2560_CSR17 0x0044 /* TSF timer 1 */
52 #define RT2560_CSR18 0x0048 /* IFS timer 0 */
53 #define RT2560_CSR19 0x004c /* IFS timer 1 */
54 #define RT2560_CSR20 0x0050 /* WAKEUP timer */
55 #define RT2560_CSR21 0x0054 /* EEPROM control */
56 #define RT2560_CSR22 0x0058 /* CFP control */
57 #define RT2560_TXCSR0 0x0060 /* TX control */
58 #define RT2560_TXCSR1 0x0064 /* TX configuration */
59 #define RT2560_TXCSR2 0x0068 /* TX descriptor configuration */
60 #define RT2560_TXCSR3 0x006c /* TX ring base address */
61 #define RT2560_TXCSR4 0x0070 /* TX ATIM ring base address */
62 #define RT2560_TXCSR5 0x0074 /* TX PRIO ring base address */
63 #define RT2560_TXCSR6 0x0078 /* Beacon base address */
64 #define RT2560_TXCSR7 0x007c /* AutoResponder control */
65 #define RT2560_RXCSR0 0x0080 /* RX control */
66 #define RT2560_RXCSR1 0x0084 /* RX descriptor configuration */
67 #define RT2560_RXCSR2 0x0088 /* RX ring base address */
68 #define RT2560_PCICSR 0x008c /* PCI control */
69 #define RT2560_RXCSR3 0x0090 /* BBP ID 0 */
70 #define RT2560_TXCSR9 0x0094 /* OFDM TX BBP */
71 #define RT2560_TXCSR8 0x0098 /* CCK TX BBP */
72 #define RT2560_ARSP_PLCP_1 0x009c /* Auto Responder Basic Rate mask */
73 #define RT2560_CNT0 0x00a0 /* FCS error counter */
74 #define RT2560_CNT1 0x00ac /* PLCP error counter */
75 #define RT2560_CNT2 0x00b0 /* Long error counter */
76 #define RT2560_CNT3 0x00b8 /* CCA false alarm counter */
77 #define RT2560_CNT4 0x00bc /* RX FIFO Overflow counter */
78 #define RT2560_CNT5 0x00c0 /* Tx FIFO Underrun counter */
79 #define RT2560_PWRCSR0 0x00c4 /* Power mode configuration */
80 #define RT2560_PSCSR0 0x00c8 /* Power state transition time */
81 #define RT2560_PSCSR1 0x00cc /* Power state transition time */
82 #define RT2560_PSCSR2 0x00d0 /* Power state transition time */
83 #define RT2560_PSCSR3 0x00d4 /* Power state transition time */
84 #define RT2560_PWRCSR1 0x00d8 /* Manual power control/status */
85 #define RT2560_TIMECSR 0x00dc /* Timer control */
86 #define RT2560_MACCSR0 0x00e0 /* MAC configuration */
87 #define RT2560_MACCSR1 0x00e4 /* MAC configuration */
88 #define RT2560_RALINKCSR 0x00e8 /* Ralink RX auto-reset BBCR */
89 #define RT2560_BCNCSR 0x00ec /* Beacon interval control */
90 #define RT2560_BBPCSR 0x00f0 /* BBP serial control */
91 #define RT2560_RFCSR 0x00f4 /* RF serial control */
92 #define RT2560_LEDCSR 0x00f8 /* LED control */
93 #define RT2560_SECCSR3 0x00fc /* XXX not documented */
94 #define RT2560_DMACSR0 0x0100 /* Current RX ring address */
95 #define RT2560_DMACSR1 0x0104 /* Current Tx ring address */
96 #define RT2560_DMACSR2 0x0104 /* Current Priority ring address */
97 #define RT2560_DMACSR3 0x0104 /* Current ATIM ring address */
98 #define RT2560_TXACKCSR0 0x0110 /* XXX not documented */
99 #define RT2560_GPIOCSR 0x0120 /* */
100 #define RT2560_BBBPPCSR 0x0124 /* BBP Pin Control */
101 #define RT2560_FIFOCSR0 0x0128 /* TX FIFO pointer */
102 #define RT2560_FIFOCSR1 0x012c /* RX FIFO pointer */
103 #define RT2560_BCNOCSR 0x0130 /* Beacon time offset */
104 #define RT2560_RLPWCSR 0x0134 /* RX_PE Low Width */
105 #define RT2560_TESTCSR 0x0138 /* Test Mode Select */
106 #define RT2560_PLCP1MCSR 0x013c /* Signal/Service/Length of ACK @1M */
107 #define RT2560_PLCP2MCSR 0x0140 /* Signal/Service/Length of ACK @2M */
108 #define RT2560_PLCP5p5MCSR 0x0144 /* Signal/Service/Length of ACK @5.5M */
109 #define RT2560_PLCP11MCSR 0x0148 /* Signal/Service/Length of ACK @11M */
110 #define RT2560_ARTCSR0 0x014c /* ACK/CTS padload consume time
111 * @ 1/2/5.5/11M
112 */
113 #define RT2560_ARTCSR1 0x0150 /* ACK/CTS padload consume time
114 * @ 18/12/9/6M
115 */
116 #define RT2560_ARTCSR2 0x0154 /* ACK/CTS padload consume time
117 * @ 54/48/36/24M
118 */
119 #define RT2560_SECCSR1 0x0158 /* WEP control */
120 #define RT2560_BBPCSR1 0x015c /* BBP TX Configuration */
121
122
123 /* possible flags for register RXCSR0 */
124 #define RT2560_DISABLE_RX (1 << 0)
125 #define RT2560_DROP_CRC_ERROR (1 << 1)
126 #define RT2560_DROP_PHY_ERROR (1 << 2)
127 #define RT2560_DROP_CTL (1 << 3)
128 #define RT2560_DROP_NOT_TO_ME (1 << 4)
129 #define RT2560_DROP_TODS (1 << 5)
130 #define RT2560_DROP_VERSION_ERROR (1 << 6)
131
132 /* possible flags for register CSR1 */
133 #define RT2560_RESET_ASIC (1 << 0)
134 #define RT2560_RESET_BBP (1 << 1)
135 #define RT2560_HOST_READY (1 << 2)
136
137 /* possible flags for register CSR14 */
138 #define RT2560_ENABLE_TSF (1 << 0)
139 #define RT2560_ENABLE_TSF_SYNC(x) (((x) & 0x3) << 1)
140 #define RT2560_ENABLE_TBCN (1 << 3)
141 #define RT2560_ENABLE_BEACON_GENERATOR (1 << 6)
142
143 /* possible flags for register CSR21 */
144 #define RT2560_C (1 << 1)
145 #define RT2560_S (1 << 2)
146 #define RT2560_D (1 << 3)
147 #define RT2560_Q (1 << 4)
148 #define RT2560_93C46 (1 << 5)
149
150 #define RT2560_SHIFT_D 3
151 #define RT2560_SHIFT_Q 4
152
153 /* possible flags for register TXCSR0 */
154 #define RT2560_KICK_TX (1 << 0)
155 #define RT2560_KICK_ATIM (1 << 1)
156 #define RT2560_KICK_PRIO (1 << 2)
157 #define RT2560_ABORT_TX (1 << 3)
158
159 /* possible flags for register SECCSR0 */
160 #define RT2560_KICK_DECRYPT (1 << 0)
161
162 /* possible flags for register SECCSR1 */
163 #define RT2560_KICK_ENCRYPT (1 << 0)
164
165 /* possible flags for register CSR7 */
166 #define RT2560_BEACON_EXPIRE 0x00000001
167 #define RT2560_WAKEUP_EXPIRE 0x00000002
168 #define RT2560_ATIM_EXPIRE 0x00000004
169 #define RT2560_TX_DONE 0x00000008
170 #define RT2560_ATIM_DONE 0x00000010
171 #define RT2560_PRIO_DONE 0x00000020
172 #define RT2560_RX_DONE 0x00000040
173 #define RT2560_DECRYPTION_DONE 0x00000080
174 #define RT2560_ENCRYPTION_DONE 0x00000100
175
176 #define RT2560_INTR_MASK \
177 (~(RT2560_BEACON_EXPIRE | RT2560_WAKEUP_EXPIRE | RT2560_TX_DONE | \
178 RT2560_PRIO_DONE | RT2560_RX_DONE | RT2560_DECRYPTION_DONE | \
179 RT2560_ENCRYPTION_DONE))
180
181 /* Tx descriptor */
182 struct rt2560_tx_desc {
183 uint32_t flags;
184 #define RT2560_TX_BUSY (1 << 0)
185 #define RT2560_TX_VALID (1 << 1)
186
187 #define RT2560_TX_RESULT_MASK 0x0000001c
188 #define RT2560_TX_SUCCESS (0 << 2)
189 #define RT2560_TX_SUCCESS_RETRY (1 << 2)
190 #define RT2560_TX_FAIL_RETRY (2 << 2)
191 #define RT2560_TX_FAIL_INVALID (3 << 2)
192 #define RT2560_TX_FAIL_OTHER (4 << 2)
193
194 #define RT2560_TX_MORE_FRAG (1 << 8)
195 #define RT2560_TX_ACK (1 << 9)
196 #define RT2560_TX_TIMESTAMP (1 << 10)
197 #define RT2560_TX_OFDM (1 << 11)
198 #define RT2560_TX_CIPHER_BUSY (1 << 12)
199
200 #define RT2560_TX_IFS_MASK 0x00006000
201 #define RT2560_TX_IFS_BACKOFF (0 << 13)
202 #define RT2560_TX_IFS_SIFS (1 << 13)
203 #define RT2560_TX_IFS_NEWBACKOFF (2 << 13)
204 #define RT2560_TX_IFS_NONE (3 << 13)
205
206 #define RT2560_TX_LONG_RETRY (1 << 15)
207
208 #define RT2560_TX_CIPHER_MASK 0xe0000000
209 #define RT2560_TX_CIPHER_NONE (0 << 29)
210 #define RT2560_TX_CIPHER_WEP40 (1 << 29)
211 #define RT2560_TX_CIPHER_WEP104 (2 << 29)
212 #define RT2560_TX_CIPHER_TKIP (3 << 29)
213 #define RT2560_TX_CIPHER_AES (4 << 29)
214
215 uint32_t physaddr;
216 uint16_t wme;
217 #define RT2560_LOGCWMAX(x) (((x) & 0xf) << 12)
218 #define RT2560_LOGCWMIN(x) (((x) & 0xf) << 8)
219 #define RT2560_AIFSN(x) (((x) & 0x3) << 6)
220 #define RT2560_IVOFFSET(x) (((x) & 0x3f))
221
222 uint16_t reserved1;
223 uint8_t plcp_signal;
224 uint8_t plcp_service;
225 #define RT2560_PLCP_LENGEXT 0x80
226
227 uint8_t plcp_length_lo;
228 uint8_t plcp_length_hi;
229 uint32_t iv;
230 uint32_t eiv;
231 uint8_t key[IEEE80211_KEYBUF_SIZE];
232 uint32_t reserved2[2];
233 } __packed;
234
235 /* Rx descriptor */
236 struct rt2560_rx_desc {
237 uint32_t flags;
238 #define RT2560_RX_BUSY (1 << 0)
239 #define RT2560_RX_CRC_ERROR (1 << 5)
240 #define RT2560_RX_OFDM (1 << 6)
241 #define RT2560_RX_PHY_ERROR (1 << 7)
242 #define RT2560_RX_CIPHER_BUSY (1 << 8)
243 #define RT2560_RX_ICV_ERROR (1 << 9)
244
245 #define RT2560_RX_CIPHER_MASK 0xe0000000
246 #define RT2560_RX_CIPHER_NONE (0 << 29)
247 #define RT2560_RX_CIPHER_WEP40 (1 << 29)
248 #define RT2560_RX_CIPHER_WEP104 (2 << 29)
249 #define RT2560_RX_CIPHER_TKIP (3 << 29)
250 #define RT2560_RX_CIPHER_AES (4 << 29)
251
252 uint32_t physaddr;
253 uint8_t rate;
254 uint8_t rssi;
255 uint8_t ta[IEEE80211_ADDR_LEN];
256 uint32_t iv;
257 uint32_t eiv;
258 uint8_t key[IEEE80211_KEYBUF_SIZE];
259 uint32_t reserved[2];
260 } __packed;
261
262 #define RAL_RF1 0
263 #define RAL_RF2 2
264 #define RAL_RF3 1
265 #define RAL_RF4 3
266
267 #define RT2560_RF1_AUTOTUNE 0x08000
268 #define RT2560_RF3_AUTOTUNE 0x00040
269
270 #define RT2560_BBP_BUSY (1 << 15)
271 #define RT2560_BBP_WRITE (1 << 16)
272 #define RT2560_RF_20BIT (20 << 24)
273 #define RT2560_RF_BUSY (1 << 31)
274
275 #define RT2560_RF_2522 0x00
276 #define RT2560_RF_2523 0x01
277 #define RT2560_RF_2524 0x02
278 #define RT2560_RF_2525 0x03
279 #define RT2560_RF_2525E 0x04
280 #define RT2560_RF_2526 0x05
281 /* dual-band RF */
282 #define RT2560_RF_5222 0x10
283
284 #define RT2560_BBP_VERSION 0
285 #define RT2560_BBP_TX 2
286 #define RT2560_BBP_RX 14
287
288 #define RT2560_BBP_ANTA 0x00
289 #define RT2560_BBP_DIVERSITY 0x01
290 #define RT2560_BBP_ANTB 0x02
291 #define RT2560_BBP_ANTMASK 0x03
292 #define RT2560_BBP_FLIPIQ 0x04
293
294 #define RT2560_LED_MODE_DEFAULT 0
295 #define RT2560_LED_MODE_TXRX_ACTIVITY 1
296 #define RT2560_LED_MODE_SINGLE 2
297 #define RT2560_LED_MODE_ASUS 3
298
299 #define RT2560_JAPAN_FILTER 0x8
300
301 #define RT2560_EEPROM_DELAY 1 /* minimum hold time (microsecond) */
302
303 #define RT2560_EEPROM_CONFIG0 16
304 #define RT2560_EEPROM_BBP_BASE 19
305 #define RT2560_EEPROM_TXPOWER 35
306
307 /*
308 * control and status registers access macros
309 */
310 #define RAL_READ(sc, reg) \
311 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg))
312
313 #define RAL_WRITE(sc, reg, val) \
314 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val))
315
316 /*
317 * EEPROM access macro
318 */
319 #define RT2560_EEPROM_CTL(sc, val) do { \
320 RAL_WRITE((sc), RT2560_CSR21, (val)); \
321 DELAY(RT2560_EEPROM_DELAY); \
322 } while (/* CONSTCOND */0)
323
324 /*
325 * Default values for MAC registers; values taken from the reference driver.
326 */
327 #define RT2560_DEF_MAC \
328 { RT2560_PSCSR0, 0x00020002 }, \
329 { RT2560_PSCSR1, 0x00000002 }, \
330 { RT2560_PSCSR2, 0x00020002 }, \
331 { RT2560_PSCSR3, 0x00000002 }, \
332 { RT2560_TIMECSR, 0x00003f21 }, \
333 { RT2560_CSR9, 0x00000780 }, \
334 { RT2560_CSR11, 0x07041483 }, \
335 { RT2560_CNT3, 0x00000000 }, \
336 { RT2560_TXCSR1, 0x07614562 }, \
337 { RT2560_TXCSR8, 0x8c8d8b8a }, \
338 { RT2560_ARTCSR0, 0x7038140a }, \
339 { RT2560_ARTCSR1, 0x1d21252d }, \
340 { RT2560_ARTCSR2, 0x1919191d }, \
341 { RT2560_RXCSR0, 0xffffffff }, \
342 { RT2560_RXCSR3, 0xb3aab3af }, \
343 { RT2560_PCICSR, 0x000003b8 }, \
344 { RT2560_PWRCSR0, 0x3f3b3100 }, \
345 { RT2560_GPIOCSR, 0x0000ff00 }, \
346 { RT2560_TESTCSR, 0x000000f0 }, \
347 { RT2560_PWRCSR1, 0x000001ff }, \
348 { RT2560_MACCSR0, 0x00213223 }, \
349 { RT2560_MACCSR1, 0x00235518 }, \
350 { RT2560_RLPWCSR, 0x00000040 }, \
351 { RT2560_RALINKCSR, 0x9a009a11 }, \
352 { RT2560_CSR7, 0xffffffff }, \
353 { RT2560_BBPCSR1, 0x82188200 }, \
354 { RT2560_TXACKCSR0, 0x00000020 }, \
355 { RT2560_SECCSR3, 0x0000e78f }
356
357 /*
358 * Default values for BBP registers; values taken from the reference driver.
359 */
360 #define RT2560_DEF_BBP \
361 { 3, 0x02 }, \
362 { 4, 0x19 }, \
363 { 14, 0x1c }, \
364 { 15, 0x30 }, \
365 { 16, 0xac }, \
366 { 17, 0x48 }, \
367 { 18, 0x18 }, \
368 { 19, 0xff }, \
369 { 20, 0x1e }, \
370 { 21, 0x08 }, \
371 { 22, 0x08 }, \
372 { 23, 0x08 }, \
373 { 24, 0x80 }, \
374 { 25, 0x50 }, \
375 { 26, 0x08 }, \
376 { 27, 0x23 }, \
377 { 30, 0x10 }, \
378 { 31, 0x2b }, \
379 { 32, 0xb9 }, \
380 { 34, 0x12 }, \
381 { 35, 0x50 }, \
382 { 39, 0xc4 }, \
383 { 40, 0x02 }, \
384 { 41, 0x60 }, \
385 { 53, 0x10 }, \
386 { 54, 0x18 }, \
387 { 56, 0x08 }, \
388 { 57, 0x10 }, \
389 { 58, 0x08 }, \
390 { 61, 0x60 }, \
391 { 62, 0x10 }, \
392 { 75, 0xff }
393
394 /*
395 * Default values for RF register R2 indexed by channel numbers; values taken
396 * from the reference driver.
397 */
398 #define RT2560_RF2522_R2 \
399 { \
400 0x307f6, 0x307fb, 0x30800, 0x30805, 0x3080a, 0x3080f, 0x30814, \
401 0x30819, 0x3081e, 0x30823, 0x30828, 0x3082d, 0x30832, 0x3083e \
402 }
403
404 #define RT2560_RF2523_R2 \
405 { \
406 0x00327, 0x00328, 0x00329, 0x0032a, 0x0032b, 0x0032c, 0x0032d, \
407 0x0032e, 0x0032f, 0x00340, 0x00341, 0x00342, 0x00343, 0x00346 \
408 }
409
410 #define RT2560_RF2524_R2 \
411 { \
412 0x00327, 0x00328, 0x00329, 0x0032a, 0x0032b, 0x0032c, 0x0032d, \
413 0x0032e, 0x0032f, 0x00340, 0x00341, 0x00342, 0x00343, 0x00346 \
414 }
415
416 #define RT2560_RF2525_R2 \
417 { \
418 0x20327, 0x20328, 0x20329, 0x2032a, 0x2032b, 0x2032c, 0x2032d, \
419 0x2032e, 0x2032f, 0x20340, 0x20341, 0x20342, 0x20343, 0x20346 \
420 }
421
422 #define RT2560_RF2525_HI_R2 \
423 { \
424 0x2032f, 0x20340, 0x20341, 0x20342, 0x20343, 0x20344, 0x20345, \
425 0x20346, 0x20347, 0x20348, 0x20349, 0x2034a, 0x2034b, 0x2034e \
426 }
427
428 #define RT2560_RF2525E_R2 \
429 { \
430 0x2044d, 0x2044e, 0x2044f, 0x20460, 0x20461, 0x20462, 0x20463, \
431 0x20464, 0x20465, 0x20466, 0x20467, 0x20468, 0x20469, 0x2046b \
432 }
433
434 #define RT2560_RF2526_HI_R2 \
435 { \
436 0x0022a, 0x0022b, 0x0022b, 0x0022c, 0x0022c, 0x0022d, 0x0022d, \
437 0x0022e, 0x0022e, 0x0022f, 0x0022d, 0x00240, 0x00240, 0x00241 \
438 }
439
440 #define RT2560_RF2526_R2 \
441 { \
442 0x00226, 0x00227, 0x00227, 0x00228, 0x00228, 0x00229, 0x00229, \
443 0x0022a, 0x0022a, 0x0022b, 0x0022b, 0x0022c, 0x0022c, 0x0022d \
444 }
445
446 /*
447 * For dual-band RF, RF registers R1 and R4 also depend on channel number;
448 * values taken from the reference driver.
449 */
450 #define RT2560_RF5222 \
451 { 1, 0x08808, 0x0044d, 0x00282 }, \
452 { 2, 0x08808, 0x0044e, 0x00282 }, \
453 { 3, 0x08808, 0x0044f, 0x00282 }, \
454 { 4, 0x08808, 0x00460, 0x00282 }, \
455 { 5, 0x08808, 0x00461, 0x00282 }, \
456 { 6, 0x08808, 0x00462, 0x00282 }, \
457 { 7, 0x08808, 0x00463, 0x00282 }, \
458 { 8, 0x08808, 0x00464, 0x00282 }, \
459 { 9, 0x08808, 0x00465, 0x00282 }, \
460 { 10, 0x08808, 0x00466, 0x00282 }, \
461 { 11, 0x08808, 0x00467, 0x00282 }, \
462 { 12, 0x08808, 0x00468, 0x00282 }, \
463 { 13, 0x08808, 0x00469, 0x00282 }, \
464 { 14, 0x08808, 0x0046b, 0x00286 }, \
465 \
466 { 36, 0x08804, 0x06225, 0x00287 }, \
467 { 40, 0x08804, 0x06226, 0x00287 }, \
468 { 44, 0x08804, 0x06227, 0x00287 }, \
469 { 48, 0x08804, 0x06228, 0x00287 }, \
470 { 52, 0x08804, 0x06229, 0x00287 }, \
471 { 56, 0x08804, 0x0622a, 0x00287 }, \
472 { 60, 0x08804, 0x0622b, 0x00287 }, \
473 { 64, 0x08804, 0x0622c, 0x00287 }, \
474 \
475 { 100, 0x08804, 0x02200, 0x00283 }, \
476 { 104, 0x08804, 0x02201, 0x00283 }, \
477 { 108, 0x08804, 0x02202, 0x00283 }, \
478 { 112, 0x08804, 0x02203, 0x00283 }, \
479 { 116, 0x08804, 0x02204, 0x00283 }, \
480 { 120, 0x08804, 0x02205, 0x00283 }, \
481 { 124, 0x08804, 0x02206, 0x00283 }, \
482 { 128, 0x08804, 0x02207, 0x00283 }, \
483 { 132, 0x08804, 0x02208, 0x00283 }, \
484 { 136, 0x08804, 0x02209, 0x00283 }, \
485 { 140, 0x08804, 0x0220a, 0x00283 }, \
486 \
487 { 149, 0x08808, 0x02429, 0x00281 }, \
488 { 153, 0x08808, 0x0242b, 0x00281 }, \
489 { 157, 0x08808, 0x0242d, 0x00281 }, \
490 { 161, 0x08808, 0x0242f, 0x00281 }
DragonFly BSD