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kernel - Make the x86-64 double-fault exception operational
[dragonfly.git] / sys / platform / pc64 / x86_64 / mp_machdep.c
blob3709c4ba8952b45a4eca8351b8a724996542e0d5
1 /*
2 * Copyright (c) 1996, by Steve Passe
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. The name of the developer may NOT be used to endorse or promote products
11 * derived from this software without specific prior written permission.
12 *
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
23 * SUCH DAMAGE.
24 *
25 * $FreeBSD: src/sys/i386/i386/mp_machdep.c,v 1.115.2.15 2003/03/14 21:22:35 jhb Exp $
26 * $DragonFly: src/sys/platform/pc32/i386/mp_machdep.c,v 1.60 2008/06/07 12:03:52 mneumann Exp $
27 */
28
29 #include "opt_cpu.h"
30
31 #include <sys/param.h>
32 #include <sys/systm.h>
33 #include <sys/kernel.h>
34 #include <sys/sysctl.h>
35 #include <sys/malloc.h>
36 #include <sys/memrange.h>
37 #include <sys/cons.h> /* cngetc() */
38 #include <sys/machintr.h>
39
40 #include <sys/mplock2.h>
41
42 #include <vm/vm.h>
43 #include <vm/vm_param.h>
44 #include <vm/pmap.h>
45 #include <vm/vm_kern.h>
46 #include <vm/vm_extern.h>
47 #include <sys/lock.h>
48 #include <vm/vm_map.h>
49 #include <sys/user.h>
50 #ifdef GPROF
51 #include <sys/gmon.h>
52 #endif
53
54 #include <machine/smp.h>
55 #include <machine_base/apic/apicreg.h>
56 #include <machine/atomic.h>
57 #include <machine/cpufunc.h>
58 #include <machine_base/apic/mpapic.h>
59 #include <machine/psl.h>
60 #include <machine/segments.h>
61 #include <machine/tss.h>
62 #include <machine/specialreg.h>
63 #include <machine/globaldata.h>
64 #include <machine/pmap_inval.h>
65
66 #include <machine/md_var.h> /* setidt() */
67 #include <machine_base/icu/icu.h> /* IPIs */
68 #include <machine_base/isa/intr_machdep.h> /* IPIs */
69
70 #define FIXUP_EXTRA_APIC_INTS 8 /* additional entries we may create */
71
72 #define WARMBOOT_TARGET 0
73 #define WARMBOOT_OFF (KERNBASE + 0x0467)
74 #define WARMBOOT_SEG (KERNBASE + 0x0469)
75
76 #define BIOS_BASE (0xf0000)
77 #define BIOS_SIZE (0x10000)
78 #define BIOS_COUNT (BIOS_SIZE/4)
79
80 #define CMOS_REG (0x70)
81 #define CMOS_DATA (0x71)
82 #define BIOS_RESET (0x0f)
83 #define BIOS_WARM (0x0a)
84
85 #define PROCENTRY_FLAG_EN 0x01
86 #define PROCENTRY_FLAG_BP 0x02
87 #define IOAPICENTRY_FLAG_EN 0x01
88
89
90 /* MP Floating Pointer Structure */
91 typedef struct MPFPS {
92 char signature[4];
93 u_int32_t pap;
94 u_char length;
95 u_char spec_rev;
96 u_char checksum;
97 u_char mpfb1;
98 u_char mpfb2;
99 u_char mpfb3;
100 u_char mpfb4;
101 u_char mpfb5;
102 } *mpfps_t;
103
104 /* MP Configuration Table Header */
105 typedef struct MPCTH {
106 char signature[4];
107 u_short base_table_length;
108 u_char spec_rev;
109 u_char checksum;
110 u_char oem_id[8];
111 u_char product_id[12];
112 u_int32_t oem_table_pointer;
113 u_short oem_table_size;
114 u_short entry_count;
115 u_int32_t apic_address;
116 u_short extended_table_length;
117 u_char extended_table_checksum;
118 u_char reserved;
119 } *mpcth_t;
120
121
122 typedef struct PROCENTRY {
123 u_char type;
124 u_char apic_id;
125 u_char apic_version;
126 u_char cpu_flags;
127 u_int32_t cpu_signature;
128 u_int32_t feature_flags;
129 u_int32_t reserved1;
130 u_int32_t reserved2;
131 } *proc_entry_ptr;
132
133 typedef struct BUSENTRY {
134 u_char type;
135 u_char bus_id;
136 char bus_type[6];
137 } *bus_entry_ptr;
138
139 typedef struct IOAPICENTRY {
140 u_char type;
141 u_char apic_id;
142 u_char apic_version;
143 u_char apic_flags;
144 u_int32_t apic_address;
145 } *io_apic_entry_ptr;
146
147 typedef struct INTENTRY {
148 u_char type;
149 u_char int_type;
150 u_short int_flags;
151 u_char src_bus_id;
152 u_char src_bus_irq;
153 u_char dst_apic_id;
154 u_char dst_apic_int;
155 } *int_entry_ptr;
156
157 /* descriptions of MP basetable entries */
158 typedef struct BASETABLE_ENTRY {
159 u_char type;
160 u_char length;
161 char name[16];
162 } basetable_entry;
163
164 struct mptable_pos {
165 mpfps_t mp_fps;
166 mpcth_t mp_cth;
167 vm_size_t mp_cth_mapsz;
168 };
169
170 typedef int (*mptable_iter_func)(void *, const void *, int);
171
172 /*
173 * this code MUST be enabled here and in mpboot.s.
174 * it follows the very early stages of AP boot by placing values in CMOS ram.
175 * it NORMALLY will never be needed and thus the primitive method for enabling.
176 *
177 */
178 #if defined(CHECK_POINTS)
179 #define CHECK_READ(A) (outb(CMOS_REG, (A)), inb(CMOS_DATA))
180 #define CHECK_WRITE(A,D) (outb(CMOS_REG, (A)), outb(CMOS_DATA, (D)))
181
182 #define CHECK_INIT(D); \
183 CHECK_WRITE(0x34, (D)); \
184 CHECK_WRITE(0x35, (D)); \
185 CHECK_WRITE(0x36, (D)); \
186 CHECK_WRITE(0x37, (D)); \
187 CHECK_WRITE(0x38, (D)); \
188 CHECK_WRITE(0x39, (D));
189
190 #define CHECK_PRINT(S); \
191 kprintf("%s: %d, %d, %d, %d, %d, %d\n", \
192 (S), \
193 CHECK_READ(0x34), \
194 CHECK_READ(0x35), \
195 CHECK_READ(0x36), \
196 CHECK_READ(0x37), \
197 CHECK_READ(0x38), \
198 CHECK_READ(0x39));
199
200 #else /* CHECK_POINTS */
201
202 #define CHECK_INIT(D)
203 #define CHECK_PRINT(S)
204
205 #endif /* CHECK_POINTS */
206
207 /*
208 * Values to send to the POST hardware.
209 */
210 #define MP_BOOTADDRESS_POST 0x10
211 #define MP_PROBE_POST 0x11
212 #define MPTABLE_PASS1_POST 0x12
213
214 #define MP_START_POST 0x13
215 #define MP_ENABLE_POST 0x14
216 #define MPTABLE_PASS2_POST 0x15
217
218 #define START_ALL_APS_POST 0x16
219 #define INSTALL_AP_TRAMP_POST 0x17
220 #define START_AP_POST 0x18
221
222 #define MP_ANNOUNCE_POST 0x19
223
224 static int need_hyperthreading_fixup;
225 static u_int logical_cpus;
226 u_int logical_cpus_mask;
227
228 static int madt_probe_test;
229 TUNABLE_INT("hw.madt_probe_test", &madt_probe_test);
230
231 /** XXX FIXME: where does this really belong, isa.h/isa.c perhaps? */
232 int current_postcode;
233
234 /** XXX FIXME: what system files declare these??? */
235 extern struct region_descriptor r_gdt, r_idt;
236
237 int mp_naps; /* # of Applications processors */
238 #ifdef APIC_IO
239 static int mp_nbusses; /* # of busses */
240 int mp_napics; /* # of IO APICs */
241 #endif
242 vm_offset_t cpu_apic_address;
243 #ifdef APIC_IO
244 vm_offset_t io_apic_address[NAPICID]; /* NAPICID is more than enough */
245 u_int32_t *io_apic_versions;
246 #endif
247 extern int nkpt;
248
249 u_int32_t cpu_apic_versions[MAXCPU];
250 int64_t tsc0_offset;
251 extern int64_t tsc_offsets[];
252
253 extern u_long ebda_addr;
254
255 #ifdef APIC_IO
256 struct apic_intmapinfo int_to_apicintpin[APIC_INTMAPSIZE];
257 #endif
258
259 /*
260 * APIC ID logical/physical mapping structures.
261 * We oversize these to simplify boot-time config.
262 */
263 int cpu_num_to_apic_id[NAPICID];
264 #ifdef APIC_IO
265 int io_num_to_apic_id[NAPICID];
266 #endif
267 int apic_id_to_logical[NAPICID];
268
269 /* AP uses this during bootstrap. Do not staticize. */
270 char *bootSTK;
271 static int bootAP;
272
273 /*
274 * SMP page table page. Setup by locore to point to a page table
275 * page from which we allocate per-cpu privatespace areas io_apics,
276 * and so forth.
277 */
278
279 #define IO_MAPPING_START_INDEX \
280 (SMP_MAXCPU * sizeof(struct privatespace) / PAGE_SIZE)
281
282 extern pt_entry_t *SMPpt;
283
284 struct pcb stoppcbs[MAXCPU];
285
286 extern inthand_t IDTVEC(fast_syscall), IDTVEC(fast_syscall32);
287
288 static basetable_entry basetable_entry_types[] =
289 {
290 {0, 20, "Processor"},
291 {1, 8, "Bus"},
292 {2, 8, "I/O APIC"},
293 {3, 8, "I/O INT"},
294 {4, 8, "Local INT"}
295 };
296
297 /*
298 * Local data and functions.
299 */
300
301 static u_int boot_address;
302 static u_int base_memory;
303 static int mp_finish;
304
305 static void mp_enable(u_int boot_addr);
306
307 static int mptable_iterate_entries(const mpcth_t,
308 mptable_iter_func, void *);
309 static int mptable_probe(void);
310 static int mptable_check(vm_paddr_t);
311 static long mptable_search_sig(u_int32_t target, int count);
312 static void mptable_hyperthread_fixup(u_int id_mask);
313 static void mptable_pass1(struct mptable_pos *);
314 static int mptable_pass2(struct mptable_pos *);
315 static void mptable_default(int type);
316 static void mptable_fix(void);
317 static int mptable_map(struct mptable_pos *, vm_paddr_t);
318 static void mptable_unmap(struct mptable_pos *);
319
320 #ifdef APIC_IO
321 static void setup_apic_irq_mapping(void);
322 static int apic_int_is_bus_type(int intr, int bus_type);
323 #endif
324 static int start_all_aps(u_int boot_addr);
325 #if 0
326 static void install_ap_tramp(u_int boot_addr);
327 #endif
328 static int start_ap(struct mdglobaldata *gd, u_int boot_addr, int smibest);
329 static int smitest(void);
330
331 static cpumask_t smp_startup_mask = 1; /* which cpus have been started */
332 cpumask_t smp_active_mask = 1; /* which cpus are ready for IPIs etc? */
333 SYSCTL_INT(_machdep, OID_AUTO, smp_active, CTLFLAG_RD, &smp_active_mask, 0, "");
334 static u_int bootMP_size;
335
336 /*
337 * Calculate usable address in base memory for AP trampoline code.
338 */
339 u_int
340 mp_bootaddress(u_int basemem)
341 {
342 POSTCODE(MP_BOOTADDRESS_POST);
343
344 base_memory = basemem;
345
346 bootMP_size = mptramp_end - mptramp_start;
347 boot_address = trunc_page(basemem * 1024); /* round down to 4k boundary */
348 if (((basemem * 1024) - boot_address) < bootMP_size)
349 boot_address -= PAGE_SIZE; /* not enough, lower by 4k */
350 /* 3 levels of page table pages */
351 mptramp_pagetables = boot_address - (PAGE_SIZE * 3);
352
353 return mptramp_pagetables;
354 }
355
356
357 /*
358 * Look for an Intel MP spec table (ie, SMP capable hardware).
359 */
360 static int
361 mptable_probe(void)
362 {
363 long x;
364 u_int32_t target;
365
366 /*
367 * Make sure our SMPpt[] page table is big enough to hold all the
368 * mappings we need.
369 */
370 KKASSERT(IO_MAPPING_START_INDEX < NPTEPG - 2);
371
372 POSTCODE(MP_PROBE_POST);
373
374 /* see if EBDA exists */
375 if (ebda_addr != 0) {
376 /* search first 1K of EBDA */
377 target = (u_int32_t)ebda_addr;
378 if ((x = mptable_search_sig(target, 1024 / 4)) > 0)
379 return x;
380 } else {
381 /* last 1K of base memory, effective 'top of base' passed in */
382 target = (u_int32_t)(base_memory - 0x400);
383 if ((x = mptable_search_sig(target, 1024 / 4)) > 0)
384 return x;
385 }
386
387 /* search the BIOS */
388 target = (u_int32_t)BIOS_BASE;
389 if ((x = mptable_search_sig(target, BIOS_COUNT)) > 0)
390 return x;
391
392 /* nothing found */
393 return 0;
394 }
395
396 struct mptable_check_cbarg {
397 int cpu_count;
398 int found_bsp;
399 };
400
401 static int
402 mptable_check_callback(void *xarg, const void *pos, int type)
403 {
404 const struct PROCENTRY *ent;
405 struct mptable_check_cbarg *arg = xarg;
406
407 if (type != 0)
408 return 0;
409 ent = pos;
410
411 if ((ent->cpu_flags & PROCENTRY_FLAG_EN) == 0)
412 return 0;
413 arg->cpu_count++;
414
415 if (ent->cpu_flags & PROCENTRY_FLAG_BP) {
416 if (arg->found_bsp) {
417 kprintf("more than one BSP in base MP table\n");
418 return EINVAL;
419 }
420 arg->found_bsp = 1;
421 }
422 return 0;
423 }
424
425 static int
426 mptable_check(vm_paddr_t mpfps_paddr)
427 {
428 struct mptable_pos mpt;
429 struct mptable_check_cbarg arg;
430 mpcth_t cth;
431 int error;
432
433 if (mpfps_paddr == 0)
434 return EOPNOTSUPP;
435
436 error = mptable_map(&mpt, mpfps_paddr);
437 if (error)
438 return error;
439
440 if (mpt.mp_fps->mpfb1 != 0)
441 goto done;
442
443 error = EINVAL;
444
445 cth = mpt.mp_cth;
446 if (cth == NULL)
447 goto done;
448 if (cth->apic_address == 0)
449 goto done;
450
451 bzero(&arg, sizeof(arg));
452 error = mptable_iterate_entries(cth, mptable_check_callback, &arg);
453 if (!error) {
454 if (arg.cpu_count == 0) {
455 kprintf("MP table contains no processor entries\n");
456 error = EINVAL;
457 } else if (!arg.found_bsp) {
458 kprintf("MP table does not contains BSP entry\n");
459 error = EINVAL;
460 }
461 }
462 done:
463 mptable_unmap(&mpt);
464 return error;
465 }
466
467 static int
468 mptable_iterate_entries(const mpcth_t cth, mptable_iter_func func, void *arg)
469 {
470 int count, total_size;
471 const void *position;
472
473 KKASSERT(cth->base_table_length >= sizeof(struct MPCTH));
474 total_size = cth->base_table_length - sizeof(struct MPCTH);
475 position = (const uint8_t *)cth + sizeof(struct MPCTH);
476 count = cth->entry_count;
477
478 while (count--) {
479 int type, error;
480
481 KKASSERT(total_size >= 0);
482 if (total_size == 0) {
483 kprintf("invalid base MP table, "
484 "entry count and length mismatch\n");
485 return EINVAL;
486 }
487
488 type = *(const uint8_t *)position;
489 switch (type) {
490 case 0: /* processor_entry */
491 case 1: /* bus_entry */
492 case 2: /* io_apic_entry */
493 case 3: /* int_entry */
494 case 4: /* int_entry */
495 break;
496 default:
497 kprintf("unknown base MP table entry type %d\n", type);
498 return EINVAL;
499 }
500
501 if (total_size < basetable_entry_types[type].length) {
502 kprintf("invalid base MP table length, "
503 "does not contain all entries\n");
504 return EINVAL;
505 }
506 total_size -= basetable_entry_types[type].length;
507
508 error = func(arg, position, type);
509 if (error)
510 return error;
511
512 position = (const uint8_t *)position +
513 basetable_entry_types[type].length;
514 }
515 return 0;
516 }
517
518
519 /*
520 * Startup the SMP processors.
521 */
522 void
523 mp_start(void)
524 {
525 POSTCODE(MP_START_POST);
526 mp_enable(boot_address);
527 }
528
529
530 /*
531 * Print various information about the SMP system hardware and setup.
532 */
533 void
534 mp_announce(void)
535 {
536 int x;
537
538 POSTCODE(MP_ANNOUNCE_POST);
539
540 kprintf("DragonFly/MP: Multiprocessor motherboard\n");
541 kprintf(" cpu0 (BSP): apic id: %2d", CPU_TO_ID(0));
542 kprintf(", version: 0x%08x", cpu_apic_versions[0]);
543 kprintf(", at 0x%08jx\n", (intmax_t)cpu_apic_address);
544 for (x = 1; x <= mp_naps; ++x) {
545 kprintf(" cpu%d (AP): apic id: %2d", x, CPU_TO_ID(x));
546 kprintf(", version: 0x%08x", cpu_apic_versions[x]);
547 kprintf(", at 0x%08jx\n", (intmax_t)cpu_apic_address);
548 }
549
550 #if defined(APIC_IO)
551 for (x = 0; x < mp_napics; ++x) {
552 kprintf(" io%d (APIC): apic id: %2d", x, IO_TO_ID(x));
553 kprintf(", version: 0x%08x", io_apic_versions[x]);
554 kprintf(", at 0x%08lx\n", io_apic_address[x]);
555 }
556 #else
557 kprintf(" Warning: APIC I/O disabled\n");
558 #endif /* APIC_IO */
559 }
560
561 /*
562 * AP cpu's call this to sync up protected mode.
563 *
564 * WARNING! %gs is not set up on entry. This routine sets up %gs.
565 */
566 void
567 init_secondary(void)
568 {
569 int gsel_tss;
570 int x, myid = bootAP;
571 u_int64_t msr, cr0;
572 struct mdglobaldata *md;
573 struct privatespace *ps;
574
575 ps = &CPU_prvspace[myid];
576
577 gdt_segs[GPROC0_SEL].ssd_base =
578 (long) &ps->mdglobaldata.gd_common_tss;
579 ps->mdglobaldata.mi.gd_prvspace = ps;
580
581 /* We fill the 32-bit segment descriptors */
582 for (x = 0; x < NGDT; x++) {
583 if (x != GPROC0_SEL && x != (GPROC0_SEL + 1))
584 ssdtosd(&gdt_segs[x], &gdt[myid * NGDT + x]);
585 }
586 /* And now a 64-bit one */
587 ssdtosyssd(&gdt_segs[GPROC0_SEL],
588 (struct system_segment_descriptor *)&gdt[myid * NGDT + GPROC0_SEL]);
589
590 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1;
591 r_gdt.rd_base = (long) &gdt[myid * NGDT];
592 lgdt(&r_gdt); /* does magic intra-segment return */
593
594 /* lgdt() destroys the GSBASE value, so we load GSBASE after lgdt() */
595 wrmsr(MSR_FSBASE, 0); /* User value */
596 wrmsr(MSR_GSBASE, (u_int64_t)ps);
597 wrmsr(MSR_KGSBASE, 0); /* XXX User value while we're in the kernel */
598
599 lidt(&r_idt);
600
601 #if 0
602 lldt(_default_ldt);
603 mdcpu->gd_currentldt = _default_ldt;
604 #endif
605
606 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL);
607 gdt[myid * NGDT + GPROC0_SEL].sd_type = SDT_SYSTSS;
608
609 md = mdcpu; /* loaded through %gs:0 (mdglobaldata.mi.gd_prvspace)*/
610
611 md->gd_common_tss.tss_rsp0 = 0; /* not used until after switch */
612 #if 0 /* JG XXX */
613 md->gd_common_tss.tss_ioopt = (sizeof md->gd_common_tss) << 16;
614 #endif
615 md->gd_tss_gdt = &gdt[myid * NGDT + GPROC0_SEL];
616 md->gd_common_tssd = *md->gd_tss_gdt;
617
618 /* double fault stack */
619 md->gd_common_tss.tss_ist1 =
620 (long)&md->mi.gd_prvspace->idlestack[
621 sizeof(md->mi.gd_prvspace->idlestack)];
622
623 ltr(gsel_tss);
624
625 /*
626 * Set to a known state:
627 * Set by mpboot.s: CR0_PG, CR0_PE
628 * Set by cpu_setregs: CR0_NE, CR0_MP, CR0_TS, CR0_WP, CR0_AM
629 */
630 cr0 = rcr0();
631 cr0 &= ~(CR0_CD | CR0_NW | CR0_EM);
632 load_cr0(cr0);
633
634 /* Set up the fast syscall stuff */
635 msr = rdmsr(MSR_EFER) | EFER_SCE;
636 wrmsr(MSR_EFER, msr);
637 wrmsr(MSR_LSTAR, (u_int64_t)IDTVEC(fast_syscall));
638 wrmsr(MSR_CSTAR, (u_int64_t)IDTVEC(fast_syscall32));
639 msr = ((u_int64_t)GSEL(GCODE_SEL, SEL_KPL) << 32) |
640 ((u_int64_t)GSEL(GUCODE32_SEL, SEL_UPL) << 48);
641 wrmsr(MSR_STAR, msr);
642 wrmsr(MSR_SF_MASK, PSL_NT|PSL_T|PSL_I|PSL_C|PSL_D);
643
644 pmap_set_opt(); /* PSE/4MB pages, etc */
645 #if JGXXX
646 /* Initialize the PAT MSR. */
647 pmap_init_pat();
648 #endif
649
650 /* set up CPU registers and state */
651 cpu_setregs();
652
653 /* set up SSE/NX registers */
654 initializecpu();
655
656 /* set up FPU state on the AP */
657 npxinit(__INITIAL_NPXCW__);
658
659 /* disable the APIC, just to be SURE */
660 lapic->svr &= ~APIC_SVR_ENABLE;
661
662 /* data returned to BSP */
663 cpu_apic_versions[0] = lapic->version;
664 }
665
666 /*******************************************************************
667 * local functions and data
668 */
669
670 /*
671 * start the SMP system
672 */
673 static void
674 mp_enable(u_int boot_addr)
675 {
676 int x;
677 #if defined(APIC_IO)
678 int apic;
679 u_int ux;
680 #endif /* APIC_IO */
681 vm_paddr_t mpfps_paddr;
682
683 POSTCODE(MP_ENABLE_POST);
684
685 if (madt_probe_test) {
686 mpfps_paddr = 0;
687 } else {
688 mpfps_paddr = mptable_probe();
689 if (mptable_check(mpfps_paddr))
690 mpfps_paddr = 0;
691 }
692
693 if (mpfps_paddr) {
694 struct mptable_pos mpt;
695
696 mptable_map(&mpt, mpfps_paddr);
697
698 /*
699 * We can safely map physical memory into SMPpt after
700 * mptable_pass1() completes.
701 */
702 mptable_pass1(&mpt);
703
704 if (cpu_apic_address == 0)
705 panic("mp_enable: no local apic!\n");
706
707 /* examine the MP table for needed info */
708 x = mptable_pass2(&mpt);
709
710 mptable_unmap(&mpt);
711
712 /*
713 * can't process default configs till the
714 * CPU APIC is pmapped
715 */
716 if (x)
717 mptable_default(x);
718
719 /* post scan cleanup */
720 mptable_fix();
721
722 /*
723 * lapic not mapped yet (pmap_init is called too late)
724 */
725 lapic = pmap_mapdev_uncacheable(cpu_apic_address,
726 sizeof(struct LAPIC));
727 } else {
728 vm_paddr_t madt_paddr;
729 int bsp_apic_id;
730
731 madt_paddr = madt_probe();
732 if (madt_paddr == 0)
733 panic("mp_enable: madt_probe failed\n");
734
735 cpu_apic_address = madt_pass1(madt_paddr);
736 if (cpu_apic_address == 0)
737 panic("mp_enable: no local apic (madt)!\n");
738
739 /*
740 * lapic not mapped yet (pmap_init is called too late)
741 *
742 * XXX: where is the best place to set lapic?
743 */
744 lapic = pmap_mapdev_uncacheable(cpu_apic_address,
745 sizeof(struct LAPIC));
746
747 bsp_apic_id = (lapic->id & 0xff000000) >> 24;
748 if (madt_pass2(madt_paddr, bsp_apic_id))
749 panic("mp_enable: madt_pass2 failed\n");
750 }
751
752 #if defined(APIC_IO)
753
754 setup_apic_irq_mapping();
755
756 /* fill the LOGICAL io_apic_versions table */
757 for (apic = 0; apic < mp_napics; ++apic) {
758 ux = io_apic_read(apic, IOAPIC_VER);
759 io_apic_versions[apic] = ux;
760 io_apic_set_id(apic, IO_TO_ID(apic));
761 }
762
763 /* program each IO APIC in the system */
764 for (apic = 0; apic < mp_napics; ++apic)
765 if (io_apic_setup(apic) < 0)
766 panic("IO APIC setup failure");
767
768 #endif /* APIC_IO */
769
770 /*
771 * These are required for SMP operation
772 */
773
774 /* install a 'Spurious INTerrupt' vector */
775 setidt(XSPURIOUSINT_OFFSET, Xspuriousint,
776 SDT_SYSIGT, SEL_KPL, 0);
777
778 /* install an inter-CPU IPI for TLB invalidation */
779 setidt(XINVLTLB_OFFSET, Xinvltlb,
780 SDT_SYSIGT, SEL_KPL, 0);
781
782 /* install an inter-CPU IPI for IPIQ messaging */
783 setidt(XIPIQ_OFFSET, Xipiq,
784 SDT_SYSIGT, SEL_KPL, 0);
785
786 /* install a timer vector */
787 setidt(XTIMER_OFFSET, Xtimer,
788 SDT_SYSIGT, SEL_KPL, 0);
789
790 /* install an inter-CPU IPI for CPU stop/restart */
791 setidt(XCPUSTOP_OFFSET, Xcpustop,
792 SDT_SYSIGT, SEL_KPL, 0);
793
794 /* start each Application Processor */
795 start_all_aps(boot_addr);
796 }
797
798
799 /*
800 * look for the MP spec signature
801 */
802
803 /* string defined by the Intel MP Spec as identifying the MP table */
804 #define MP_SIG 0x5f504d5f /* _MP_ */
805 #define NEXT(X) ((X) += 4)
806 static long
807 mptable_search_sig(u_int32_t target, int count)
808 {
809 vm_size_t map_size;
810 u_int32_t *addr;
811 int x, ret;
812
813 KKASSERT(target != 0);
814
815 map_size = count * sizeof(u_int32_t);
816 addr = pmap_mapdev((vm_paddr_t)target, map_size);
817
818 ret = 0;
819 for (x = 0; x < count; NEXT(x)) {
820 if (addr[x] == MP_SIG) {
821 /* make array index a byte index */
822 ret = target + (x * sizeof(u_int32_t));
823 break;
824 }
825 }
826
827 pmap_unmapdev((vm_offset_t)addr, map_size);
828 return ret;
829 }
830
831
832 typedef struct BUSDATA {
833 u_char bus_id;
834 enum busTypes bus_type;
835 } bus_datum;
836
837 typedef struct INTDATA {
838 u_char int_type;
839 u_short int_flags;
840 u_char src_bus_id;
841 u_char src_bus_irq;
842 u_char dst_apic_id;
843 u_char dst_apic_int;
844 u_char int_vector;
845 } io_int, local_int;
846
847 typedef struct BUSTYPENAME {
848 u_char type;
849 char name[7];
850 } bus_type_name;
851
852 #ifdef APIC_IO
853
854 static bus_type_name bus_type_table[] =
855 {
856 {CBUS, "CBUS"},
857 {CBUSII, "CBUSII"},
858 {EISA, "EISA"},
859 {MCA, "MCA"},
860 {UNKNOWN_BUSTYPE, "---"},
861 {ISA, "ISA"},
862 {MCA, "MCA"},
863 {UNKNOWN_BUSTYPE, "---"},
864 {UNKNOWN_BUSTYPE, "---"},
865 {UNKNOWN_BUSTYPE, "---"},
866 {UNKNOWN_BUSTYPE, "---"},
867 {UNKNOWN_BUSTYPE, "---"},
868 {PCI, "PCI"},
869 {UNKNOWN_BUSTYPE, "---"},
870 {UNKNOWN_BUSTYPE, "---"},
871 {UNKNOWN_BUSTYPE, "---"},
872 {UNKNOWN_BUSTYPE, "---"},
873 {XPRESS, "XPRESS"},
874 {UNKNOWN_BUSTYPE, "---"}
875 };
876
877 /* from MP spec v1.4, table 5-1 */
878 static int default_data[7][5] =
879 {
880 /* nbus, id0, type0, id1, type1 */
881 {1, 0, ISA, 255, 255},
882 {1, 0, EISA, 255, 255},
883 {1, 0, EISA, 255, 255},
884 {1, 0, MCA, 255, 255},
885 {2, 0, ISA, 1, PCI},
886 {2, 0, EISA, 1, PCI},
887 {2, 0, MCA, 1, PCI}
888 };
889
890 /* the bus data */
891 static bus_datum *bus_data;
892
893 /* the IO INT data, one entry per possible APIC INTerrupt */
894 static io_int *io_apic_ints;
895 static int nintrs;
896
897 #endif
898
899 static int processor_entry (proc_entry_ptr entry, int cpu);
900 #ifdef APIC_IO
901 static int bus_entry (bus_entry_ptr entry, int bus);
902 static int io_apic_entry (io_apic_entry_ptr entry, int apic);
903 static int int_entry (int_entry_ptr entry, int intr);
904 static int lookup_bus_type (char *name);
905 #endif
906
907
908 /*
909 * 1st pass on motherboard's Intel MP specification table.
910 *
911 * determines:
912 * cpu_apic_address (common to all CPUs)
913 * io_apic_address[N]
914 * mp_naps
915 * mp_nbusses
916 * mp_napics
917 * nintrs
918 * need_hyperthreading_fixup
919 * logical_cpus
920 */
921 static void
922 mptable_pass1(struct mptable_pos *mpt)
923 {
924 #ifdef APIC_IO
925 int x;
926 #endif
927 mpfps_t fps;
928 mpcth_t cth;
929 int totalSize;
930 void* position;
931 int count;
932 int type;
933 u_int id_mask;
934
935 POSTCODE(MPTABLE_PASS1_POST);
936
937 fps = mpt->mp_fps;
938 KKASSERT(fps != NULL);
939
940 #ifdef APIC_IO
941 /* clear various tables */
942 for (x = 0; x < NAPICID; ++x) {
943 io_apic_address[x] = ~0; /* IO APIC address table */
944 }
945 #endif
946
947 /* init everything to empty */
948 mp_naps = 0;
949 #ifdef APIC_IO
950 mp_nbusses = 0;
951 mp_napics = 0;
952 nintrs = 0;
953 #endif
954 id_mask = 0;
955
956 /* check for use of 'default' configuration */
957 if (fps->mpfb1 != 0) {
958 /* use default addresses */
959 cpu_apic_address = DEFAULT_APIC_BASE;
960 #ifdef APIC_IO
961 io_apic_address[0] = DEFAULT_IO_APIC_BASE;
962 #endif
963
964 /* fill in with defaults */
965 mp_naps = 2; /* includes BSP */
966 #if defined(APIC_IO)
967 mp_nbusses = default_data[fps->mpfb1 - 1][0];
968 mp_napics = 1;
969 nintrs = 16;
970 #endif /* APIC_IO */
971 }
972 else {
973 cth = mpt->mp_cth;
974 if (cth == NULL)
975 panic("MP Configuration Table Header MISSING!");
976
977 cpu_apic_address = (vm_offset_t) cth->apic_address;
978
979 /* walk the table, recording info of interest */
980 totalSize = cth->base_table_length - sizeof(struct MPCTH);
981 position = (u_char *) cth + sizeof(struct MPCTH);
982 count = cth->entry_count;
983
984 while (count--) {
985 switch (type = *(u_char *) position) {
986 case 0: /* processor_entry */
987 if (((proc_entry_ptr)position)->cpu_flags
988 & PROCENTRY_FLAG_EN) {
989 ++mp_naps;
990 id_mask |= 1 <<
991 ((proc_entry_ptr)position)->apic_id;
992 }
993 break;
994 case 1: /* bus_entry */
995 #ifdef APIC_IO
996 ++mp_nbusses;
997 #endif
998 break;
999 case 2: /* io_apic_entry */
1000 #ifdef APIC_IO
1001 if (((io_apic_entry_ptr)position)->apic_flags
1002 & IOAPICENTRY_FLAG_EN)
1003 io_apic_address[mp_napics++] =
1004 (vm_offset_t)((io_apic_entry_ptr)
1005 position)->apic_address;
1006 #endif
1007 break;
1008 case 3: /* int_entry */
1009 #ifdef APIC_IO
1010 ++nintrs;
1011 #endif
1012 break;
1013 case 4: /* int_entry */
1014 break;
1015 default:
1016 panic("mpfps Base Table HOSED!");
1017 /* NOTREACHED */
1018 }
1019
1020 totalSize -= basetable_entry_types[type].length;
1021 position = (uint8_t *)position +
1022 basetable_entry_types[type].length;
1023 }
1024 }
1025
1026 /* qualify the numbers */
1027 if (mp_naps > MAXCPU) {
1028 kprintf("Warning: only using %d of %d available CPUs!\n",
1029 MAXCPU, mp_naps);
1030 mp_naps = MAXCPU;
1031 }
1032
1033 /* See if we need to fixup HT logical CPUs. */
1034 mptable_hyperthread_fixup(id_mask);
1035
1036 --mp_naps; /* subtract the BSP */
1037 }
1038
1039
1040 /*
1041 * 2nd pass on motherboard's Intel MP specification table.
1042 *
1043 * sets:
1044 * logical_cpus_mask
1045 * ID_TO_IO(N), phy APIC ID to log CPU/IO table
1046 * CPU_TO_ID(N), logical CPU to APIC ID table
1047 * IO_TO_ID(N), logical IO to APIC ID table
1048 * bus_data[N]
1049 * io_apic_ints[N]
1050 */
1051 static int
1052 mptable_pass2(struct mptable_pos *mpt)
1053 {
1054 struct PROCENTRY proc;
1055 int x;
1056 mpfps_t fps;
1057 mpcth_t cth;
1058 int totalSize;
1059 void* position;
1060 int count;
1061 int type;
1062 int apic, bus, cpu, intr;
1063 int i;
1064
1065 POSTCODE(MPTABLE_PASS2_POST);
1066
1067 fps = mpt->mp_fps;
1068 KKASSERT(fps != NULL);
1069
1070 /* Initialize fake proc entry for use with HT fixup. */
1071 bzero(&proc, sizeof(proc));
1072 proc.type = 0;
1073 proc.cpu_flags = PROCENTRY_FLAG_EN;
1074
1075 #ifdef APIC_IO
1076 MALLOC(io_apic_versions, u_int32_t *, sizeof(u_int32_t) * mp_napics,
1077 M_DEVBUF, M_WAITOK);
1078 MALLOC(ioapic, volatile ioapic_t **, sizeof(ioapic_t *) * mp_napics,
1079 M_DEVBUF, M_WAITOK | M_ZERO);
1080 MALLOC(io_apic_ints, io_int *, sizeof(io_int) * (nintrs + FIXUP_EXTRA_APIC_INTS),
1081 M_DEVBUF, M_WAITOK);
1082 MALLOC(bus_data, bus_datum *, sizeof(bus_datum) * mp_nbusses,
1083 M_DEVBUF, M_WAITOK);
1084 #endif
1085
1086 #ifdef APIC_IO
1087 for (i = 0; i < mp_napics; i++) {
1088 ioapic[i] = permanent_io_mapping(io_apic_address[i]);
1089 }
1090 #endif
1091
1092 /* clear various tables */
1093 for (x = 0; x < NAPICID; ++x) {
1094 CPU_TO_ID(x) = -1; /* logical CPU to APIC ID table */
1095 #ifdef APIC_IO
1096 ID_TO_IO(x) = -1; /* phy APIC ID to log CPU/IO table */
1097 IO_TO_ID(x) = -1; /* logical IO to APIC ID table */
1098 #endif
1099 }
1100
1101 #ifdef APIC_IO
1102 /* clear bus data table */
1103 for (x = 0; x < mp_nbusses; ++x)
1104 bus_data[x].bus_id = 0xff;
1105
1106 /* clear IO APIC INT table */
1107 for (x = 0; x < (nintrs + 1); ++x) {
1108 io_apic_ints[x].int_type = 0xff;
1109 io_apic_ints[x].int_vector = 0xff;
1110 }
1111 #endif
1112
1113 /* record whether PIC or virtual-wire mode */
1114 machintr_setvar_simple(MACHINTR_VAR_IMCR_PRESENT, fps->mpfb2 & 0x80);
1115
1116 /* check for use of 'default' configuration */
1117 if (fps->mpfb1 != 0)
1118 return fps->mpfb1; /* return default configuration type */
1119
1120 cth = mpt->mp_cth;
1121 if (cth == NULL)
1122 panic("MP Configuration Table Header MISSING!");
1123
1124 /* walk the table, recording info of interest */
1125 totalSize = cth->base_table_length - sizeof(struct MPCTH);
1126 position = (u_char *) cth + sizeof(struct MPCTH);
1127 count = cth->entry_count;
1128 apic = bus = intr = 0;
1129 cpu = 1; /* pre-count the BSP */
1130
1131 while (count--) {
1132 switch (type = *(u_char *) position) {
1133 case 0:
1134 if (processor_entry(position, cpu))
1135 ++cpu;
1136
1137 if (need_hyperthreading_fixup) {
1138 /*
1139 * Create fake mptable processor entries
1140 * and feed them to processor_entry() to
1141 * enumerate the logical CPUs.
1142 */
1143 proc.apic_id = ((proc_entry_ptr)position)->apic_id;
1144 for (i = 1; i < logical_cpus; i++) {
1145 proc.apic_id++;
1146 processor_entry(&proc, cpu);
1147 logical_cpus_mask |= (1 << cpu);
1148 cpu++;
1149 }
1150 }
1151 break;
1152 case 1:
1153 #ifdef APIC_IO
1154 if (bus_entry(position, bus))
1155 ++bus;
1156 #endif
1157 break;
1158 case 2:
1159 #ifdef APIC_IO
1160 if (io_apic_entry(position, apic))
1161 ++apic;
1162 #endif
1163 break;
1164 case 3:
1165 #ifdef APIC_IO
1166 if (int_entry(position, intr))
1167 ++intr;
1168 #endif
1169 break;
1170 case 4:
1171 /* int_entry(position); */
1172 break;
1173 default:
1174 panic("mpfps Base Table HOSED!");
1175 /* NOTREACHED */
1176 }
1177
1178 totalSize -= basetable_entry_types[type].length;
1179 position = (uint8_t *)position + basetable_entry_types[type].length;
1180 }
1181
1182 if (CPU_TO_ID(0) < 0)
1183 panic("NO BSP found!");
1184
1185 /* report fact that its NOT a default configuration */
1186 return 0;
1187 }
1188
1189
1190 /*
1191 * Check if we should perform a hyperthreading "fix-up" to
1192 * enumerate any logical CPU's that aren't already listed
1193 * in the table.
1194 *
1195 * XXX: We assume that all of the physical CPUs in the
1196 * system have the same number of logical CPUs.
1197 *
1198 * XXX: We assume that APIC ID's are allocated such that
1199 * the APIC ID's for a physical processor are aligned
1200 * with the number of logical CPU's in the processor.
1201 */
1202 static void
1203 mptable_hyperthread_fixup(u_int id_mask)
1204 {
1205 int i, id, lcpus_max;
1206
1207 if ((cpu_feature & CPUID_HTT) == 0)
1208 return;
1209
1210 lcpus_max = (cpu_procinfo & CPUID_HTT_CORES) >> 16;
1211 if (lcpus_max <= 1)
1212 return;
1213
1214 if (strcmp(cpu_vendor, "GenuineIntel") == 0) {
1215 /*
1216 * INSTRUCTION SET REFERENCE, A-M (#253666)
1217 * Page 3-181, Table 3-20
1218 * "The nearest power-of-2 integer that is not smaller
1219 * than EBX[23:16] is the number of unique initial APIC
1220 * IDs reserved for addressing different logical
1221 * processors in a physical package."
1222 */
1223 for (i = 0; ; ++i) {
1224 if ((1 << i) >= lcpus_max) {
1225 lcpus_max = 1 << i;
1226 break;
1227 }
1228 }
1229 }
1230
1231 if (mp_naps == lcpus_max) {
1232 /* We have nothing to fix */
1233 return;
1234 } else if (mp_naps == 1) {
1235 /* XXX this may be incorrect */
1236 logical_cpus = lcpus_max;
1237 } else {
1238 int cur, prev, dist;
1239
1240 /*
1241 * Calculate the distances between two nearest
1242 * APIC IDs. If all such distances are same,
1243 * then it is the number of missing cpus that
1244 * we are going to fill later.
1245 */
1246 dist = cur = prev = -1;
1247 for (id = 0; id < MAXCPU; ++id) {
1248 if ((id_mask & 1 << id) == 0)
1249 continue;
1250
1251 cur = id;
1252 if (prev >= 0) {
1253 int new_dist = cur - prev;
1254
1255 if (dist < 0)
1256 dist = new_dist;
1257
1258 /*
1259 * Make sure that all distances
1260 * between two nearest APIC IDs
1261 * are same.
1262 */
1263 if (dist != new_dist)
1264 return;
1265 }
1266 prev = cur;
1267 }
1268 if (dist == 1)
1269 return;
1270
1271 /* Must be power of 2 */
1272 if (dist & (dist - 1))
1273 return;
1274
1275 /* Can't exceed CPU package capacity */
1276 if (dist > lcpus_max)
1277 logical_cpus = lcpus_max;
1278 else
1279 logical_cpus = dist;
1280 }
1281
1282 /*
1283 * For each APIC ID of a CPU that is set in the mask,
1284 * scan the other candidate APIC ID's for this
1285 * physical processor. If any of those ID's are
1286 * already in the table, then kill the fixup.
1287 */
1288 for (id = 0; id < MAXCPU; id++) {
1289 if ((id_mask & 1 << id) == 0)
1290 continue;
1291 /* First, make sure we are on a logical_cpus boundary. */
1292 if (id % logical_cpus != 0)
1293 return;
1294 for (i = id + 1; i < id + logical_cpus; i++)
1295 if ((id_mask & 1 << i) != 0)
1296 return;
1297 }
1298
1299 /*
1300 * Ok, the ID's checked out, so enable the fixup. We have to fixup
1301 * mp_naps right now.
1302 */
1303 need_hyperthreading_fixup = 1;
1304 mp_naps *= logical_cpus;
1305 }
1306
1307 static int
1308 mptable_map(struct mptable_pos *mpt, vm_paddr_t mpfps_paddr)
1309 {
1310 mpfps_t fps = NULL;
1311 mpcth_t cth = NULL;
1312 vm_size_t cth_mapsz = 0;
1313
1314 bzero(mpt, sizeof(*mpt));
1315
1316 fps = pmap_mapdev(mpfps_paddr, sizeof(*fps));
1317 if (fps->pap != 0) {
1318 /*
1319 * Map configuration table header to get
1320 * the base table size
1321 */
1322 cth = pmap_mapdev(fps->pap, sizeof(*cth));
1323 cth_mapsz = cth->base_table_length;
1324 pmap_unmapdev((vm_offset_t)cth, sizeof(*cth));
1325
1326 if (cth_mapsz < sizeof(*cth)) {
1327 kprintf("invalid base MP table length %d\n",
1328 (int)cth_mapsz);
1329 pmap_unmapdev((vm_offset_t)fps, sizeof(*fps));
1330 return EINVAL;
1331 }
1332
1333 /*
1334 * Map the base table
1335 */
1336 cth = pmap_mapdev(fps->pap, cth_mapsz);
1337 }
1338
1339 mpt->mp_fps = fps;
1340 mpt->mp_cth = cth;
1341 mpt->mp_cth_mapsz = cth_mapsz;
1342
1343 return 0;
1344 }
1345
1346 static void
1347 mptable_unmap(struct mptable_pos *mpt)
1348 {
1349 if (mpt->mp_cth != NULL) {
1350 pmap_unmapdev((vm_offset_t)mpt->mp_cth, mpt->mp_cth_mapsz);
1351 mpt->mp_cth = NULL;
1352 mpt->mp_cth_mapsz = 0;
1353 }
1354 if (mpt->mp_fps != NULL) {
1355 pmap_unmapdev((vm_offset_t)mpt->mp_fps, sizeof(*mpt->mp_fps));
1356 mpt->mp_fps = NULL;
1357 }
1358 }
1359
1360 #ifdef APIC_IO
1361
1362 void
1363 assign_apic_irq(int apic, int intpin, int irq)
1364 {
1365 int x;
1366
1367 if (int_to_apicintpin[irq].ioapic != -1)
1368 panic("assign_apic_irq: inconsistent table");
1369
1370 int_to_apicintpin[irq].ioapic = apic;
1371 int_to_apicintpin[irq].int_pin = intpin;
1372 int_to_apicintpin[irq].apic_address = ioapic[apic];
1373 int_to_apicintpin[irq].redirindex = IOAPIC_REDTBL + 2 * intpin;
1374
1375 for (x = 0; x < nintrs; x++) {
1376 if ((io_apic_ints[x].int_type == 0 ||
1377 io_apic_ints[x].int_type == 3) &&
1378 io_apic_ints[x].int_vector == 0xff &&
1379 io_apic_ints[x].dst_apic_id == IO_TO_ID(apic) &&
1380 io_apic_ints[x].dst_apic_int == intpin)
1381 io_apic_ints[x].int_vector = irq;
1382 }
1383 }
1384
1385 void
1386 revoke_apic_irq(int irq)
1387 {
1388 int x;
1389 int oldapic;
1390 int oldintpin;
1391
1392 if (int_to_apicintpin[irq].ioapic == -1)
1393 panic("revoke_apic_irq: inconsistent table");
1394
1395 oldapic = int_to_apicintpin[irq].ioapic;
1396 oldintpin = int_to_apicintpin[irq].int_pin;
1397
1398 int_to_apicintpin[irq].ioapic = -1;
1399 int_to_apicintpin[irq].int_pin = 0;
1400 int_to_apicintpin[irq].apic_address = NULL;
1401 int_to_apicintpin[irq].redirindex = 0;
1402
1403 for (x = 0; x < nintrs; x++) {
1404 if ((io_apic_ints[x].int_type == 0 ||
1405 io_apic_ints[x].int_type == 3) &&
1406 io_apic_ints[x].int_vector != 0xff &&
1407 io_apic_ints[x].dst_apic_id == IO_TO_ID(oldapic) &&
1408 io_apic_ints[x].dst_apic_int == oldintpin)
1409 io_apic_ints[x].int_vector = 0xff;
1410 }
1411 }
1412
1413 /*
1414 * Allocate an IRQ
1415 */
1416 static void
1417 allocate_apic_irq(int intr)
1418 {
1419 int apic;
1420 int intpin;
1421 int irq;
1422
1423 if (io_apic_ints[intr].int_vector != 0xff)
1424 return; /* Interrupt handler already assigned */
1425
1426 if (io_apic_ints[intr].int_type != 0 &&
1427 (io_apic_ints[intr].int_type != 3 ||
1428 (io_apic_ints[intr].dst_apic_id == IO_TO_ID(0) &&
1429 io_apic_ints[intr].dst_apic_int == 0)))
1430 return; /* Not INT or ExtInt on != (0, 0) */
1431
1432 irq = 0;
1433 while (irq < APIC_INTMAPSIZE &&
1434 int_to_apicintpin[irq].ioapic != -1)
1435 irq++;
1436
1437 if (irq >= APIC_INTMAPSIZE)
1438 return; /* No free interrupt handlers */
1439
1440 apic = ID_TO_IO(io_apic_ints[intr].dst_apic_id);
1441 intpin = io_apic_ints[intr].dst_apic_int;
1442
1443 assign_apic_irq(apic, intpin, irq);
1444 }
1445
1446
1447 static void
1448 swap_apic_id(int apic, int oldid, int newid)
1449 {
1450 int x;
1451 int oapic;
1452
1453
1454 if (oldid == newid)
1455 return; /* Nothing to do */
1456
1457 kprintf("Changing APIC ID for IO APIC #%d from %d to %d in MP table\n",
1458 apic, oldid, newid);
1459
1460 /* Swap physical APIC IDs in interrupt entries */
1461 for (x = 0; x < nintrs; x++) {
1462 if (io_apic_ints[x].dst_apic_id == oldid)
1463 io_apic_ints[x].dst_apic_id = newid;
1464 else if (io_apic_ints[x].dst_apic_id == newid)
1465 io_apic_ints[x].dst_apic_id = oldid;
1466 }
1467
1468 /* Swap physical APIC IDs in IO_TO_ID mappings */
1469 for (oapic = 0; oapic < mp_napics; oapic++)
1470 if (IO_TO_ID(oapic) == newid)
1471 break;
1472
1473 if (oapic < mp_napics) {
1474 kprintf("Changing APIC ID for IO APIC #%d from "
1475 "%d to %d in MP table\n",
1476 oapic, newid, oldid);
1477 IO_TO_ID(oapic) = oldid;
1478 }
1479 IO_TO_ID(apic) = newid;
1480 }
1481
1482
1483 static void
1484 fix_id_to_io_mapping(void)
1485 {
1486 int x;
1487
1488 for (x = 0; x < NAPICID; x++)
1489 ID_TO_IO(x) = -1;
1490
1491 for (x = 0; x <= mp_naps; x++)
1492 if (CPU_TO_ID(x) < NAPICID)
1493 ID_TO_IO(CPU_TO_ID(x)) = x;
1494
1495 for (x = 0; x < mp_napics; x++)
1496 if (IO_TO_ID(x) < NAPICID)
1497 ID_TO_IO(IO_TO_ID(x)) = x;
1498 }
1499
1500
1501 static int
1502 first_free_apic_id(void)
1503 {
1504 int freeid, x;
1505
1506 for (freeid = 0; freeid < NAPICID; freeid++) {
1507 for (x = 0; x <= mp_naps; x++)
1508 if (CPU_TO_ID(x) == freeid)
1509 break;
1510 if (x <= mp_naps)
1511 continue;
1512 for (x = 0; x < mp_napics; x++)
1513 if (IO_TO_ID(x) == freeid)
1514 break;
1515 if (x < mp_napics)
1516 continue;
1517 return freeid;
1518 }
1519 return freeid;
1520 }
1521
1522
1523 static int
1524 io_apic_id_acceptable(int apic, int id)
1525 {
1526 int cpu; /* Logical CPU number */
1527 int oapic; /* Logical IO APIC number for other IO APIC */
1528
1529 if (id >= NAPICID)
1530 return 0; /* Out of range */
1531
1532 for (cpu = 0; cpu <= mp_naps; cpu++)
1533 if (CPU_TO_ID(cpu) == id)
1534 return 0; /* Conflict with CPU */
1535
1536 for (oapic = 0; oapic < mp_napics && oapic < apic; oapic++)
1537 if (IO_TO_ID(oapic) == id)
1538 return 0; /* Conflict with other APIC */
1539
1540 return 1; /* ID is acceptable for IO APIC */
1541 }
1542
1543 static
1544 io_int *
1545 io_apic_find_int_entry(int apic, int pin)
1546 {
1547 int x;
1548
1549 /* search each of the possible INTerrupt sources */
1550 for (x = 0; x < nintrs; ++x) {
1551 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1552 (pin == io_apic_ints[x].dst_apic_int))
1553 return (&io_apic_ints[x]);
1554 }
1555 return NULL;
1556 }
1557
1558 #endif
1559
1560 /*
1561 * parse an Intel MP specification table
1562 */
1563 static void
1564 mptable_fix(void)
1565 {
1566 #ifdef APIC_IO
1567 int x;
1568 int id;
1569 int apic; /* IO APIC unit number */
1570 int freeid; /* Free physical APIC ID */
1571 int physid; /* Current physical IO APIC ID */
1572 io_int *io14;
1573 int bus_0 = 0; /* Stop GCC warning */
1574 int bus_pci = 0; /* Stop GCC warning */
1575 int num_pci_bus;
1576
1577 /*
1578 * Fix mis-numbering of the PCI bus and its INT entries if the BIOS
1579 * did it wrong. The MP spec says that when more than 1 PCI bus
1580 * exists the BIOS must begin with bus entries for the PCI bus and use
1581 * actual PCI bus numbering. This implies that when only 1 PCI bus
1582 * exists the BIOS can choose to ignore this ordering, and indeed many
1583 * MP motherboards do ignore it. This causes a problem when the PCI
1584 * sub-system makes requests of the MP sub-system based on PCI bus
1585 * numbers. So here we look for the situation and renumber the
1586 * busses and associated INTs in an effort to "make it right".
1587 */
1588
1589 /* find bus 0, PCI bus, count the number of PCI busses */
1590 for (num_pci_bus = 0, x = 0; x < mp_nbusses; ++x) {
1591 if (bus_data[x].bus_id == 0) {
1592 bus_0 = x;
1593 }
1594 if (bus_data[x].bus_type == PCI) {
1595 ++num_pci_bus;
1596 bus_pci = x;
1597 }
1598 }
1599 /*
1600 * bus_0 == slot of bus with ID of 0
1601 * bus_pci == slot of last PCI bus encountered
1602 */
1603
1604 /* check the 1 PCI bus case for sanity */
1605 /* if it is number 0 all is well */
1606 if (num_pci_bus == 1 &&
1607 bus_data[bus_pci].bus_id != 0) {
1608
1609 /* mis-numbered, swap with whichever bus uses slot 0 */
1610
1611 /* swap the bus entry types */
1612 bus_data[bus_pci].bus_type = bus_data[bus_0].bus_type;
1613 bus_data[bus_0].bus_type = PCI;
1614
1615 /* swap each relavant INTerrupt entry */
1616 id = bus_data[bus_pci].bus_id;
1617 for (x = 0; x < nintrs; ++x) {
1618 if (io_apic_ints[x].src_bus_id == id) {
1619 io_apic_ints[x].src_bus_id = 0;
1620 }
1621 else if (io_apic_ints[x].src_bus_id == 0) {
1622 io_apic_ints[x].src_bus_id = id;
1623 }
1624 }
1625 }
1626
1627 /* Assign IO APIC IDs.
1628 *
1629 * First try the existing ID. If a conflict is detected, try
1630 * the ID in the MP table. If a conflict is still detected, find
1631 * a free id.
1632 *
1633 * We cannot use the ID_TO_IO table before all conflicts has been
1634 * resolved and the table has been corrected.
1635 */
1636 for (apic = 0; apic < mp_napics; ++apic) { /* For all IO APICs */
1637
1638 /* First try to use the value set by the BIOS */
1639 physid = io_apic_get_id(apic);
1640 if (io_apic_id_acceptable(apic, physid)) {
1641 if (IO_TO_ID(apic) != physid)
1642 swap_apic_id(apic, IO_TO_ID(apic), physid);
1643 continue;
1644 }
1645
1646 /* Then check if the value in the MP table is acceptable */
1647 if (io_apic_id_acceptable(apic, IO_TO_ID(apic)))
1648 continue;
1649
1650 /* Last resort, find a free APIC ID and use it */
1651 freeid = first_free_apic_id();
1652 if (freeid >= NAPICID)
1653 panic("No free physical APIC IDs found");
1654
1655 if (io_apic_id_acceptable(apic, freeid)) {
1656 swap_apic_id(apic, IO_TO_ID(apic), freeid);
1657 continue;
1658 }
1659 panic("Free physical APIC ID not usable");
1660 }
1661 fix_id_to_io_mapping();
1662
1663 /* detect and fix broken Compaq MP table */
1664 if (apic_int_type(0, 0) == -1) {
1665 kprintf("APIC_IO: MP table broken: 8259->APIC entry missing!\n");
1666 io_apic_ints[nintrs].int_type = 3; /* ExtInt */
1667 io_apic_ints[nintrs].int_vector = 0xff; /* Unassigned */
1668 /* XXX fixme, set src bus id etc, but it doesn't seem to hurt */
1669 io_apic_ints[nintrs].dst_apic_id = IO_TO_ID(0);
1670 io_apic_ints[nintrs].dst_apic_int = 0; /* Pin 0 */
1671 nintrs++;
1672 } else if (apic_int_type(0, 0) == 0) {
1673 kprintf("APIC_IO: MP table broken: ExtINT entry corrupt!\n");
1674 for (x = 0; x < nintrs; ++x)
1675 if ((0 == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1676 (0 == io_apic_ints[x].dst_apic_int)) {
1677 io_apic_ints[x].int_type = 3;
1678 io_apic_ints[x].int_vector = 0xff;
1679 break;
1680 }
1681 }
1682
1683 /*
1684 * Fix missing IRQ 15 when IRQ 14 is an ISA interrupt. IDE
1685 * controllers universally come in pairs. If IRQ 14 is specified
1686 * as an ISA interrupt, then IRQ 15 had better be too.
1687 *
1688 * [ Shuttle XPC / AMD Athlon X2 ]
1689 * The MPTable is missing an entry for IRQ 15. Note that the
1690 * ACPI table has an entry for both 14 and 15.
1691 */
1692 if (apic_int_type(0, 14) == 0 && apic_int_type(0, 15) == -1) {
1693 kprintf("APIC_IO: MP table broken: IRQ 15 not ISA when IRQ 14 is!\n");
1694 io14 = io_apic_find_int_entry(0, 14);
1695 io_apic_ints[nintrs] = *io14;
1696 io_apic_ints[nintrs].src_bus_irq = 15;
1697 io_apic_ints[nintrs].dst_apic_int = 15;
1698 nintrs++;
1699 }
1700 #endif
1701 }
1702
1703 #ifdef APIC_IO
1704
1705 /* Assign low level interrupt handlers */
1706 static void
1707 setup_apic_irq_mapping(void)
1708 {
1709 int x;
1710 int int_vector;
1711
1712 /* Clear array */
1713 for (x = 0; x < APIC_INTMAPSIZE; x++) {
1714 int_to_apicintpin[x].ioapic = -1;
1715 int_to_apicintpin[x].int_pin = 0;
1716 int_to_apicintpin[x].apic_address = NULL;
1717 int_to_apicintpin[x].redirindex = 0;
1718 }
1719
1720 /* First assign ISA/EISA interrupts */
1721 for (x = 0; x < nintrs; x++) {
1722 int_vector = io_apic_ints[x].src_bus_irq;
1723 if (int_vector < APIC_INTMAPSIZE &&
1724 io_apic_ints[x].int_vector == 0xff &&
1725 int_to_apicintpin[int_vector].ioapic == -1 &&
1726 (apic_int_is_bus_type(x, ISA) ||
1727 apic_int_is_bus_type(x, EISA)) &&
1728 io_apic_ints[x].int_type == 0) {
1729 assign_apic_irq(ID_TO_IO(io_apic_ints[x].dst_apic_id),
1730 io_apic_ints[x].dst_apic_int,
1731 int_vector);
1732 }
1733 }
1734
1735 /* Assign ExtInt entry if no ISA/EISA interrupt 0 entry */
1736 for (x = 0; x < nintrs; x++) {
1737 if (io_apic_ints[x].dst_apic_int == 0 &&
1738 io_apic_ints[x].dst_apic_id == IO_TO_ID(0) &&
1739 io_apic_ints[x].int_vector == 0xff &&
1740 int_to_apicintpin[0].ioapic == -1 &&
1741 io_apic_ints[x].int_type == 3) {
1742 assign_apic_irq(0, 0, 0);
1743 break;
1744 }
1745 }
1746
1747 /* Assign PCI interrupts */
1748 for (x = 0; x < nintrs; ++x) {
1749 if (io_apic_ints[x].int_type == 0 &&
1750 io_apic_ints[x].int_vector == 0xff &&
1751 apic_int_is_bus_type(x, PCI))
1752 allocate_apic_irq(x);
1753 }
1754 }
1755
1756 #endif
1757
1758 void
1759 mp_set_cpuids(int cpu_id, int apic_id)
1760 {
1761 CPU_TO_ID(cpu_id) = apic_id;
1762 ID_TO_CPU(apic_id) = cpu_id;
1763 }
1764
1765 static int
1766 processor_entry(proc_entry_ptr entry, int cpu)
1767 {
1768 KKASSERT(cpu > 0);
1769
1770 /* check for usability */
1771 if (!(entry->cpu_flags & PROCENTRY_FLAG_EN))
1772 return 0;
1773
1774 if(entry->apic_id >= NAPICID)
1775 panic("CPU APIC ID out of range (0..%d)", NAPICID - 1);
1776 /* check for BSP flag */
1777 if (entry->cpu_flags & PROCENTRY_FLAG_BP) {
1778 mp_set_cpuids(0, entry->apic_id);
1779 return 0; /* its already been counted */
1780 }
1781
1782 /* add another AP to list, if less than max number of CPUs */
1783 else if (cpu < MAXCPU) {
1784 mp_set_cpuids(cpu, entry->apic_id);
1785 return 1;
1786 }
1787
1788 return 0;
1789 }
1790
1791 #ifdef APIC_IO
1792
1793 static int
1794 bus_entry(bus_entry_ptr entry, int bus)
1795 {
1796 int x;
1797 char c, name[8];
1798
1799 /* encode the name into an index */
1800 for (x = 0; x < 6; ++x) {
1801 if ((c = entry->bus_type[x]) == ' ')
1802 break;
1803 name[x] = c;
1804 }
1805 name[x] = '\0';
1806
1807 if ((x = lookup_bus_type(name)) == UNKNOWN_BUSTYPE)
1808 panic("unknown bus type: '%s'", name);
1809
1810 bus_data[bus].bus_id = entry->bus_id;
1811 bus_data[bus].bus_type = x;
1812
1813 return 1;
1814 }
1815
1816 static int
1817 io_apic_entry(io_apic_entry_ptr entry, int apic)
1818 {
1819 if (!(entry->apic_flags & IOAPICENTRY_FLAG_EN))
1820 return 0;
1821
1822 IO_TO_ID(apic) = entry->apic_id;
1823 if (entry->apic_id < NAPICID)
1824 ID_TO_IO(entry->apic_id) = apic;
1825
1826 return 1;
1827 }
1828
1829 static int
1830 lookup_bus_type(char *name)
1831 {
1832 int x;
1833
1834 for (x = 0; x < MAX_BUSTYPE; ++x)
1835 if (strcmp(bus_type_table[x].name, name) == 0)
1836 return bus_type_table[x].type;
1837
1838 return UNKNOWN_BUSTYPE;
1839 }
1840
1841 static int
1842 int_entry(int_entry_ptr entry, int intr)
1843 {
1844 int apic;
1845
1846 io_apic_ints[intr].int_type = entry->int_type;
1847 io_apic_ints[intr].int_flags = entry->int_flags;
1848 io_apic_ints[intr].src_bus_id = entry->src_bus_id;
1849 io_apic_ints[intr].src_bus_irq = entry->src_bus_irq;
1850 if (entry->dst_apic_id == 255) {
1851 /* This signal goes to all IO APICS. Select an IO APIC
1852 with sufficient number of interrupt pins */
1853 for (apic = 0; apic < mp_napics; apic++)
1854 if (((io_apic_read(apic, IOAPIC_VER) &
1855 IOART_VER_MAXREDIR) >> MAXREDIRSHIFT) >=
1856 entry->dst_apic_int)
1857 break;
1858 if (apic < mp_napics)
1859 io_apic_ints[intr].dst_apic_id = IO_TO_ID(apic);
1860 else
1861 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id;
1862 } else
1863 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id;
1864 io_apic_ints[intr].dst_apic_int = entry->dst_apic_int;
1865
1866 return 1;
1867 }
1868
1869 static int
1870 apic_int_is_bus_type(int intr, int bus_type)
1871 {
1872 int bus;
1873
1874 for (bus = 0; bus < mp_nbusses; ++bus)
1875 if ((bus_data[bus].bus_id == io_apic_ints[intr].src_bus_id)
1876 && ((int) bus_data[bus].bus_type == bus_type))
1877 return 1;
1878
1879 return 0;
1880 }
1881
1882 /*
1883 * Given a traditional ISA INT mask, return an APIC mask.
1884 */
1885 u_int
1886 isa_apic_mask(u_int isa_mask)
1887 {
1888 int isa_irq;
1889 int apic_pin;
1890
1891 #if defined(SKIP_IRQ15_REDIRECT)
1892 if (isa_mask == (1 << 15)) {
1893 kprintf("skipping ISA IRQ15 redirect\n");
1894 return isa_mask;
1895 }
1896 #endif /* SKIP_IRQ15_REDIRECT */
1897
1898 isa_irq = ffs(isa_mask); /* find its bit position */
1899 if (isa_irq == 0) /* doesn't exist */
1900 return 0;
1901 --isa_irq; /* make it zero based */
1902
1903 apic_pin = isa_apic_irq(isa_irq); /* look for APIC connection */
1904 if (apic_pin == -1)
1905 return 0;
1906
1907 return (1 << apic_pin); /* convert pin# to a mask */
1908 }
1909
1910 /*
1911 * Determine which APIC pin an ISA/EISA INT is attached to.
1912 */
1913 #define INTTYPE(I) (io_apic_ints[(I)].int_type)
1914 #define INTPIN(I) (io_apic_ints[(I)].dst_apic_int)
1915 #define INTIRQ(I) (io_apic_ints[(I)].int_vector)
1916 #define INTAPIC(I) (ID_TO_IO(io_apic_ints[(I)].dst_apic_id))
1917
1918 #define SRCBUSIRQ(I) (io_apic_ints[(I)].src_bus_irq)
1919 int
1920 isa_apic_irq(int isa_irq)
1921 {
1922 int intr;
1923
1924 for (intr = 0; intr < nintrs; ++intr) { /* check each record */
1925 if (INTTYPE(intr) == 0) { /* standard INT */
1926 if (SRCBUSIRQ(intr) == isa_irq) {
1927 if (apic_int_is_bus_type(intr, ISA) ||
1928 apic_int_is_bus_type(intr, EISA)) {
1929 if (INTIRQ(intr) == 0xff)
1930 return -1; /* unassigned */
1931 return INTIRQ(intr); /* found */
1932 }
1933 }
1934 }
1935 }
1936 return -1; /* NOT found */
1937 }
1938
1939
1940 /*
1941 * Determine which APIC pin a PCI INT is attached to.
1942 */
1943 #define SRCBUSID(I) (io_apic_ints[(I)].src_bus_id)
1944 #define SRCBUSDEVICE(I) ((io_apic_ints[(I)].src_bus_irq >> 2) & 0x1f)
1945 #define SRCBUSLINE(I) (io_apic_ints[(I)].src_bus_irq & 0x03)
1946 int
1947 pci_apic_irq(int pciBus, int pciDevice, int pciInt)
1948 {
1949 int intr;
1950
1951 --pciInt; /* zero based */
1952
1953 for (intr = 0; intr < nintrs; ++intr) { /* check each record */
1954 if ((INTTYPE(intr) == 0) /* standard INT */
1955 && (SRCBUSID(intr) == pciBus)
1956 && (SRCBUSDEVICE(intr) == pciDevice)
1957 && (SRCBUSLINE(intr) == pciInt)) { /* a candidate IRQ */
1958 if (apic_int_is_bus_type(intr, PCI)) {
1959 if (INTIRQ(intr) == 0xff) {
1960 kprintf("IOAPIC: pci_apic_irq() "
1961 "failed\n");
1962 return -1; /* unassigned */
1963 }
1964 return INTIRQ(intr); /* exact match */
1965 }
1966 }
1967 }
1968
1969 return -1; /* NOT found */
1970 }
1971
1972 int
1973 next_apic_irq(int irq)
1974 {
1975 int intr, ointr;
1976 int bus, bustype;
1977
1978 bus = 0;
1979 bustype = 0;
1980 for (intr = 0; intr < nintrs; intr++) {
1981 if (INTIRQ(intr) != irq || INTTYPE(intr) != 0)
1982 continue;
1983 bus = SRCBUSID(intr);
1984 bustype = apic_bus_type(bus);
1985 if (bustype != ISA &&
1986 bustype != EISA &&
1987 bustype != PCI)
1988 continue;
1989 break;
1990 }
1991 if (intr >= nintrs) {
1992 return -1;
1993 }
1994 for (ointr = intr + 1; ointr < nintrs; ointr++) {
1995 if (INTTYPE(ointr) != 0)
1996 continue;
1997 if (bus != SRCBUSID(ointr))
1998 continue;
1999 if (bustype == PCI) {
2000 if (SRCBUSDEVICE(intr) != SRCBUSDEVICE(ointr))
2001 continue;
2002 if (SRCBUSLINE(intr) != SRCBUSLINE(ointr))
2003 continue;
2004 }
2005 if (bustype == ISA || bustype == EISA) {
2006 if (SRCBUSIRQ(intr) != SRCBUSIRQ(ointr))
2007 continue;
2008 }
2009 if (INTPIN(intr) == INTPIN(ointr))
2010 continue;
2011 break;
2012 }
2013 if (ointr >= nintrs) {
2014 return -1;
2015 }
2016 return INTIRQ(ointr);
2017 }
2018 #undef SRCBUSLINE
2019 #undef SRCBUSDEVICE
2020 #undef SRCBUSID
2021 #undef SRCBUSIRQ
2022
2023 #undef INTPIN
2024 #undef INTIRQ
2025 #undef INTAPIC
2026 #undef INTTYPE
2027
2028 #endif
2029
2030 /*
2031 * Reprogram the MB chipset to NOT redirect an ISA INTerrupt.
2032 *
2033 * XXX FIXME:
2034 * Exactly what this means is unclear at this point. It is a solution
2035 * for motherboards that redirect the MBIRQ0 pin. Generically a motherboard
2036 * could route any of the ISA INTs to upper (>15) IRQ values. But most would
2037 * NOT be redirected via MBIRQ0, thus "undirect()ing" them would NOT be an
2038 * option.
2039 */
2040 int
2041 undirect_isa_irq(int rirq)
2042 {
2043 #if defined(READY)
2044 if (bootverbose)
2045 kprintf("Freeing redirected ISA irq %d.\n", rirq);
2046 /** FIXME: tickle the MB redirector chip */
2047 return /* XXX */;
2048 #else
2049 if (bootverbose)
2050 kprintf("Freeing (NOT implemented) redirected ISA irq %d.\n", rirq);
2051 return 0;
2052 #endif /* READY */
2053 }
2054
2055
2056 /*
2057 * Reprogram the MB chipset to NOT redirect a PCI INTerrupt
2058 */
2059 int
2060 undirect_pci_irq(int rirq)
2061 {
2062 #if defined(READY)
2063 if (bootverbose)
2064 kprintf("Freeing redirected PCI irq %d.\n", rirq);
2065
2066 /** FIXME: tickle the MB redirector chip */
2067 return /* XXX */;
2068 #else
2069 if (bootverbose)
2070 kprintf("Freeing (NOT implemented) redirected PCI irq %d.\n",
2071 rirq);
2072 return 0;
2073 #endif /* READY */
2074 }
2075
2076
2077 #ifdef APIC_IO
2078
2079 /*
2080 * given a bus ID, return:
2081 * the bus type if found
2082 * -1 if NOT found
2083 */
2084 int
2085 apic_bus_type(int id)
2086 {
2087 int x;
2088
2089 for (x = 0; x < mp_nbusses; ++x)
2090 if (bus_data[x].bus_id == id)
2091 return bus_data[x].bus_type;
2092
2093 return -1;
2094 }
2095
2096 /*
2097 * given a LOGICAL APIC# and pin#, return:
2098 * the associated src bus ID if found
2099 * -1 if NOT found
2100 */
2101 int
2102 apic_src_bus_id(int apic, int pin)
2103 {
2104 int x;
2105
2106 /* search each of the possible INTerrupt sources */
2107 for (x = 0; x < nintrs; ++x)
2108 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
2109 (pin == io_apic_ints[x].dst_apic_int))
2110 return (io_apic_ints[x].src_bus_id);
2111
2112 return -1; /* NOT found */
2113 }
2114
2115 /*
2116 * given a LOGICAL APIC# and pin#, return:
2117 * the associated src bus IRQ if found
2118 * -1 if NOT found
2119 */
2120 int
2121 apic_src_bus_irq(int apic, int pin)
2122 {
2123 int x;
2124
2125 for (x = 0; x < nintrs; x++)
2126 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
2127 (pin == io_apic_ints[x].dst_apic_int))
2128 return (io_apic_ints[x].src_bus_irq);
2129
2130 return -1; /* NOT found */
2131 }
2132
2133
2134 /*
2135 * given a LOGICAL APIC# and pin#, return:
2136 * the associated INTerrupt type if found
2137 * -1 if NOT found
2138 */
2139 int
2140 apic_int_type(int apic, int pin)
2141 {
2142 int x;
2143
2144 /* search each of the possible INTerrupt sources */
2145 for (x = 0; x < nintrs; ++x) {
2146 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
2147 (pin == io_apic_ints[x].dst_apic_int))
2148 return (io_apic_ints[x].int_type);
2149 }
2150 return -1; /* NOT found */
2151 }
2152
2153 /*
2154 * Return the IRQ associated with an APIC pin
2155 */
2156 int
2157 apic_irq(int apic, int pin)
2158 {
2159 int x;
2160 int res;
2161
2162 for (x = 0; x < nintrs; ++x) {
2163 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
2164 (pin == io_apic_ints[x].dst_apic_int)) {
2165 res = io_apic_ints[x].int_vector;
2166 if (res == 0xff)
2167 return -1;
2168 if (apic != int_to_apicintpin[res].ioapic)
2169 panic("apic_irq: inconsistent table %d/%d", apic, int_to_apicintpin[res].ioapic);
2170 if (pin != int_to_apicintpin[res].int_pin)
2171 panic("apic_irq inconsistent table (2)");
2172 return res;
2173 }
2174 }
2175 return -1;
2176 }
2177
2178
2179 /*
2180 * given a LOGICAL APIC# and pin#, return:
2181 * the associated trigger mode if found
2182 * -1 if NOT found
2183 */
2184 int
2185 apic_trigger(int apic, int pin)
2186 {
2187 int x;
2188
2189 /* search each of the possible INTerrupt sources */
2190 for (x = 0; x < nintrs; ++x)
2191 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
2192 (pin == io_apic_ints[x].dst_apic_int))
2193 return ((io_apic_ints[x].int_flags >> 2) & 0x03);
2194
2195 return -1; /* NOT found */
2196 }
2197
2198
2199 /*
2200 * given a LOGICAL APIC# and pin#, return:
2201 * the associated 'active' level if found
2202 * -1 if NOT found
2203 */
2204 int
2205 apic_polarity(int apic, int pin)
2206 {
2207 int x;
2208
2209 /* search each of the possible INTerrupt sources */
2210 for (x = 0; x < nintrs; ++x)
2211 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
2212 (pin == io_apic_ints[x].dst_apic_int))
2213 return (io_apic_ints[x].int_flags & 0x03);
2214
2215 return -1; /* NOT found */
2216 }
2217
2218 #endif
2219
2220 /*
2221 * set data according to MP defaults
2222 * FIXME: probably not complete yet...
2223 */
2224 static void
2225 mptable_default(int type)
2226 {
2227 int ap_cpu_id, boot_cpu_id;
2228 #if defined(APIC_IO)
2229 int io_apic_id;
2230 int pin;
2231 #endif /* APIC_IO */
2232
2233 #if 0
2234 kprintf(" MP default config type: %d\n", type);
2235 switch (type) {
2236 case 1:
2237 kprintf(" bus: ISA, APIC: 82489DX\n");
2238 break;
2239 case 2:
2240 kprintf(" bus: EISA, APIC: 82489DX\n");
2241 break;
2242 case 3:
2243 kprintf(" bus: EISA, APIC: 82489DX\n");
2244 break;
2245 case 4:
2246 kprintf(" bus: MCA, APIC: 82489DX\n");
2247 break;
2248 case 5:
2249 kprintf(" bus: ISA+PCI, APIC: Integrated\n");
2250 break;
2251 case 6:
2252 kprintf(" bus: EISA+PCI, APIC: Integrated\n");
2253 break;
2254 case 7:
2255 kprintf(" bus: MCA+PCI, APIC: Integrated\n");
2256 break;
2257 default:
2258 kprintf(" future type\n");
2259 break;
2260 /* NOTREACHED */
2261 }
2262 #endif /* 0 */
2263
2264 boot_cpu_id = (lapic->id & APIC_ID_MASK) >> 24;
2265 ap_cpu_id = (boot_cpu_id == 0) ? 1 : 0;
2266
2267 /* BSP */
2268 CPU_TO_ID(0) = boot_cpu_id;
2269 ID_TO_CPU(boot_cpu_id) = 0;
2270
2271 /* one and only AP */
2272 CPU_TO_ID(1) = ap_cpu_id;
2273 ID_TO_CPU(ap_cpu_id) = 1;
2274
2275 #if defined(APIC_IO)
2276 /* one and only IO APIC */
2277 io_apic_id = (io_apic_read(0, IOAPIC_ID) & APIC_ID_MASK) >> 24;
2278
2279 /*
2280 * sanity check, refer to MP spec section 3.6.6, last paragraph
2281 * necessary as some hardware isn't properly setting up the IO APIC
2282 */
2283 #if defined(REALLY_ANAL_IOAPICID_VALUE)
2284 if (io_apic_id != 2) {
2285 #else
2286 if ((io_apic_id == 0) || (io_apic_id == 1) || (io_apic_id == 15)) {
2287 #endif /* REALLY_ANAL_IOAPICID_VALUE */
2288 io_apic_set_id(0, 2);
2289 io_apic_id = 2;
2290 }
2291 IO_TO_ID(0) = io_apic_id;
2292 ID_TO_IO(io_apic_id) = 0;
2293 #endif /* APIC_IO */
2294
2295 /* fill out bus entries */
2296 switch (type) {
2297 case 1:
2298 case 2:
2299 case 3:
2300 case 4:
2301 case 5:
2302 case 6:
2303 case 7:
2304 #ifdef APIC_IO
2305 bus_data[0].bus_id = default_data[type - 1][1];
2306 bus_data[0].bus_type = default_data[type - 1][2];
2307 bus_data[1].bus_id = default_data[type - 1][3];
2308 bus_data[1].bus_type = default_data[type - 1][4];
2309 #endif
2310 break;
2311
2312 /* case 4: case 7: MCA NOT supported */
2313 default: /* illegal/reserved */
2314 panic("BAD default MP config: %d", type);
2315 /* NOTREACHED */
2316 }
2317
2318 #if defined(APIC_IO)
2319 /* general cases from MP v1.4, table 5-2 */
2320 for (pin = 0; pin < 16; ++pin) {
2321 io_apic_ints[pin].int_type = 0;
2322 io_apic_ints[pin].int_flags = 0x05; /* edge/active-hi */
2323 io_apic_ints[pin].src_bus_id = 0;
2324 io_apic_ints[pin].src_bus_irq = pin; /* IRQ2 caught below */
2325 io_apic_ints[pin].dst_apic_id = io_apic_id;
2326 io_apic_ints[pin].dst_apic_int = pin; /* 1-to-1 */
2327 }
2328
2329 /* special cases from MP v1.4, table 5-2 */
2330 if (type == 2) {
2331 io_apic_ints[2].int_type = 0xff; /* N/C */
2332 io_apic_ints[13].int_type = 0xff; /* N/C */
2333 #if !defined(APIC_MIXED_MODE)
2334 /** FIXME: ??? */
2335 panic("sorry, can't support type 2 default yet");
2336 #endif /* APIC_MIXED_MODE */
2337 }
2338 else
2339 io_apic_ints[2].src_bus_irq = 0; /* ISA IRQ0 is on APIC INT 2 */
2340
2341 if (type == 7)
2342 io_apic_ints[0].int_type = 0xff; /* N/C */
2343 else
2344 io_apic_ints[0].int_type = 3; /* vectored 8259 */
2345 #endif /* APIC_IO */
2346 }
2347
2348 /*
2349 * Map a physical memory address representing I/O into KVA. The I/O
2350 * block is assumed not to cross a page boundary.
2351 */
2352 void *
2353 permanent_io_mapping(vm_paddr_t pa)
2354 {
2355 KKASSERT(pa < 0x100000000LL);
2356
2357 return pmap_mapdev_uncacheable(pa, PAGE_SIZE);
2358 }
2359
2360 /*
2361 * start each AP in our list
2362 */
2363 static int
2364 start_all_aps(u_int boot_addr)
2365 {
2366 vm_offset_t va = boot_address + KERNBASE;
2367 u_int64_t *pt4, *pt3, *pt2;
2368 int x, i, pg;
2369 int shift;
2370 int smicount;
2371 int smibest;
2372 int smilast;
2373 u_char mpbiosreason;
2374 u_long mpbioswarmvec;
2375 struct mdglobaldata *gd;
2376 struct privatespace *ps;
2377
2378 POSTCODE(START_ALL_APS_POST);
2379
2380 /* Initialize BSP's local APIC */
2381 apic_initialize(TRUE);
2382
2383 /* install the AP 1st level boot code */
2384 pmap_kenter(va, boot_address);
2385 cpu_invlpg((void *)va); /* JG XXX */
2386 bcopy(mptramp_start, (void *)va, bootMP_size);
2387
2388 /* Locate the page tables, they'll be below the trampoline */
2389 pt4 = (u_int64_t *)(uintptr_t)(mptramp_pagetables + KERNBASE);
2390 pt3 = pt4 + (PAGE_SIZE) / sizeof(u_int64_t);
2391 pt2 = pt3 + (PAGE_SIZE) / sizeof(u_int64_t);
2392
2393 /* Create the initial 1GB replicated page tables */
2394 for (i = 0; i < 512; i++) {
2395 /* Each slot of the level 4 pages points to the same level 3 page */
2396 pt4[i] = (u_int64_t)(uintptr_t)(mptramp_pagetables + PAGE_SIZE);
2397 pt4[i] |= PG_V | PG_RW | PG_U;
2398
2399 /* Each slot of the level 3 pages points to the same level 2 page */
2400 pt3[i] = (u_int64_t)(uintptr_t)(mptramp_pagetables + (2 * PAGE_SIZE));
2401 pt3[i] |= PG_V | PG_RW | PG_U;
2402
2403 /* The level 2 page slots are mapped with 2MB pages for 1GB. */
2404 pt2[i] = i * (2 * 1024 * 1024);
2405 pt2[i] |= PG_V | PG_RW | PG_PS | PG_U;
2406 }
2407
2408 /* save the current value of the warm-start vector */
2409 mpbioswarmvec = *((u_int32_t *) WARMBOOT_OFF);
2410 outb(CMOS_REG, BIOS_RESET);
2411 mpbiosreason = inb(CMOS_DATA);
2412
2413 /* setup a vector to our boot code */
2414 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET;
2415 *((volatile u_short *) WARMBOOT_SEG) = (boot_address >> 4);
2416 outb(CMOS_REG, BIOS_RESET);
2417 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */
2418
2419 /*
2420 * If we have a TSC we can figure out the SMI interrupt rate.
2421 * The SMI does not necessarily use a constant rate. Spend
2422 * up to 250ms trying to figure it out.
2423 */
2424 smibest = 0;
2425 if (cpu_feature & CPUID_TSC) {
2426 set_apic_timer(275000);
2427 smilast = read_apic_timer();
2428 for (x = 0; x < 20 && read_apic_timer(); ++x) {
2429 smicount = smitest();
2430 if (smibest == 0 || smilast - smicount < smibest)
2431 smibest = smilast - smicount;
2432 smilast = smicount;
2433 }
2434 if (smibest > 250000)
2435 smibest = 0;
2436 if (smibest) {
2437 smibest = smibest * (int64_t)1000000 /
2438 get_apic_timer_frequency();
2439 }
2440 }
2441 if (smibest)
2442 kprintf("SMI Frequency (worst case): %d Hz (%d us)\n",
2443 1000000 / smibest, smibest);
2444
2445 /* start each AP */
2446 for (x = 1; x <= mp_naps; ++x) {
2447
2448 /* This is a bit verbose, it will go away soon. */
2449
2450 /* first page of AP's private space */
2451 pg = x * x86_64_btop(sizeof(struct privatespace));
2452
2453 /* allocate new private data page(s) */
2454 gd = (struct mdglobaldata *)kmem_alloc(&kernel_map,
2455 MDGLOBALDATA_BASEALLOC_SIZE);
2456
2457 gd = &CPU_prvspace[x].mdglobaldata; /* official location */
2458 bzero(gd, sizeof(*gd));
2459 gd->mi.gd_prvspace = ps = &CPU_prvspace[x];
2460
2461 /* prime data page for it to use */
2462 mi_gdinit(&gd->mi, x);
2463 cpu_gdinit(gd, x);
2464 gd->gd_CMAP1 = &SMPpt[pg + 0];
2465 gd->gd_CMAP2 = &SMPpt[pg + 1];
2466 gd->gd_CMAP3 = &SMPpt[pg + 2];
2467 gd->gd_PMAP1 = &SMPpt[pg + 3];
2468 gd->gd_CADDR1 = ps->CPAGE1;
2469 gd->gd_CADDR2 = ps->CPAGE2;
2470 gd->gd_CADDR3 = ps->CPAGE3;
2471 gd->gd_PADDR1 = (pt_entry_t *)ps->PPAGE1;
2472 gd->mi.gd_ipiq = (void *)kmem_alloc(&kernel_map, sizeof(lwkt_ipiq) * (mp_naps + 1));
2473 bzero(gd->mi.gd_ipiq, sizeof(lwkt_ipiq) * (mp_naps + 1));
2474
2475 /* setup a vector to our boot code */
2476 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET;
2477 *((volatile u_short *) WARMBOOT_SEG) = (boot_addr >> 4);
2478 outb(CMOS_REG, BIOS_RESET);
2479 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */
2480
2481 /*
2482 * Setup the AP boot stack
2483 */
2484 bootSTK = &ps->idlestack[UPAGES*PAGE_SIZE/2];
2485 bootAP = x;
2486
2487 /* attempt to start the Application Processor */
2488 CHECK_INIT(99); /* setup checkpoints */
2489 if (!start_ap(gd, boot_addr, smibest)) {
2490 kprintf("AP #%d (PHY# %d) failed!\n", x, CPU_TO_ID(x));
2491 CHECK_PRINT("trace"); /* show checkpoints */
2492 /* better panic as the AP may be running loose */
2493 kprintf("panic y/n? [y] ");
2494 if (cngetc() != 'n')
2495 panic("bye-bye");
2496 }
2497 CHECK_PRINT("trace"); /* show checkpoints */
2498
2499 /* record its version info */
2500 cpu_apic_versions[x] = cpu_apic_versions[0];
2501 }
2502
2503 /* set ncpus to 1 + highest logical cpu. Not all may have come up */
2504 ncpus = x;
2505
2506 /* ncpus2 -- ncpus rounded down to the nearest power of 2 */
2507 for (shift = 0; (1 << shift) <= ncpus; ++shift)
2508 ;
2509 --shift;
2510 ncpus2_shift = shift;
2511 ncpus2 = 1 << shift;
2512 ncpus2_mask = ncpus2 - 1;
2513
2514 /* ncpus_fit -- ncpus rounded up to the nearest power of 2 */
2515 if ((1 << shift) < ncpus)
2516 ++shift;
2517 ncpus_fit = 1 << shift;
2518 ncpus_fit_mask = ncpus_fit - 1;
2519
2520 /* build our map of 'other' CPUs */
2521 mycpu->gd_other_cpus = smp_startup_mask & ~(1 << mycpu->gd_cpuid);
2522 mycpu->gd_ipiq = (void *)kmem_alloc(&kernel_map, sizeof(lwkt_ipiq) * ncpus);
2523 bzero(mycpu->gd_ipiq, sizeof(lwkt_ipiq) * ncpus);
2524
2525 /* fill in our (BSP) APIC version */
2526 cpu_apic_versions[0] = lapic->version;
2527
2528 /* restore the warmstart vector */
2529 *(u_long *) WARMBOOT_OFF = mpbioswarmvec;
2530 outb(CMOS_REG, BIOS_RESET);
2531 outb(CMOS_DATA, mpbiosreason);
2532
2533 /*
2534 * NOTE! The idlestack for the BSP was setup by locore. Finish
2535 * up, clean out the P==V mapping we did earlier.
2536 */
2537 pmap_set_opt();
2538
2539 /* number of APs actually started */
2540 return ncpus - 1;
2541 }
2542
2543
2544 /*
2545 * load the 1st level AP boot code into base memory.
2546 */
2547
2548 /* targets for relocation */
2549 extern void bigJump(void);
2550 extern void bootCodeSeg(void);
2551 extern void bootDataSeg(void);
2552 extern void MPentry(void);
2553 extern u_int MP_GDT;
2554 extern u_int mp_gdtbase;
2555
2556 #if 0
2557
2558 static void
2559 install_ap_tramp(u_int boot_addr)
2560 {
2561 int x;
2562 int size = *(int *) ((u_long) & bootMP_size);
2563 u_char *src = (u_char *) ((u_long) bootMP);
2564 u_char *dst = (u_char *) boot_addr + KERNBASE;
2565 u_int boot_base = (u_int) bootMP;
2566 u_int8_t *dst8;
2567 u_int16_t *dst16;
2568 u_int32_t *dst32;
2569
2570 POSTCODE(INSTALL_AP_TRAMP_POST);
2571
2572 for (x = 0; x < size; ++x)
2573 *dst++ = *src++;
2574
2575 /*
2576 * modify addresses in code we just moved to basemem. unfortunately we
2577 * need fairly detailed info about mpboot.s for this to work. changes
2578 * to mpboot.s might require changes here.
2579 */
2580
2581 /* boot code is located in KERNEL space */
2582 dst = (u_char *) boot_addr + KERNBASE;
2583
2584 /* modify the lgdt arg */
2585 dst32 = (u_int32_t *) (dst + ((u_int) & mp_gdtbase - boot_base));
2586 *dst32 = boot_addr + ((u_int) & MP_GDT - boot_base);
2587
2588 /* modify the ljmp target for MPentry() */
2589 dst32 = (u_int32_t *) (dst + ((u_int) bigJump - boot_base) + 1);
2590 *dst32 = ((u_int) MPentry - KERNBASE);
2591
2592 /* modify the target for boot code segment */
2593 dst16 = (u_int16_t *) (dst + ((u_int) bootCodeSeg - boot_base));
2594 dst8 = (u_int8_t *) (dst16 + 1);
2595 *dst16 = (u_int) boot_addr & 0xffff;
2596 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
2597
2598 /* modify the target for boot data segment */
2599 dst16 = (u_int16_t *) (dst + ((u_int) bootDataSeg - boot_base));
2600 dst8 = (u_int8_t *) (dst16 + 1);
2601 *dst16 = (u_int) boot_addr & 0xffff;
2602 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
2603 }
2604
2605 #endif
2606
2607 /*
2608 * This function starts the AP (application processor) identified
2609 * by the APIC ID 'physicalCpu'. It does quite a "song and dance"
2610 * to accomplish this. This is necessary because of the nuances
2611 * of the different hardware we might encounter. It ain't pretty,
2612 * but it seems to work.
2613 *
2614 * NOTE: eventually an AP gets to ap_init(), which is called just
2615 * before the AP goes into the LWKT scheduler's idle loop.
2616 */
2617 static int
2618 start_ap(struct mdglobaldata *gd, u_int boot_addr, int smibest)
2619 {
2620 int physical_cpu;
2621 int vector;
2622 u_long icr_lo, icr_hi;
2623
2624 POSTCODE(START_AP_POST);
2625
2626 /* get the PHYSICAL APIC ID# */
2627 physical_cpu = CPU_TO_ID(gd->mi.gd_cpuid);
2628
2629 /* calculate the vector */
2630 vector = (boot_addr >> 12) & 0xff;
2631
2632 /* We don't want anything interfering */
2633 cpu_disable_intr();
2634
2635 /* Make sure the target cpu sees everything */
2636 wbinvd();
2637
2638 /*
2639 * Try to detect when a SMI has occurred, wait up to 200ms.
2640 *
2641 * If a SMI occurs during an AP reset but before we issue
2642 * the STARTUP command, the AP may brick. To work around
2643 * this problem we hold off doing the AP startup until
2644 * after we have detected the SMI. Hopefully another SMI
2645 * will not occur before we finish the AP startup.
2646 *
2647 * Retries don't seem to help. SMIs have a window of opportunity
2648 * and if USB->legacy keyboard emulation is enabled in the BIOS
2649 * the interrupt rate can be quite high.
2650 *
2651 * NOTE: Don't worry about the L1 cache load, it might bloat
2652 * ldelta a little but ndelta will be so huge when the SMI
2653 * occurs the detection logic will still work fine.
2654 */
2655 if (smibest) {
2656 set_apic_timer(200000);
2657 smitest();
2658 }
2659
2660 /*
2661 * first we do an INIT/RESET IPI this INIT IPI might be run, reseting
2662 * and running the target CPU. OR this INIT IPI might be latched (P5
2663 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be
2664 * ignored.
2665 *
2666 * see apic/apicreg.h for icr bit definitions.
2667 *
2668 * TIME CRITICAL CODE, DO NOT DO ANY KPRINTFS IN THE HOT PATH.
2669 */
2670
2671 /*
2672 * Setup the address for the target AP. We can setup
2673 * icr_hi once and then just trigger operations with
2674 * icr_lo.
2675 */
2676 icr_hi = lapic->icr_hi & ~APIC_ID_MASK;
2677 icr_hi |= (physical_cpu << 24);
2678 icr_lo = lapic->icr_lo & 0xfff00000;
2679 lapic->icr_hi = icr_hi;
2680
2681 /*
2682 * Do an INIT IPI: assert RESET
2683 *
2684 * Use edge triggered mode to assert INIT
2685 */
2686 lapic->icr_lo = icr_lo | 0x00004500;
2687 while (lapic->icr_lo & APIC_DELSTAT_MASK)
2688 /* spin */ ;
2689
2690 /*
2691 * The spec calls for a 10ms delay but we may have to use a
2692 * MUCH lower delay to avoid bricking an AP due to a fast SMI
2693 * interrupt. We have other loops here too and dividing by 2
2694 * doesn't seem to be enough even after subtracting 350us,
2695 * so we divide by 4.
2696 *
2697 * Our minimum delay is 150uS, maximum is 10ms. If no SMI
2698 * interrupt was detected we use the full 10ms.
2699 */
2700 if (smibest == 0)
2701 u_sleep(10000);
2702 else if (smibest < 150 * 4 + 350)
2703 u_sleep(150);
2704 else if ((smibest - 350) / 4 < 10000)
2705 u_sleep((smibest - 350) / 4);
2706 else
2707 u_sleep(10000);
2708
2709 /*
2710 * Do an INIT IPI: deassert RESET
2711 *
2712 * Use level triggered mode to deassert. It is unclear
2713 * why we need to do this.
2714 */
2715 lapic->icr_lo = icr_lo | 0x00008500;
2716 while (lapic->icr_lo & APIC_DELSTAT_MASK)
2717 /* spin */ ;
2718 u_sleep(150); /* wait 150us */
2719
2720 /*
2721 * Next we do a STARTUP IPI: the previous INIT IPI might still be
2722 * latched, (P5 bug) this 1st STARTUP would then terminate
2723 * immediately, and the previously started INIT IPI would continue. OR
2724 * the previous INIT IPI has already run. and this STARTUP IPI will
2725 * run. OR the previous INIT IPI was ignored. and this STARTUP IPI
2726 * will run.
2727 */
2728 lapic->icr_lo = icr_lo | 0x00000600 | vector;
2729 while (lapic->icr_lo & APIC_DELSTAT_MASK)
2730 /* spin */ ;
2731 u_sleep(200); /* wait ~200uS */
2732
2733 /*
2734 * Finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF
2735 * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR
2736 * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is
2737 * recognized after hardware RESET or INIT IPI.
2738 */
2739 lapic->icr_lo = icr_lo | 0x00000600 | vector;
2740 while (lapic->icr_lo & APIC_DELSTAT_MASK)
2741 /* spin */ ;
2742
2743 /* Resume normal operation */
2744 cpu_enable_intr();
2745
2746 /* wait for it to start, see ap_init() */
2747 set_apic_timer(5000000);/* == 5 seconds */
2748 while (read_apic_timer()) {
2749 if (smp_startup_mask & (1 << gd->mi.gd_cpuid))
2750 return 1; /* return SUCCESS */
2751 }
2752
2753 return 0; /* return FAILURE */
2754 }
2755
2756 static
2757 int
2758 smitest(void)
2759 {
2760 int64_t ltsc;
2761 int64_t ntsc;
2762 int64_t ldelta;
2763 int64_t ndelta;
2764 int count;
2765
2766 ldelta = 0;
2767 ndelta = 0;
2768 while (read_apic_timer()) {
2769 ltsc = rdtsc();
2770 for (count = 0; count < 100; ++count)
2771 ntsc = rdtsc(); /* force loop to occur */
2772 if (ldelta) {
2773 ndelta = ntsc - ltsc;
2774 if (ldelta > ndelta)
2775 ldelta = ndelta;
2776 if (ndelta > ldelta * 2)
2777 break;
2778 } else {
2779 ldelta = ntsc - ltsc;
2780 }
2781 }
2782 return(read_apic_timer());
2783 }
2784
2785 /*
2786 * Synchronously flush the TLB on all other CPU's. The current cpu's
2787 * TLB is not flushed. If the caller wishes to flush the current cpu's
2788 * TLB the caller must call cpu_invltlb() in addition to smp_invltlb().
2789 *
2790 * NOTE: If for some reason we were unable to start all cpus we cannot
2791 * safely use broadcast IPIs.
2792 */
2793
2794 static cpumask_t smp_invltlb_req;
2795
2796 void
2797 smp_invltlb(void)
2798 {
2799 #ifdef SMP
2800 struct mdglobaldata *md = mdcpu;
2801 #ifdef SMP_INVLTLB_DEBUG
2802 long count = 0;
2803 long xcount = 0;
2804 #endif
2805
2806 crit_enter_gd(&md->mi);
2807 md->gd_invltlb_ret = 0;
2808 ++md->mi.gd_cnt.v_smpinvltlb;
2809 atomic_set_int(&smp_invltlb_req, md->mi.gd_cpumask);
2810 #ifdef SMP_INVLTLB_DEBUG
2811 again:
2812 #endif
2813 if (smp_startup_mask == smp_active_mask) {
2814 all_but_self_ipi(XINVLTLB_OFFSET);
2815 } else {
2816 selected_apic_ipi(smp_active_mask & ~md->mi.gd_cpumask,
2817 XINVLTLB_OFFSET, APIC_DELMODE_FIXED);
2818 }
2819
2820 #ifdef SMP_INVLTLB_DEBUG
2821 if (xcount)
2822 kprintf("smp_invltlb: ipi sent\n");
2823 #endif
2824 while ((md->gd_invltlb_ret & smp_active_mask & ~md->mi.gd_cpumask) !=
2825 (smp_active_mask & ~md->mi.gd_cpumask)) {
2826 cpu_mfence();
2827 cpu_pause();
2828 #ifdef SMP_INVLTLB_DEBUG
2829 /* DEBUGGING */
2830 if (++count == 400000000) {
2831 print_backtrace(-1);
2832 kprintf("smp_invltlb: endless loop %08lx %08lx, "
2833 "rflags %016jx retry",
2834 (long)md->gd_invltlb_ret,
2835 (long)smp_invltlb_req,
2836 (intmax_t)read_rflags());
2837 __asm __volatile ("sti");
2838 ++xcount;
2839 if (xcount > 2)
2840 lwkt_process_ipiq();
2841 if (xcount > 3) {
2842 int bcpu = bsfl(~md->gd_invltlb_ret & ~md->mi.gd_cpumask & smp_active_mask);
2843 globaldata_t xgd;
2844
2845 kprintf("bcpu %d\n", bcpu);
2846 xgd = globaldata_find(bcpu);
2847 kprintf("thread %p %s\n", xgd->gd_curthread, xgd->gd_curthread->td_comm);
2848 }
2849 if (xcount > 5)
2850 Debugger("giving up");
2851 count = 0;
2852 goto again;
2853 }
2854 #endif
2855 }
2856 atomic_clear_int(&smp_invltlb_req, md->mi.gd_cpumask);
2857 crit_exit_gd(&md->mi);
2858 #endif
2859 }
2860
2861 #ifdef SMP
2862
2863 /*
2864 * Called from Xinvltlb assembly with interrupts disabled. We didn't
2865 * bother to bump the critical section count or nested interrupt count
2866 * so only do very low level operations here.
2867 */
2868 void
2869 smp_invltlb_intr(void)
2870 {
2871 struct mdglobaldata *md = mdcpu;
2872 struct mdglobaldata *omd;
2873 cpumask_t mask;
2874 int cpu;
2875
2876 cpu_mfence();
2877 mask = smp_invltlb_req;
2878 cpu_invltlb();
2879 while (mask) {
2880 cpu = bsfl(mask);
2881 mask &= ~(1 << cpu);
2882 omd = (struct mdglobaldata *)globaldata_find(cpu);
2883 atomic_set_int(&omd->gd_invltlb_ret, md->mi.gd_cpumask);
2884 }
2885 }
2886
2887 #endif
2888
2889 /*
2890 * When called the executing CPU will send an IPI to all other CPUs
2891 * requesting that they halt execution.
2892 *
2893 * Usually (but not necessarily) called with 'other_cpus' as its arg.
2894 *
2895 * - Signals all CPUs in map to stop.
2896 * - Waits for each to stop.
2897 *
2898 * Returns:
2899 * -1: error
2900 * 0: NA
2901 * 1: ok
2902 *
2903 * XXX FIXME: this is not MP-safe, needs a lock to prevent multiple CPUs
2904 * from executing at same time.
2905 */
2906 int
2907 stop_cpus(u_int map)
2908 {
2909 map &= smp_active_mask;
2910
2911 /* send the Xcpustop IPI to all CPUs in map */
2912 selected_apic_ipi(map, XCPUSTOP_OFFSET, APIC_DELMODE_FIXED);
2913
2914 while ((stopped_cpus & map) != map)
2915 /* spin */ ;
2916
2917 return 1;
2918 }
2919
2920
2921 /*
2922 * Called by a CPU to restart stopped CPUs.
2923 *
2924 * Usually (but not necessarily) called with 'stopped_cpus' as its arg.
2925 *
2926 * - Signals all CPUs in map to restart.
2927 * - Waits for each to restart.
2928 *
2929 * Returns:
2930 * -1: error
2931 * 0: NA
2932 * 1: ok
2933 */
2934 int
2935 restart_cpus(u_int map)
2936 {
2937 /* signal other cpus to restart */
2938 started_cpus = map & smp_active_mask;
2939
2940 while ((stopped_cpus & map) != 0) /* wait for each to clear its bit */
2941 /* spin */ ;
2942
2943 return 1;
2944 }
2945
2946 /*
2947 * This is called once the mpboot code has gotten us properly relocated
2948 * and the MMU turned on, etc. ap_init() is actually the idle thread,
2949 * and when it returns the scheduler will call the real cpu_idle() main
2950 * loop for the idlethread. Interrupts are disabled on entry and should
2951 * remain disabled at return.
2952 */
2953 void
2954 ap_init(void)
2955 {
2956 u_int apic_id;
2957
2958 /*
2959 * Adjust smp_startup_mask to signal the BSP that we have started
2960 * up successfully. Note that we do not yet hold the BGL. The BSP
2961 * is waiting for our signal.
2962 *
2963 * We can't set our bit in smp_active_mask yet because we are holding
2964 * interrupts physically disabled and remote cpus could deadlock
2965 * trying to send us an IPI.
2966 */
2967 smp_startup_mask |= 1 << mycpu->gd_cpuid;
2968 cpu_mfence();
2969
2970 /*
2971 * Interlock for finalization. Wait until mp_finish is non-zero,
2972 * then get the MP lock.
2973 *
2974 * Note: We are in a critical section.
2975 *
2976 * Note: We have to synchronize td_mpcount to our desired MP state
2977 * before calling cpu_try_mplock().
2978 *
2979 * Note: we are the idle thread, we can only spin.
2980 *
2981 * Note: The load fence is memory volatile and prevents the compiler
2982 * from improperly caching mp_finish, and the cpu from improperly
2983 * caching it.
2984 */
2985 while (mp_finish == 0)
2986 cpu_lfence();
2987 ++curthread->td_mpcount;
2988 while (cpu_try_mplock() == 0)
2989 ;
2990
2991 if (cpu_feature & CPUID_TSC) {
2992 /*
2993 * The BSP is constantly updating tsc0_offset, figure out the
2994 * relative difference to synchronize ktrdump.
2995 */
2996 tsc_offsets[mycpu->gd_cpuid] = rdtsc() - tsc0_offset;
2997 }
2998
2999 /* BSP may have changed PTD while we're waiting for the lock */
3000 cpu_invltlb();
3001
3002 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
3003 lidt(&r_idt);
3004 #endif
3005
3006 /* Build our map of 'other' CPUs. */
3007 mycpu->gd_other_cpus = smp_startup_mask & ~(1 << mycpu->gd_cpuid);
3008
3009 kprintf("SMP: AP CPU #%d Launched!\n", mycpu->gd_cpuid);
3010
3011 /* A quick check from sanity claus */
3012 apic_id = (apic_id_to_logical[(lapic->id & 0x0f000000) >> 24]);
3013 if (mycpu->gd_cpuid != apic_id) {
3014 kprintf("SMP: cpuid = %d\n", mycpu->gd_cpuid);
3015 kprintf("SMP: apic_id = %d\n", apic_id);
3016 #if JGXXX
3017 kprintf("PTD[MPPTDI] = %p\n", (void *)PTD[MPPTDI]);
3018 #endif
3019 panic("cpuid mismatch! boom!!");
3020 }
3021
3022 /* Initialize AP's local APIC for irq's */
3023 apic_initialize(FALSE);
3024
3025 /* Set memory range attributes for this CPU to match the BSP */
3026 mem_range_AP_init();
3027
3028 /*
3029 * Once we go active we must process any IPIQ messages that may
3030 * have been queued, because no actual IPI will occur until we
3031 * set our bit in the smp_active_mask. If we don't the IPI
3032 * message interlock could be left set which would also prevent
3033 * further IPIs.
3034 *
3035 * The idle loop doesn't expect the BGL to be held and while
3036 * lwkt_switch() normally cleans things up this is a special case
3037 * because we returning almost directly into the idle loop.
3038 *
3039 * The idle thread is never placed on the runq, make sure
3040 * nothing we've done put it there.
3041 */
3042 KKASSERT(curthread->td_mpcount == 1);
3043 smp_active_mask |= 1 << mycpu->gd_cpuid;
3044
3045 /*
3046 * Enable interrupts here. idle_restore will also do it, but
3047 * doing it here lets us clean up any strays that got posted to
3048 * the CPU during the AP boot while we are still in a critical
3049 * section.
3050 */
3051 __asm __volatile("sti; pause; pause"::);
3052 mdcpu->gd_fpending = 0;
3053
3054 initclocks_pcpu(); /* clock interrupts (via IPIs) */
3055 lwkt_process_ipiq();
3056
3057 /*
3058 * Releasing the mp lock lets the BSP finish up the SMP init
3059 */
3060 rel_mplock();
3061 KKASSERT((curthread->td_flags & TDF_RUNQ) == 0);
3062 }
3063
3064 /*
3065 * Get SMP fully working before we start initializing devices.
3066 */
3067 static
3068 void
3069 ap_finish(void)
3070 {
3071 mp_finish = 1;
3072 if (bootverbose)
3073 kprintf("Finish MP startup\n");
3074 if (cpu_feature & CPUID_TSC)
3075 tsc0_offset = rdtsc();
3076 tsc_offsets[0] = 0;
3077 rel_mplock();
3078 while (smp_active_mask != smp_startup_mask) {
3079 cpu_lfence();
3080 if (cpu_feature & CPUID_TSC)
3081 tsc0_offset = rdtsc();
3082 }
3083 while (try_mplock() == 0)
3084 ;
3085 if (bootverbose)
3086 kprintf("Active CPU Mask: %08x\n", smp_active_mask);
3087 }
3088
3089 SYSINIT(finishsmp, SI_BOOT2_FINISH_SMP, SI_ORDER_FIRST, ap_finish, NULL)
3090
3091 void
3092 cpu_send_ipiq(int dcpu)
3093 {
3094 if ((1 << dcpu) & smp_active_mask)
3095 single_apic_ipi(dcpu, XIPIQ_OFFSET, APIC_DELMODE_FIXED);
3096 }
3097
3098 #if 0 /* single_apic_ipi_passive() not working yet */
3099 /*
3100 * Returns 0 on failure, 1 on success
3101 */
3102 int
3103 cpu_send_ipiq_passive(int dcpu)
3104 {
3105 int r = 0;
3106 if ((1 << dcpu) & smp_active_mask) {
3107 r = single_apic_ipi_passive(dcpu, XIPIQ_OFFSET,
3108 APIC_DELMODE_FIXED);
3109 }
3110 return(r);
3111 }
3112 #endif
3113
DragonFly BSD