sys/bus/usb/ehcireg.h

   1 /*      $NetBSD: ehcireg.h,v 1.18 2004/10/22 10:38:17 augustss Exp $    */
   2 /*      $FreeBSD: src/sys/dev/usb/ehcireg.h,v 1.7.2.1 2006/01/26 01:43:13 iedowse Exp $ */
   3 /*      $DragonFly: src/sys/bus/usb/ehcireg.h,v 1.7 2007/06/27 12:27:59 hasso Exp $     */
   4
   5 /*
   6  * Copyright (c) 2001 The NetBSD Foundation, Inc.
   7  * All rights reserved.
   8  *
   9  * This code is derived from software contributed to The NetBSD Foundation
  10  * by Lennart Augustsson (lennart@augustsson.net).
  11  *
  12  * Redistribution and use in source and binary forms, with or without
  13  * modification, are permitted provided that the following conditions
  14  * are met:
  15  * 1. Redistributions of source code must retain the above copyright
  16  *    notice, this list of conditions and the following disclaimer.
  17  * 2. Redistributions in binary form must reproduce the above copyright
  18  *    notice, this list of conditions and the following disclaimer in the
  19  *    documentation and/or other materials provided with the distribution.
  20  * 3. All advertising materials mentioning features or use of this software
  21  *    must display the following acknowledgement:
  22  *        This product includes software developed by the NetBSD
  23  *        Foundation, Inc. and its contributors.
  24  * 4. Neither the name of The NetBSD Foundation nor the names of its
  25  *    contributors may be used to endorse or promote products derived
  26  *    from this software without specific prior written permission.
  27  *
  28  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
  29  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  30  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  31  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
  32  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  33  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  34  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  35  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  36  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  37  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  38  * POSSIBILITY OF SUCH DAMAGE.
  39  */
  40
  41 /*
  42  * The EHCI 0.96 spec can be found at
  43  * http://developer.intel.com/technology/usb/download/ehci-r096.pdf
  44  * and the USB 2.0 spec at
  45  * http://www.usb.org/developers/data/usb_20.zip
  46  */
  47
  48 #ifndef _DEV_PCI_EHCIREG_H_
  49 #define _DEV_PCI_EHCIREG_H_
  50
  51 /*** PCI config registers ***/
  52
  53 #define PCI_CBMEM               0x10    /* configuration base MEM */
  54
  55 #define PCI_INTERFACE_EHCI      0x20
  56
  57 #define PCI_USBREV              0x60    /* RO USB protocol revision */
  58 #define  PCI_USBREV_MASK        0xff
  59 #define  PCI_USBREV_PRE_1_0     0x00
  60 #define  PCI_USBREV_1_0         0x10
  61 #define  PCI_USBREV_1_1         0x11
  62 #define  PCI_USBREV_2_0         0x20
  63
  64 #define PCI_EHCI_FLADJ          0x61    /*RW Frame len adj, SOF=59488+6*fladj */
  65
  66 #define PCI_EHCI_PORTWAKECAP    0x62    /* RW Port wake caps (opt)  */
  67
  68 /* EHCI Extended Capabilities */
  69 #define EHCI_EC_LEGSUP          0x01
  70
  71 #define EHCI_EECP_NEXT(x)       (((x) >> 8) & 0xff)
  72 #define EHCI_EECP_ID(x)         ((x) & 0xff)
  73
  74 /* Legacy support extended capability */
  75 #define EHCI_LEGSUP_LEGSUP      0x01
  76 #define  EHCI_LEGSUP_OSOWNED    0x01000000 /* OS owned semaphore */
  77 #define  EHCI_LEGSUP_BIOSOWNED  0x00010000 /* BIOS owned semaphore */
  78 #define EHCI_LEGSUP_USBLEGCTLSTS 0x04
  79
  80 /*** EHCI capability registers ***/
  81
  82 #define EHCI_CAPLENGTH          0x00    /*RO Capability register length field */
  83 /* reserved                     0x01 */
  84 #define EHCI_HCIVERSION         0x02    /* RO Interface version number */
  85
  86 #define EHCI_HCSPARAMS          0x04    /* RO Structural parameters */
  87 #define  EHCI_HCS_DEBUGPORT(x)  (((x) >> 20) & 0xf)
  88 #define  EHCI_HCS_P_INDICATOR(x) ((x) & 0x10000)
  89 #define  EHCI_HCS_N_CC(x)       (((x) >> 12) & 0xf) /* # of companion ctlrs */
  90 #define  EHCI_HCS_N_PCC(x)      (((x) >> 8) & 0xf) /* # of ports per comp. */
  91 #define  EHCI_HCS_PPC(x)        ((x) & 0x10) /* port power control */
  92 #define  EHCI_HCS_N_PORTS(x)    ((x) & 0xf) /* # of ports */
  93
  94 #define EHCI_HCCPARAMS          0x08    /* RO Capability parameters */
  95 #define  EHCI_HCC_EECP(x)       (((x) >> 8) & 0xff) /* extended ports caps */
  96 #define  EHCI_HCC_IST(x)        (((x) >> 4) & 0xf) /* isoc sched threshold */
  97 #define  EHCI_HCC_ASPC(x)       ((x) & 0x4) /* async sched park cap */
  98 #define  EHCI_HCC_PFLF(x)       ((x) & 0x2) /* prog frame list flag */
  99 #define  EHCI_HCC_64BIT(x)      ((x) & 0x1) /* 64 bit address cap */
 100
 101 #define EHCI_HCSP_PORTROUTE     0x0c    /*RO Companion port route description */
 102
 103 /* EHCI operational registers.  Offset given by EHCI_CAPLENGTH register */
 104 #define EHCI_USBCMD             0x00    /* RO, RW, WO Command register */
 105 #define  EHCI_CMD_ITC_M         0x00ff0000 /* RW interrupt threshold ctrl */
 106 #define   EHCI_CMD_ITC_1        0x00010000
 107 #define   EHCI_CMD_ITC_2        0x00020000
 108 #define   EHCI_CMD_ITC_4        0x00040000
 109 #define   EHCI_CMD_ITC_8        0x00080000
 110 #define   EHCI_CMD_ITC_16       0x00100000
 111 #define   EHCI_CMD_ITC_32       0x00200000
 112 #define   EHCI_CMD_ITC_64       0x00400000
 113 #define  EHCI_CMD_ASPME         0x00000800 /* RW/RO async park enable */
 114 #define  EHCI_CMD_ASPMC         0x00000300 /* RW/RO async park count */
 115 #define  EHCI_CMD_LHCR          0x00000080 /* RW light host ctrl reset */
 116 #define  EHCI_CMD_IAAD          0x00000040 /* RW intr on async adv door bell */
 117 #define  EHCI_CMD_ASE           0x00000020 /* RW async sched enable */
 118 #define  EHCI_CMD_PSE           0x00000010 /* RW periodic sched enable */
 119 #define  EHCI_CMD_FLS_M         0x0000000c /* RW/RO frame list size */
 120 #define  EHCI_CMD_FLS(x)        (((x) >> 2) & 3) /* RW/RO frame list size */
 121 #define  EHCI_CMD_HCRESET       0x00000002 /* RW reset */
 122 #define  EHCI_CMD_RS            0x00000001 /* RW run/stop */
 123
 124 #define EHCI_USBSTS             0x04    /* RO, RW, RWC Status register */
 125 #define  EHCI_STS_ASS           0x00008000 /* RO async sched status */
 126 #define  EHCI_STS_PSS           0x00004000 /* RO periodic sched status */
 127 #define  EHCI_STS_REC           0x00002000 /* RO reclamation */
 128 #define  EHCI_STS_HCH           0x00001000 /* RO host controller halted */
 129 #define  EHCI_STS_IAA           0x00000020 /* RWC interrupt on async adv */
 130 #define  EHCI_STS_HSE           0x00000010 /* RWC host system error */
 131 #define  EHCI_STS_FLR           0x00000008 /* RWC frame list rollover */
 132 #define  EHCI_STS_PCD           0x00000004 /* RWC port change detect */
 133 #define  EHCI_STS_ERRINT        0x00000002 /* RWC error interrupt */
 134 #define  EHCI_STS_INT           0x00000001 /* RWC interrupt */
 135 #define  EHCI_STS_INTRS(x)      ((x) & 0x3f)
 136
 137 #define EHCI_NORMAL_INTRS (EHCI_STS_IAA | EHCI_STS_HSE | EHCI_STS_PCD | EHCI_STS_ERRINT | EHCI_STS_INT)
 138
 139 #define EHCI_USBINTR            0x08    /* RW Interrupt register */
 140 #define EHCI_INTR_IAAE          0x00000020 /* interrupt on async advance ena */
 141 #define EHCI_INTR_HSEE          0x00000010 /* host system error ena */
 142 #define EHCI_INTR_FLRE          0x00000008 /* frame list rollover ena */
 143 #define EHCI_INTR_PCIE          0x00000004 /* port change ena */
 144 #define EHCI_INTR_UEIE          0x00000002 /* USB error intr ena */
 145 #define EHCI_INTR_UIE           0x00000001 /* USB intr ena */
 146
 147 #define EHCI_FRINDEX            0x0c    /* RW Frame Index register */
 148
 149 #define EHCI_CTRLDSSEGMENT      0x10    /* RW Control Data Structure Segment */
 150
 151 #define EHCI_PERIODICLISTBASE   0x14    /* RW Periodic List Base */
 152 #define EHCI_ASYNCLISTADDR      0x18    /* RW Async List Base */
 153
 154 #define EHCI_CONFIGFLAG         0x40    /* RW Configure Flag register */
 155 #define  EHCI_CONF_CF           0x00000001 /* RW configure flag */
 156
 157 #define EHCI_PORTSC(n)          (0x40+4*(n)) /* RO, RW, RWC Port Status reg */
 158 #define  EHCI_PS_WKOC_E         0x00400000 /* RW wake on over current ena */
 159 #define  EHCI_PS_WKDSCNNT_E     0x00200000 /* RW wake on disconnect ena */
 160 #define  EHCI_PS_WKCNNT_E       0x00100000 /* RW wake on connect ena */
 161 #define  EHCI_PS_PTC            0x000f0000 /* RW port test control */
 162 #define  EHCI_PS_PIC            0x0000c000 /* RW port indicator control */
 163 #define  EHCI_PS_PO             0x00002000 /* RW port owner */
 164 #define  EHCI_PS_PP             0x00001000 /* RW,RO port power */
 165 #define  EHCI_PS_LS             0x00000c00 /* RO line status */
 166 #define  EHCI_PS_IS_LOWSPEED(x) (((x) & EHCI_PS_LS) == 0x00000400)
 167 #define  EHCI_PS_PR             0x00000100 /* RW port reset */
 168 #define  EHCI_PS_SUSP           0x00000080 /* RW suspend */
 169 #define  EHCI_PS_FPR            0x00000040 /* RW force port resume */
 170 #define  EHCI_PS_OCC            0x00000020 /* RWC over current change */
 171 #define  EHCI_PS_OCA            0x00000010 /* RO over current active */
 172 #define  EHCI_PS_PEC            0x00000008 /* RWC port enable change */
 173 #define  EHCI_PS_PE             0x00000004 /* RW port enable */
 174 #define  EHCI_PS_CSC            0x00000002 /* RWC connect status change */
 175 #define  EHCI_PS_CS             0x00000001 /* RO connect status */
 176 #define  EHCI_PS_CLEAR          (EHCI_PS_OCC|EHCI_PS_PEC|EHCI_PS_CSC)
 177
 178 #define EHCI_PORT_RESET_COMPLETE 2 /* ms */
 179
 180 #define EHCI_FLALIGN_ALIGN      0x1000
 181
 182 /* No data structure may cross a page boundary. */
 183 #define EHCI_PAGE_SIZE 0x1000
 184 #define EHCI_PAGE(x) ((x) &~ 0xfff)
 185 #define EHCI_PAGE_OFFSET(x) ((x) & 0xfff)
 186 #define EHCI_PAGE_MASK(x) ((x) & 0xfff)
 187
 188 typedef u_int32_t ehci_link_t;
 189 #define EHCI_LINK_TERMINATE     0x00000001
 190 #define EHCI_LINK_TYPE(x)       ((x) & 0x00000006)
 191 #define  EHCI_LINK_ITD          0x0
 192 #define  EHCI_LINK_QH           0x2
 193 #define  EHCI_LINK_SITD         0x4
 194 #define  EHCI_LINK_FSTN         0x6
 195 #define EHCI_LINK_ADDR(x)       ((x) &~ 0x1f)
 196
 197 typedef u_int32_t ehci_physaddr_t;
 198
 199 /* Isochronous Transfer Descriptor */
 200 typedef struct {
 201         ehci_link_t     itd_next;
 202         /* XXX many more */
 203 } ehci_itd_t;
 204 #define EHCI_ITD_ALIGN 32
 205
 206 /* Split Transaction Isochronous Transfer Descriptor */
 207 typedef struct {
 208         ehci_link_t     sitd_next;
 209         /* XXX many more */
 210 } ehci_sitd_t;
 211 #define EHCI_SITD_ALIGN 32
 212
 213 /* Queue Element Transfer Descriptor */
 214 #define EHCI_QTD_NBUFFERS 5
 215 typedef struct {
 216         ehci_link_t     qtd_next;
 217         ehci_link_t     qtd_altnext;
 218         u_int32_t       qtd_status;
 219 #define EHCI_QTD_GET_STATUS(x)  (((x) >>  0) & 0xff)
 220 #define EHCI_QTD_SET_STATUS(x) ((x) <<  0)
 221 #define  EHCI_QTD_ACTIVE        0x80
 222 #define  EHCI_QTD_HALTED        0x40
 223 #define  EHCI_QTD_BUFERR        0x20
 224 #define  EHCI_QTD_BABBLE        0x10
 225 #define  EHCI_QTD_XACTERR       0x08
 226 #define  EHCI_QTD_MISSEDMICRO   0x04
 227 #define  EHCI_QTD_SPLITXSTATE   0x02
 228 #define  EHCI_QTD_PINGSTATE     0x01
 229 #define  EHCI_QTD_STATERRS      0x7c
 230 #define EHCI_QTD_GET_PID(x)     (((x) >>  8) & 0x3)
 231 #define EHCI_QTD_SET_PID(x)     ((x) <<  8)
 232 #define  EHCI_QTD_PID_OUT       0x0
 233 #define  EHCI_QTD_PID_IN        0x1
 234 #define  EHCI_QTD_PID_SETUP     0x2
 235 #define EHCI_QTD_GET_CERR(x)    (((x) >> 10) &  0x3)
 236 #define EHCI_QTD_SET_CERR(x)    ((x) << 10)
 237 #define EHCI_QTD_GET_C_PAGE(x)  (((x) >> 12) &  0x7)
 238 #define EHCI_QTD_SET_C_PAGE(x)  ((x) << 12)
 239 #define EHCI_QTD_GET_IOC(x)     (((x) >> 15) &  0x1)
 240 #define EHCI_QTD_IOC            0x00008000
 241 #define EHCI_QTD_GET_BYTES(x)   (((x) >> 16) &  0x7fff)
 242 #define EHCI_QTD_SET_BYTES(x)   ((x) << 16)
 243 #define EHCI_QTD_GET_TOGGLE(x)  (((x) >> 31) &  0x1)
 244 #define EHCI_QTD_SET_TOGGLE(x)  ((x) << 31)
 245 #define EHCI_QTD_TOGGLE_MASK    0x80000000
 246         ehci_physaddr_t qtd_buffer[EHCI_QTD_NBUFFERS];
 247         ehci_physaddr_t qtd_buffer_hi[EHCI_QTD_NBUFFERS];
 248 } ehci_qtd_t;
 249 #define EHCI_QTD_ALIGN 32
 250
 251 /* Queue Head */
 252 typedef struct {
 253         ehci_link_t     qh_link;
 254         u_int32_t       qh_endp;
 255 #define EHCI_QH_GET_ADDR(x)     (((x) >>  0) & 0x7f) /* endpoint addr */
 256 #define EHCI_QH_SET_ADDR(x)     (x)
 257 #define EHCI_QH_ADDRMASK        0x0000007f
 258 #define EHCI_QH_GET_INACT(x)    (((x) >>  7) & 0x01) /* inactivate on next */
 259 #define EHCI_QH_INACT           0x00000080
 260 #define EHCI_QH_GET_ENDPT(x)    (((x) >>  8) & 0x0f) /* endpoint no */
 261 #define EHCI_QH_SET_ENDPT(x)    ((x) <<  8)
 262 #define EHCI_QH_GET_EPS(x)      (((x) >> 12) & 0x03) /* endpoint speed */
 263 #define EHCI_QH_SET_EPS(x)      ((x) << 12)
 264 #define  EHCI_QH_SPEED_FULL     0x0
 265 #define  EHCI_QH_SPEED_LOW      0x1
 266 #define  EHCI_QH_SPEED_HIGH     0x2
 267 #define EHCI_QH_GET_DTC(x)      (((x) >> 14) & 0x01) /* data toggle control */
 268 #define EHCI_QH_DTC             0x00004000
 269 #define EHCI_QH_GET_HRECL(x)    (((x) >> 15) & 0x01) /* head of reclamation */
 270 #define EHCI_QH_HRECL           0x00008000
 271 #define EHCI_QH_GET_MPL(x)      (((x) >> 16) & 0x7ff) /* max packet len */
 272 #define EHCI_QH_SET_MPL(x)      ((x) << 16)
 273 #define EHCI_QH_MPLMASK         0x07ff0000
 274 #define EHCI_QH_GET_CTL(x)      (((x) >> 27) & 0x01) /* control endpoint */
 275 #define EHCI_QH_CTL             0x08000000
 276 #define EHCI_QH_GET_NRL(x)      (((x) >> 28) & 0x0f) /* NAK reload */
 277 #define EHCI_QH_SET_NRL(x)      ((x) << 28)
 278         u_int32_t       qh_endphub;
 279 #define EHCI_QH_GET_SMASK(x)    (((x) >>  0) & 0xff) /* intr sched mask */
 280 #define EHCI_QH_SET_SMASK(x)    ((x) <<  0)
 281 #define EHCI_QH_GET_CMASK(x)    (((x) >>  8) & 0xff) /* split completion mask */
 282 #define EHCI_QH_SET_CMASK(x)    ((x) <<  8)
 283 #define EHCI_QH_GET_HUBA(x)     (((x) >> 16) & 0x7f) /* hub address */
 284 #define EHCI_QH_SET_HUBA(x)     ((x) << 16)
 285 #define EHCI_QH_GET_PORT(x)     (((x) >> 23) & 0x7f) /* hub port */
 286 #define EHCI_QH_SET_PORT(x)     ((x) << 23)
 287 #define EHCI_QH_GET_MULT(x)     (((x) >> 30) & 0x03) /* pipe multiplier */
 288 #define EHCI_QH_SET_MULT(x)     ((x) << 30)
 289         ehci_link_t     qh_curqtd;
 290         ehci_qtd_t      qh_qtd;
 291 } ehci_qh_t;
 292 #define EHCI_QH_ALIGN 32
 293
 294 /* Periodic Frame Span Traversal Node */
 295 typedef struct {
 296         ehci_link_t     fstn_link;
 297         ehci_link_t     fstn_back;
 298 } ehci_fstn_t;
 299 #define EHCI_FSTN_ALIGN 32
 300
 301 #endif /* _DEV_PCI_EHCIREG_H_ */