2 * Copyright (c) 2002 Adaptec Inc.
5 * Written by: David Jeffery
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * $FreeBSD: src/sys/dev/ips/ips.h,v 1.10 2004/05/30 20:08:34 phk Exp $
29 * $DragonFly: src/sys/dev/raid/ips/ips.h,v 1.13 2006/12/22 23:26:23 swildner Exp $
33 #include <sys/param.h>
34 #include <sys/systm.h>
35 #include <sys/kernel.h>
36 #include <sys/module.h>
39 #include <sys/types.h>
40 #include <sys/thread.h>
41 #include <sys/queue.h>
43 #include <sys/malloc.h>
48 #include <sys/thread2.h>
50 #include <bus/pci/pcireg.h>
51 #include <bus/pci/pcivar.h>
53 MALLOC_DECLARE(M_IPSBUF
);
58 #define IPS_VENDOR_ID 0x1014
59 #define IPS_VENDOR_ID_ADAPTEC 0x9005
60 #define IPS_MORPHEUS_DEVICE_ID 0x01BD
61 #define IPS_COPPERHEAD_DEVICE_ID 0x002E
62 #define IPS_MARCO_DEVICE_ID 0x0250
66 /* amounts of memory to allocate for certain commands */
67 #define IPS_ADAPTER_INFO_LEN (sizeof(ips_adapter_info_t))
68 #define IPS_DRIVE_INFO_LEN (sizeof(ips_drive_info_t))
69 #define IPS_COMMAND_LEN 24
70 #define IPS_MAX_SG_LEN (sizeof(ips_sg_element_t) * IPS_MAX_SG_ELEMENTS)
71 #define IPS_NVRAM_PAGE_SIZE 128
73 #define IPS_STATIC_FLAG 1
75 /* states for the card to be in */
76 #define IPS_DEV_OPEN 0x01
77 #define IPS_TIMEOUT 0x02 /* command time out, need reset */
78 #define IPS_OFFLINE 0x04 /* can't reset card/card failure */
79 #define IPS_STATIC_BUSY 0x08 /* static command slot in use */
81 /* max number of commands set to something low for now */
82 #define IPS_MAX_CMD_NUM 128
83 #define IPS_MAX_NUM_DRIVES 8
84 #define IPS_MAX_SG_ELEMENTS 32
85 #define IPS_MAX_IOBUF_SIZE (64 * 1024)
86 #define IPS_BLKSIZE 512
88 /* logical drive states */
90 #define IPS_LD_OFFLINE 0x02
91 #define IPS_LD_OKAY 0x03
92 #define IPS_LD_DEGRADED 0x04
93 #define IPS_LD_FREE 0x00
94 #define IPS_LD_SYS 0x06
95 #define IPS_LD_CRS 0x24
97 /* register offsets */
98 #define MORPHEUS_REG_OMR0 0x0018 /* Outbound Msg. Reg. 0 */
99 #define MORPHEUS_REG_OMR1 0x001C /* Outbound Msg. Reg. 1 */
100 #define MORPHEUS_REG_IDR 0x0020 /* Inbound Doorbell Reg. */
101 #define MORPHEUS_REG_IISR 0x0024 /* Inbound IRQ Status Reg. */
102 #define MORPHEUS_REG_IIMR 0x0028 /* Inbound IRQ Mask Reg. */
103 #define MORPHEUS_REG_OISR 0x0030 /* Outbound IRQ Status Reg. */
104 #define MORPHEUS_REG_OIMR 0x0034 /* Outbound IRQ Status Reg. */
105 #define MORPHEUS_REG_IQPR 0x0040 /* Inbound Queue Port Reg. */
106 #define MORPHEUS_REG_OQPR 0x0044 /* Outbound Queue Port Reg. */
108 #define COPPER_REG_SCPR 0x05 /* Subsystem Ctrl. Port Reg. */
109 #define COPPER_REG_ISPR 0x06 /* IRQ Status Port Reg. */
110 #define COPPER_REG_CBSP 0x07 /* ? Reg. */
111 #define COPPER_REG_HISR 0x08 /* Host IRQ Status Reg. */
112 #define COPPER_REG_CCSAR 0x10 /* Cmd. Channel Sys Addr Reg.*/
113 #define COPPER_REG_CCCR 0x14 /* Cmd. Channel Ctrl. Reg. */
114 #define COPPER_REG_SQHR 0x20 /* Status Queue Head Reg. */
115 #define COPPER_REG_SQTR 0x24 /* Status Queue Tail Reg. */
116 #define COPPER_REG_SQER 0x28 /* Status Queue End Reg. */
117 #define COPPER_REG_SQSR 0x2C /* Status Queue Start Reg. */
119 /* bit definitions */
120 #define MORPHEUS_BIT_POST1 0x01
121 #define MORPHEUS_BIT_POST2 0x02
122 #define MORPHEUS_BIT_CMD_IRQ 0x08
124 #define COPPER_CMD_START 0x101A
125 #define COPPER_SEM_BIT 0x08
126 #define COPPER_EI_BIT 0x80
127 #define COPPER_EBM_BIT 0x02
128 #define COPPER_RESET_BIT 0x80
129 #define COPPER_GHI_BIT 0x04
130 #define COPPER_SCE_BIT 0x01
131 #define COPPER_OP_BIT 0x01
132 #define COPPER_ILE_BIT 0x10
135 #define IPS_POST1_OK 0x8000
136 #define IPS_POST2_OK 0x000f
138 /* command op codes */
139 #define IPS_READ_CMD 0x02
140 #define IPS_WRITE_CMD 0x03
141 #define IPS_ADAPTER_INFO_CMD 0x05
142 #define IPS_CACHE_FLUSH_CMD 0x0A
143 #define IPS_REBUILD_STATUS_CMD 0x0C
144 #define IPS_ERROR_TABLE_CMD 0x17
145 #define IPS_DRIVE_INFO_CMD 0x19
146 #define IPS_SUBSYS_PARAM_CMD 0x40
147 #define IPS_CONFIG_SYNC_CMD 0x58
148 #define IPS_SG_READ_CMD 0x82
149 #define IPS_SG_WRITE_CMD 0x83
150 #define IPS_RW_NVRAM_CMD 0xBC
151 #define IPS_FFDC_CMD 0xD7
153 /* error information returned by the adapter */
154 #define IPS_MIN_ERROR 0x02
155 #define IPS_ERROR_STATUS 0x13000200 /* ahh, magic numbers */
157 #define IPS_OS_FREEBSD 8
158 #define IPS_VERSION_MAJOR "0.90"
159 #define IPS_VERSION_MINOR ".10"
162 #define IPS_ADAPTER_COPPERHEAD 0x01
163 #define IPS_ADAPTER_COPPERHEAD2 0x02
164 #define IPS_ADAPTER_COPPERHEADOB1 0x03
165 #define IPS_ADAPTER_COPPERHEADOB2 0x04
166 #define IPS_ADAPTER_CLARINET 0x05
167 #define IPS_ADAPTER_CLARINETLITE 0x06
168 #define IPS_ADAPTER_TROMBONE 0x07
169 #define IPS_ADAPTER_MORPHEUS 0x08
170 #define IPS_ADAPTER_MORPHEUSLITE 0x09
171 #define IPS_ADAPTER_NEO 0x0A
172 #define IPS_ADAPTER_NEOLITE 0x0B
173 #define IPS_ADAPTER_SARASOTA2 0x0C
174 #define IPS_ADAPTER_SARASOTA1 0x0D
175 #define IPS_ADAPTER_MARCO 0x0E
176 #define IPS_ADAPTER_SEBRING 0x0F
177 #define IPS_ADAPTER_MAX_T IPS_ADAPTER_SEBRING
179 /* values for ffdc_settime (from gmtime) */
180 #define IPS_SECSPERMIN 60
181 #define IPS_MINSPERHOUR 60
182 #define IPS_HOURSPERDAY 24
183 #define IPS_DAYSPERWEEK 7
184 #define IPS_DAYSPERNYEAR 365
185 #define IPS_DAYSPERLYEAR 366
186 #define IPS_SECSPERHOUR (IPS_SECSPERMIN * IPS_MINSPERHOUR)
187 #define IPS_SECSPERDAY ((long) IPS_SECSPERHOUR * IPS_HOURSPERDAY)
188 #define IPS_MONSPERYEAR 12
189 #define IPS_EPOCH_YEAR 1970
190 #define IPS_LEAPS_THRU_END_OF(y) ((y) / 4 - (y) / 100 + (y) / 400)
191 #define ips_isleap(y) (((y) % 4) == 0 && (((y) % 100) != 0 || ((y) % 400) == 0))
197 /* struct buf to struct bio changes */
199 #define d_maxsize si_iosize_max
201 #if defined(PCIR_MAPS) && !defined(PCIR_BARS)
202 # define PCIR_BAR(x) (PCIR_BARS + (x) * 4)
203 # define PCIR_BARS PCIR_MAPS
211 #define ips_read_1(sc,offset) bus_space_read_1(sc->bustag, sc->bushandle, offset)
212 #define ips_read_2(sc,offset) bus_space_read_2(sc->bustag, sc->bushandle, offset)
213 #define ips_read_4(sc,offset) bus_space_read_4(sc->bustag, sc->bushandle, offset)
215 #define ips_write_1(sc,offset,value) bus_space_write_1(sc->bustag, sc->bushandle, offset, value)
216 #define ips_write_2(sc,offset,value) bus_space_write_2(sc->bustag, sc->bushandle, offset, value)
217 #define ips_write_4(sc,offset,value) bus_space_write_4(sc->bustag, sc->bushandle, offset, value)
219 #define ips_read_request(iobuf) ((bio)->bio_buf->b_cmd == BUF_CMD_READ)
221 #define COMMAND_ERROR(status) (((status)->fields.basic_status & 0x0f) >= IPS_MIN_ERROR)
224 #define DEVICE_PRINTF(x...)
227 #define DEVICE_PRINTF(level,x...) if(IPS_DEBUG >= level)device_printf(x)
228 #define PRINTF(level,x...) if(IPS_DEBUG >= level)kprintf(x)
244 } __attribute__ ((packed
)) ips_generic_cmd
;
255 } __attribute__ ((packed
)) ips_io_cmd
;
265 } __attribute__ ((packed
)) ips_rw_nvram_cmd
;
275 } __attribute__ ((packed
)) ips_drive_cmd
;
281 u_int8_t commandtype
;
285 } __attribute__((packed
)) ips_adapter_info_cmd
;
290 u_int8_t reset_count
;
296 u_int8_t reserve1
[4];
301 } __attribute__((packed
)) ips_adapter_ffdc_cmd
;
304 ips_generic_cmd generic_cmd
;
305 ips_drive_cmd drive_cmd
;
306 ips_adapter_info_cmd adapter_info_cmd
;
312 u_int8_t adapter_slot
;
313 u_int16_t adapter_type
;
314 u_int8_t bios_high
[4];
315 u_int8_t bios_low
[4];
318 u_int8_t operating_system
;
319 u_int8_t driver_high
[4];
320 u_int8_t driver_low
[4];
321 u_int8_t reserve4
[100];
322 } __attribute__((packed
)) ips_nvram_page5
;
334 u_int32_t sector_count
;
335 } __attribute__((packed
)) ips_drive_t
;
341 ips_drive_t drives
[IPS_MAX_NUM_DRIVES
];
342 } __attribute__((packed
)) ips_drive_info_t
;
349 u_int8_t pwr_chg_count
;
350 u_int8_t wrong_addr_count
;
351 u_int8_t unident_count
;
352 u_int8_t nvram_dev_chg_count
;
353 u_int8_t codeblock_version
[8];
354 u_int8_t bootblock_version
[8];
355 u_int32_t drive_sector_count
[IPS_MAX_NUM_DRIVES
];
356 u_int8_t max_concurrent_cmds
;
357 u_int8_t max_phys_devices
;
358 u_int16_t flash_prog_count
;
359 u_int8_t defunct_disks
;
360 u_int8_t rebuildflags
;
361 u_int8_t offline_drivecount
;
362 u_int8_t critical_drivecount
;
363 u_int16_t config_update_count
;
364 u_int8_t blockedflags
;
366 u_int16_t addr_dead_disk
[4*16]; /* ugly, max # channels * max # scsi devices per channel */
367 } __attribute__((packed
)) ips_adapter_info_t
;
370 u_int32_t status
[IPS_MAX_CMD_NUM
];
371 u_int32_t base_phys_addr
;
373 bus_dma_tag_t dmatag
;
375 } ips_copper_queue_t
;
381 u_int8_t basic_status
;
382 u_int8_t extended_status
;
384 volatile u_int32_t value
;
387 /* used to keep track of current commands to the card */
388 typedef struct ips_command
{
389 u_int8_t command_number
;
392 struct ips_softc
*sc
;
393 bus_dmamap_t command_dmamap
;
394 void *command_buffer
;
395 u_int32_t command_phys_addr
; /*WARNING! must be changed if 64bit addressing ever used*/
396 bus_dma_tag_t data_dmatag
;
397 bus_dmamap_t data_dmamap
;
398 /* members below are zero'd when handed out */
399 ips_cmd_status_t status
;
400 SLIST_ENTRY(ips_command
) next
;
403 void (*callback
)(struct ips_command
*command
);
407 typedef struct ips_wait_list
{
408 STAILQ_ENTRY(ips_wait_list
) next
;
410 int (* callback
)(ips_command_t
*command
);
413 typedef struct ips_softc
{
414 struct resource
*iores
;
415 struct resource
*irqres
;
416 struct intr_config_hook ips_ich
;
423 bus_space_tag_t bustag
;
424 bus_space_handle_t bushandle
;
425 bus_dma_tag_t adapter_dmatag
;
426 bus_dma_tag_t command_dmatag
;
427 bus_dma_tag_t sg_dmatag
;
429 struct callout timer
;
430 u_int16_t adapter_type
;
431 ips_adapter_info_t adapter_info
;
432 device_t diskdev
[IPS_MAX_NUM_DRIVES
];
433 ips_drive_t drives
[IPS_MAX_NUM_DRIVES
];
435 u_int16_t ffdc_resetcount
;
436 struct timeval ffdc_resettime
;
439 volatile u_int8_t used_commands
;
440 ips_command_t
*commandarray
;
441 ips_command_t
*staticcmd
;
442 SLIST_HEAD(command_list
, ips_command
) free_cmd_list
;
443 int (*ips_adapter_reinit
)(struct ips_softc
*sc
,
445 void (*ips_adapter_intr
)(void *sc
);
446 void (*ips_issue_cmd
)(ips_command_t
*command
);
447 void (*ips_poll_cmd
)(ips_command_t
*command
);
448 ips_copper_queue_t
*copper_queue
;
450 struct lock queue_lock
;
451 struct bio_queue_head bio_queue
;
454 /* function defines from ips_ioctl.c */
455 extern int ips_ioctl_request(ips_softc_t
*sc
, u_long ioctl_cmd
, caddr_t addr
,
457 /* function defines from ips_disk.c */
458 extern void ipsd_finish(struct bio
*iobuf
);
460 /* function defines from ips_commands.c */
461 extern int ips_flush_cache(ips_softc_t
*sc
);
462 extern void ips_start_io_request(ips_softc_t
*sc
);
463 extern int ips_get_drive_info(ips_softc_t
*sc
);
464 extern int ips_get_adapter_info(ips_softc_t
*sc
);
465 extern int ips_ffdc_reset(ips_softc_t
*sc
);
466 extern int ips_update_nvram(ips_softc_t
*sc
);
467 extern int ips_clear_adapter(ips_softc_t
*sc
);
469 /* function defines from ips.c */
470 extern int ips_get_free_cmd(ips_softc_t
*sc
, ips_command_t
**command
,
471 unsigned long flags
);
472 extern void ips_insert_free_cmd(ips_softc_t
*sc
, ips_command_t
*command
);
473 extern int ips_adapter_init(ips_softc_t
*sc
);
474 extern int ips_morpheus_reinit(ips_softc_t
*sc
, int force
);
475 extern int ips_adapter_free(ips_softc_t
*sc
);
476 extern void ips_morpheus_intr(void *sc
);
477 extern void ips_issue_morpheus_cmd(ips_command_t
*command
);
478 extern void ips_morpheus_poll(ips_command_t
*command
);
479 extern int ips_copperhead_reinit(ips_softc_t
*sc
, int force
);
480 extern void ips_copperhead_intr(void *sc
);
481 extern void ips_issue_copperhead_cmd(ips_command_t
*command
);
482 extern void ips_copperhead_poll(ips_command_t
*command
);
483 int ips_timed_wait(ips_command_t
*, const char *, int);
485 #define IPS_CDEV_MAJOR 175
486 #define IPSD_CDEV_MAJOR 176