sys/dev/disk/aha/ahareg.h

   1 /*
   2  * Generic register and struct definitions for the Adaptech 154x/164x
   3  * SCSI host adapters. Product specific probe and attach routines can
   4  * be found in:
   5  *      <fill in list here>
   6  *
   7  * Derived from bt.c written by:
   8  *
   9  * Copyright (c) 1998 Justin T. Gibbs.
  10  * All rights reserved.
  11  *
  12  * Redistribution and use in source and binary forms, with or without
  13  * modification, are permitted provided that the following conditions
  14  * are met:
  15  * 1. Redistributions of source code must retain the above copyright
  16  *    notice, this list of conditions, and the following disclaimer,
  17  *    without modification, immediately at the beginning of the file.
  18  * 2. The name of the author may not be used to endorse or promote products
  19  *    derived from this software without specific prior written permission.
  20  *
  21  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  22  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  24  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
  25  * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  26  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  27  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  28  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  29  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  30  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  31  * SUCH DAMAGE.
  32  *
  33  * $FreeBSD: src/sys/dev/aha/ahareg.h,v 1.8.2.1 2000/08/02 22:24:40 peter Exp $
  34  * $DragonFly: src/sys/dev/disk/aha/ahareg.h,v 1.4 2005/09/11 13:03:16 sephe Exp $
  35  */
  36
  37 #ifndef _AHAREG_H_
  38 #define _AHAREG_H_
  39
  40 #include "use_aha.h"
  41
  42 #include <sys/queue.h>
  43 #include <bus/cam/scsi/scsi_all.h>
  44
  45 #define AHA_MAXTRANSFER_SIZE     0xffffff       /* limited by 24bit counter */
  46 #define AHA_NSEG                17      /* The number of dma segments
  47                                          * supported. */
  48 #define ALL_TARGETS (~0)
  49
  50 /*
  51  * Control Register pp. 1-8, 1-9 (Write Only)
  52  */
  53 #define CONTROL_REG             0x00
  54 #define         HARD_RESET      0x80    /* Hard Reset - return to POST state */
  55 #define         SOFT_RESET      0x40    /* Soft Reset - Clears Adapter state */
  56 #define         RESET_INTR      0x20    /* Reset/Ack Interrupt */
  57 #define         RESET_SBUS      0x10    /* Drive SCSI bus reset signal */
  58
  59 /*
  60  * Status Register pp. 1-9, 1-10 (Read Only)
  61  */
  62 #define STATUS_REG                      0x00
  63 #define         DIAG_ACTIVE             0x80    /* Performing Internal Diags */
  64 #define         DIAG_FAIL               0x40    /* Internal Diags failed */
  65 #define         INIT_REQUIRED           0x20    /* MBOXes need initialization */
  66 #define         HA_READY                0x10    /* HA ready for new commands */
  67 #define         CMD_REG_BUSY            0x08    /* HA busy with last cmd byte */
  68 #define         DATAIN_REG_READY        0x04    /* Data-in Byte available */
  69 #define         STATUS_REG_RSVD         0x02
  70 #define         CMD_INVALID             0x01    /* Invalid Command detected */
  71
  72 /*
  73  * Command/Parameter Register pp. 1-10, 1-11 (Write Only)
  74  */
  75 #define COMMAND_REG                     0x01
  76
  77 /*
  78  * Data in Register p. 1-11 (Read Only)
  79  */
  80 #define DATAIN_REG                      0x01
  81
  82 /*
  83  * Interrupt Status Register pp. 1-12 -> 1-14 (Read Only)
  84  */
  85 #define INTSTAT_REG                     0x02
  86 #define         INTR_PENDING            0x80    /* There is a pending INTR */
  87 #define         INTSTAT_REG_RSVD        0x70
  88 #define         SCSI_BUS_RESET          0x08    /* Bus Reset detected */
  89 #define         CMD_COMPLETE            0x04
  90 #define         OMB_READY               0x02    /* Outgoin Mailbox Ready */
  91 #define         IMB_LOADED              0x01    /* Incoming Mailbox loaded */
  92
  93 /*
  94  * Definitions for the "undocumented" geometry register, we just need
  95  * its location.
  96  */
  97 #define GEOMETRY_REG                    0x03
  98
  99 #define AHA_NREGS       (4)
 100
 101 /*
 102  * Opcodes for Adapter commands.
 103  */
 104 typedef enum {
 105         AOP_NOP                 = 0x00,
 106         AOP_INITIALIZE_MBOX     = 0x01,
 107         AOP_START_MBOX          = 0x02,
 108         AOP_EXECUTE_BIOS_CMD    = 0x03,
 109         AOP_INQUIRE_BOARD_ID    = 0x04,
 110         AOP_ENABLE_OMBR_INT     = 0x05,
 111         AOP_SET_SEL_TIMOUT      = 0x06,
 112         AOP_SET_TIME_ON_BUS     = 0x07,
 113         AOP_SET_TIME_OFF_BUS    = 0x08,
 114         AOP_SET_BUS_TRANS_RATE  = 0x09,
 115         AOP_INQUIRE_INST_LDEVS  = 0x0A,
 116         AOP_INQUIRE_CONFIG      = 0x0B,
 117         AOP_ENABLE_TARGET_MODE  = 0x0C,
 118         AOP_INQUIRE_SETUP_INFO  = 0x0D,
 119         AOP_WRITE_LRAM          = 0x1A,
 120         AOP_READ_LRAM           = 0x1B,
 121         AOP_WRITE_CHIP_FIFO     = 0x1C,
 122         AOP_READ_CHIP_FIFO      = 0x1D,
 123         AOP_ECHO_DATA_BYTE      = 0x1F,
 124         AOP_ADAPTER_DIAGNOSTICS = 0x20,
 125         AOP_SET_ADAPTER_OPTIONS = 0x21,
 126         AOP_SET_EEPROM          = 0x22,
 127         AOP_RETURN_EEPROM       = 0x23,
 128         AOP_ENABLE_SHADOW_RAM   = 0x24,
 129         AOP_INIT_BIOS_MBOX      = 0x25,
 130         AOP_SET_BIOS_BANK_1     = 0x26,
 131         AOP_SET_BIOS_BANK_2     = 0x27,
 132         AOP_RETURN_EXT_BIOS_INFO= 0x28,
 133         AOP_MBOX_IF_ENABLE      = 0x29,
 134         AOP_SCSI_TERM_STATUS    = 0x2C,
 135         AOP_INQUIRE_SCAM_DEV    = 0x2D,
 136         AOP_SCSI_DEV_TABLE      = 0x2E,
 137         AOP_SCAM_OP             = 0x2F,
 138         AOP_START_BIOS_CMD      = 0x82,
 139         AOP_INQUIRE_ESETUP_INFO = 0x8D
 140 } aha_op_t;
 141
 142 /************** Definitions of Multi-byte commands and responses ************/
 143
 144 struct  aha_extbios
 145 {
 146         u_int8_t flags;                 /* Bit 3 == 1 extended bios enabled */
 147         u_int8_t mailboxlock;           /* mail box lock code to unlock it */
 148 };
 149
 150 typedef struct {
 151         u_int8_t num_mboxes;
 152         u_int8_t base_addr[3];
 153 } init_24b_mbox_params_t;
 154
 155 typedef struct {
 156         u_int8_t board_type;
 157 /* These values are mostly from the aha-1540CP technical reference, but */
 158 /* with other values from the old aha1542.c driver. The values from the */
 159 /* aha-1540CP technical manual are used where conflicts arise */
 160 #define         BOARD_1540_16HEAD_BIOS  0x00
 161 #define         BOARD_1540_64HEAD_BIOS  0x30
 162 #define         BOARD_1542              0x41    /* aha-1540/1542 w/64-h bios */
 163 #define         BOARD_1640              0x42    /* aha-1640 */
 164 #define         BOARD_1740              0x43    /* aha-1740A/1742A/1744 */
 165 #define         BOARD_1542C             0x44    /* aha-1542C */
 166 #define         BOARD_1542CF            0x45    /* aha-1542CF */
 167 #define         BOARD_1542CP            0x46    /* aha-1542CP, plug and play */
 168         u_int8_t cust_features;
 169 #define         FEATURES_STANDARD       0x30
 170         u_int8_t firmware_rev_major;
 171         u_int8_t firmware_rev_minor;
 172 } board_id_data_t;
 173
 174 typedef struct {
 175         u_int8_t dma_chan;
 176 #define         DMA_CHAN_5      0x20
 177 #define         DMA_CHAN_6      0x40
 178 #define         DMA_CHAN_7      0x80
 179         u_int8_t irq;
 180 #define         IRQ_9           0x01
 181 #define         IRQ_10          0x02
 182 #define         IRQ_11          0x04
 183 #define         IRQ_12          0x08
 184 #define         IRQ_14          0x20
 185 #define         IRQ_15          0x40
 186         u_int8_t scsi_id;
 187 } config_data_t;
 188
 189 typedef struct {
 190         u_int8_t enable;
 191 } target_mode_params_t;
 192
 193 typedef struct {
 194         u_int8_t offset : 4,
 195                  period : 3,
 196                  sync   : 1;
 197 } targ_syncinfo_t;
 198
 199 typedef struct {
 200         u_int8_t        initiate_sync   : 1,
 201                         parity_enable   : 1,
 202                                         : 6;
 203
 204         u_int8_t        bus_transfer_rate;
 205         u_int8_t        time_on_bus;
 206         u_int8_t        time_off_bus;
 207         u_int8_t        num_mboxes;
 208         u_int8_t        mbox_base_addr[3];
 209         targ_syncinfo_t syncinfo[8];
 210         u_int8_t        discinfo;
 211         u_int8_t        customer_sig[20];
 212         u_int8_t        auto_retry;
 213         u_int8_t        board_switches;
 214         u_int8_t        firmware_cksum[2];
 215         u_int8_t        bios_mbox_addr[3];
 216 } setup_data_t;
 217
 218 struct aha_isa_port {
 219         u_int16_t addr;
 220         u_int8_t  bio;  /* board IO offset */
 221 };
 222
 223 #define AHA_NUM_ISAPORTS 6
 224
 225 typedef enum {
 226         BIO_330         = 0,
 227         BIO_334         = 1,
 228         BIO_230         = 2,
 229         BIO_234         = 3,
 230         BIO_130         = 4,
 231         BIO_134         = 5,
 232         BIO_DISABLED    = 6,
 233         BIO_DISABLED2   = 7
 234 } isa_compat_io_t;
 235
 236 typedef struct {
 237         u_int8_t sync_rate[16];         /* Sync in 10ns units */
 238 } target_sync_info_data_t;
 239
 240 typedef struct {
 241         u_int8_t len[3];
 242         u_int8_t addr[3];
 243 } aha_sg_t;
 244
 245 /********************** Mail Box definitions *******************************/
 246
 247 typedef enum {
 248         AMBO_FREE               = 0x0,  /* MBO intry is free */
 249         AMBO_START              = 0x1,  /* MBO activate entry */
 250         AMBO_ABORT              = 0x2   /* MBO abort entry */
 251 } aha_mbo_action_code_t;
 252
 253 typedef struct aha_mbox_out {
 254         u_int8_t  action_code;
 255         u_int8_t  ccb_addr[3];
 256 } aha_mbox_out_t;
 257
 258 typedef enum {
 259         AMBI_FREE               = 0x0,  /* MBI entry is free */
 260         AMBI_OK                 = 0x1,  /* completed without error */
 261         AMBI_ABORT              = 0x2,  /* aborted ccb */
 262         AMBI_NOT_FOUND          = 0x3,  /* Tried to abort invalid CCB */
 263         AMBI_ERROR              = 0x4   /* Completed with error */
 264 } aha_mbi_comp_code_t;
 265
 266 typedef struct aha_mbox_in {
 267         u_int8_t  comp_code;
 268         u_int8_t  ccb_addr[3];
 269 } aha_mbox_in_t;
 270
 271 /****************** Hardware CCB definition *********************************/
 272 typedef enum {
 273         INITIATOR_CCB           = 0x00,
 274         INITIATOR_SG_CCB        = 0x02,
 275         INITIATOR_CCB_WRESID    = 0x03,
 276         INITIATOR_SG_CCB_WRESID = 0x04,
 277         INITIATOR_BUS_DEV_RESET = 0x81
 278 } aha_ccb_opcode_t;
 279
 280 typedef enum {
 281         AHASTAT_NOERROR                 = 0x00,
 282         AHASTAT_SELTIMEOUT              = 0x11,
 283         AHASTAT_DATARUN_ERROR           = 0x12,
 284         AHASTAT_UNEXPECTED_BUSFREE      = 0x13,
 285         AHASTAT_INVALID_PHASE           = 0x14,
 286         AHASTAT_INVALID_ACTION_CODE     = 0x15,
 287         AHASTAT_INVALID_OPCODE          = 0x16,
 288         AHASTAT_LINKED_CCB_LUN_MISMATCH = 0x17,
 289         AHASTAT_INVALID_CCB_OR_SG_PARAM = 0x1A,
 290         AHASTAT_HA_SCSI_BUS_RESET       = 0x22, /* stolen from bt */
 291         AHASTAT_HA_BDR                  = 0x25  /* Stolen from bt */
 292 } ahastat_t;
 293
 294 struct aha_hccb {
 295         u_int8_t  opcode;                       /* 0 */
 296         u_int8_t  lun           : 3,            /* 1 */
 297                   datain        : 1,
 298                   dataout       : 1,
 299                   target        : 3;
 300         u_int8_t  cmd_len;                      /* 2 */
 301         u_int8_t  sense_len;                    /* 3 */
 302         u_int8_t  data_len[3];                  /* 4 */
 303         u_int8_t  data_addr[3];                 /* 7 */
 304         u_int8_t  link_ptr[3];                  /* 10 */
 305         u_int8_t  link_id;                      /* 13 */
 306         u_int8_t  ahastat;                      /* 14 */
 307         u_int8_t  sdstat;                       /* 15 */
 308         u_int8_t  reserved1;                    /* 16 */
 309         u_int8_t  reserved2;                    /* 17 */
 310         u_int8_t  scsi_cdb[16];                 /* 18 */
 311         u_int8_t  sense_data[SSD_FULL_SIZE];
 312 };
 313
 314 typedef enum {
 315         ACCB_FREE               = 0x0,
 316         ACCB_ACTIVE             = 0x1,
 317         ACCB_DEVICE_RESET       = 0x2,
 318         ACCB_RELEASE_SIMQ       = 0x4
 319 } accb_flags_t;
 320
 321 struct aha_ccb {
 322         struct  aha_hccb         hccb;          /* hccb assumed to be at 0 */
 323         SLIST_ENTRY(aha_ccb)     links;
 324         u_int32_t                flags;
 325         union ccb               *ccb;
 326         bus_dmamap_t             dmamap;
 327         aha_sg_t                *sg_list;
 328         u_int32_t                sg_list_phys;
 329 };
 330
 331 struct sg_map_node {
 332         bus_dmamap_t             sg_dmamap;
 333         bus_addr_t               sg_physaddr;
 334         aha_sg_t*                sg_vaddr;
 335         SLIST_ENTRY(sg_map_node) links;
 336 };
 337
 338 struct aha_softc {
 339         bus_space_tag_t          tag;
 340         bus_space_handle_t       bsh;
 341         struct  cam_sim         *sim;
 342         struct  cam_path        *path;
 343         aha_mbox_out_t          *cur_outbox;
 344         aha_mbox_in_t           *cur_inbox;
 345         aha_mbox_out_t          *last_outbox;
 346         aha_mbox_in_t           *last_inbox;
 347         struct  aha_ccb         *aha_ccb_array;
 348         SLIST_HEAD(,aha_ccb)     free_aha_ccbs;
 349         LIST_HEAD(,ccb_hdr)      pending_ccbs;
 350         u_int                    active_ccbs;
 351         u_int32_t                aha_ccb_physbase;
 352         aha_ccb_opcode_t         ccb_sg_opcode;
 353         aha_ccb_opcode_t         ccb_ccb_opcode;
 354         aha_mbox_in_t           *in_boxes;
 355         aha_mbox_out_t          *out_boxes;
 356         struct scsi_sense_data  *sense_buffers;
 357         u_int32_t                sense_buffers_physbase;
 358         struct  aha_ccb         *recovery_accb;
 359         u_int                    num_boxes;
 360         bus_dma_tag_t            parent_dmat;   /*
 361                                                  * All dmat's derive from
 362                                                  * the dmat defined by our
 363                                                  * bus.
 364                                                  */
 365         bus_dma_tag_t            buffer_dmat;   /* dmat for buffer I/O */
 366         bus_dma_tag_t            mailbox_dmat;  /* dmat for our mailboxes */
 367         bus_dmamap_t             mailbox_dmamap;
 368         bus_dma_tag_t            ccb_dmat;      /* dmat for our ccb array */
 369         bus_dmamap_t             ccb_dmamap;
 370         bus_dma_tag_t            sg_dmat;       /* dmat for our sg maps */
 371         SLIST_HEAD(, sg_map_node) sg_maps;
 372         bus_addr_t               mailbox_physbase;
 373         u_int                    num_ccbs;      /* Number of CCBs malloc'd */
 374         u_int                    max_ccbs;      /* Maximum allocatable CCBs */
 375         u_int                    max_sg;
 376         u_int                    scsi_id;
 377         u_int32_t                extended_trans   :1,
 378                                  diff_bus         :1,
 379                                  extended_lun     :1,
 380                                  strict_rr        :1,
 381                                  tag_capable      :1,
 382                                  resource_shortage:1,
 383                                                   :26;
 384         u_int16_t                disc_permitted;
 385         u_int16_t                sync_permitted;
 386         u_int8_t                 init_level;
 387         volatile u_int8_t        command_cmp;
 388         volatile u_int8_t        latched_status;
 389         u_int32_t                bios_addr;
 390         u_int8_t                 fw_major;
 391         u_int8_t                 fw_minor;
 392         char                     model[32];
 393         u_int8_t                 boardid;
 394         struct resource         *irq;
 395         int                      irqrid;
 396         struct resource         *port;
 397         int                      portrid;
 398         struct resource         *drq;
 399         int                      drqrid;
 400         void                    **ih;
 401         device_t                dev;
 402 };
 403
 404 extern struct aha_softc *aha_softcs[];  /* XXX Config should handle this */
 405 extern u_long aha_unit;
 406
 407 #define AHA_TEMP_UNIT 0xFF              /* Unit for probes */
 408 struct aha_softc*       aha_alloc(device_t, bus_space_tag_t, bus_space_handle_t);
 409 int                     aha_attach(struct aha_softc *);
 410 int                     aha_cmd(struct aha_softc *, aha_op_t, u_int8_t *,
 411                             u_int, u_int8_t *, u_int, u_int);
 412 int                     aha_detach(struct aha_softc *);
 413 int                     aha_fetch_adapter_info(struct aha_softc *);
 414 void                    aha_find_probe_range(int, int *, int *);
 415 void                    aha_free(struct aha_softc *);
 416 int                     aha_init(struct aha_softc *);
 417 void                    aha_intr(void *);
 418 int                     aha_iop_from_bio(isa_compat_io_t);
 419 char *                  aha_name(struct aha_softc *);
 420 int                     aha_probe(struct aha_softc *);
 421
 422 #define DEFAULT_CMD_TIMEOUT 10000       /* 1 sec */
 423
 424 #define aha_inb(aha, port)                              \
 425         bus_space_read_1((aha)->tag, (aha)->bsh, port)
 426
 427 #define aha_outb(aha, port, value)                      \
 428         bus_space_write_1((aha)->tag, (aha)->bsh, port, value)
 429
 430 /* XXX BAD */
 431 #define EXTRA_AHA 4
 432 #define NAHATOT (NAHA + EXTRA_AHA)
 433
 434 #define ADP0100_PNP             0x00019004      /* ADP0100 */
 435 #define AHA1540_PNP             0x40159004      /* ADP1540 */
 436 #define AHA1542_PNP             0x42159004      /* ADP1542 */
 437 #define AHA1542_PNPCOMPAT       0xA000D040      /* PNP00A0 */
 438 #define ICU0091_PNP             0X91005AA4      /* ICU0091 */
 439
 440 #endif  /* _AHA_H_ */