sys/dev/agp/agp_intel.c

   1 /*-
   2  * Copyright (c) 2000 Doug Rabson
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  * 1. Redistributions of source code must retain the above copyright
   9  *    notice, this list of conditions and the following disclaimer.
  10  * 2. Redistributions in binary form must reproduce the above copyright
  11  *    notice, this list of conditions and the following disclaimer in the
  12  *    documentation and/or other materials provided with the distribution.
  13  *
  14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  15  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  16  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  17  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  18  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  19  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  20  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  21  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  22  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  23  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  24  * SUCH DAMAGE.
  25  *
  26  *      $FreeBSD: src/sys/dev/agp/agp_intel.c,v 1.36 2007/11/12 21:51:36 jhb Exp $
  27  *      $DragonFly: src/sys/dev/agp/agp_intel.c,v 1.10 2008/01/07 01:34:58 corecode Exp $
  28  */
  29
  30 #include "opt_bus.h"
  31
  32 #include <sys/param.h>
  33 #include <sys/systm.h>
  34 #include <sys/malloc.h>
  35 #include <sys/kernel.h>
  36 #include <sys/bus.h>
  37 #include <sys/lock.h>
  38
  39 #include <bus/pci/pcivar.h>
  40 #include <bus/pci/pcireg.h>
  41 #include "agppriv.h"
  42 #include "agpreg.h"
  43
  44 #include <vm/vm.h>
  45 #include <vm/vm_object.h>
  46 #include <vm/pmap.h>
  47
  48 #define MAX_APSIZE      0x3f            /* 256 MB */
  49
  50 struct agp_intel_softc {
  51         struct agp_softc agp;
  52         u_int32_t       initial_aperture; /* aperture size at startup */
  53         struct agp_gatt *gatt;
  54         u_int           aperture_mask;
  55         u_int32_t       current_aperture; /* current aperture size */
  56 };
  57
  58 static const char*
  59 agp_intel_match(device_t dev)
  60 {
  61         if (pci_get_class(dev) != PCIC_BRIDGE
  62             || pci_get_subclass(dev) != PCIS_BRIDGE_HOST)
  63                 return (NULL);
  64
  65         if (agp_find_caps(dev) == 0)
  66                 return (NULL);
  67
  68         switch (pci_get_devid(dev)) {
  69         /* Intel -- vendor 0x8086 */
  70         case 0x71808086:
  71                 return ("Intel 82443LX (440 LX) host to PCI bridge");
  72         case 0x71908086:
  73                 return ("Intel 82443BX (440 BX) host to PCI bridge");
  74         case 0x71a08086:
  75                 return ("Intel 82443GX host to PCI bridge");
  76         case 0x71a18086:
  77                 return ("Intel 82443GX host to AGP bridge");
  78         case 0x11308086:
  79                 return ("Intel 82815 (i815 GMCH) host to PCI bridge");
  80         case 0x25008086:
  81         case 0x25018086:
  82                 return ("Intel 82820 host to AGP bridge");
  83         case 0x35758086:
  84                 return ("Intel 82830 host to AGP bridge");
  85         case 0x1a218086:
  86                 return ("Intel 82840 host to AGP bridge");
  87         case 0x1a308086:
  88                 return ("Intel 82845 host to AGP bridge");
  89         case 0x25308086:
  90                 return ("Intel 82850 host to AGP bridge");
  91         case 0x33408086:
  92                 return ("Intel 82855 host to AGP bridge");
  93         case 0x25318086:
  94                 return ("Intel 82860 host to AGP bridge");
  95         case 0x25708086:
  96                 return ("Intel 82865 host to AGP bridge");
  97         case 0x255d8086:
  98                 return ("Intel E7205 host to AGP bridge");
  99         case 0x25508086:
 100                 return ("Intel E7505 host to AGP bridge");
 101         case 0x25788086:
 102                 return ("Intel 82875P host to AGP bridge");
 103         case 0x25608086:
 104                 return ("Intel 82845G host to AGP bridge");
 105         case 0x35808086:
 106                 return ("Intel 82855GM host to AGP bridge");
 107         };
 108
 109         return (NULL);
 110 }
 111
 112 static int
 113 agp_intel_probe(device_t dev)
 114 {
 115         const char *desc;
 116
 117         if (resource_disabled("agp", device_get_unit(dev)))
 118                 return (ENXIO);
 119         desc = agp_intel_match(dev);
 120         if (desc) {
 121                 device_verbose(dev);
 122                 device_set_desc(dev, desc);
 123                 return (BUS_PROBE_DEFAULT);
 124         }
 125
 126         return (ENXIO);
 127 }
 128
 129 static void
 130 agp_intel_commit_gatt(device_t dev)
 131 {
 132         struct agp_intel_softc *sc;
 133         u_int32_t type;
 134         u_int32_t value;
 135
 136         sc = device_get_softc(dev);
 137         type = pci_get_devid(dev);
 138
 139         /* Install the gatt. */
 140         pci_write_config(dev, AGP_INTEL_ATTBASE, sc->gatt->ag_physical, 4);
 141
 142         /* Enable the GLTB and setup the control register. */
 143         switch (type) {
 144         case 0x71908086: /* 440LX/EX */
 145                 pci_write_config(dev, AGP_INTEL_AGPCTRL, 0x2080, 4);
 146                 break;
 147         case 0x71808086: /* 440BX */
 148                 /*
 149                  * XXX: Should be 0xa080?  Bit 9 is undefined, and
 150                  * bit 13 being on and bit 15 being clear is illegal.
 151                  */
 152                 pci_write_config(dev, AGP_INTEL_AGPCTRL, 0x2280, 4);
 153                 break;
 154         default:
 155                 value = pci_read_config(dev, AGP_INTEL_AGPCTRL, 4);
 156                 pci_write_config(dev, AGP_INTEL_AGPCTRL, value | 0x80, 4);
 157         }
 158
 159         /* Enable aperture accesses. */
 160         switch (type) {
 161         case 0x25008086: /* i820 */
 162         case 0x25018086: /* i820 */
 163                 pci_write_config(dev, AGP_INTEL_I820_RDCR,
 164                                  (pci_read_config(dev, AGP_INTEL_I820_RDCR, 1)
 165                                   | (1 << 1)), 1);
 166                 break;
 167         case 0x1a308086: /* i845 */
 168         case 0x25608086: /* i845G */
 169         case 0x33408086: /* i855 */
 170         case 0x35808086: /* i855GM */
 171         case 0x25708086: /* i865 */
 172         case 0x25788086: /* i875P */
 173                 pci_write_config(dev, AGP_INTEL_I845_AGPM,
 174                                  (pci_read_config(dev, AGP_INTEL_I845_AGPM, 1)
 175                                   | (1 << 1)), 1);
 176                 break;
 177         case 0x1a218086: /* i840 */
 178         case 0x25308086: /* i850 */
 179         case 0x25318086: /* i860 */
 180         case 0x255d8086: /* E7205 */
 181         case 0x25508086: /* E7505 */
 182                 pci_write_config(dev, AGP_INTEL_MCHCFG,
 183                                  (pci_read_config(dev, AGP_INTEL_MCHCFG, 2)
 184                                   | (1 << 9)), 2);
 185                 break;
 186         default: /* Intel Generic (maybe) */
 187                 pci_write_config(dev, AGP_INTEL_NBXCFG,
 188                                  (pci_read_config(dev, AGP_INTEL_NBXCFG, 4)
 189                                   & ~(1 << 10)) | (1 << 9), 4);
 190         }
 191
 192         /* Clear errors. */
 193         switch (type) {
 194         case 0x1a218086: /* i840 */
 195                 pci_write_config(dev, AGP_INTEL_I8XX_ERRSTS, 0xc000, 2);
 196                 break;
 197         case 0x25008086: /* i820 */
 198         case 0x25018086: /* i820 */
 199         case 0x1a308086: /* i845 */
 200         case 0x25608086: /* i845G */
 201         case 0x25308086: /* i850 */
 202         case 0x33408086: /* i855 */
 203         case 0x25318086: /* i860 */
 204         case 0x25708086: /* i865 */
 205         case 0x25788086: /* i875P */
 206         case 0x255d8086: /* E7205 */
 207         case 0x25508086: /* E7505 */
 208                 pci_write_config(dev, AGP_INTEL_I8XX_ERRSTS, 0x00ff, 2);
 209                 break;
 210         default: /* Intel Generic (maybe) */
 211                 pci_write_config(dev, AGP_INTEL_ERRSTS + 1, 7, 1);
 212         }
 213 }
 214
 215 static int
 216 agp_intel_attach(device_t dev)
 217 {
 218         struct agp_intel_softc *sc;
 219         struct agp_gatt *gatt;
 220         u_int32_t value;
 221         int error;
 222
 223         sc = device_get_softc(dev);
 224
 225         error = agp_generic_attach(dev);
 226         if (error)
 227                 return (error);
 228
 229         /* Determine maximum supported aperture size. */
 230         value = pci_read_config(dev, AGP_INTEL_APSIZE, 1);
 231         pci_write_config(dev, AGP_INTEL_APSIZE, MAX_APSIZE, 1);
 232         sc->aperture_mask = pci_read_config(dev, AGP_INTEL_APSIZE, 1) &
 233             MAX_APSIZE;
 234         pci_write_config(dev, AGP_INTEL_APSIZE, value, 1);
 235         sc->current_aperture = sc->initial_aperture = AGP_GET_APERTURE(dev);
 236         if (sc->initial_aperture == 0) {
 237                 device_printf(dev, "bad initial aperture size, disabling\n");
 238                 return ENXIO;
 239         }
 240
 241         for (;;) {
 242                 gatt = agp_alloc_gatt(dev);
 243                 if (gatt)
 244                         break;
 245
 246                 /*
 247                  * Probably contigmalloc failure. Try reducing the
 248                  * aperture so that the gatt size reduces.
 249                  */
 250                 if (AGP_SET_APERTURE(dev, AGP_GET_APERTURE(dev) / 2)) {
 251                         agp_generic_detach(dev);
 252                         return (ENOMEM);
 253                 }
 254         }
 255         sc->gatt = gatt;
 256
 257         agp_intel_commit_gatt(dev);
 258
 259         return (0);
 260 }
 261
 262 static int
 263 agp_intel_detach(device_t dev)
 264 {
 265         struct agp_intel_softc *sc;
 266         u_int32_t reg;
 267
 268         sc = device_get_softc(dev);
 269
 270         agp_free_cdev(dev);
 271
 272         /* Disable aperture accesses. */
 273         switch (pci_get_devid(dev)) {
 274         case 0x25008086: /* i820 */
 275         case 0x25018086: /* i820 */
 276                 reg = pci_read_config(dev, AGP_INTEL_I820_RDCR, 1) & ~(1 << 1);
 277                 kprintf("%s: set RDCR to %02x\n", __func__, reg & 0xff);
 278                 pci_write_config(dev, AGP_INTEL_I820_RDCR, reg, 1);
 279                 break;
 280         case 0x1a308086: /* i845 */
 281         case 0x25608086: /* i845G */
 282         case 0x33408086: /* i855 */
 283         case 0x35808086: /* i855GM */
 284         case 0x25708086: /* i865 */
 285         case 0x25788086: /* i875P */
 286                 reg = pci_read_config(dev, AGP_INTEL_I845_AGPM, 1) & ~(1 << 1);
 287                 kprintf("%s: set AGPM to %02x\n", __func__, reg & 0xff);
 288                 pci_write_config(dev, AGP_INTEL_I845_AGPM, reg, 1);
 289                 break;
 290         case 0x1a218086: /* i840 */
 291         case 0x25308086: /* i850 */
 292         case 0x25318086: /* i860 */
 293         case 0x255d8086: /* E7205 */
 294         case 0x25508086: /* E7505 */
 295                 reg = pci_read_config(dev, AGP_INTEL_MCHCFG, 2) & ~(1 << 9);
 296                 kprintf("%s: set MCHCFG to %x04\n", __func__, reg & 0xffff);
 297                 pci_write_config(dev, AGP_INTEL_MCHCFG, reg, 2);
 298                 break;
 299         default: /* Intel Generic (maybe) */
 300                 reg = pci_read_config(dev, AGP_INTEL_NBXCFG, 4) & ~(1 << 9);
 301                 kprintf("%s: set NBXCFG to %08x\n", __func__, reg);
 302                 pci_write_config(dev, AGP_INTEL_NBXCFG, reg, 4);
 303         }
 304         pci_write_config(dev, AGP_INTEL_ATTBASE, 0, 4);
 305         AGP_SET_APERTURE(dev, sc->initial_aperture);
 306         agp_free_gatt(sc->gatt);
 307         agp_free_res(dev);
 308
 309         return (0);
 310 }
 311
 312 static int
 313 agp_intel_resume(device_t dev)
 314 {
 315         struct agp_intel_softc *sc;
 316         sc = device_get_softc(dev);
 317
 318         AGP_SET_APERTURE(dev, sc->current_aperture);
 319         agp_intel_commit_gatt(dev);
 320         return (bus_generic_resume(dev));
 321 }
 322
 323 static u_int32_t
 324 agp_intel_get_aperture(device_t dev)
 325 {
 326         struct agp_intel_softc *sc;
 327         u_int32_t apsize;
 328
 329         sc = device_get_softc(dev);
 330
 331         apsize = pci_read_config(dev, AGP_INTEL_APSIZE, 1) & sc->aperture_mask;
 332
 333         /*
 334          * The size is determined by the number of low bits of
 335          * register APBASE which are forced to zero. The low 22 bits
 336          * are always forced to zero and each zero bit in the apsize
 337          * field just read forces the corresponding bit in the 27:22
 338          * to be zero. We calculate the aperture size accordingly.
 339          */
 340         return ((((apsize ^ sc->aperture_mask) << 22) | ((1 << 22) - 1)) + 1);
 341 }
 342
 343 static int
 344 agp_intel_set_aperture(device_t dev, u_int32_t aperture)
 345 {
 346         struct agp_intel_softc *sc;
 347         u_int32_t apsize;
 348
 349         sc = device_get_softc(dev);
 350
 351         /*
 352          * Reverse the magic from get_aperture.
 353          */
 354         apsize = ((aperture - 1) >> 22) ^ sc->aperture_mask;
 355
 356         /*
 357          * Double check for sanity.
 358          */
 359         if ((((apsize ^ sc->aperture_mask) << 22) | ((1 << 22) - 1)) + 1 != aperture)
 360                 return (EINVAL);
 361
 362         sc->current_aperture = apsize;
 363
 364         pci_write_config(dev, AGP_INTEL_APSIZE, apsize, 1);
 365
 366         return (0);
 367 }
 368
 369 static int
 370 agp_intel_bind_page(device_t dev, int offset, vm_offset_t physical)
 371 {
 372         struct agp_intel_softc *sc;
 373
 374         sc = device_get_softc(dev);
 375
 376         if (offset < 0 || offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT))
 377                 return (EINVAL);
 378
 379         sc->gatt->ag_virtual[offset >> AGP_PAGE_SHIFT] = physical | 0x17;
 380         return (0);
 381 }
 382
 383 static int
 384 agp_intel_unbind_page(device_t dev, int offset)
 385 {
 386         struct agp_intel_softc *sc;
 387
 388         sc = device_get_softc(dev);
 389
 390         if (offset < 0 || offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT))
 391                 return (EINVAL);
 392
 393         sc->gatt->ag_virtual[offset >> AGP_PAGE_SHIFT] = 0;
 394         return (0);
 395 }
 396
 397 static void
 398 agp_intel_flush_tlb(device_t dev)
 399 {
 400         u_int32_t val;
 401
 402         val = pci_read_config(dev, AGP_INTEL_AGPCTRL, 4);
 403         pci_write_config(dev, AGP_INTEL_AGPCTRL, val & ~(1 << 7), 4);
 404         pci_write_config(dev, AGP_INTEL_AGPCTRL, val, 4);
 405 }
 406
 407 static device_method_t agp_intel_methods[] = {
 408         /* Device interface */
 409         DEVMETHOD(device_probe,         agp_intel_probe),
 410         DEVMETHOD(device_attach,        agp_intel_attach),
 411         DEVMETHOD(device_detach,        agp_intel_detach),
 412         DEVMETHOD(device_shutdown,      bus_generic_shutdown),
 413         DEVMETHOD(device_suspend,       bus_generic_suspend),
 414         DEVMETHOD(device_resume,        agp_intel_resume),
 415
 416         /* AGP interface */
 417         DEVMETHOD(agp_get_aperture,     agp_intel_get_aperture),
 418         DEVMETHOD(agp_set_aperture,     agp_intel_set_aperture),
 419         DEVMETHOD(agp_bind_page,        agp_intel_bind_page),
 420         DEVMETHOD(agp_unbind_page,      agp_intel_unbind_page),
 421         DEVMETHOD(agp_flush_tlb,        agp_intel_flush_tlb),
 422         DEVMETHOD(agp_enable,           agp_generic_enable),
 423         DEVMETHOD(agp_alloc_memory,     agp_generic_alloc_memory),
 424         DEVMETHOD(agp_free_memory,      agp_generic_free_memory),
 425         DEVMETHOD(agp_bind_memory,      agp_generic_bind_memory),
 426         DEVMETHOD(agp_unbind_memory,    agp_generic_unbind_memory),
 427
 428         { 0, 0 }
 429 };
 430
 431 static driver_t agp_intel_driver = {
 432         "agp",
 433         agp_intel_methods,
 434         sizeof(struct agp_intel_softc),
 435 };
 436
 437 static devclass_t agp_devclass;
 438
 439 DRIVER_MODULE(agp_intel, pci, agp_intel_driver, agp_devclass, 0, 0);
 440 MODULE_DEPEND(agp_intel, agp, 1, 1, 1);
 441 MODULE_DEPEND(agp_intel, pci, 1, 1, 1);