1 /***************************************************************************
2 * Copyright (C) 2007 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Copyright (C) 2007,2008,2009 by Øyvind Harboe *
6 * oyvind.harboe@zylin.com *
8 * This program is free software; you can redistribute it and/or modify *
9 * it under the terms of the GNU General Public License as published by *
10 * the Free Software Foundation; either version 2 of the License, or *
11 * (at your option) any later version. *
13 * This program is distributed in the hope that it will be useful, *
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
16 * GNU General Public License for more details. *
18 * You should have received a copy of the GNU General Public License *
19 * along with this program; if not, write to the *
20 * Free Software Foundation, Inc., *
21 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
22 ***************************************************************************/
27 #include "arm926ejs.h"
28 #include "time_support.h"
29 #include "target_type.h"
33 * The ARM926 is built around the ARM9EJ-S core, and most JTAG docs
34 * are in the ARM9EJ-S Technical Reference Manual (ARM DDI 0222B) not
35 * the ARM926 manual (ARM DDI 0198E). The scan chains are:
37 * 1 ... core debugging
39 * 3 ... external boundary scan (SoC-specific, unused here)
41 * 15 ... coprocessor 15
45 #define _DEBUG_INSTRUCTION_EXECUTION_
48 #define ARM926EJS_CP15_ADDR(opcode_1, opcode_2, CRn, CRm) ((opcode_1 << 11) | (opcode_2 << 8) | (CRn << 4) | (CRm << 0))
50 static int arm926ejs_cp15_read(target_t
*target
, uint32_t op1
, uint32_t op2
,
51 uint32_t CRn
, uint32_t CRm
, uint32_t *value
)
53 int retval
= ERROR_OK
;
54 struct arm7_9_common_s
*arm7_9
= target_to_arm7_9(target
);
55 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
56 uint32_t address
= ARM926EJS_CP15_ADDR(op1
, op2
, CRn
, CRm
);
57 scan_field_t fields
[4];
58 uint8_t address_buf
[2];
62 buf_set_u32(address_buf
, 0, 14, address
);
64 jtag_set_end_state(TAP_IDLE
);
65 if ((retval
= arm_jtag_scann(jtag_info
, 0xf)) != ERROR_OK
)
69 arm_jtag_set_instr(jtag_info
, jtag_info
->intest_instr
, NULL
);
71 fields
[0].tap
= jtag_info
->tap
;
72 fields
[0].num_bits
= 32;
73 fields
[0].out_value
= NULL
;
74 fields
[0].in_value
= (uint8_t *)value
;
77 fields
[1].tap
= jtag_info
->tap
;
78 fields
[1].num_bits
= 1;
79 fields
[1].out_value
= &access
;
80 fields
[1].in_value
= &access
;
82 fields
[2].tap
= jtag_info
->tap
;
83 fields
[2].num_bits
= 14;
84 fields
[2].out_value
= address_buf
;
85 fields
[2].in_value
= NULL
;
87 fields
[3].tap
= jtag_info
->tap
;
88 fields
[3].num_bits
= 1;
89 fields
[3].out_value
= &nr_w_buf
;
90 fields
[3].in_value
= NULL
;
92 jtag_add_dr_scan(4, fields
, jtag_get_end_state());
94 long long then
= timeval_ms();
98 /* rescan with NOP, to wait for the access to complete */
101 jtag_add_dr_scan(4, fields
, jtag_get_end_state());
103 jtag_add_callback(arm_le_to_h_u32
, (jtag_callback_data_t
)value
);
105 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
110 if (buf_get_u32(&access
, 0, 1) == 1)
116 if ((timeval_ms()-then
)>10)
118 LOG_ERROR("cp15 read operation timed out");
123 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
124 LOG_DEBUG("addr: 0x%x value: %8.8x", address
, *value
);
127 arm_jtag_set_instr(jtag_info
, 0xc, NULL
);
132 static int arm926ejs_mrc(target_t
*target
, int cpnum
, uint32_t op1
,
133 uint32_t op2
, uint32_t CRn
, uint32_t CRm
, uint32_t *value
)
136 LOG_ERROR("Only cp15 is supported");
139 return arm926ejs_cp15_read(target
, op1
, op2
, CRn
, CRm
, value
);
142 static int arm926ejs_cp15_write(target_t
*target
, uint32_t op1
, uint32_t op2
,
143 uint32_t CRn
, uint32_t CRm
, uint32_t value
)
145 int retval
= ERROR_OK
;
146 struct arm7_9_common_s
*arm7_9
= target_to_arm7_9(target
);
147 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
148 uint32_t address
= ARM926EJS_CP15_ADDR(op1
, op2
, CRn
, CRm
);
149 scan_field_t fields
[4];
150 uint8_t value_buf
[4];
151 uint8_t address_buf
[2];
152 uint8_t nr_w_buf
= 1;
155 buf_set_u32(address_buf
, 0, 14, address
);
156 buf_set_u32(value_buf
, 0, 32, value
);
158 jtag_set_end_state(TAP_IDLE
);
159 if ((retval
= arm_jtag_scann(jtag_info
, 0xf)) != ERROR_OK
)
163 arm_jtag_set_instr(jtag_info
, jtag_info
->intest_instr
, NULL
);
165 fields
[0].tap
= jtag_info
->tap
;
166 fields
[0].num_bits
= 32;
167 fields
[0].out_value
= value_buf
;
168 fields
[0].in_value
= NULL
;
170 fields
[1].tap
= jtag_info
->tap
;
171 fields
[1].num_bits
= 1;
172 fields
[1].out_value
= &access
;
173 fields
[1].in_value
= &access
;
175 fields
[2].tap
= jtag_info
->tap
;
176 fields
[2].num_bits
= 14;
177 fields
[2].out_value
= address_buf
;
178 fields
[2].in_value
= NULL
;
180 fields
[3].tap
= jtag_info
->tap
;
181 fields
[3].num_bits
= 1;
182 fields
[3].out_value
= &nr_w_buf
;
183 fields
[3].in_value
= NULL
;
185 jtag_add_dr_scan(4, fields
, jtag_get_end_state());
187 long long then
= timeval_ms();
191 /* rescan with NOP, to wait for the access to complete */
194 jtag_add_dr_scan(4, fields
, jtag_get_end_state());
195 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
200 if (buf_get_u32(&access
, 0, 1) == 1)
206 if ((timeval_ms()-then
)>10)
208 LOG_ERROR("cp15 write operation timed out");
213 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
214 LOG_DEBUG("addr: 0x%x value: %8.8x", address
, value
);
217 arm_jtag_set_instr(jtag_info
, 0xf, NULL
);
222 static int arm926ejs_mcr(target_t
*target
, int cpnum
, uint32_t op1
,
223 uint32_t op2
, uint32_t CRn
, uint32_t CRm
, uint32_t value
)
226 LOG_ERROR("Only cp15 is supported");
229 return arm926ejs_cp15_write(target
, op1
, op2
, CRn
, CRm
, value
);
232 static int arm926ejs_examine_debug_reason(target_t
*target
)
234 struct arm7_9_common_s
*arm7_9
= target_to_arm7_9(target
);
235 reg_t
*dbg_stat
= &arm7_9
->eice_cache
->reg_list
[EICE_DBG_STAT
];
239 embeddedice_read_reg(dbg_stat
);
240 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
243 /* Method-Of-Entry (MOE) field */
244 debug_reason
= buf_get_u32(dbg_stat
->value
, 6, 4);
246 switch (debug_reason
)
249 LOG_DEBUG("no *NEW* debug entry (?missed one?)");
250 /* ... since last restart or debug reset ... */
251 target
->debug_reason
= DBG_REASON_DBGRQ
;
254 LOG_DEBUG("breakpoint from EICE unit 0");
255 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
258 LOG_DEBUG("breakpoint from EICE unit 1");
259 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
262 LOG_DEBUG("soft breakpoint (BKPT instruction)");
263 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
266 LOG_DEBUG("vector catch breakpoint");
267 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
270 LOG_DEBUG("external breakpoint");
271 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
274 LOG_DEBUG("watchpoint from EICE unit 0");
275 target
->debug_reason
= DBG_REASON_WATCHPOINT
;
278 LOG_DEBUG("watchpoint from EICE unit 1");
279 target
->debug_reason
= DBG_REASON_WATCHPOINT
;
282 LOG_DEBUG("external watchpoint");
283 target
->debug_reason
= DBG_REASON_WATCHPOINT
;
286 LOG_DEBUG("internal debug request");
287 target
->debug_reason
= DBG_REASON_DBGRQ
;
290 LOG_DEBUG("external debug request");
291 target
->debug_reason
= DBG_REASON_DBGRQ
;
294 LOG_DEBUG("debug re-entry from system speed access");
295 /* This is normal when connecting to something that's
296 * already halted, or in some related code paths, but
297 * otherwise is surprising (and presumably wrong).
299 switch (target
->debug_reason
) {
300 case DBG_REASON_DBGRQ
:
303 LOG_ERROR("unexpected -- debug re-entry");
305 case DBG_REASON_UNDEFINED
:
306 target
->debug_reason
= DBG_REASON_DBGRQ
;
311 /* FIX!!!! here be dragons!!! We need to fail here so
312 * the target will interpreted as halted but we won't
313 * try to talk to it right now... a resume + halt seems
314 * to sync things up again. Please send an email to
315 * openocd development mailing list if you have hardware
316 * to donate to look into this problem....
318 LOG_WARNING("WARNING: mystery debug reason MOE = 0xc. Try issuing a resume + halt.");
319 target
->debug_reason
= DBG_REASON_DBGRQ
;
322 LOG_WARNING("WARNING: unknown debug reason: 0x%x", debug_reason
);
323 /* Oh agony! should we interpret this as a halt request or
324 * that the target stopped on it's own accord?
326 target
->debug_reason
= DBG_REASON_DBGRQ
;
327 /* if we fail here, we won't talk to the target and it will
328 * be reported to be in the halted state */
335 static uint32_t arm926ejs_get_ttb(target_t
*target
)
337 struct arm926ejs_common_s
*arm926ejs
= target_to_arm926(target
);
341 if ((retval
= arm926ejs
->read_cp15(target
, 0, 0, 2, 0, &ttb
)) != ERROR_OK
)
347 static void arm926ejs_disable_mmu_caches(target_t
*target
, int mmu
,
348 int d_u_cache
, int i_cache
)
350 struct arm926ejs_common_s
*arm926ejs
= target_to_arm926(target
);
351 uint32_t cp15_control
;
353 /* read cp15 control register */
354 arm926ejs
->read_cp15(target
, 0, 0, 1, 0, &cp15_control
);
355 jtag_execute_queue();
360 arm926ejs
->write_cp15(target
, 0, 0, 8, 7, 0x0);
362 cp15_control
&= ~0x1U
;
367 uint32_t debug_override
;
368 /* read-modify-write CP15 debug override register
369 * to enable "test and clean all" */
370 arm926ejs
->read_cp15(target
, 0, 0, 15, 0, &debug_override
);
371 debug_override
|= 0x80000;
372 arm926ejs
->write_cp15(target
, 0, 0, 15, 0, debug_override
);
374 /* clean and invalidate DCache */
375 arm926ejs
->write_cp15(target
, 0, 0, 7, 5, 0x0);
377 /* write CP15 debug override register
378 * to disable "test and clean all" */
379 debug_override
&= ~0x80000;
380 arm926ejs
->write_cp15(target
, 0, 0, 15, 0, debug_override
);
382 cp15_control
&= ~0x4U
;
387 /* invalidate ICache */
388 arm926ejs
->write_cp15(target
, 0, 0, 7, 5, 0x0);
390 cp15_control
&= ~0x1000U
;
393 arm926ejs
->write_cp15(target
, 0, 0, 1, 0, cp15_control
);
396 static void arm926ejs_enable_mmu_caches(target_t
*target
, int mmu
,
397 int d_u_cache
, int i_cache
)
399 struct arm926ejs_common_s
*arm926ejs
= target_to_arm926(target
);
400 uint32_t cp15_control
;
402 /* read cp15 control register */
403 arm926ejs
->read_cp15(target
, 0, 0, 1, 0, &cp15_control
);
404 jtag_execute_queue();
407 cp15_control
|= 0x1U
;
410 cp15_control
|= 0x4U
;
413 cp15_control
|= 0x1000U
;
415 arm926ejs
->write_cp15(target
, 0, 0, 1, 0, cp15_control
);
418 static void arm926ejs_post_debug_entry(target_t
*target
)
420 struct arm926ejs_common_s
*arm926ejs
= target_to_arm926(target
);
422 /* examine cp15 control reg */
423 arm926ejs
->read_cp15(target
, 0, 0, 1, 0, &arm926ejs
->cp15_control_reg
);
424 jtag_execute_queue();
425 LOG_DEBUG("cp15_control_reg: %8.8" PRIx32
"", arm926ejs
->cp15_control_reg
);
427 if (arm926ejs
->armv4_5_mmu
.armv4_5_cache
.ctype
== -1)
429 uint32_t cache_type_reg
;
430 /* identify caches */
431 arm926ejs
->read_cp15(target
, 0, 1, 0, 0, &cache_type_reg
);
432 jtag_execute_queue();
433 armv4_5_identify_cache(cache_type_reg
, &arm926ejs
->armv4_5_mmu
.armv4_5_cache
);
436 arm926ejs
->armv4_5_mmu
.mmu_enabled
= (arm926ejs
->cp15_control_reg
& 0x1U
) ? 1 : 0;
437 arm926ejs
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
= (arm926ejs
->cp15_control_reg
& 0x4U
) ? 1 : 0;
438 arm926ejs
->armv4_5_mmu
.armv4_5_cache
.i_cache_enabled
= (arm926ejs
->cp15_control_reg
& 0x1000U
) ? 1 : 0;
440 /* save i/d fault status and address register */
441 arm926ejs
->read_cp15(target
, 0, 0, 5, 0, &arm926ejs
->d_fsr
);
442 arm926ejs
->read_cp15(target
, 0, 1, 5, 0, &arm926ejs
->i_fsr
);
443 arm926ejs
->read_cp15(target
, 0, 0, 6, 0, &arm926ejs
->d_far
);
445 LOG_DEBUG("D FSR: 0x%8.8" PRIx32
", D FAR: 0x%8.8" PRIx32
", I FSR: 0x%8.8" PRIx32
"",
446 arm926ejs
->d_fsr
, arm926ejs
->d_far
, arm926ejs
->i_fsr
);
448 uint32_t cache_dbg_ctrl
;
450 /* read-modify-write CP15 cache debug control register
451 * to disable I/D-cache linefills and force WT */
452 arm926ejs
->read_cp15(target
, 7, 0, 15, 0, &cache_dbg_ctrl
);
453 cache_dbg_ctrl
|= 0x7;
454 arm926ejs
->write_cp15(target
, 7, 0, 15, 0, cache_dbg_ctrl
);
457 static void arm926ejs_pre_restore_context(target_t
*target
)
459 struct arm926ejs_common_s
*arm926ejs
= target_to_arm926(target
);
461 /* restore i/d fault status and address register */
462 arm926ejs
->write_cp15(target
, 0, 0, 5, 0, arm926ejs
->d_fsr
);
463 arm926ejs
->write_cp15(target
, 0, 1, 5, 0, arm926ejs
->i_fsr
);
464 arm926ejs
->write_cp15(target
, 0, 0, 6, 0, arm926ejs
->d_far
);
466 uint32_t cache_dbg_ctrl
;
468 /* read-modify-write CP15 cache debug control register
469 * to reenable I/D-cache linefills and disable WT */
470 arm926ejs
->read_cp15(target
, 7, 0, 15, 0, &cache_dbg_ctrl
);
471 cache_dbg_ctrl
&= ~0x7;
472 arm926ejs
->write_cp15(target
, 7, 0, 15, 0, cache_dbg_ctrl
);
475 static const char arm926_not
[] = "target is not an ARM926";
477 static int arm926ejs_verify_pointer(struct command_context_s
*cmd_ctx
,
478 struct arm926ejs_common_s
*arm926
)
480 if (arm926
->common_magic
!= ARM926EJS_COMMON_MAGIC
) {
481 command_print(cmd_ctx
, arm926_not
);
482 return ERROR_TARGET_INVALID
;
487 /** Logs summary of ARM926 state for a halted target. */
488 int arm926ejs_arch_state(struct target_s
*target
)
490 static const char *state
[] =
492 "disabled", "enabled"
495 struct arm926ejs_common_s
*arm926ejs
= target_to_arm926(target
);
496 struct armv4_5_common_s
*armv4_5
;
498 if (arm926ejs
->common_magic
!= ARM926EJS_COMMON_MAGIC
)
500 LOG_ERROR("BUG: %s", arm926_not
);
501 return ERROR_TARGET_INVALID
;
504 armv4_5
= &arm926ejs
->arm9tdmi_common
.arm7_9_common
.armv4_5_common
;
506 LOG_USER("target halted in %s state due to %s, current mode: %s\n"
507 "cpsr: 0x%8.8" PRIx32
" pc: 0x%8.8" PRIx32
"\n"
508 "MMU: %s, D-Cache: %s, I-Cache: %s",
509 armv4_5_state_strings
[armv4_5
->core_state
],
510 Jim_Nvp_value2name_simple(nvp_target_debug_reason
,target
->debug_reason
)->name
,
511 armv4_5_mode_strings
[armv4_5_mode_to_number(armv4_5
->core_mode
)],
512 buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 32),
513 buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32),
514 state
[arm926ejs
->armv4_5_mmu
.mmu_enabled
],
515 state
[arm926ejs
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
],
516 state
[arm926ejs
->armv4_5_mmu
.armv4_5_cache
.i_cache_enabled
]);
521 int arm926ejs_soft_reset_halt(struct target_s
*target
)
523 int retval
= ERROR_OK
;
524 struct arm926ejs_common_s
*arm926ejs
= target_to_arm926(target
);
525 struct arm7_9_common_s
*arm7_9
= target_to_arm7_9(target
);
526 struct armv4_5_common_s
*armv4_5
= &arm7_9
->armv4_5_common
;
527 reg_t
*dbg_stat
= &arm7_9
->eice_cache
->reg_list
[EICE_DBG_STAT
];
529 if ((retval
= target_halt(target
)) != ERROR_OK
)
534 long long then
= timeval_ms();
536 while (!(timeout
= ((timeval_ms()-then
) > 1000)))
538 if (buf_get_u32(dbg_stat
->value
, EICE_DBG_STATUS_DBGACK
, 1) == 0)
540 embeddedice_read_reg(dbg_stat
);
541 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
549 if (debug_level
>= 1)
551 /* do not eat all CPU, time out after 1 se*/
560 LOG_ERROR("Failed to halt CPU after 1 sec");
561 return ERROR_TARGET_TIMEOUT
;
564 target
->state
= TARGET_HALTED
;
566 /* SVC, ARM state, IRQ and FIQ disabled */
567 buf_set_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 8, 0xd3);
568 armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].dirty
= 1;
569 armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].valid
= 1;
571 /* start fetching from 0x0 */
572 buf_set_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32, 0x0);
573 armv4_5
->core_cache
->reg_list
[15].dirty
= 1;
574 armv4_5
->core_cache
->reg_list
[15].valid
= 1;
576 armv4_5
->core_mode
= ARMV4_5_MODE_SVC
;
577 armv4_5
->core_state
= ARMV4_5_STATE_ARM
;
579 arm926ejs_disable_mmu_caches(target
, 1, 1, 1);
580 arm926ejs
->armv4_5_mmu
.mmu_enabled
= 0;
581 arm926ejs
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
= 0;
582 arm926ejs
->armv4_5_mmu
.armv4_5_cache
.i_cache_enabled
= 0;
584 return target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
587 /** Writes a buffer, in the specified word size, with current MMU settings. */
588 int arm926ejs_write_memory(struct target_s
*target
, uint32_t address
,
589 uint32_t size
, uint32_t count
, uint8_t *buffer
)
592 struct arm926ejs_common_s
*arm926ejs
= target_to_arm926(target
);
594 /* FIX!!!! this should be cleaned up and made much more general. The
595 * plan is to write up and test on arm926ejs specifically and
596 * then generalize and clean up afterwards. */
597 if (arm926ejs
->armv4_5_mmu
.mmu_enabled
&& (count
== 1) && ((size
==2) || (size
==4)))
599 /* special case the handling of single word writes to bypass MMU
600 * to allow implementation of breakpoints in memory marked read only
602 if (arm926ejs
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
)
604 /* flush and invalidate data cache
606 * MCR p15,0,p,c7,c10,1 - clean cache line using virtual address
609 retval
= arm926ejs
->write_cp15(target
, 0, 1, 7, 10, address
&~0x3);
610 if (retval
!= ERROR_OK
)
615 retval
= target
->type
->virt2phys(target
, address
, &pa
);
616 if (retval
!= ERROR_OK
)
619 /* write directly to physical memory bypassing any read only MMU bits, etc. */
620 retval
= armv4_5_mmu_write_physical(target
, &arm926ejs
->armv4_5_mmu
, pa
, size
, count
, buffer
);
621 if (retval
!= ERROR_OK
)
625 if ((retval
= arm7_9_write_memory(target
, address
, size
, count
, buffer
)) != ERROR_OK
)
629 /* If ICache is enabled, we have to invalidate affected ICache lines
630 * the DCache is forced to write-through, so we don't have to clean it here
632 if (arm926ejs
->armv4_5_mmu
.armv4_5_cache
.i_cache_enabled
)
636 /* invalidate ICache single entry with MVA */
637 arm926ejs
->write_cp15(target
, 0, 1, 7, 5, address
);
641 /* invalidate ICache */
642 arm926ejs
->write_cp15(target
, 0, 0, 7, 5, address
);
649 static int arm926ejs_write_phys_memory(struct target_s
*target
,
650 uint32_t address
, uint32_t size
,
651 uint32_t count
, uint8_t *buffer
)
653 struct arm926ejs_common_s
*arm926ejs
= target_to_arm926(target
);
655 return armv4_5_mmu_write_physical(target
, &arm926ejs
->armv4_5_mmu
,
656 address
, size
, count
, buffer
);
659 static int arm926ejs_read_phys_memory(struct target_s
*target
,
660 uint32_t address
, uint32_t size
,
661 uint32_t count
, uint8_t *buffer
)
663 struct arm926ejs_common_s
*arm926ejs
= target_to_arm926(target
);
665 return armv4_5_mmu_read_physical(target
, &arm926ejs
->armv4_5_mmu
,
666 address
, size
, count
, buffer
);
669 int arm926ejs_init_arch_info(target_t
*target
, arm926ejs_common_t
*arm926ejs
,
672 arm9tdmi_common_t
*arm9tdmi
= &arm926ejs
->arm9tdmi_common
;
673 arm7_9_common_t
*arm7_9
= &arm9tdmi
->arm7_9_common
;
675 /* initialize arm9tdmi specific info (including arm7_9 and armv4_5)
677 arm9tdmi_init_arch_info(target
, arm9tdmi
, tap
);
679 arm926ejs
->common_magic
= ARM926EJS_COMMON_MAGIC
;
681 arm7_9
->post_debug_entry
= arm926ejs_post_debug_entry
;
682 arm7_9
->pre_restore_context
= arm926ejs_pre_restore_context
;
684 arm926ejs
->read_cp15
= arm926ejs_cp15_read
;
685 arm926ejs
->write_cp15
= arm926ejs_cp15_write
;
686 arm926ejs
->armv4_5_mmu
.armv4_5_cache
.ctype
= -1;
687 arm926ejs
->armv4_5_mmu
.get_ttb
= arm926ejs_get_ttb
;
688 arm926ejs
->armv4_5_mmu
.read_memory
= arm7_9_read_memory
;
689 arm926ejs
->armv4_5_mmu
.write_memory
= arm7_9_write_memory
;
690 arm926ejs
->armv4_5_mmu
.disable_mmu_caches
= arm926ejs_disable_mmu_caches
;
691 arm926ejs
->armv4_5_mmu
.enable_mmu_caches
= arm926ejs_enable_mmu_caches
;
692 arm926ejs
->armv4_5_mmu
.has_tiny_pages
= 1;
693 arm926ejs
->armv4_5_mmu
.mmu_enabled
= 0;
695 arm7_9
->examine_debug_reason
= arm926ejs_examine_debug_reason
;
697 /* The ARM926EJ-S implements the ARMv5TE architecture which
698 * has the BKPT instruction, so we don't have to use a watchpoint comparator
700 arm7_9
->arm_bkpt
= ARMV5_BKPT(0x0);
701 arm7_9
->thumb_bkpt
= ARMV5_T_BKPT(0x0) & 0xffff;
706 static int arm926ejs_target_create(struct target_s
*target
, Jim_Interp
*interp
)
708 arm926ejs_common_t
*arm926ejs
= calloc(1,sizeof(arm926ejs_common_t
));
710 /* ARM9EJ-S core always reports 0x1 in Capture-IR */
711 target
->tap
->ir_capture_mask
= 0x0f;
713 return arm926ejs_init_arch_info(target
, arm926ejs
, target
->tap
);
716 static int arm926ejs_handle_cp15_command(struct command_context_s
*cmd_ctx
,
717 char *cmd
, char **args
, int argc
)
720 target_t
*target
= get_current_target(cmd_ctx
);
721 struct arm926ejs_common_s
*arm926ejs
= target_to_arm926(target
);
727 if ((argc
< 4) || (argc
> 5))
729 command_print(cmd_ctx
, "usage: arm926ejs cp15 <opcode_1> <opcode_2> <CRn> <CRm> [value]");
733 COMMAND_PARSE_NUMBER(int, args
[0], opcode_1
);
734 COMMAND_PARSE_NUMBER(int, args
[1], opcode_2
);
735 COMMAND_PARSE_NUMBER(int, args
[2], CRn
);
736 COMMAND_PARSE_NUMBER(int, args
[3], CRm
);
738 retval
= arm926ejs_verify_pointer(cmd_ctx
, arm926ejs
);
739 if (retval
!= ERROR_OK
)
742 if (target
->state
!= TARGET_HALTED
)
744 command_print(cmd_ctx
, "target must be stopped for \"%s\" command", cmd
);
751 if ((retval
= arm926ejs
->read_cp15(target
, opcode_1
, opcode_2
, CRn
, CRm
, &value
)) != ERROR_OK
)
753 command_print(cmd_ctx
, "couldn't access register");
756 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
761 command_print(cmd_ctx
, "%i %i %i %i: %8.8" PRIx32
"", opcode_1
, opcode_2
, CRn
, CRm
, value
);
766 COMMAND_PARSE_NUMBER(u32
, args
[4], value
);
767 if ((retval
= arm926ejs
->write_cp15(target
, opcode_1
, opcode_2
, CRn
, CRm
, value
)) != ERROR_OK
)
769 command_print(cmd_ctx
, "couldn't access register");
772 command_print(cmd_ctx
, "%i %i %i %i: %8.8" PRIx32
"", opcode_1
, opcode_2
, CRn
, CRm
, value
);
779 arm926ejs_handle_cache_info_command(struct command_context_s
*cmd_ctx
,
780 char *cmd
, char **args
, int argc
)
783 target_t
*target
= get_current_target(cmd_ctx
);
784 struct arm926ejs_common_s
*arm926ejs
= target_to_arm926(target
);
786 retval
= arm926ejs_verify_pointer(cmd_ctx
, arm926ejs
);
787 if (retval
!= ERROR_OK
)
790 return armv4_5_handle_cache_info_command(cmd_ctx
, &arm926ejs
->armv4_5_mmu
.armv4_5_cache
);
793 static int arm926ejs_virt2phys(struct target_s
*target
, uint32_t virtual, uint32_t *physical
)
799 struct arm926ejs_common_s
*arm926ejs
= target_to_arm926(target
);
801 uint32_t ret
= armv4_5_mmu_translate_va(target
, &arm926ejs
->armv4_5_mmu
, virtual, &type
, &cb
, &domain
, &ap
);
810 static int arm926ejs_mmu(struct target_s
*target
, int *enabled
)
812 struct arm926ejs_common_s
*arm926ejs
= target_to_arm926(target
);
814 if (target
->state
!= TARGET_HALTED
)
816 LOG_ERROR("Target not halted");
817 return ERROR_TARGET_INVALID
;
819 *enabled
= arm926ejs
->armv4_5_mmu
.mmu_enabled
;
823 /** Registers commands to access coprocessor, cache, and debug resources. */
824 int arm926ejs_register_commands(struct command_context_s
*cmd_ctx
)
827 command_t
*arm926ejs_cmd
;
829 retval
= arm9tdmi_register_commands(cmd_ctx
);
831 arm926ejs_cmd
= register_command(cmd_ctx
, NULL
, "arm926ejs",
833 "arm926ejs specific commands");
835 register_command(cmd_ctx
, arm926ejs_cmd
, "cp15",
836 arm926ejs_handle_cp15_command
, COMMAND_EXEC
,
837 "display/modify cp15 register "
838 "<opcode_1> <opcode_2> <CRn> <CRm> [value]");
840 register_command(cmd_ctx
, arm926ejs_cmd
, "cache_info",
841 arm926ejs_handle_cache_info_command
, COMMAND_EXEC
,
842 "display information about target caches");
847 /** Holds methods for ARM926 targets. */
848 target_type_t arm926ejs_target
=
853 .arch_state
= arm926ejs_arch_state
,
855 .target_request_data
= arm7_9_target_request_data
,
858 .resume
= arm7_9_resume
,
861 .assert_reset
= arm7_9_assert_reset
,
862 .deassert_reset
= arm7_9_deassert_reset
,
863 .soft_reset_halt
= arm926ejs_soft_reset_halt
,
865 .get_gdb_reg_list
= armv4_5_get_gdb_reg_list
,
867 .read_memory
= arm7_9_read_memory
,
868 .write_memory
= arm926ejs_write_memory
,
869 .bulk_write_memory
= arm7_9_bulk_write_memory
,
870 .checksum_memory
= arm7_9_checksum_memory
,
871 .blank_check_memory
= arm7_9_blank_check_memory
,
873 .run_algorithm
= armv4_5_run_algorithm
,
875 .add_breakpoint
= arm7_9_add_breakpoint
,
876 .remove_breakpoint
= arm7_9_remove_breakpoint
,
877 .add_watchpoint
= arm7_9_add_watchpoint
,
878 .remove_watchpoint
= arm7_9_remove_watchpoint
,
880 .register_commands
= arm926ejs_register_commands
,
881 .target_create
= arm926ejs_target_create
,
882 .init_target
= arm9tdmi_init_target
,
883 .examine
= arm9tdmi_examine
,
884 .virt2phys
= arm926ejs_virt2phys
,
885 .mmu
= arm926ejs_mmu
,
887 .read_phys_memory
= arm926ejs_read_phys_memory
,
888 .write_phys_memory
= arm926ejs_write_phys_memory
,
889 .mrc
= arm926ejs_mrc
,
890 .mcr
= arm926ejs_mcr
,