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target: remove unused "bitfield" infrastructure
[dnglaze.git] / src / target / arm11.c
bloba6f0d3cc7831feabd0a49a3b7a14dacdacfef764
1 /***************************************************************************
2 * Copyright (C) 2008 digenius technology GmbH. *
3 * Michael Bruck *
4 * *
5 * Copyright (C) 2008,2009 Oyvind Harboe oyvind.harboe@zylin.com *
6 * *
7 * Copyright (C) 2008 Georg Acher <acher@in.tum.de> *
8 * *
9 * This program is free software; you can redistribute it and/or modify *
10 * it under the terms of the GNU General Public License as published by *
11 * the Free Software Foundation; either version 2 of the License, or *
12 * (at your option) any later version. *
13 * *
14 * This program is distributed in the hope that it will be useful, *
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
17 * GNU General Public License for more details. *
18 * *
19 * You should have received a copy of the GNU General Public License *
20 * along with this program; if not, write to the *
21 * Free Software Foundation, Inc., *
22 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
23 ***************************************************************************/
24
25 #ifdef HAVE_CONFIG_H
26 #include "config.h"
27 #endif
28
29 #include "arm11.h"
30 #include "arm11_dbgtap.h"
31 #include "armv4_5.h"
32 #include "arm_simulator.h"
33 #include "time_support.h"
34 #include "target_type.h"
35
36
37 #if 0
38 #define _DEBUG_INSTRUCTION_EXECUTION_
39 #endif
40
41 #if 0
42 #define FNC_INFO LOG_DEBUG("-")
43 #else
44 #define FNC_INFO
45 #endif
46
47 #if 1
48 #define FNC_INFO_NOTIMPLEMENTED do { LOG_DEBUG("NOT IMPLEMENTED"); /*exit(-1);*/ } while (0)
49 #else
50 #define FNC_INFO_NOTIMPLEMENTED
51 #endif
52
53 static bool arm11_config_memwrite_burst = true;
54 static bool arm11_config_memwrite_error_fatal = true;
55 static uint32_t arm11_vcr = 0;
56 static bool arm11_config_step_irq_enable = false;
57 static bool arm11_config_hardware_step = false;
58
59 static int arm11_regs_arch_type = -1;
60
61 enum arm11_regtype
62 {
63 ARM11_REGISTER_CORE,
64 ARM11_REGISTER_CPSR,
65
66 ARM11_REGISTER_FX,
67 ARM11_REGISTER_FPS,
68
69 ARM11_REGISTER_FIQ,
70 ARM11_REGISTER_SVC,
71 ARM11_REGISTER_ABT,
72 ARM11_REGISTER_IRQ,
73 ARM11_REGISTER_UND,
74 ARM11_REGISTER_MON,
75
76 ARM11_REGISTER_SPSR_FIQ,
77 ARM11_REGISTER_SPSR_SVC,
78 ARM11_REGISTER_SPSR_ABT,
79 ARM11_REGISTER_SPSR_IRQ,
80 ARM11_REGISTER_SPSR_UND,
81 ARM11_REGISTER_SPSR_MON,
82
83 /* debug regs */
84 ARM11_REGISTER_DSCR,
85 ARM11_REGISTER_WDTR,
86 ARM11_REGISTER_RDTR,
87 };
88
89
90 struct arm11_reg_defs
91 {
92 char * name;
93 uint32_t num;
94 int gdb_num;
95 enum arm11_regtype type;
96 };
97
98 /* update arm11_regcache_ids when changing this */
99 static const struct arm11_reg_defs arm11_reg_defs[] =
100 {
101 {"r0", 0, 0, ARM11_REGISTER_CORE},
102 {"r1", 1, 1, ARM11_REGISTER_CORE},
103 {"r2", 2, 2, ARM11_REGISTER_CORE},
104 {"r3", 3, 3, ARM11_REGISTER_CORE},
105 {"r4", 4, 4, ARM11_REGISTER_CORE},
106 {"r5", 5, 5, ARM11_REGISTER_CORE},
107 {"r6", 6, 6, ARM11_REGISTER_CORE},
108 {"r7", 7, 7, ARM11_REGISTER_CORE},
109 {"r8", 8, 8, ARM11_REGISTER_CORE},
110 {"r9", 9, 9, ARM11_REGISTER_CORE},
111 {"r10", 10, 10, ARM11_REGISTER_CORE},
112 {"r11", 11, 11, ARM11_REGISTER_CORE},
113 {"r12", 12, 12, ARM11_REGISTER_CORE},
114 {"sp", 13, 13, ARM11_REGISTER_CORE},
115 {"lr", 14, 14, ARM11_REGISTER_CORE},
116 {"pc", 15, 15, ARM11_REGISTER_CORE},
117
118 #if ARM11_REGCACHE_FREGS
119 {"f0", 0, 16, ARM11_REGISTER_FX},
120 {"f1", 1, 17, ARM11_REGISTER_FX},
121 {"f2", 2, 18, ARM11_REGISTER_FX},
122 {"f3", 3, 19, ARM11_REGISTER_FX},
123 {"f4", 4, 20, ARM11_REGISTER_FX},
124 {"f5", 5, 21, ARM11_REGISTER_FX},
125 {"f6", 6, 22, ARM11_REGISTER_FX},
126 {"f7", 7, 23, ARM11_REGISTER_FX},
127 {"fps", 0, 24, ARM11_REGISTER_FPS},
128 #endif
129
130 {"cpsr", 0, 25, ARM11_REGISTER_CPSR},
131
132 #if ARM11_REGCACHE_MODEREGS
133 {"r8_fiq", 8, -1, ARM11_REGISTER_FIQ},
134 {"r9_fiq", 9, -1, ARM11_REGISTER_FIQ},
135 {"r10_fiq", 10, -1, ARM11_REGISTER_FIQ},
136 {"r11_fiq", 11, -1, ARM11_REGISTER_FIQ},
137 {"r12_fiq", 12, -1, ARM11_REGISTER_FIQ},
138 {"r13_fiq", 13, -1, ARM11_REGISTER_FIQ},
139 {"r14_fiq", 14, -1, ARM11_REGISTER_FIQ},
140 {"spsr_fiq", 0, -1, ARM11_REGISTER_SPSR_FIQ},
141
142 {"r13_svc", 13, -1, ARM11_REGISTER_SVC},
143 {"r14_svc", 14, -1, ARM11_REGISTER_SVC},
144 {"spsr_svc", 0, -1, ARM11_REGISTER_SPSR_SVC},
145
146 {"r13_abt", 13, -1, ARM11_REGISTER_ABT},
147 {"r14_abt", 14, -1, ARM11_REGISTER_ABT},
148 {"spsr_abt", 0, -1, ARM11_REGISTER_SPSR_ABT},
149
150 {"r13_irq", 13, -1, ARM11_REGISTER_IRQ},
151 {"r14_irq", 14, -1, ARM11_REGISTER_IRQ},
152 {"spsr_irq", 0, -1, ARM11_REGISTER_SPSR_IRQ},
153
154 {"r13_und", 13, -1, ARM11_REGISTER_UND},
155 {"r14_und", 14, -1, ARM11_REGISTER_UND},
156 {"spsr_und", 0, -1, ARM11_REGISTER_SPSR_UND},
157
158 /* ARM1176 only */
159 {"r13_mon", 13, -1, ARM11_REGISTER_MON},
160 {"r14_mon", 14, -1, ARM11_REGISTER_MON},
161 {"spsr_mon", 0, -1, ARM11_REGISTER_SPSR_MON},
162 #endif
163
164 /* Debug Registers */
165 {"dscr", 0, -1, ARM11_REGISTER_DSCR},
166 {"wdtr", 0, -1, ARM11_REGISTER_WDTR},
167 {"rdtr", 0, -1, ARM11_REGISTER_RDTR},
168 };
169
170 enum arm11_regcache_ids
171 {
172 ARM11_RC_R0,
173 ARM11_RC_RX = ARM11_RC_R0,
174
175 ARM11_RC_R1,
176 ARM11_RC_R2,
177 ARM11_RC_R3,
178 ARM11_RC_R4,
179 ARM11_RC_R5,
180 ARM11_RC_R6,
181 ARM11_RC_R7,
182 ARM11_RC_R8,
183 ARM11_RC_R9,
184 ARM11_RC_R10,
185 ARM11_RC_R11,
186 ARM11_RC_R12,
187 ARM11_RC_R13,
188 ARM11_RC_SP = ARM11_RC_R13,
189 ARM11_RC_R14,
190 ARM11_RC_LR = ARM11_RC_R14,
191 ARM11_RC_R15,
192 ARM11_RC_PC = ARM11_RC_R15,
193
194 #if ARM11_REGCACHE_FREGS
195 ARM11_RC_F0,
196 ARM11_RC_FX = ARM11_RC_F0,
197 ARM11_RC_F1,
198 ARM11_RC_F2,
199 ARM11_RC_F3,
200 ARM11_RC_F4,
201 ARM11_RC_F5,
202 ARM11_RC_F6,
203 ARM11_RC_F7,
204 ARM11_RC_FPS,
205 #endif
206
207 ARM11_RC_CPSR,
208
209 #if ARM11_REGCACHE_MODEREGS
210 ARM11_RC_R8_FIQ,
211 ARM11_RC_R9_FIQ,
212 ARM11_RC_R10_FIQ,
213 ARM11_RC_R11_FIQ,
214 ARM11_RC_R12_FIQ,
215 ARM11_RC_R13_FIQ,
216 ARM11_RC_R14_FIQ,
217 ARM11_RC_SPSR_FIQ,
218
219 ARM11_RC_R13_SVC,
220 ARM11_RC_R14_SVC,
221 ARM11_RC_SPSR_SVC,
222
223 ARM11_RC_R13_ABT,
224 ARM11_RC_R14_ABT,
225 ARM11_RC_SPSR_ABT,
226
227 ARM11_RC_R13_IRQ,
228 ARM11_RC_R14_IRQ,
229 ARM11_RC_SPSR_IRQ,
230
231 ARM11_RC_R13_UND,
232 ARM11_RC_R14_UND,
233 ARM11_RC_SPSR_UND,
234
235 ARM11_RC_R13_MON,
236 ARM11_RC_R14_MON,
237 ARM11_RC_SPSR_MON,
238 #endif
239
240 ARM11_RC_DSCR,
241 ARM11_RC_WDTR,
242 ARM11_RC_RDTR,
243
244 ARM11_RC_MAX,
245 };
246
247 #define ARM11_GDB_REGISTER_COUNT 26
248
249 /* FIXME these are *identical* to the ARMv4_5 dummies ... except
250 * for their names, and being static vs global, and having different
251 * addresses. Ditto ARMv7a and ARMv7m dummies.
252 */
253
254 static uint8_t arm11_gdb_dummy_fp_value[12];
255
256 static struct reg arm11_gdb_dummy_fp_reg =
257 {
258 .name = "GDB dummy floating-point register",
259 .value = arm11_gdb_dummy_fp_value,
260 .dirty = 0,
261 .valid = 1,
262 .size = 96,
263 .arch_info = NULL,
264 .arch_type = 0,
265 };
266
267 static uint8_t arm11_gdb_dummy_fps_value[4];
268
269 static struct reg arm11_gdb_dummy_fps_reg =
270 {
271 .name = "GDB dummy floating-point status register",
272 .value = arm11_gdb_dummy_fps_value,
273 .dirty = 0,
274 .valid = 1,
275 .size = 32,
276 .arch_info = NULL,
277 .arch_type = 0,
278 };
279
280
281 static int arm11_on_enter_debug_state(struct arm11_common *arm11);
282 static int arm11_step(struct target *target, int current,
283 uint32_t address, int handle_breakpoints);
284 /* helpers */
285 static int arm11_build_reg_cache(struct target *target);
286 static int arm11_set_reg(struct reg *reg, uint8_t *buf);
287 static int arm11_get_reg(struct reg *reg);
288
289 static void arm11_record_register_history(struct arm11_common * arm11);
290 static void arm11_dump_reg_changes(struct arm11_common * arm11);
291
292
293 /** Check and if necessary take control of the system
294 *
295 * \param arm11 Target state variable.
296 * \param dscr If the current DSCR content is
297 * available a pointer to a word holding the
298 * DSCR can be passed. Otherwise use NULL.
299 */
300 static int arm11_check_init(struct arm11_common *arm11, uint32_t *dscr)
301 {
302 FNC_INFO;
303
304 uint32_t dscr_local_tmp_copy;
305
306 if (!dscr)
307 {
308 dscr = &dscr_local_tmp_copy;
309
310 CHECK_RETVAL(arm11_read_DSCR(arm11, dscr));
311 }
312
313 if (!(*dscr & ARM11_DSCR_MODE_SELECT))
314 {
315 LOG_DEBUG("Bringing target into debug mode");
316
317 *dscr |= ARM11_DSCR_MODE_SELECT; /* Halt debug-mode */
318 arm11_write_DSCR(arm11, *dscr);
319
320 /* add further reset initialization here */
321
322 arm11->simulate_reset_on_next_halt = true;
323
324 if (*dscr & ARM11_DSCR_CORE_HALTED)
325 {
326 /** \todo TODO: this needs further scrutiny because
327 * arm11_on_enter_debug_state() never gets properly called.
328 * As a result we don't read the actual register states from
329 * the target.
330 */
331
332 arm11->target->state = TARGET_HALTED;
333 arm11->target->debug_reason = arm11_get_DSCR_debug_reason(*dscr);
334 }
335 else
336 {
337 arm11->target->state = TARGET_RUNNING;
338 arm11->target->debug_reason = DBG_REASON_NOTHALTED;
339 }
340
341 arm11_sc7_clear_vbw(arm11);
342 }
343
344 return ERROR_OK;
345 }
346
347
348
349 #define R(x) \
350 (arm11->reg_values[ARM11_RC_##x])
351
352 /** Save processor state.
353 *
354 * This is called when the HALT instruction has succeeded
355 * or on other occasions that stop the processor.
356 *
357 */
358 static int arm11_on_enter_debug_state(struct arm11_common *arm11)
359 {
360 int retval;
361 FNC_INFO;
362
363 for (size_t i = 0; i < asizeof(arm11->reg_values); i++)
364 {
365 arm11->reg_list[i].valid = 1;
366 arm11->reg_list[i].dirty = 0;
367 }
368
369 /* Save DSCR */
370 CHECK_RETVAL(arm11_read_DSCR(arm11, &R(DSCR)));
371
372 /* Save wDTR */
373
374 if (R(DSCR) & ARM11_DSCR_WDTR_FULL)
375 {
376 arm11_add_debug_SCAN_N(arm11, 0x05, ARM11_TAP_DEFAULT);
377
378 arm11_add_IR(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT);
379
380 struct scan_field chain5_fields[3];
381
382 arm11_setup_field(arm11, 32, NULL, &R(WDTR), chain5_fields + 0);
383 arm11_setup_field(arm11, 1, NULL, NULL, chain5_fields + 1);
384 arm11_setup_field(arm11, 1, NULL, NULL, chain5_fields + 2);
385
386 arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_DRPAUSE);
387 }
388 else
389 {
390 arm11->reg_list[ARM11_RC_WDTR].valid = 0;
391 }
392
393
394 /* DSCR: set ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE */
395 /* ARM1176 spec says this is needed only for wDTR/rDTR's "ITR mode", but not to issue ITRs
396 ARM1136 seems to require this to issue ITR's as well */
397
398 uint32_t new_dscr = R(DSCR) | ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE;
399
400 /* this executes JTAG queue: */
401
402 arm11_write_DSCR(arm11, new_dscr);
403
404
405 /* From the spec:
406 Before executing any instruction in debug state you have to drain the write buffer.
407 This ensures that no imprecise Data Aborts can return at a later point:*/
408
409 /** \todo TODO: Test drain write buffer. */
410
411 #if 0
412 while (1)
413 {
414 /* MRC p14,0,R0,c5,c10,0 */
415 // arm11_run_instr_no_data1(arm11, /*0xee150e1a*/0xe320f000);
416
417 /* mcr 15, 0, r0, cr7, cr10, {4} */
418 arm11_run_instr_no_data1(arm11, 0xee070f9a);
419
420 uint32_t dscr = arm11_read_DSCR(arm11);
421
422 LOG_DEBUG("DRAIN, DSCR %08x", dscr);
423
424 if (dscr & ARM11_DSCR_STICKY_IMPRECISE_DATA_ABORT)
425 {
426 arm11_run_instr_no_data1(arm11, 0xe320f000);
427
428 dscr = arm11_read_DSCR(arm11);
429
430 LOG_DEBUG("DRAIN, DSCR %08x (DONE)", dscr);
431
432 break;
433 }
434 }
435 #endif
436
437 retval = arm11_run_instr_data_prepare(arm11);
438 if (retval != ERROR_OK)
439 return retval;
440
441 /* save r0 - r14 */
442
443 /** \todo TODO: handle other mode registers */
444
445 for (size_t i = 0; i < 15; i++)
446 {
447 /* MCR p14,0,R?,c0,c5,0 */
448 retval = arm11_run_instr_data_from_core(arm11, 0xEE000E15 | (i << 12), &R(RX + i), 1);
449 if (retval != ERROR_OK)
450 return retval;
451 }
452
453 /* save rDTR */
454
455 /* check rDTRfull in DSCR */
456
457 if (R(DSCR) & ARM11_DSCR_RDTR_FULL)
458 {
459 /* MRC p14,0,R0,c0,c5,0 (move rDTR -> r0 (-> wDTR -> local var)) */
460 retval = arm11_run_instr_data_from_core_via_r0(arm11, 0xEE100E15, &R(RDTR));
461 if (retval != ERROR_OK)
462 return retval;
463 }
464 else
465 {
466 arm11->reg_list[ARM11_RC_RDTR].valid = 0;
467 }
468
469 /* save CPSR */
470
471 /* MRS r0,CPSR (move CPSR -> r0 (-> wDTR -> local var)) */
472 retval = arm11_run_instr_data_from_core_via_r0(arm11, 0xE10F0000, &R(CPSR));
473 if (retval != ERROR_OK)
474 return retval;
475
476 /* save PC */
477
478 /* MOV R0,PC (move PC -> r0 (-> wDTR -> local var)) */
479 retval = arm11_run_instr_data_from_core_via_r0(arm11, 0xE1A0000F, &R(PC));
480 if (retval != ERROR_OK)
481 return retval;
482
483 /* adjust PC depending on ARM state */
484
485 if (R(CPSR) & ARM11_CPSR_J) /* Java state */
486 {
487 arm11->reg_values[ARM11_RC_PC] -= 0;
488 }
489 else if (R(CPSR) & ARM11_CPSR_T) /* Thumb state */
490 {
491 arm11->reg_values[ARM11_RC_PC] -= 4;
492 }
493 else /* ARM state */
494 {
495 arm11->reg_values[ARM11_RC_PC] -= 8;
496 }
497
498 if (arm11->simulate_reset_on_next_halt)
499 {
500 arm11->simulate_reset_on_next_halt = false;
501
502 LOG_DEBUG("Reset c1 Control Register");
503
504 /* Write 0 (reset value) to Control register 0 to disable MMU/Cache etc. */
505
506 /* MCR p15,0,R0,c1,c0,0 */
507 retval = arm11_run_instr_data_to_core_via_r0(arm11, 0xee010f10, 0);
508 if (retval != ERROR_OK)
509 return retval;
510
511 }
512
513 retval = arm11_run_instr_data_finish(arm11);
514 if (retval != ERROR_OK)
515 return retval;
516
517 arm11_dump_reg_changes(arm11);
518
519 return ERROR_OK;
520 }
521
522 void arm11_dump_reg_changes(struct arm11_common * arm11)
523 {
524
525 if (!(debug_level >= LOG_LVL_DEBUG))
526 {
527 return;
528 }
529
530 for (size_t i = 0; i < ARM11_REGCACHE_COUNT; i++)
531 {
532 if (!arm11->reg_list[i].valid)
533 {
534 if (arm11->reg_history[i].valid)
535 LOG_DEBUG("%8s INVALID (%08" PRIx32 ")", arm11_reg_defs[i].name, arm11->reg_history[i].value);
536 }
537 else
538 {
539 if (arm11->reg_history[i].valid)
540 {
541 if (arm11->reg_history[i].value != arm11->reg_values[i])
542 LOG_DEBUG("%8s %08" PRIx32 " (%08" PRIx32 ")", arm11_reg_defs[i].name, arm11->reg_values[i], arm11->reg_history[i].value);
543 }
544 else
545 {
546 LOG_DEBUG("%8s %08" PRIx32 " (INVALID)", arm11_reg_defs[i].name, arm11->reg_values[i]);
547 }
548 }
549 }
550 }
551
552 /** Restore processor state
553 *
554 * This is called in preparation for the RESTART function.
555 *
556 */
557 static int arm11_leave_debug_state(struct arm11_common *arm11)
558 {
559 FNC_INFO;
560 int retval;
561
562 retval = arm11_run_instr_data_prepare(arm11);
563 if (retval != ERROR_OK)
564 return retval;
565
566 /** \todo TODO: handle other mode registers */
567
568 /* restore R1 - R14 */
569
570 for (size_t i = 1; i < 15; i++)
571 {
572 if (!arm11->reg_list[ARM11_RC_RX + i].dirty)
573 continue;
574
575 /* MRC p14,0,r?,c0,c5,0 */
576 arm11_run_instr_data_to_core1(arm11, 0xee100e15 | (i << 12), R(RX + i));
577
578 // LOG_DEBUG("RESTORE R" ZU " %08x", i, R(RX + i));
579 }
580
581 retval = arm11_run_instr_data_finish(arm11);
582 if (retval != ERROR_OK)
583 return retval;
584
585 /* spec says clear wDTR and rDTR; we assume they are clear as
586 otherwise our programming would be sloppy */
587 {
588 uint32_t DSCR;
589
590 CHECK_RETVAL(arm11_read_DSCR(arm11, &DSCR));
591
592 if (DSCR & (ARM11_DSCR_RDTR_FULL | ARM11_DSCR_WDTR_FULL))
593 {
594 /*
595 The wDTR/rDTR two registers that are used to send/receive data to/from
596 the core in tandem with corresponding instruction codes that are
597 written into the core. The RDTR FULL/WDTR FULL flag indicates that the
598 registers hold data that was written by one side (CPU or JTAG) and not
599 read out by the other side.
600 */
601 LOG_ERROR("wDTR/rDTR inconsistent (DSCR %08" PRIx32 ")", DSCR);
602 return ERROR_FAIL;
603 }
604 }
605
606 retval = arm11_run_instr_data_prepare(arm11);
607 if (retval != ERROR_OK)
608 return retval;
609
610 /* restore original wDTR */
611
612 if ((R(DSCR) & ARM11_DSCR_WDTR_FULL) || arm11->reg_list[ARM11_RC_WDTR].dirty)
613 {
614 /* MCR p14,0,R0,c0,c5,0 */
615 retval = arm11_run_instr_data_to_core_via_r0(arm11, 0xee000e15, R(WDTR));
616 if (retval != ERROR_OK)
617 return retval;
618 }
619
620 /* restore CPSR */
621
622 /* MSR CPSR,R0*/
623 retval = arm11_run_instr_data_to_core_via_r0(arm11, 0xe129f000, R(CPSR));
624 if (retval != ERROR_OK)
625 return retval;
626
627
628 /* restore PC */
629
630 /* MOV PC,R0 */
631 retval = arm11_run_instr_data_to_core_via_r0(arm11, 0xe1a0f000, R(PC));
632 if (retval != ERROR_OK)
633 return retval;
634
635
636 /* restore R0 */
637
638 /* MRC p14,0,r0,c0,c5,0 */
639 arm11_run_instr_data_to_core1(arm11, 0xee100e15, R(R0));
640
641 retval = arm11_run_instr_data_finish(arm11);
642 if (retval != ERROR_OK)
643 return retval;
644
645 /* restore DSCR */
646
647 arm11_write_DSCR(arm11, R(DSCR));
648
649 /* restore rDTR */
650
651 if (R(DSCR) & ARM11_DSCR_RDTR_FULL || arm11->reg_list[ARM11_RC_RDTR].dirty)
652 {
653 arm11_add_debug_SCAN_N(arm11, 0x05, ARM11_TAP_DEFAULT);
654
655 arm11_add_IR(arm11, ARM11_EXTEST, ARM11_TAP_DEFAULT);
656
657 struct scan_field chain5_fields[3];
658
659 uint8_t Ready = 0; /* ignored */
660 uint8_t Valid = 0; /* ignored */
661
662 arm11_setup_field(arm11, 32, &R(RDTR), NULL, chain5_fields + 0);
663 arm11_setup_field(arm11, 1, &Ready, NULL, chain5_fields + 1);
664 arm11_setup_field(arm11, 1, &Valid, NULL, chain5_fields + 2);
665
666 arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_DRPAUSE);
667 }
668
669 arm11_record_register_history(arm11);
670
671 return ERROR_OK;
672 }
673
674 static void arm11_record_register_history(struct arm11_common *arm11)
675 {
676 for (size_t i = 0; i < ARM11_REGCACHE_COUNT; i++)
677 {
678 arm11->reg_history[i].value = arm11->reg_values[i];
679 arm11->reg_history[i].valid = arm11->reg_list[i].valid;
680
681 arm11->reg_list[i].valid = 0;
682 arm11->reg_list[i].dirty = 0;
683 }
684 }
685
686
687 /* poll current target status */
688 static int arm11_poll(struct target *target)
689 {
690 FNC_INFO;
691 int retval;
692
693 struct arm11_common * arm11 = target->arch_info;
694
695 uint32_t dscr;
696
697 CHECK_RETVAL(arm11_read_DSCR(arm11, &dscr));
698
699 LOG_DEBUG("DSCR %08" PRIx32 "", dscr);
700
701 CHECK_RETVAL(arm11_check_init(arm11, &dscr));
702
703 if (dscr & ARM11_DSCR_CORE_HALTED)
704 {
705 if (target->state != TARGET_HALTED)
706 {
707 enum target_state old_state = target->state;
708
709 LOG_DEBUG("enter TARGET_HALTED");
710 target->state = TARGET_HALTED;
711 target->debug_reason = arm11_get_DSCR_debug_reason(dscr);
712 retval = arm11_on_enter_debug_state(arm11);
713 if (retval != ERROR_OK)
714 return retval;
715
716 target_call_event_callbacks(target,
717 old_state == TARGET_DEBUG_RUNNING ? TARGET_EVENT_DEBUG_HALTED : TARGET_EVENT_HALTED);
718 }
719 }
720 else
721 {
722 if (target->state != TARGET_RUNNING && target->state != TARGET_DEBUG_RUNNING)
723 {
724 LOG_DEBUG("enter TARGET_RUNNING");
725 target->state = TARGET_RUNNING;
726 target->debug_reason = DBG_REASON_NOTHALTED;
727 }
728 }
729
730 return ERROR_OK;
731 }
732 /* architecture specific status reply */
733 static int arm11_arch_state(struct target *target)
734 {
735 struct arm11_common * arm11 = target->arch_info;
736
737 LOG_USER("target halted due to %s\ncpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "",
738 Jim_Nvp_value2name_simple(nvp_target_debug_reason, target->debug_reason)->name,
739 R(CPSR),
740 R(PC));
741
742 return ERROR_OK;
743 }
744
745 /* target request support */
746 static int arm11_target_request_data(struct target *target,
747 uint32_t size, uint8_t *buffer)
748 {
749 FNC_INFO_NOTIMPLEMENTED;
750
751 return ERROR_OK;
752 }
753
754 /* target execution control */
755 static int arm11_halt(struct target *target)
756 {
757 FNC_INFO;
758
759 struct arm11_common * arm11 = target->arch_info;
760
761 LOG_DEBUG("target->state: %s",
762 target_state_name(target));
763
764 if (target->state == TARGET_UNKNOWN)
765 {
766 arm11->simulate_reset_on_next_halt = true;
767 }
768
769 if (target->state == TARGET_HALTED)
770 {
771 LOG_DEBUG("target was already halted");
772 return ERROR_OK;
773 }
774
775 arm11_add_IR(arm11, ARM11_HALT, TAP_IDLE);
776
777 CHECK_RETVAL(jtag_execute_queue());
778
779 uint32_t dscr;
780
781 int i = 0;
782 while (1)
783 {
784 CHECK_RETVAL(arm11_read_DSCR(arm11, &dscr));
785
786 if (dscr & ARM11_DSCR_CORE_HALTED)
787 break;
788
789
790 long long then = 0;
791 if (i == 1000)
792 {
793 then = timeval_ms();
794 }
795 if (i >= 1000)
796 {
797 if ((timeval_ms()-then) > 1000)
798 {
799 LOG_WARNING("Timeout (1000ms) waiting for instructions to complete");
800 return ERROR_FAIL;
801 }
802 }
803 i++;
804 }
805
806 arm11_on_enter_debug_state(arm11);
807
808 enum target_state old_state = target->state;
809
810 target->state = TARGET_HALTED;
811 target->debug_reason = arm11_get_DSCR_debug_reason(dscr);
812
813 CHECK_RETVAL(
814 target_call_event_callbacks(target,
815 old_state == TARGET_DEBUG_RUNNING ? TARGET_EVENT_DEBUG_HALTED : TARGET_EVENT_HALTED));
816
817 return ERROR_OK;
818 }
819
820 static int arm11_resume(struct target *target, int current,
821 uint32_t address, int handle_breakpoints, int debug_execution)
822 {
823 FNC_INFO;
824
825 // LOG_DEBUG("current %d address %08x handle_breakpoints %d debug_execution %d",
826 // current, address, handle_breakpoints, debug_execution);
827
828 struct arm11_common * arm11 = target->arch_info;
829
830 LOG_DEBUG("target->state: %s",
831 target_state_name(target));
832
833
834 if (target->state != TARGET_HALTED)
835 {
836 LOG_ERROR("Target not halted");
837 return ERROR_TARGET_NOT_HALTED;
838 }
839
840 if (!current)
841 R(PC) = address;
842
843 LOG_DEBUG("RESUME PC %08" PRIx32 "%s", R(PC), !current ? "!" : "");
844
845 /* clear breakpoints/watchpoints and VCR*/
846 arm11_sc7_clear_vbw(arm11);
847
848 /* Set up breakpoints */
849 if (!debug_execution)
850 {
851 /* check if one matches PC and step over it if necessary */
852
853 struct breakpoint * bp;
854
855 for (bp = target->breakpoints; bp; bp = bp->next)
856 {
857 if (bp->address == R(PC))
858 {
859 LOG_DEBUG("must step over %08" PRIx32 "", bp->address);
860 arm11_step(target, 1, 0, 0);
861 break;
862 }
863 }
864
865 /* set all breakpoints */
866
867 size_t brp_num = 0;
868
869 for (bp = target->breakpoints; bp; bp = bp->next)
870 {
871 struct arm11_sc7_action brp[2];
872
873 brp[0].write = 1;
874 brp[0].address = ARM11_SC7_BVR0 + brp_num;
875 brp[0].value = bp->address;
876 brp[1].write = 1;
877 brp[1].address = ARM11_SC7_BCR0 + brp_num;
878 brp[1].value = 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (0 << 21);
879
880 arm11_sc7_run(arm11, brp, asizeof(brp));
881
882 LOG_DEBUG("Add BP " ZU " at %08" PRIx32 "", brp_num, bp->address);
883
884 brp_num++;
885 }
886
887 arm11_sc7_set_vcr(arm11, arm11_vcr);
888 }
889
890 arm11_leave_debug_state(arm11);
891
892 arm11_add_IR(arm11, ARM11_RESTART, TAP_IDLE);
893
894 CHECK_RETVAL(jtag_execute_queue());
895
896 int i = 0;
897 while (1)
898 {
899 uint32_t dscr;
900
901 CHECK_RETVAL(arm11_read_DSCR(arm11, &dscr));
902
903 LOG_DEBUG("DSCR %08" PRIx32 "", dscr);
904
905 if (dscr & ARM11_DSCR_CORE_RESTARTED)
906 break;
907
908
909 long long then = 0;
910 if (i == 1000)
911 {
912 then = timeval_ms();
913 }
914 if (i >= 1000)
915 {
916 if ((timeval_ms()-then) > 1000)
917 {
918 LOG_WARNING("Timeout (1000ms) waiting for instructions to complete");
919 return ERROR_FAIL;
920 }
921 }
922 i++;
923 }
924
925 if (!debug_execution)
926 {
927 target->state = TARGET_RUNNING;
928 target->debug_reason = DBG_REASON_NOTHALTED;
929
930 CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_RESUMED));
931 }
932 else
933 {
934 target->state = TARGET_DEBUG_RUNNING;
935 target->debug_reason = DBG_REASON_NOTHALTED;
936
937 CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_RESUMED));
938 }
939
940 return ERROR_OK;
941 }
942
943
944 static int armv4_5_to_arm11(int reg)
945 {
946 if (reg < 16)
947 return reg;
948 switch (reg)
949 {
950 case ARMV4_5_CPSR:
951 return ARM11_RC_CPSR;
952 case 16:
953 /* FIX!!! handle thumb better! */
954 return ARM11_RC_CPSR;
955 default:
956 LOG_ERROR("BUG: register translation from armv4_5 to arm11 not supported %d", reg);
957 exit(-1);
958 }
959 }
960
961
962 static uint32_t arm11_sim_get_reg(struct arm_sim_interface *sim, int reg)
963 {
964 struct arm11_common * arm11 = (struct arm11_common *)sim->user_data;
965
966 reg=armv4_5_to_arm11(reg);
967
968 return buf_get_u32(arm11->reg_list[reg].value, 0, 32);
969 }
970
971 static void arm11_sim_set_reg(struct arm_sim_interface *sim,
972 int reg, uint32_t value)
973 {
974 struct arm11_common * arm11 = (struct arm11_common *)sim->user_data;
975
976 reg=armv4_5_to_arm11(reg);
977
978 buf_set_u32(arm11->reg_list[reg].value, 0, 32, value);
979 }
980
981 static uint32_t arm11_sim_get_cpsr(struct arm_sim_interface *sim,
982 int pos, int bits)
983 {
984 struct arm11_common * arm11 = (struct arm11_common *)sim->user_data;
985
986 return buf_get_u32(arm11->reg_list[ARM11_RC_CPSR].value, pos, bits);
987 }
988
989 static enum armv4_5_state arm11_sim_get_state(struct arm_sim_interface *sim)
990 {
991 // struct arm11_common * arm11 = (struct arm11_common *)sim->user_data;
992
993 /* FIX!!!! we should implement thumb for arm11 */
994 return ARMV4_5_STATE_ARM;
995 }
996
997 static void arm11_sim_set_state(struct arm_sim_interface *sim,
998 enum armv4_5_state mode)
999 {
1000 // struct arm11_common * arm11 = (struct arm11_common *)sim->user_data;
1001
1002 /* FIX!!!! we should implement thumb for arm11 */
1003 LOG_ERROR("Not implemetned!");
1004 }
1005
1006
1007 static enum armv4_5_mode arm11_sim_get_mode(struct arm_sim_interface *sim)
1008 {
1009 //struct arm11_common * arm11 = (struct arm11_common *)sim->user_data;
1010
1011 /* FIX!!!! we should implement something that returns the current mode here!!! */
1012 return ARMV4_5_MODE_USR;
1013 }
1014
1015 static int arm11_simulate_step(struct target *target, uint32_t *dry_run_pc)
1016 {
1017 struct arm_sim_interface sim;
1018
1019 sim.user_data=target->arch_info;
1020 sim.get_reg=&arm11_sim_get_reg;
1021 sim.set_reg=&arm11_sim_set_reg;
1022 sim.get_reg_mode=&arm11_sim_get_reg;
1023 sim.set_reg_mode=&arm11_sim_set_reg;
1024 sim.get_cpsr=&arm11_sim_get_cpsr;
1025 sim.get_mode=&arm11_sim_get_mode;
1026 sim.get_state=&arm11_sim_get_state;
1027 sim.set_state=&arm11_sim_set_state;
1028
1029 return arm_simulate_step_core(target, dry_run_pc, &sim);
1030
1031 }
1032
1033 static int arm11_step(struct target *target, int current,
1034 uint32_t address, int handle_breakpoints)
1035 {
1036 FNC_INFO;
1037
1038 LOG_DEBUG("target->state: %s",
1039 target_state_name(target));
1040
1041 if (target->state != TARGET_HALTED)
1042 {
1043 LOG_WARNING("target was not halted");
1044 return ERROR_TARGET_NOT_HALTED;
1045 }
1046
1047 struct arm11_common * arm11 = target->arch_info;
1048
1049 if (!current)
1050 R(PC) = address;
1051
1052 LOG_DEBUG("STEP PC %08" PRIx32 "%s", R(PC), !current ? "!" : "");
1053
1054
1055 /** \todo TODO: Thumb not supported here */
1056
1057 uint32_t next_instruction;
1058
1059 CHECK_RETVAL(arm11_read_memory_word(arm11, R(PC), &next_instruction));
1060
1061 /* skip over BKPT */
1062 if ((next_instruction & 0xFFF00070) == 0xe1200070)
1063 {
1064 R(PC) += 4;
1065 arm11->reg_list[ARM11_RC_PC].valid = 1;
1066 arm11->reg_list[ARM11_RC_PC].dirty = 0;
1067 LOG_DEBUG("Skipping BKPT");
1068 }
1069 /* skip over Wait for interrupt / Standby */
1070 /* mcr 15, 0, r?, cr7, cr0, {4} */
1071 else if ((next_instruction & 0xFFFF0FFF) == 0xee070f90)
1072 {
1073 R(PC) += 4;
1074 arm11->reg_list[ARM11_RC_PC].valid = 1;
1075 arm11->reg_list[ARM11_RC_PC].dirty = 0;
1076 LOG_DEBUG("Skipping WFI");
1077 }
1078 /* ignore B to self */
1079 else if ((next_instruction & 0xFEFFFFFF) == 0xeafffffe)
1080 {
1081 LOG_DEBUG("Not stepping jump to self");
1082 }
1083 else
1084 {
1085 /** \todo TODO: check if break-/watchpoints make any sense at all in combination
1086 * with this. */
1087
1088 /** \todo TODO: check if disabling IRQs might be a good idea here. Alternatively
1089 * the VCR might be something worth looking into. */
1090
1091
1092 /* Set up breakpoint for stepping */
1093
1094 struct arm11_sc7_action brp[2];
1095
1096 brp[0].write = 1;
1097 brp[0].address = ARM11_SC7_BVR0;
1098 brp[1].write = 1;
1099 brp[1].address = ARM11_SC7_BCR0;
1100
1101 if (arm11_config_hardware_step)
1102 {
1103 /* hardware single stepping be used if possible or is it better to
1104 * always use the same code path? Hardware single stepping is not supported
1105 * on all hardware
1106 */
1107 brp[0].value = R(PC);
1108 brp[1].value = 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (2 << 21);
1109 } else
1110 {
1111 /* sets a breakpoint on the next PC(calculated by simulation),
1112 */
1113 uint32_t next_pc;
1114 int retval;
1115 retval = arm11_simulate_step(target, &next_pc);
1116 if (retval != ERROR_OK)
1117 return retval;
1118
1119 brp[0].value = next_pc;
1120 brp[1].value = 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (0 << 21);
1121 }
1122
1123 CHECK_RETVAL(arm11_sc7_run(arm11, brp, asizeof(brp)));
1124
1125 /* resume */
1126
1127
1128 if (arm11_config_step_irq_enable)
1129 R(DSCR) &= ~ARM11_DSCR_INTERRUPTS_DISABLE; /* should be redundant */
1130 else
1131 R(DSCR) |= ARM11_DSCR_INTERRUPTS_DISABLE;
1132
1133
1134 CHECK_RETVAL(arm11_leave_debug_state(arm11));
1135
1136 arm11_add_IR(arm11, ARM11_RESTART, TAP_IDLE);
1137
1138 CHECK_RETVAL(jtag_execute_queue());
1139
1140 /* wait for halt */
1141 int i = 0;
1142 while (1)
1143 {
1144 uint32_t dscr;
1145
1146 CHECK_RETVAL(arm11_read_DSCR(arm11, &dscr));
1147
1148 LOG_DEBUG("DSCR %08" PRIx32 "e", dscr);
1149
1150 if ((dscr & (ARM11_DSCR_CORE_RESTARTED | ARM11_DSCR_CORE_HALTED)) ==
1151 (ARM11_DSCR_CORE_RESTARTED | ARM11_DSCR_CORE_HALTED))
1152 break;
1153
1154 long long then = 0;
1155 if (i == 1000)
1156 {
1157 then = timeval_ms();
1158 }
1159 if (i >= 1000)
1160 {
1161 if ((timeval_ms()-then) > 1000)
1162 {
1163 LOG_WARNING("Timeout (1000ms) waiting for instructions to complete");
1164 return ERROR_FAIL;
1165 }
1166 }
1167 i++;
1168 }
1169
1170 /* clear breakpoint */
1171 arm11_sc7_clear_vbw(arm11);
1172
1173 /* save state */
1174 CHECK_RETVAL(arm11_on_enter_debug_state(arm11));
1175
1176 /* restore default state */
1177 R(DSCR) &= ~ARM11_DSCR_INTERRUPTS_DISABLE;
1178
1179 }
1180
1181 // target->state = TARGET_HALTED;
1182 target->debug_reason = DBG_REASON_SINGLESTEP;
1183
1184 CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_HALTED));
1185
1186 return ERROR_OK;
1187 }
1188
1189 static int arm11_assert_reset(struct target *target)
1190 {
1191 FNC_INFO;
1192 int retval;
1193
1194 struct arm11_common * arm11 = target->arch_info;
1195 retval = arm11_check_init(arm11, NULL);
1196 if (retval != ERROR_OK)
1197 return retval;
1198
1199 target->state = TARGET_UNKNOWN;
1200
1201 /* we would very much like to reset into the halted, state,
1202 * but resetting and halting is second best... */
1203 if (target->reset_halt)
1204 {
1205 CHECK_RETVAL(target_halt(target));
1206 }
1207
1208
1209 /* srst is funny. We can not do *anything* else while it's asserted
1210 * and it has unkonwn side effects. Make sure no other code runs
1211 * meanwhile.
1212 *
1213 * Code below assumes srst:
1214 *
1215 * - Causes power-on-reset (but of what parts of the system?). Bug
1216 * in arm11?
1217 *
1218 * - Messes us TAP state without asserting trst.
1219 *
1220 * - There is another bug in the arm11 core. When you generate an access to
1221 * external logic (for example ddr controller via AHB bus) and that block
1222 * is not configured (perhaps it is still held in reset), that transaction
1223 * will never complete. This will hang arm11 core but it will also hang
1224 * JTAG controller. Nothing, short of srst assertion will bring it out of
1225 * this.
1226 *
1227 * Mysteries:
1228 *
1229 * - What should the PC be after an srst reset when starting in the halted
1230 * state?
1231 */
1232
1233 jtag_add_reset(0, 1);
1234 jtag_add_reset(0, 0);
1235
1236 /* How long do we have to wait? */
1237 jtag_add_sleep(5000);
1238
1239 /* un-mess up TAP state */
1240 jtag_add_tlr();
1241
1242 retval = jtag_execute_queue();
1243 if (retval != ERROR_OK)
1244 {
1245 return retval;
1246 }
1247
1248 return ERROR_OK;
1249 }
1250
1251 static int arm11_deassert_reset(struct target *target)
1252 {
1253 return ERROR_OK;
1254 }
1255
1256 static int arm11_soft_reset_halt(struct target *target)
1257 {
1258 FNC_INFO_NOTIMPLEMENTED;
1259
1260 return ERROR_OK;
1261 }
1262
1263 /* target register access for gdb */
1264 static int arm11_get_gdb_reg_list(struct target *target,
1265 struct reg **reg_list[], int *reg_list_size)
1266 {
1267 FNC_INFO;
1268
1269 struct arm11_common * arm11 = target->arch_info;
1270
1271 *reg_list_size = ARM11_GDB_REGISTER_COUNT;
1272 *reg_list = malloc(sizeof(struct reg*) * ARM11_GDB_REGISTER_COUNT);
1273
1274 for (size_t i = 16; i < 24; i++)
1275 {
1276 (*reg_list)[i] = &arm11_gdb_dummy_fp_reg;
1277 }
1278
1279 (*reg_list)[24] = &arm11_gdb_dummy_fps_reg;
1280
1281 for (size_t i = 0; i < ARM11_REGCACHE_COUNT; i++)
1282 {
1283 if (arm11_reg_defs[i].gdb_num == -1)
1284 continue;
1285
1286 (*reg_list)[arm11_reg_defs[i].gdb_num] = arm11->reg_list + i;
1287 }
1288
1289 return ERROR_OK;
1290 }
1291
1292 /* target memory access
1293 * size: 1 = byte (8bit), 2 = half-word (16bit), 4 = word (32bit)
1294 * count: number of items of <size>
1295 *
1296 * arm11_config_memrw_no_increment - in the future we may want to be able
1297 * to read/write a range of data to a "port". a "port" is an action on
1298 * read memory address for some peripheral.
1299 */
1300 static int arm11_read_memory_inner(struct target *target,
1301 uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer,
1302 bool arm11_config_memrw_no_increment)
1303 {
1304 /** \todo TODO: check if buffer cast to uint32_t* and uint16_t* might cause alignment problems */
1305 int retval;
1306
1307 FNC_INFO;
1308
1309 if (target->state != TARGET_HALTED)
1310 {
1311 LOG_WARNING("target was not halted");
1312 return ERROR_TARGET_NOT_HALTED;
1313 }
1314
1315 LOG_DEBUG("ADDR %08" PRIx32 " SIZE %08" PRIx32 " COUNT %08" PRIx32 "", address, size, count);
1316
1317 struct arm11_common * arm11 = target->arch_info;
1318
1319 retval = arm11_run_instr_data_prepare(arm11);
1320 if (retval != ERROR_OK)
1321 return retval;
1322
1323 /* MRC p14,0,r0,c0,c5,0 */
1324 retval = arm11_run_instr_data_to_core1(arm11, 0xee100e15, address);
1325 if (retval != ERROR_OK)
1326 return retval;
1327
1328 switch (size)
1329 {
1330 case 1:
1331 /** \todo TODO: check if dirty is the right choice to force a rewrite on arm11_resume() */
1332 arm11->reg_list[ARM11_RC_R1].dirty = 1;
1333
1334 for (size_t i = 0; i < count; i++)
1335 {
1336 /* ldrb r1, [r0], #1 */
1337 /* ldrb r1, [r0] */
1338 arm11_run_instr_no_data1(arm11,
1339 !arm11_config_memrw_no_increment ? 0xe4d01001 : 0xe5d01000);
1340
1341 uint32_t res;
1342 /* MCR p14,0,R1,c0,c5,0 */
1343 arm11_run_instr_data_from_core(arm11, 0xEE001E15, &res, 1);
1344
1345 *buffer++ = res;
1346 }
1347
1348 break;
1349
1350 case 2:
1351 {
1352 arm11->reg_list[ARM11_RC_R1].dirty = 1;
1353
1354 for (size_t i = 0; i < count; i++)
1355 {
1356 /* ldrh r1, [r0], #2 */
1357 arm11_run_instr_no_data1(arm11,
1358 !arm11_config_memrw_no_increment ? 0xe0d010b2 : 0xe1d010b0);
1359
1360 uint32_t res;
1361
1362 /* MCR p14,0,R1,c0,c5,0 */
1363 arm11_run_instr_data_from_core(arm11, 0xEE001E15, &res, 1);
1364
1365 uint16_t svalue = res;
1366 memcpy(buffer + i * sizeof(uint16_t), &svalue, sizeof(uint16_t));
1367 }
1368
1369 break;
1370 }
1371
1372 case 4:
1373 {
1374 uint32_t instr = !arm11_config_memrw_no_increment ? 0xecb05e01 : 0xed905e00;
1375 /** \todo TODO: buffer cast to uint32_t* causes alignment warnings */
1376 uint32_t *words = (uint32_t *)buffer;
1377
1378 /* LDC p14,c5,[R0],#4 */
1379 /* LDC p14,c5,[R0] */
1380 arm11_run_instr_data_from_core(arm11, instr, words, count);
1381 break;
1382 }
1383 }
1384
1385 return arm11_run_instr_data_finish(arm11);
1386 }
1387
1388 static int arm11_read_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
1389 {
1390 return arm11_read_memory_inner(target, address, size, count, buffer, false);
1391 }
1392
1393 /*
1394 * arm11_config_memrw_no_increment - in the future we may want to be able
1395 * to read/write a range of data to a "port". a "port" is an action on
1396 * read memory address for some peripheral.
1397 */
1398 static int arm11_write_memory_inner(struct target *target,
1399 uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer,
1400 bool arm11_config_memrw_no_increment)
1401 {
1402 int retval;
1403 FNC_INFO;
1404
1405 if (target->state != TARGET_HALTED)
1406 {
1407 LOG_WARNING("target was not halted");
1408 return ERROR_TARGET_NOT_HALTED;
1409 }
1410
1411 LOG_DEBUG("ADDR %08" PRIx32 " SIZE %08" PRIx32 " COUNT %08" PRIx32 "", address, size, count);
1412
1413 struct arm11_common * arm11 = target->arch_info;
1414
1415 retval = arm11_run_instr_data_prepare(arm11);
1416 if (retval != ERROR_OK)
1417 return retval;
1418
1419 /* MRC p14,0,r0,c0,c5,0 */
1420 retval = arm11_run_instr_data_to_core1(arm11, 0xee100e15, address);
1421 if (retval != ERROR_OK)
1422 return retval;
1423
1424 /* burst writes are not used for single words as those may well be
1425 * reset init script writes.
1426 *
1427 * The other advantage is that as burst writes are default, we'll
1428 * now exercise both burst and non-burst code paths with the
1429 * default settings, increasing code coverage.
1430 */
1431 bool burst = arm11_config_memwrite_burst && (count > 1);
1432
1433 switch (size)
1434 {
1435 case 1:
1436 {
1437 arm11->reg_list[ARM11_RC_R1].dirty = 1;
1438
1439 for (size_t i = 0; i < count; i++)
1440 {
1441 /* MRC p14,0,r1,c0,c5,0 */
1442 retval = arm11_run_instr_data_to_core1(arm11, 0xee101e15, *buffer++);
1443 if (retval != ERROR_OK)
1444 return retval;
1445
1446 /* strb r1, [r0], #1 */
1447 /* strb r1, [r0] */
1448 retval = arm11_run_instr_no_data1(arm11,
1449 !arm11_config_memrw_no_increment ? 0xe4c01001 : 0xe5c01000);
1450 if (retval != ERROR_OK)
1451 return retval;
1452 }
1453
1454 break;
1455 }
1456
1457 case 2:
1458 {
1459 arm11->reg_list[ARM11_RC_R1].dirty = 1;
1460
1461 for (size_t i = 0; i < count; i++)
1462 {
1463 uint16_t value;
1464 memcpy(&value, buffer + i * sizeof(uint16_t), sizeof(uint16_t));
1465
1466 /* MRC p14,0,r1,c0,c5,0 */
1467 retval = arm11_run_instr_data_to_core1(arm11, 0xee101e15, value);
1468 if (retval != ERROR_OK)
1469 return retval;
1470
1471 /* strh r1, [r0], #2 */
1472 /* strh r1, [r0] */
1473 retval = arm11_run_instr_no_data1(arm11,
1474 !arm11_config_memrw_no_increment ? 0xe0c010b2 : 0xe1c010b0);
1475 if (retval != ERROR_OK)
1476 return retval;
1477 }
1478
1479 break;
1480 }
1481
1482 case 4: {
1483 uint32_t instr = !arm11_config_memrw_no_increment ? 0xeca05e01 : 0xed805e00;
1484
1485 /** \todo TODO: buffer cast to uint32_t* causes alignment warnings */
1486 uint32_t *words = (uint32_t*)buffer;
1487
1488 if (!burst)
1489 {
1490 /* STC p14,c5,[R0],#4 */
1491 /* STC p14,c5,[R0]*/
1492 retval = arm11_run_instr_data_to_core(arm11, instr, words, count);
1493 if (retval != ERROR_OK)
1494 return retval;
1495 }
1496 else
1497 {
1498 /* STC p14,c5,[R0],#4 */
1499 /* STC p14,c5,[R0]*/
1500 retval = arm11_run_instr_data_to_core_noack(arm11, instr, words, count);
1501 if (retval != ERROR_OK)
1502 return retval;
1503 }
1504
1505 break;
1506 }
1507 }
1508
1509 /* r0 verification */
1510 if (!arm11_config_memrw_no_increment)
1511 {
1512 uint32_t r0;
1513
1514 /* MCR p14,0,R0,c0,c5,0 */
1515 retval = arm11_run_instr_data_from_core(arm11, 0xEE000E15, &r0, 1);
1516 if (retval != ERROR_OK)
1517 return retval;
1518
1519 if (address + size * count != r0)
1520 {
1521 LOG_ERROR("Data transfer failed. Expected end "
1522 "address 0x%08x, got 0x%08x",
1523 (unsigned) (address + size * count),
1524 (unsigned) r0);
1525
1526 if (burst)
1527 LOG_ERROR("use 'arm11 memwrite burst disable' to disable fast burst mode");
1528
1529 if (arm11_config_memwrite_error_fatal)
1530 return ERROR_FAIL;
1531 }
1532 }
1533
1534 return arm11_run_instr_data_finish(arm11);
1535 }
1536
1537 static int arm11_write_memory(struct target *target,
1538 uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
1539 {
1540 return arm11_write_memory_inner(target, address, size, count, buffer, false);
1541 }
1542
1543 /* write target memory in multiples of 4 byte, optimized for writing large quantities of data */
1544 static int arm11_bulk_write_memory(struct target *target,
1545 uint32_t address, uint32_t count, uint8_t *buffer)
1546 {
1547 FNC_INFO;
1548
1549 if (target->state != TARGET_HALTED)
1550 {
1551 LOG_WARNING("target was not halted");
1552 return ERROR_TARGET_NOT_HALTED;
1553 }
1554
1555 return arm11_write_memory(target, address, 4, count, buffer);
1556 }
1557
1558 /* here we have nothing target specific to contribute, so we fail and then the
1559 * fallback code will read data from the target and calculate the CRC on the
1560 * host.
1561 */
1562 static int arm11_checksum_memory(struct target *target,
1563 uint32_t address, uint32_t count, uint32_t* checksum)
1564 {
1565 return ERROR_FAIL;
1566 }
1567
1568 /* target break-/watchpoint control
1569 * rw: 0 = write, 1 = read, 2 = access
1570 */
1571 static int arm11_add_breakpoint(struct target *target,
1572 struct breakpoint *breakpoint)
1573 {
1574 FNC_INFO;
1575
1576 struct arm11_common * arm11 = target->arch_info;
1577
1578 #if 0
1579 if (breakpoint->type == BKPT_SOFT)
1580 {
1581 LOG_INFO("sw breakpoint requested, but software breakpoints not enabled");
1582 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1583 }
1584 #endif
1585
1586 if (!arm11->free_brps)
1587 {
1588 LOG_DEBUG("no breakpoint unit available for hardware breakpoint");
1589 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1590 }
1591
1592 if (breakpoint->length != 4)
1593 {
1594 LOG_DEBUG("only breakpoints of four bytes length supported");
1595 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1596 }
1597
1598 arm11->free_brps--;
1599
1600 return ERROR_OK;
1601 }
1602
1603 static int arm11_remove_breakpoint(struct target *target,
1604 struct breakpoint *breakpoint)
1605 {
1606 FNC_INFO;
1607
1608 struct arm11_common * arm11 = target->arch_info;
1609
1610 arm11->free_brps++;
1611
1612 return ERROR_OK;
1613 }
1614
1615 static int arm11_add_watchpoint(struct target *target,
1616 struct watchpoint *watchpoint)
1617 {
1618 FNC_INFO_NOTIMPLEMENTED;
1619
1620 return ERROR_OK;
1621 }
1622
1623 static int arm11_remove_watchpoint(struct target *target,
1624 struct watchpoint *watchpoint)
1625 {
1626 FNC_INFO_NOTIMPLEMENTED;
1627
1628 return ERROR_OK;
1629 }
1630
1631 // HACKHACKHACK - FIXME mode/state
1632 /* target algorithm support */
1633 static int arm11_run_algorithm(struct target *target,
1634 int num_mem_params, struct mem_param *mem_params,
1635 int num_reg_params, struct reg_param *reg_params,
1636 uint32_t entry_point, uint32_t exit_point,
1637 int timeout_ms, void *arch_info)
1638 {
1639 struct arm11_common *arm11 = target->arch_info;
1640 // enum armv4_5_state core_state = arm11->core_state;
1641 // enum armv4_5_mode core_mode = arm11->core_mode;
1642 uint32_t context[16];
1643 uint32_t cpsr;
1644 int exit_breakpoint_size = 0;
1645 int retval = ERROR_OK;
1646 LOG_DEBUG("Running algorithm");
1647
1648
1649 if (target->state != TARGET_HALTED)
1650 {
1651 LOG_WARNING("target not halted");
1652 return ERROR_TARGET_NOT_HALTED;
1653 }
1654
1655 // FIXME
1656 // if (armv4_5_mode_to_number(arm11->core_mode)==-1)
1657 // return ERROR_FAIL;
1658
1659 // Save regs
1660 for (unsigned i = 0; i < 16; i++)
1661 {
1662 context[i] = buf_get_u32((uint8_t*)(&arm11->reg_values[i]),0,32);
1663 LOG_DEBUG("Save %u: 0x%" PRIx32 "", i, context[i]);
1664 }
1665
1666 cpsr = buf_get_u32((uint8_t*)(arm11->reg_values + ARM11_RC_CPSR),0,32);
1667 LOG_DEBUG("Save CPSR: 0x%" PRIx32 "", cpsr);
1668
1669 for (int i = 0; i < num_mem_params; i++)
1670 {
1671 target_write_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value);
1672 }
1673
1674 // Set register parameters
1675 for (int i = 0; i < num_reg_params; i++)
1676 {
1677 struct reg *reg = register_get_by_name(arm11->core_cache, reg_params[i].reg_name, 0);
1678 if (!reg)
1679 {
1680 LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
1681 exit(-1);
1682 }
1683
1684 if (reg->size != reg_params[i].size)
1685 {
1686 LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name);
1687 exit(-1);
1688 }
1689 arm11_set_reg(reg,reg_params[i].value);
1690 // printf("%i: Set %s =%08x\n", i, reg_params[i].reg_name,val);
1691 }
1692
1693 exit_breakpoint_size = 4;
1694
1695 /* arm11->core_state = arm11_algorithm_info->core_state;
1696 if (arm11->core_state == ARMV4_5_STATE_ARM)
1697 exit_breakpoint_size = 4;
1698 else if (arm11->core_state == ARMV4_5_STATE_THUMB)
1699 exit_breakpoint_size = 2;
1700 else
1701 {
1702 LOG_ERROR("BUG: can't execute algorithms when not in ARM or Thumb state");
1703 exit(-1);
1704 }
1705 */
1706
1707
1708 /* arm11 at this point only supports ARM not THUMB mode
1709 however if this test needs to be reactivated the current state can be read back
1710 from CPSR */
1711 #if 0
1712 if (arm11_algorithm_info->core_mode != ARMV4_5_MODE_ANY)
1713 {
1714 LOG_DEBUG("setting core_mode: 0x%2.2x", arm11_algorithm_info->core_mode);
1715 buf_set_u32(arm11->reg_list[ARM11_RC_CPSR].value, 0, 5, arm11_algorithm_info->core_mode);
1716 arm11->reg_list[ARM11_RC_CPSR].dirty = 1;
1717 arm11->reg_list[ARM11_RC_CPSR].valid = 1;
1718 }
1719 #endif
1720
1721 if ((retval = breakpoint_add(target, exit_point, exit_breakpoint_size, BKPT_HARD)) != ERROR_OK)
1722 {
1723 LOG_ERROR("can't add breakpoint to finish algorithm execution");
1724 retval = ERROR_TARGET_FAILURE;
1725 goto restore;
1726 }
1727
1728 // no debug, otherwise breakpoint is not set
1729 CHECK_RETVAL(target_resume(target, 0, entry_point, 1, 0));
1730
1731 CHECK_RETVAL(target_wait_state(target, TARGET_HALTED, timeout_ms));
1732
1733 if (target->state != TARGET_HALTED)
1734 {
1735 CHECK_RETVAL(target_halt(target));
1736
1737 CHECK_RETVAL(target_wait_state(target, TARGET_HALTED, 500));
1738
1739 retval = ERROR_TARGET_TIMEOUT;
1740
1741 goto del_breakpoint;
1742 }
1743
1744 if (buf_get_u32(arm11->reg_list[15].value, 0, 32) != exit_point)
1745 {
1746 LOG_WARNING("target reentered debug state, but not at the desired exit point: 0x%4.4" PRIx32 "",
1747 buf_get_u32(arm11->reg_list[15].value, 0, 32));
1748 retval = ERROR_TARGET_TIMEOUT;
1749 goto del_breakpoint;
1750 }
1751
1752 for (int i = 0; i < num_mem_params; i++)
1753 {
1754 if (mem_params[i].direction != PARAM_OUT)
1755 target_read_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value);
1756 }
1757
1758 for (int i = 0; i < num_reg_params; i++)
1759 {
1760 if (reg_params[i].direction != PARAM_OUT)
1761 {
1762 struct reg *reg = register_get_by_name(arm11->core_cache, reg_params[i].reg_name, 0);
1763 if (!reg)
1764 {
1765 LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
1766 exit(-1);
1767 }
1768
1769 if (reg->size != reg_params[i].size)
1770 {
1771 LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name);
1772 exit(-1);
1773 }
1774
1775 buf_set_u32(reg_params[i].value, 0, 32, buf_get_u32(reg->value, 0, 32));
1776 }
1777 }
1778
1779 del_breakpoint:
1780 breakpoint_remove(target, exit_point);
1781
1782 restore:
1783 // Restore context
1784 for (size_t i = 0; i < 16; i++)
1785 {
1786 LOG_DEBUG("restoring register %s with value 0x%8.8" PRIx32 "",
1787 arm11->reg_list[i].name, context[i]);
1788 arm11_set_reg(&arm11->reg_list[i], (uint8_t*)&context[i]);
1789 }
1790 LOG_DEBUG("restoring CPSR with value 0x%8.8" PRIx32 "", cpsr);
1791 arm11_set_reg(&arm11->reg_list[ARM11_RC_CPSR], (uint8_t*)&cpsr);
1792
1793 // arm11->core_state = core_state;
1794 // arm11->core_mode = core_mode;
1795
1796 return retval;
1797 }
1798
1799 static int arm11_target_create(struct target *target, Jim_Interp *interp)
1800 {
1801 FNC_INFO;
1802
1803 NEW(struct arm11_common, arm11, 1);
1804
1805 arm11->target = target;
1806
1807 if (target->tap == NULL)
1808 return ERROR_FAIL;
1809
1810 if (target->tap->ir_length != 5)
1811 {
1812 LOG_ERROR("'target arm11' expects IR LENGTH = 5");
1813 return ERROR_COMMAND_SYNTAX_ERROR;
1814 }
1815
1816 target->arch_info = arm11;
1817
1818 return ERROR_OK;
1819 }
1820
1821 static int arm11_init_target(struct command_context *cmd_ctx,
1822 struct target *target)
1823 {
1824 /* Initialize anything we can set up without talking to the target */
1825 return arm11_build_reg_cache(target);
1826 }
1827
1828 /* talk to the target and set things up */
1829 static int arm11_examine(struct target *target)
1830 {
1831 int retval;
1832
1833 FNC_INFO;
1834
1835 struct arm11_common * arm11 = target->arch_info;
1836
1837 /* check IDCODE */
1838
1839 arm11_add_IR(arm11, ARM11_IDCODE, ARM11_TAP_DEFAULT);
1840
1841 struct scan_field idcode_field;
1842
1843 arm11_setup_field(arm11, 32, NULL, &arm11->device_id, &idcode_field);
1844
1845 arm11_add_dr_scan_vc(1, &idcode_field, TAP_DRPAUSE);
1846
1847 /* check DIDR */
1848
1849 arm11_add_debug_SCAN_N(arm11, 0x00, ARM11_TAP_DEFAULT);
1850
1851 arm11_add_IR(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT);
1852
1853 struct scan_field chain0_fields[2];
1854
1855 arm11_setup_field(arm11, 32, NULL, &arm11->didr, chain0_fields + 0);
1856 arm11_setup_field(arm11, 8, NULL, &arm11->implementor, chain0_fields + 1);
1857
1858 arm11_add_dr_scan_vc(asizeof(chain0_fields), chain0_fields, TAP_IDLE);
1859
1860 CHECK_RETVAL(jtag_execute_queue());
1861
1862 switch (arm11->device_id & 0x0FFFF000)
1863 {
1864 case 0x07B36000: LOG_INFO("found ARM1136"); break;
1865 case 0x07B56000: LOG_INFO("found ARM1156"); break;
1866 case 0x07B76000: LOG_INFO("found ARM1176"); break;
1867 default:
1868 {
1869 LOG_ERROR("'target arm11' expects IDCODE 0x*7B*7****");
1870 return ERROR_FAIL;
1871 }
1872 }
1873
1874 arm11->debug_version = (arm11->didr >> 16) & 0x0F;
1875
1876 if (arm11->debug_version != ARM11_DEBUG_V6 &&
1877 arm11->debug_version != ARM11_DEBUG_V61)
1878 {
1879 LOG_ERROR("Only ARMv6 v6 and v6.1 architectures supported.");
1880 return ERROR_FAIL;
1881 }
1882
1883 arm11->brp = ((arm11->didr >> 24) & 0x0F) + 1;
1884 arm11->wrp = ((arm11->didr >> 28) & 0x0F) + 1;
1885
1886 /** \todo TODO: reserve one brp slot if we allow breakpoints during step */
1887 arm11->free_brps = arm11->brp;
1888 arm11->free_wrps = arm11->wrp;
1889
1890 LOG_DEBUG("IDCODE %08" PRIx32 " IMPLEMENTOR %02x DIDR %08" PRIx32 "",
1891 arm11->device_id,
1892 (int)(arm11->implementor),
1893 arm11->didr);
1894
1895 /* as a side-effect this reads DSCR and thus
1896 * clears the ARM11_DSCR_STICKY_PRECISE_DATA_ABORT / Sticky Precise Data Abort Flag
1897 * as suggested by the spec.
1898 */
1899
1900 retval = arm11_check_init(arm11, NULL);
1901 if (retval != ERROR_OK)
1902 return retval;
1903
1904 target_set_examined(target);
1905
1906 return ERROR_OK;
1907 }
1908
1909
1910 /** Load a register that is marked !valid in the register cache */
1911 static int arm11_get_reg(struct reg *reg)
1912 {
1913 FNC_INFO;
1914
1915 struct target * target = ((struct arm11_reg_state *)reg->arch_info)->target;
1916
1917 if (target->state != TARGET_HALTED)
1918 {
1919 LOG_WARNING("target was not halted");
1920 return ERROR_TARGET_NOT_HALTED;
1921 }
1922
1923 /** \todo TODO: Check this. We assume that all registers are fetched at debug entry. */
1924
1925 #if 0
1926 struct arm11_common *arm11 = target->arch_info;
1927 const struct arm11_reg_defs * arm11_reg_info = arm11_reg_defs + ((struct arm11_reg_state *)reg->arch_info)->def_index;
1928 #endif
1929
1930 return ERROR_OK;
1931 }
1932
1933 /** Change a value in the register cache */
1934 static int arm11_set_reg(struct reg *reg, uint8_t *buf)
1935 {
1936 FNC_INFO;
1937
1938 struct target * target = ((struct arm11_reg_state *)reg->arch_info)->target;
1939 struct arm11_common *arm11 = target->arch_info;
1940 // const struct arm11_reg_defs * arm11_reg_info = arm11_reg_defs + ((struct arm11_reg_state *)reg->arch_info)->def_index;
1941
1942 arm11->reg_values[((struct arm11_reg_state *)reg->arch_info)->def_index] = buf_get_u32(buf, 0, 32);
1943 reg->valid = 1;
1944 reg->dirty = 1;
1945
1946 return ERROR_OK;
1947 }
1948
1949 static int arm11_build_reg_cache(struct target *target)
1950 {
1951 struct arm11_common *arm11 = target->arch_info;
1952
1953 NEW(struct reg_cache, cache, 1);
1954 NEW(struct reg, reg_list, ARM11_REGCACHE_COUNT);
1955 NEW(struct arm11_reg_state, arm11_reg_states, ARM11_REGCACHE_COUNT);
1956
1957 if (arm11_regs_arch_type == -1)
1958 arm11_regs_arch_type = register_reg_arch_type(arm11_get_reg, arm11_set_reg);
1959
1960 register_init_dummy(&arm11_gdb_dummy_fp_reg);
1961 register_init_dummy(&arm11_gdb_dummy_fps_reg);
1962
1963 arm11->reg_list = reg_list;
1964
1965 /* Build the process context cache */
1966 cache->name = "arm11 registers";
1967 cache->next = NULL;
1968 cache->reg_list = reg_list;
1969 cache->num_regs = ARM11_REGCACHE_COUNT;
1970
1971 struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache);
1972 (*cache_p) = cache;
1973
1974 arm11->core_cache = cache;
1975 // armv7m->process_context = cache;
1976
1977 size_t i;
1978
1979 /* Not very elegant assertion */
1980 if (ARM11_REGCACHE_COUNT != asizeof(arm11->reg_values) ||
1981 ARM11_REGCACHE_COUNT != asizeof(arm11_reg_defs) ||
1982 ARM11_REGCACHE_COUNT != ARM11_RC_MAX)
1983 {
1984 LOG_ERROR("BUG: arm11->reg_values inconsistent (%d " ZU " " ZU " %d)", ARM11_REGCACHE_COUNT, asizeof(arm11->reg_values), asizeof(arm11_reg_defs), ARM11_RC_MAX);
1985 exit(-1);
1986 }
1987
1988 for (i = 0; i < ARM11_REGCACHE_COUNT; i++)
1989 {
1990 struct reg * r = reg_list + i;
1991 const struct arm11_reg_defs * rd = arm11_reg_defs + i;
1992 struct arm11_reg_state * rs = arm11_reg_states + i;
1993
1994 r->name = rd->name;
1995 r->size = 32;
1996 r->value = (uint8_t *)(arm11->reg_values + i);
1997 r->dirty = 0;
1998 r->valid = 0;
1999 r->arch_type = arm11_regs_arch_type;
2000 r->arch_info = rs;
2001
2002 rs->def_index = i;
2003 rs->target = target;
2004 }
2005
2006 return ERROR_OK;
2007 }
2008
2009 static COMMAND_HELPER(arm11_handle_bool, bool *var, char *name)
2010 {
2011 if (argc == 0)
2012 {
2013 LOG_INFO("%s is %s.", name, *var ? "enabled" : "disabled");
2014 return ERROR_OK;
2015 }
2016
2017 if (argc != 1)
2018 return ERROR_COMMAND_SYNTAX_ERROR;
2019
2020 switch (args[0][0])
2021 {
2022 case '0': /* 0 */
2023 case 'f': /* false */
2024 case 'F':
2025 case 'd': /* disable */
2026 case 'D':
2027 *var = false;
2028 break;
2029
2030 case '1': /* 1 */
2031 case 't': /* true */
2032 case 'T':
2033 case 'e': /* enable */
2034 case 'E':
2035 *var = true;
2036 break;
2037 }
2038
2039 LOG_INFO("%s %s.", *var ? "Enabled" : "Disabled", name);
2040
2041 return ERROR_OK;
2042 }
2043
2044 #define BOOL_WRAPPER(name, print_name) \
2045 COMMAND_HANDLER(arm11_handle_bool_##name) \
2046 { \
2047 return CALL_COMMAND_HANDLER(arm11_handle_bool, \
2048 &arm11_config_##name, print_name); \
2049 }
2050
2051 BOOL_WRAPPER(memwrite_burst, "memory write burst mode")
2052 BOOL_WRAPPER(memwrite_error_fatal, "fatal error mode for memory writes")
2053 BOOL_WRAPPER(step_irq_enable, "IRQs while stepping")
2054 BOOL_WRAPPER(hardware_step, "hardware single step")
2055
2056 COMMAND_HANDLER(arm11_handle_vcr)
2057 {
2058 switch (argc) {
2059 case 0:
2060 break;
2061 case 1:
2062 COMMAND_PARSE_NUMBER(u32, args[0], arm11_vcr);
2063 break;
2064 default:
2065 return ERROR_COMMAND_SYNTAX_ERROR;
2066 }
2067
2068 LOG_INFO("VCR 0x%08" PRIx32 "", arm11_vcr);
2069 return ERROR_OK;
2070 }
2071
2072 static const uint32_t arm11_coproc_instruction_limits[] =
2073 {
2074 15, /* coprocessor */
2075 7, /* opcode 1 */
2076 15, /* CRn */
2077 15, /* CRm */
2078 7, /* opcode 2 */
2079 0xFFFFFFFF, /* value */
2080 };
2081
2082 static struct arm11_common * arm11_find_target(const char * arg)
2083 {
2084 struct jtag_tap * tap;
2085 struct target * t;
2086
2087 tap = jtag_tap_by_string(arg);
2088
2089 if (!tap)
2090 return 0;
2091
2092 for (t = all_targets; t; t = t->next)
2093 {
2094 if (t->tap != tap)
2095 continue;
2096
2097 /* if (t->type == arm11_target) */
2098 if (0 == strcmp(target_get_name(t), "arm11"))
2099 return t->arch_info;
2100 }
2101
2102 return 0;
2103 }
2104
2105 static int arm11_mrc_inner(struct target *target, int cpnum,
2106 uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm,
2107 uint32_t *value, bool read)
2108 {
2109 int retval;
2110
2111 if (target->state != TARGET_HALTED)
2112 {
2113 LOG_ERROR("Target not halted");
2114 return ERROR_FAIL;
2115 }
2116
2117 struct arm11_common * arm11 = target->arch_info;
2118
2119 uint32_t instr = 0xEE000010 |
2120 (cpnum << 8) |
2121 (op1 << 21) |
2122 (CRn << 16) |
2123 (CRm << 0) |
2124 (op2 << 5);
2125
2126 if (read)
2127 instr |= 0x00100000;
2128
2129 retval = arm11_run_instr_data_prepare(arm11);
2130 if (retval != ERROR_OK)
2131 return retval;
2132
2133 if (read)
2134 {
2135 retval = arm11_run_instr_data_from_core_via_r0(arm11, instr, value);
2136 if (retval != ERROR_OK)
2137 return retval;
2138 }
2139 else
2140 {
2141 retval = arm11_run_instr_data_to_core_via_r0(arm11, instr, *value);
2142 if (retval != ERROR_OK)
2143 return retval;
2144 }
2145
2146 return arm11_run_instr_data_finish(arm11);
2147 }
2148
2149 static int arm11_mrc(struct target *target, int cpnum,
2150 uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t *value)
2151 {
2152 return arm11_mrc_inner(target, cpnum, op1, op2, CRn, CRm, value, true);
2153 }
2154
2155 static int arm11_mcr(struct target *target, int cpnum,
2156 uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t value)
2157 {
2158 return arm11_mrc_inner(target, cpnum, op1, op2, CRn, CRm, &value, false);
2159 }
2160
2161 static COMMAND_HELPER(arm11_handle_etm_read_write, bool read)
2162 {
2163 if (argc != (read ? 2 : 3))
2164 {
2165 LOG_ERROR("Invalid number of arguments.");
2166 return ERROR_COMMAND_SYNTAX_ERROR;
2167 }
2168
2169 struct arm11_common * arm11 = arm11_find_target(args[0]);
2170
2171 if (!arm11)
2172 {
2173 LOG_ERROR("Parameter 1 is not the target name of an ARM11 device.");
2174 return ERROR_COMMAND_SYNTAX_ERROR;
2175 }
2176
2177 uint32_t address;
2178 COMMAND_PARSE_NUMBER(u32, args[1], address);
2179
2180 if (!read)
2181 {
2182 uint32_t value;
2183 COMMAND_PARSE_NUMBER(u32, args[2], value);
2184
2185 LOG_INFO("ETM write register 0x%02" PRIx32 " (%" PRId32 ") = 0x%08" PRIx32 " (%" PRId32 ")",
2186 address, address, value, value);
2187
2188 CHECK_RETVAL(arm11_write_etm(arm11, address, value));
2189 }
2190 else
2191 {
2192 uint32_t value;
2193
2194 CHECK_RETVAL(arm11_read_etm(arm11, address, &value));
2195
2196 LOG_INFO("ETM read register 0x%02" PRIx32 " (%" PRId32 ") = 0x%08" PRIx32 " (%" PRId32 ")",
2197 address, address, value, value);
2198 }
2199
2200 return ERROR_OK;
2201 }
2202
2203 COMMAND_HANDLER(arm11_handle_etmr)
2204 {
2205 return CALL_COMMAND_HANDLER(arm11_handle_etm_read_write, true);
2206 }
2207
2208 COMMAND_HANDLER(arm11_handle_etmw)
2209 {
2210 return CALL_COMMAND_HANDLER(arm11_handle_etm_read_write, false);
2211 }
2212
2213 #define ARM11_HANDLER(x) .x = arm11_##x
2214
2215 struct target_type arm11_target = {
2216 .name = "arm11",
2217
2218 ARM11_HANDLER(poll),
2219 ARM11_HANDLER(arch_state),
2220
2221 ARM11_HANDLER(target_request_data),
2222
2223 ARM11_HANDLER(halt),
2224 ARM11_HANDLER(resume),
2225 ARM11_HANDLER(step),
2226
2227 ARM11_HANDLER(assert_reset),
2228 ARM11_HANDLER(deassert_reset),
2229 ARM11_HANDLER(soft_reset_halt),
2230
2231 ARM11_HANDLER(get_gdb_reg_list),
2232
2233 ARM11_HANDLER(read_memory),
2234 ARM11_HANDLER(write_memory),
2235
2236 ARM11_HANDLER(bulk_write_memory),
2237
2238 ARM11_HANDLER(checksum_memory),
2239
2240 ARM11_HANDLER(add_breakpoint),
2241 ARM11_HANDLER(remove_breakpoint),
2242 ARM11_HANDLER(add_watchpoint),
2243 ARM11_HANDLER(remove_watchpoint),
2244
2245 ARM11_HANDLER(run_algorithm),
2246
2247 ARM11_HANDLER(register_commands),
2248 ARM11_HANDLER(target_create),
2249 ARM11_HANDLER(init_target),
2250 ARM11_HANDLER(examine),
2251
2252 ARM11_HANDLER(mrc),
2253 ARM11_HANDLER(mcr),
2254 };
2255
2256
2257 int arm11_register_commands(struct command_context *cmd_ctx)
2258 {
2259 FNC_INFO;
2260
2261 struct command *top_cmd, *mw_cmd;
2262
2263 top_cmd = register_command(cmd_ctx, NULL, "arm11",
2264 NULL, COMMAND_ANY, NULL);
2265
2266 register_command(cmd_ctx, top_cmd, "etmr",
2267 arm11_handle_etmr, COMMAND_ANY,
2268 "Read Embedded Trace Macrocell (ETM) register. etmr <jtag_target> <ETM register address>");
2269
2270 register_command(cmd_ctx, top_cmd, "etmw",
2271 arm11_handle_etmw, COMMAND_ANY,
2272 "Write Embedded Trace Macrocell (ETM) register. etmr <jtag_target> <ETM register address> <value>");
2273
2274 /* "hardware_step" is only here to check if the default
2275 * simulate + breakpoint implementation is broken.
2276 * TEMPORARY! NOT DOCUMENTED!
2277 */
2278 register_command(cmd_ctx, top_cmd, "hardware_step",
2279 arm11_handle_bool_hardware_step, COMMAND_ANY,
2280 "DEBUG ONLY - Hardware single stepping"
2281 " (default: disabled)");
2282
2283 mw_cmd = register_command(cmd_ctx, top_cmd, "memwrite",
2284 NULL, COMMAND_ANY, NULL);
2285 register_command(cmd_ctx, mw_cmd, "burst",
2286 arm11_handle_bool_memwrite_burst, COMMAND_ANY,
2287 "Enable/Disable non-standard but fast burst mode"
2288 " (default: enabled)");
2289 register_command(cmd_ctx, mw_cmd, "error_fatal",
2290 arm11_handle_bool_memwrite_error_fatal, COMMAND_ANY,
2291 "Terminate program if transfer error was found"
2292 " (default: enabled)");
2293
2294 register_command(cmd_ctx, top_cmd, "step_irq_enable",
2295 arm11_handle_bool_step_irq_enable, COMMAND_ANY,
2296 "Enable interrupts while stepping"
2297 " (default: disabled)");
2298 register_command(cmd_ctx, top_cmd, "vcr",
2299 arm11_handle_vcr, COMMAND_ANY,
2300 "Control (Interrupt) Vector Catch Register");
2301
2302 return ERROR_OK;
2303 }