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Do a major clean-up of the BUSDMA architecture. A large number of
[dfdiff.git] / sys / net / i4b / layer1 / ifpi / i4b_ifpi_pci.c
blob257b6aad5d4650b66f113e9e989f78a8c0d5f84b
1 /*
2 * Copyright (c) 1999, 2000 Gary Jennejohn. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
6 * are met:
7 *
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. Neither the name of the author nor the names of any co-contributors
14 * may be used to endorse or promote products derived from this software
15 * without specific prior written permission.
16 * 4. Altered versions must be plainly marked as such, and must not be
17 * misrepresented as being the original software and/or documentation.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 * SUCH DAMAGE.
30 *
31 *---------------------------------------------------------------------------
32 *
33 * i4b_ifpi_pci.c: AVM Fritz!Card PCI hardware driver
34 * --------------------------------------------------
35 *
36 * $Id: i4b_ifpi_pci.c,v 1.4 2000/06/02 11:58:56 hm Exp $
37 *
38 * $FreeBSD: src/sys/i4b/layer1/ifpi/i4b_ifpi_pci.c,v 1.6.2.1 2001/08/10 14:08:37 obrien Exp $
39 * $DragonFly: src/sys/net/i4b/layer1/ifpi/i4b_ifpi_pci.c,v 1.14 2006/10/25 20:56:03 dillon Exp $
40 *
41 * last edit-date: [Fri Jan 12 17:01:26 2001]
42 *
43 *---------------------------------------------------------------------------*/
44
45 #include "use_ifpi.h"
46 #include "use_pci.h"
47 #include "opt_i4b.h"
48
49 #if (NIFPI > 0) && (NPCI > 0)
50
51 #include <sys/param.h>
52 #include <sys/kernel.h>
53 #include <sys/systm.h>
54 #include <sys/mbuf.h>
55 #include <sys/bus.h>
56 #include <sys/rman.h>
57 #include <sys/socket.h>
58 #include <sys/thread2.h>
59
60 #include <bus/pci/pcireg.h>
61 #include <bus/pci/pcivar.h>
62
63 #include <net/if.h>
64 #include <net/i4b/include/machine/i4b_debug.h>
65 #include <net/i4b/include/machine/i4b_ioctl.h>
66 #include <net/i4b/include/machine/i4b_trace.h>
67
68 #include "../../include/i4b_global.h"
69 #include "../../include/i4b_mbuf.h"
70
71 #include "../i4b_l1.h"
72 #include "../isic/i4b_isic.h"
73 #include "../isic/i4b_isac.h"
74 #include "../isic/i4b_hscx.h"
75
76 #include "i4b_ifpi_ext.h"
77
78 #define PCI_AVMA1_VID 0x1244
79 #define PCI_AVMA1_DID 0x0a00
80
81 /* prototypes */
82 static void avma1pp_disable(device_t);
83
84 static void avma1pp_intr(void *);
85 static void hscx_write_reg(int, u_int, u_int, struct l1_softc *);
86 static u_char hscx_read_reg(int, u_int, struct l1_softc *);
87 static u_int hscx_read_reg_int(int, u_int, struct l1_softc *);
88 static void hscx_read_fifo(int, void *, size_t, struct l1_softc *);
89 static void hscx_write_fifo(int, void *, size_t, struct l1_softc *);
90 static void avma1pp_hscx_int_handler(struct l1_softc *);
91 static void avma1pp_hscx_intr(int, u_int, struct l1_softc *);
92 static void avma1pp_init_linktab(struct l1_softc *);
93 static void avma1pp_bchannel_setup(int, int, int, int);
94 static void avma1pp_bchannel_start(int, int);
95 static void avma1pp_hscx_init(struct l1_softc *, int, int);
96 static void avma1pp_bchannel_stat(int, int, bchan_statistics_t *);
97 static void avma1pp_set_linktab(int, int, drvr_link_t *);
98 static isdn_link_t * avma1pp_ret_linktab(int, int);
99 static int avma1pp_pci_probe(device_t);
100 static int avma1pp_hscx_fifo(l1_bchan_state_t *, struct l1_softc *);
101 int avma1pp_attach_avma1pp(device_t);
102 static void ifpi_isac_intr(struct l1_softc *sc);
103
104 static device_method_t avma1pp_pci_methods[] = {
105 /* Device interface */
106 DEVMETHOD(device_probe, avma1pp_pci_probe),
107 DEVMETHOD(device_attach, avma1pp_attach_avma1pp),
108 DEVMETHOD(device_shutdown, avma1pp_disable),
109
110 /* bus interface */
111 DEVMETHOD(bus_print_child, bus_generic_print_child),
112 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
113
114 { 0, 0 }
115 };
116
117 #if 0 /* use what's in l1_softc */
118 /* a minimal softc for the Fritz!Card PCI */
119 struct avma1pp_softc
120 {
121 bus_space_handle_t avma1pp_bhandle;
122 bus_space_tag_t avma1pp_btag;
123 void *avma1pp_intrhand;
124 struct resource *avma1pp_irq;
125 struct resource *avma1pp_res;
126 /* pointer to ifpi_sc */
127 struct l1_softc *avma1pp_isc;
128 };
129 #endif
130
131 static driver_t avma1pp_pci_driver = {
132 "ifpi",
133 avma1pp_pci_methods,
134 sizeof(struct l1_softc)
135 };
136
137 static devclass_t avma1pp_pci_devclass;
138
139 DRIVER_MODULE(avma1pp, pci, avma1pp_pci_driver, avma1pp_pci_devclass, 0, 0);
140
141 /* jump table for multiplex routines */
142
143 struct i4b_l1mux_func avma1pp_l1mux_func = {
144 avma1pp_ret_linktab,
145 avma1pp_set_linktab,
146 ifpi_mph_command_req,
147 ifpi_ph_data_req,
148 ifpi_ph_activate_req,
149 };
150
151 struct l1_softc *ifpi_scp[IFPI_MAXUNIT];
152
153 /*---------------------------------------------------------------------------*
154 * AVM PCI Fritz!Card special registers
155 *---------------------------------------------------------------------------*/
156
157 /*
158 * register offsets from i/o base
159 */
160 #define STAT0_OFFSET 0x02
161 #define STAT1_OFFSET 0x03
162 #define ADDR_REG_OFFSET 0x04
163 /*#define MODREG_OFFSET 0x06
164 #define VERREG_OFFSET 0x07*/
165
166 /* these 2 are used to select an ISAC register set */
167 #define ISAC_LO_REG_OFFSET 0x04
168 #define ISAC_HI_REG_OFFSET 0x06
169
170 /* offset higher than this goes to the HI register set */
171 #define MAX_LO_REG_OFFSET 0x2f
172
173 /* mask for the offset */
174 #define ISAC_REGSET_MASK 0x0f
175
176 /* the offset from the base to the ISAC registers */
177 #define ISAC_REG_OFFSET 0x10
178
179 /* the offset from the base to the ISAC FIFO */
180 #define ISAC_FIFO 0x02
181
182 /* not really the HSCX, but sort of */
183 #define HSCX_FIFO 0x00
184 #define HSCX_STAT 0x04
185
186 /*
187 * AVM PCI Status Latch 0 read only bits
188 */
189 #define ASL_IRQ_ISAC 0x01 /* ISAC interrupt, active low */
190 #define ASL_IRQ_HSCX 0x02 /* HSX interrupt, active low */
191 #define ASL_IRQ_TIMER 0x04 /* Timer interrupt, active low */
192 #define ASL_IRQ_BCHAN ASL_IRQ_HSCX
193 /* actually active LOW */
194 #define ASL_IRQ_Pending (ASL_IRQ_ISAC | ASL_IRQ_HSCX | ASL_IRQ_TIMER)
195
196 /*
197 * AVM Status Latch 0 write only bits
198 */
199 #define ASL_RESET_ALL 0x01 /* reset siemens IC's, active 1 */
200 #define ASL_TIMERDISABLE 0x02 /* active high */
201 #define ASL_TIMERRESET 0x04 /* active high */
202 #define ASL_ENABLE_INT 0x08 /* active high */
203 #define ASL_TESTBIT 0x10 /* active high */
204
205 /*
206 * AVM Status Latch 1 write only bits
207 */
208 #define ASL1_INTSEL 0x0f /* active high */
209 #define ASL1_ENABLE_IOM 0x80 /* active high */
210
211 /*
212 * "HSCX" mode bits
213 */
214 #define HSCX_MODE_ITF_FLG 0x01
215 #define HSCX_MODE_TRANS 0x02
216 #define HSCX_MODE_CCR_7 0x04
217 #define HSCX_MODE_CCR_16 0x08
218 #define HSCX_MODE_TESTLOOP 0x80
219
220 /*
221 * "HSCX" status bits
222 */
223 #define HSCX_STAT_RME 0x01
224 #define HSCX_STAT_RDO 0x10
225 #define HSCX_STAT_CRCVFRRAB 0x0E
226 #define HSCX_STAT_CRCVFR 0x06
227 #define HSCX_STAT_RML_MASK 0x3f00
228
229 /*
230 * "HSCX" interrupt bits
231 */
232 #define HSCX_INT_XPR 0x80
233 #define HSCX_INT_XDU 0x40
234 #define HSCX_INT_RPR 0x20
235 #define HSCX_INT_MASK 0xE0
236
237 /*
238 * "HSCX" command bits
239 */
240 #define HSCX_CMD_XRS 0x80
241 #define HSCX_CMD_XME 0x01
242 #define HSCX_CMD_RRS 0x20
243 #define HSCX_CMD_XML_MASK 0x3f00
244
245 /*
246 * Commands and parameters are sent to the "HSCX" as a long, but the
247 * fields are handled as bytes.
248 *
249 * The long contains:
250 * (prot << 16)|(txl << 8)|cmd
251 *
252 * where:
253 * prot = protocol to use
254 * txl = transmit length
255 * cmd = the command to be executed
256 *
257 * The fields are defined as u_char in struct l1_softc.
258 *
259 * Macro to coalesce the byte fields into a u_int
260 */
261 #define AVMA1PPSETCMDLONG(f) (f) = ((sc->avma1pp_cmd) | (sc->avma1pp_txl << 8) \
262 | (sc->avma1pp_prot << 16))
263
264 /*
265 * to prevent deactivating the "HSCX" when both channels are active we
266 * define an HSCX_ACTIVE flag which is or'd into the channel's state
267 * flag in avma1pp_bchannel_setup upon active and cleared upon deactivation.
268 * It is set high to allow room for new flags.
269 */
270 #define HSCX_AVMA1PP_ACTIVE 0x1000
271
272 /*---------------------------------------------------------------------------*
273 * AVM read fifo routines
274 *---------------------------------------------------------------------------*/
275
276 static void
277 avma1pp_read_fifo(struct l1_softc *sc, int what, void *buf, size_t size)
278 {
279 bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
280 bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
281
282 switch (what) {
283 case ISIC_WHAT_ISAC:
284 bus_space_write_1(btag, bhandle, ADDR_REG_OFFSET, ISAC_FIFO);
285 bus_space_read_multi_1(btag, bhandle, ISAC_REG_OFFSET, buf, size);
286 break;
287 case ISIC_WHAT_HSCXA:
288 hscx_read_fifo(0, buf, size, sc);
289 break;
290 case ISIC_WHAT_HSCXB:
291 hscx_read_fifo(1, buf, size, sc);
292 break;
293 }
294 }
295
296 static void
297 hscx_read_fifo(int chan, void *buf, size_t len, struct l1_softc *sc)
298 {
299 u_int32_t *ip;
300 size_t cnt;
301 bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
302 bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
303
304 bus_space_write_4(btag, bhandle, ADDR_REG_OFFSET, chan);
305 ip = (u_int32_t *)buf;
306 cnt = 0;
307 /* what if len isn't a multiple of sizeof(int) and buf is */
308 /* too small ???? */
309 while (cnt < len)
310 {
311 *ip++ = bus_space_read_4(btag, bhandle, ISAC_REG_OFFSET);
312 cnt += 4;
313 }
314 }
315
316 /*---------------------------------------------------------------------------*
317 * AVM write fifo routines
318 *---------------------------------------------------------------------------*/
319 static void
320 avma1pp_write_fifo(struct l1_softc *sc, int what, void *buf, size_t size)
321 {
322 bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
323 bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
324
325 switch (what) {
326 case ISIC_WHAT_ISAC:
327 bus_space_write_1(btag, bhandle, ADDR_REG_OFFSET, ISAC_FIFO);
328 bus_space_write_multi_1(btag, bhandle, ISAC_REG_OFFSET, (u_int8_t*)buf, size);
329 break;
330 case ISIC_WHAT_HSCXA:
331 hscx_write_fifo(0, buf, size, sc);
332 break;
333 case ISIC_WHAT_HSCXB:
334 hscx_write_fifo(1, buf, size, sc);
335 break;
336 }
337 }
338
339 static void
340 hscx_write_fifo(int chan, void *buf, size_t len, struct l1_softc *sc)
341 {
342 u_int32_t *ip;
343 size_t cnt;
344 l1_bchan_state_t *Bchan = &sc->sc_chan[chan];
345 bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
346 bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
347
348
349 sc->avma1pp_cmd &= ~HSCX_CMD_XME;
350 sc->avma1pp_txl = 0;
351 if (Bchan->out_mbuf_cur == NULL)
352 {
353 if (Bchan->bprot != BPROT_NONE)
354 sc->avma1pp_cmd |= HSCX_CMD_XME;
355 }
356 if (len != sc->sc_bfifolen)
357 sc->avma1pp_txl = len;
358
359 cnt = 0; /* borrow cnt */
360 AVMA1PPSETCMDLONG(cnt);
361 hscx_write_reg(chan, HSCX_STAT, cnt, sc);
362
363 ip = (u_int32_t *)buf;
364 cnt = 0;
365 while (cnt < len)
366 {
367 bus_space_write_4(btag, bhandle, ISAC_REG_OFFSET, *ip);
368 ip++;
369 cnt += 4;
370 }
371 }
372
373 /*---------------------------------------------------------------------------*
374 * AVM write register routines
375 *---------------------------------------------------------------------------*/
376
377 static void
378 avma1pp_write_reg(struct l1_softc *sc, int what, bus_size_t offs, u_int8_t data)
379 {
380 u_char reg_bank;
381 bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
382 bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
383
384 switch (what) {
385 case ISIC_WHAT_ISAC:
386 reg_bank = (offs > MAX_LO_REG_OFFSET) ? ISAC_HI_REG_OFFSET:ISAC_LO_REG_OFFSET;
387 #ifdef AVMA1PCI_DEBUG
388 printf("write_reg bank %d off %ld.. ", (int)reg_bank, (long)offs);
389 #endif
390 /* set the register bank */
391 bus_space_write_1(btag, bhandle, ADDR_REG_OFFSET, reg_bank);
392 bus_space_write_1(btag, bhandle, ISAC_REG_OFFSET + (offs & ISAC_REGSET_MASK), data);
393 break;
394 case ISIC_WHAT_HSCXA:
395 hscx_write_reg(0, offs, data, sc);
396 break;
397 case ISIC_WHAT_HSCXB:
398 hscx_write_reg(1, offs, data, sc);
399 break;
400 }
401 }
402
403 static void
404 hscx_write_reg(int chan, u_int off, u_int val, struct l1_softc *sc)
405 {
406 bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
407 bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
408
409 /* point at the correct channel */
410 bus_space_write_4(btag, bhandle, ADDR_REG_OFFSET, chan);
411 bus_space_write_4(btag, bhandle, ISAC_REG_OFFSET + off, val);
412 }
413
414 /*---------------------------------------------------------------------------*
415 * AVM read register routines
416 *---------------------------------------------------------------------------*/
417 static u_int8_t
418 avma1pp_read_reg(struct l1_softc *sc, int what, bus_size_t offs)
419 {
420 u_char reg_bank;
421 bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
422 bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
423
424 switch (what) {
425 case ISIC_WHAT_ISAC:
426 reg_bank = (offs > MAX_LO_REG_OFFSET) ? ISAC_HI_REG_OFFSET:ISAC_LO_REG_OFFSET;
427 #ifdef AVMA1PCI_DEBUG
428 printf("read_reg bank %d off %ld.. ", (int)reg_bank, (long)offs);
429 #endif
430 /* set the register bank */
431 bus_space_write_1(btag, bhandle, ADDR_REG_OFFSET, reg_bank);
432 return(bus_space_read_1(btag, bhandle, ISAC_REG_OFFSET +
433 (offs & ISAC_REGSET_MASK)));
434 case ISIC_WHAT_HSCXA:
435 return hscx_read_reg(0, offs, sc);
436 case ISIC_WHAT_HSCXB:
437 return hscx_read_reg(1, offs, sc);
438 }
439 return 0;
440 }
441
442 static u_char
443 hscx_read_reg(int chan, u_int off, struct l1_softc *sc)
444 {
445 return(hscx_read_reg_int(chan, off, sc) & 0xff);
446 }
447
448 /*
449 * need to be able to return an int because the RBCH is in the 2nd
450 * byte.
451 */
452 static u_int
453 hscx_read_reg_int(int chan, u_int off, struct l1_softc *sc)
454 {
455 bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
456 bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
457
458 /* point at the correct channel */
459 bus_space_write_4(btag, bhandle, ADDR_REG_OFFSET, chan);
460 return(bus_space_read_4(btag, bhandle, ISAC_REG_OFFSET + off));
461 }
462
463 /*---------------------------------------------------------------------------*
464 * avma1pp_probe - probe for a card
465 *---------------------------------------------------------------------------*/
466 static int
467 avma1pp_pci_probe(device_t dev)
468 {
469 u_int16_t did, vid;
470
471 vid = pci_get_vendor(dev);
472 did = pci_get_device(dev);
473
474 if ((vid == PCI_AVMA1_VID) && (did == PCI_AVMA1_DID)) {
475 device_set_desc(dev, "AVM Fritz!Card PCI");
476 return(0);
477 }
478
479 return(ENXIO);
480 }
481
482 /*---------------------------------------------------------------------------*
483 * avma1pp_attach_avma1pp - attach Fritz!Card PCI
484 *---------------------------------------------------------------------------*/
485 int
486 avma1pp_attach_avma1pp(device_t dev)
487 {
488 struct l1_softc *sc;
489 u_int v;
490 int unit, error = 0;
491 u_int16_t did, vid;
492 void *ih = 0;
493 bus_space_handle_t bhandle;
494 bus_space_tag_t btag;
495
496 crit_enter();
497
498 vid = pci_get_vendor(dev);
499 did = pci_get_device(dev);
500 sc = device_get_softc(dev);
501 unit = device_get_unit(dev);
502 bzero(sc, sizeof(struct l1_softc));
503
504 /* probably not really required */
505 if(unit > IFPI_MAXUNIT) {
506 printf("avma1pp%d: Error, unit > IFPI_MAXUNIT!\n", unit);
507 crit_exit();
508 return(ENXIO);
509 }
510
511 if ((vid != PCI_AVMA1_VID) && (did != PCI_AVMA1_DID)) {
512 printf("avma1pp%d: unknown device!?\n", unit);
513 goto fail;
514 }
515
516 ifpi_scp[unit] = sc;
517
518 sc->sc_resources.io_rid[0] = PCIR_MAPS+4;
519 sc->sc_resources.io_base[0] = bus_alloc_resource(dev, SYS_RES_IOPORT,
520 &sc->sc_resources.io_rid[0],
521 0, ~0, 1, RF_ACTIVE);
522
523 if (sc->sc_resources.io_base[0] == NULL) {
524 printf("avma1pp%d: couldn't map IO port\n", unit);
525 error = ENXIO;
526 goto fail;
527 }
528
529 bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
530 btag = rman_get_bustag(sc->sc_resources.io_base[0]);
531
532 /* Allocate interrupt */
533 sc->sc_resources.irq_rid = 0;
534 sc->sc_resources.irq = bus_alloc_resource(dev, SYS_RES_IRQ,
535 &sc->sc_resources.irq_rid, 0, ~0, 1, RF_SHAREABLE | RF_ACTIVE);
536
537 if (sc->sc_resources.irq == NULL) {
538 bus_release_resource(dev, SYS_RES_IOPORT, PCIR_MAPS+4, sc->sc_resources.io_base[0]);
539 printf("avma1pp%d: couldn't map interrupt\n", unit);
540 error = ENXIO;
541 goto fail;
542 }
543
544 error = bus_setup_intr(dev, sc->sc_resources.irq, 0,
545 avma1pp_intr, sc, &ih, NULL);
546
547 if (error) {
548 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_resources.irq);
549 bus_release_resource(dev, SYS_RES_IOPORT, PCIR_MAPS+4, sc->sc_resources.io_base[0]);
550 printf("avma1pp%d: couldn't set up irq\n", unit);
551 goto fail;
552 }
553
554 sc->sc_unit = unit;
555
556 /* end of new-bus stuff */
557
558 ISAC_BASE = (caddr_t)ISIC_WHAT_ISAC;
559
560 HSCX_A_BASE = (caddr_t)ISIC_WHAT_HSCXA;
561 HSCX_B_BASE = (caddr_t)ISIC_WHAT_HSCXB;
562
563 /* setup access routines */
564
565 sc->clearirq = NULL;
566 sc->readreg = avma1pp_read_reg;
567 sc->writereg = avma1pp_write_reg;
568
569 sc->readfifo = avma1pp_read_fifo;
570 sc->writefifo = avma1pp_write_fifo;
571
572 /* setup card type */
573
574 sc->sc_cardtyp = CARD_TYPEP_AVMA1PCI;
575
576 /* setup IOM bus type */
577
578 sc->sc_bustyp = BUS_TYPE_IOM2;
579
580 /* set up some other miscellaneous things */
581 sc->sc_ipac = 0;
582 sc->sc_bfifolen = HSCX_FIFO_LEN;
583
584 /* reset the card */
585 /* the Linux driver does this to clear any pending ISAC interrupts */
586 v = 0;
587 v = ISAC_READ(I_STAR);
588 #ifdef AVMA1PCI_DEBUG
589 printf("avma1pp_attach: I_STAR %x...", v);
590 #endif
591 v = ISAC_READ(I_MODE);
592 #ifdef AVMA1PCI_DEBUG
593 printf("avma1pp_attach: I_MODE %x...", v);
594 #endif
595 v = ISAC_READ(I_ADF2);
596 #ifdef AVMA1PCI_DEBUG
597 printf("avma1pp_attach: I_ADF2 %x...", v);
598 #endif
599 v = ISAC_READ(I_ISTA);
600 #ifdef AVMA1PCI_DEBUG
601 printf("avma1pp_attach: I_ISTA %x...", v);
602 #endif
603 if (v & ISAC_ISTA_EXI)
604 {
605 v = ISAC_READ(I_EXIR);
606 #ifdef AVMA1PCI_DEBUG
607 printf("avma1pp_attach: I_EXIR %x...", v);
608 #endif
609 }
610 v = ISAC_READ(I_CIRR);
611 #ifdef AVMA1PCI_DEBUG
612 printf("avma1pp_attach: I_CIRR %x...", v);
613 #endif
614 ISAC_WRITE(I_MASK, 0xff);
615 /* the Linux driver does this to clear any pending HSCX interrupts */
616 v = hscx_read_reg_int(0, HSCX_STAT, sc);
617 #ifdef AVMA1PCI_DEBUG
618 printf("avma1pp_attach: 0 HSCX_STAT %x...", v);
619 #endif
620 v = hscx_read_reg_int(1, HSCX_STAT, sc);
621 #ifdef AVMA1PCI_DEBUG
622 printf("avma1pp_attach: 1 HSCX_STAT %x\n", v);
623 #endif
624
625 bus_space_write_1(btag, bhandle, STAT0_OFFSET, ASL_RESET_ALL|ASL_TIMERDISABLE);
626 DELAY(SEC_DELAY/100); /* 10 ms */
627 bus_space_write_1(btag, bhandle, STAT0_OFFSET, ASL_TIMERRESET|ASL_ENABLE_INT|ASL_TIMERDISABLE);
628 DELAY(SEC_DELAY/100); /* 10 ms */
629 #ifdef AVMA1PCI_DEBUG
630 bus_space_write_1(btag, bhandle, STAT1_OFFSET, ASL1_ENABLE_IOM|sc->sc_irq);
631 DELAY(SEC_DELAY/100); /* 10 ms */
632 v = bus_space_read_1(btag, bhandle, STAT1_OFFSET);
633 printf("after reset: S1 %#x\n", v);
634
635 v = bus_space_read_4(btag, bhandle, 0);
636 printf("avma1pp_attach_avma1pp: v %#x\n", v);
637 #endif
638
639 /* from here to the end would normally be done in isic_pciattach */
640
641 printf("ifpi%d: ISAC %s (IOM-%c)\n", unit,
642 "2085 Version A1/A2 or 2086/2186 Version 1.1",
643 sc->sc_bustyp == BUS_TYPE_IOM1 ? '1' : '2');
644
645 /* init the ISAC */
646 ifpi_isac_init(sc);
647
648 /* init the "HSCX" */
649 avma1pp_bchannel_setup(sc->sc_unit, HSCX_CH_A, BPROT_NONE, 0);
650
651 avma1pp_bchannel_setup(sc->sc_unit, HSCX_CH_B, BPROT_NONE, 0);
652
653 /* can't use the normal B-Channel stuff */
654 avma1pp_init_linktab(sc);
655
656 /* set trace level */
657
658 sc->sc_trace = TRACE_OFF;
659
660 sc->sc_state = ISAC_IDLE;
661
662 sc->sc_ibuf = NULL;
663 sc->sc_ib = NULL;
664 sc->sc_ilen = 0;
665
666 sc->sc_obuf = NULL;
667 sc->sc_op = NULL;
668 sc->sc_ol = 0;
669 sc->sc_freeflag = 0;
670
671 sc->sc_obuf2 = NULL;
672 sc->sc_freeflag2 = 0;
673
674 callout_init(&sc->sc_T3_timeout);
675 callout_init(&sc->sc_T4_timeout);
676
677 /* init higher protocol layers */
678
679 i4b_l1_mph_status_ind(L0IFPIUNIT(sc->sc_unit), STI_ATTACH, sc->sc_cardtyp, &avma1pp_l1mux_func);
680
681 fail:
682 crit_exit();
683 return(error);
684 }
685
686 /*
687 * this is the real interrupt routine
688 */
689 static void
690 avma1pp_hscx_intr(int h_chan, u_int stat, struct l1_softc *sc)
691 {
692 l1_bchan_state_t *chan = &sc->sc_chan[h_chan];
693 int activity = -1;
694 u_int param = 0;
695
696 NDBGL1(L1_H_IRQ, "%#x", stat);
697
698 if((stat & HSCX_INT_XDU) && (chan->bprot != BPROT_NONE))/* xmit data underrun */
699 {
700 chan->stat_XDU++;
701 NDBGL1(L1_H_XFRERR, "xmit data underrun");
702 /* abort the transmission */
703 sc->avma1pp_txl = 0;
704 sc->avma1pp_cmd |= HSCX_CMD_XRS;
705 AVMA1PPSETCMDLONG(param);
706 hscx_write_reg(h_chan, HSCX_STAT, param, sc);
707 sc->avma1pp_cmd &= ~HSCX_CMD_XRS;
708 AVMA1PPSETCMDLONG(param);
709 hscx_write_reg(h_chan, HSCX_STAT, param, sc);
710
711 if (chan->out_mbuf_head != NULL) /* don't continue to transmit this buffer */
712 {
713 i4b_Bfreembuf(chan->out_mbuf_head);
714 chan->out_mbuf_cur = chan->out_mbuf_head = NULL;
715 }
716 }
717
718 /*
719 * The following is based on examination of the Linux driver.
720 *
721 * The logic here is different than with a "real" HSCX; all kinds
722 * of information (interrupt/status bits) are in stat.
723 * HSCX_INT_RPR indicates a receive interrupt
724 * HSCX_STAT_RDO indicates an overrun condition, abort -
725 * otherwise read the bytes ((stat & HSCX_STZT_RML_MASK) >> 8)
726 * HSCX_STAT_RME indicates end-of-frame and apparently any
727 * CRC/framing errors are only reported in this state.
728 * if ((stat & HSCX_STAT_CRCVFRRAB) != HSCX_STAT_CRCVFR)
729 * CRC/framing error
730 */
731
732 if(stat & HSCX_INT_RPR)
733 {
734 int fifo_data_len;
735 int error = 0;
736 /* always have to read the FIFO, so use a scratch buffer */
737 u_char scrbuf[HSCX_FIFO_LEN];
738
739 if(stat & HSCX_STAT_RDO)
740 {
741 chan->stat_RDO++;
742 NDBGL1(L1_H_XFRERR, "receive data overflow");
743 error++;
744 }
745
746 /*
747 * check whether we're receiving data for an inactive B-channel
748 * and discard it. This appears to happen for telephony when
749 * both B-channels are active and one is deactivated. Since
750 * it is not really possible to deactivate the channel in that
751 * case (the ASIC seems to deactivate _both_ channels), the
752 * "deactivated" channel keeps receiving data which can lead
753 * to exhaustion of mbufs and a kernel panic.
754 *
755 * This is a hack, but it's the only solution I can think of
756 * without having the documentation for the ASIC.
757 * GJ - 28 Nov 1999
758 */
759 if (chan->state == HSCX_IDLE)
760 {
761 NDBGL1(L1_H_XFRERR, "toss data from %d", h_chan);
762 error++;
763 }
764
765 fifo_data_len = ((stat & HSCX_STAT_RML_MASK) >> 8);
766
767 if(fifo_data_len == 0)
768 fifo_data_len = sc->sc_bfifolen;
769
770 /* ALWAYS read data from HSCX fifo */
771
772 HSCX_RDFIFO(h_chan, scrbuf, fifo_data_len);
773 chan->rxcount += fifo_data_len;
774
775 /* all error conditions checked, now decide and take action */
776
777 if(error == 0)
778 {
779 if(chan->in_mbuf == NULL)
780 {
781 if((chan->in_mbuf = i4b_Bgetmbuf(BCH_MAX_DATALEN)) == NULL)
782 panic("L1 avma1pp_hscx_intr: RME, cannot allocate mbuf!\n");
783 chan->in_cbptr = chan->in_mbuf->m_data;
784 chan->in_len = 0;
785 }
786
787 if((chan->in_len + fifo_data_len) <= BCH_MAX_DATALEN)
788 {
789 /* OK to copy the data */
790 bcopy(scrbuf, chan->in_cbptr, fifo_data_len);
791 chan->in_cbptr += fifo_data_len;
792 chan->in_len += fifo_data_len;
793
794 /* setup mbuf data length */
795
796 chan->in_mbuf->m_len = chan->in_len;
797 chan->in_mbuf->m_pkthdr.len = chan->in_len;
798
799 if(sc->sc_trace & TRACE_B_RX)
800 {
801 i4b_trace_hdr_t hdr;
802 hdr.unit = L0IFPIUNIT(sc->sc_unit);
803 hdr.type = (h_chan == HSCX_CH_A ? TRC_CH_B1 : TRC_CH_B2);
804 hdr.dir = FROM_NT;
805 hdr.count = ++sc->sc_trace_bcount;
806 MICROTIME(hdr.time);
807 i4b_l1_trace_ind(&hdr, chan->in_mbuf->m_len, chan->in_mbuf->m_data);
808 }
809
810 if (stat & HSCX_STAT_RME)
811 {
812 if((stat & HSCX_STAT_CRCVFRRAB) == HSCX_STAT_CRCVFR)
813 {
814 (*chan->isic_drvr_linktab->bch_rx_data_ready)(chan->isic_drvr_linktab->unit);
815 activity = ACT_RX;
816
817 /* mark buffer ptr as unused */
818
819 chan->in_mbuf = NULL;
820 chan->in_cbptr = NULL;
821 chan->in_len = 0;
822 }
823 else
824 {
825 chan->stat_CRC++;
826 NDBGL1(L1_H_XFRERR, "CRC/RAB");
827 if (chan->in_mbuf != NULL)
828 {
829 i4b_Bfreembuf(chan->in_mbuf);
830 chan->in_mbuf = NULL;
831 chan->in_cbptr = NULL;
832 chan->in_len = 0;
833 }
834 }
835 }
836 } /* END enough space in mbuf */
837 else
838 {
839 if(chan->bprot == BPROT_NONE)
840 {
841 /* setup mbuf data length */
842
843 chan->in_mbuf->m_len = chan->in_len;
844 chan->in_mbuf->m_pkthdr.len = chan->in_len;
845
846 if(sc->sc_trace & TRACE_B_RX)
847 {
848 i4b_trace_hdr_t hdr;
849 hdr.unit = L0IFPIUNIT(sc->sc_unit);
850 hdr.type = (h_chan == HSCX_CH_A ? TRC_CH_B1 : TRC_CH_B2);
851 hdr.dir = FROM_NT;
852 hdr.count = ++sc->sc_trace_bcount;
853 MICROTIME(hdr.time);
854 i4b_l1_trace_ind(&hdr, chan->in_mbuf->m_len, chan->in_mbuf->m_data);
855 }
856
857 if(!(i4b_l1_bchan_tel_silence(chan->in_mbuf->m_data, chan->in_mbuf->m_len)))
858 activity = ACT_RX;
859
860 /* move rx'd data to rx queue */
861
862 if(!(IF_QFULL(&chan->rx_queue)))
863 {
864 IF_ENQUEUE(&chan->rx_queue, chan->in_mbuf);
865 }
866 else
867 {
868 i4b_Bfreembuf(chan->in_mbuf);
869 }
870 /* signal upper layer that data are available */
871 (*chan->isic_drvr_linktab->bch_rx_data_ready)(chan->isic_drvr_linktab->unit);
872
873 /* alloc new buffer */
874
875 if((chan->in_mbuf = i4b_Bgetmbuf(BCH_MAX_DATALEN)) == NULL)
876 panic("L1 avma1pp_hscx_intr: RPF, cannot allocate new mbuf!\n");
877
878 /* setup new data ptr */
879
880 chan->in_cbptr = chan->in_mbuf->m_data;
881
882 /* OK to copy the data */
883 bcopy(scrbuf, chan->in_cbptr, fifo_data_len);
884
885 chan->in_cbptr += fifo_data_len;
886 chan->in_len = fifo_data_len;
887
888 chan->rxcount += fifo_data_len;
889 }
890 else
891 {
892 NDBGL1(L1_H_XFRERR, "RAWHDLC rx buffer overflow in RPF, in_len=%d", chan->in_len);
893 chan->in_cbptr = chan->in_mbuf->m_data;
894 chan->in_len = 0;
895 }
896 }
897 } /* if(error == 0) */
898 else
899 {
900 /* land here for RDO */
901 if (chan->in_mbuf != NULL)
902 {
903 i4b_Bfreembuf(chan->in_mbuf);
904 chan->in_mbuf = NULL;
905 chan->in_cbptr = NULL;
906 chan->in_len = 0;
907 }
908 sc->avma1pp_txl = 0;
909 sc->avma1pp_cmd |= HSCX_CMD_RRS;
910 AVMA1PPSETCMDLONG(param);
911 hscx_write_reg(h_chan, HSCX_STAT, param, sc);
912 sc->avma1pp_cmd &= ~HSCX_CMD_RRS;
913 AVMA1PPSETCMDLONG(param);
914 hscx_write_reg(h_chan, HSCX_STAT, param, sc);
915 }
916 }
917
918
919 /* transmit fifo empty, new data can be written to fifo */
920
921 if(stat & HSCX_INT_XPR)
922 {
923 /*
924 * for a description what is going on here, please have
925 * a look at isic_bchannel_start() in i4b_bchan.c !
926 */
927
928 NDBGL1(L1_H_IRQ, "unit %d, chan %d - XPR, Tx Fifo Empty!", sc->sc_unit, h_chan);
929
930 if(chan->out_mbuf_cur == NULL) /* last frame is transmitted */
931 {
932 IF_DEQUEUE(&chan->tx_queue, chan->out_mbuf_head);
933
934 if(chan->out_mbuf_head == NULL)
935 {
936 chan->state &= ~HSCX_TX_ACTIVE;
937 (*chan->isic_drvr_linktab->bch_tx_queue_empty)(chan->isic_drvr_linktab->unit);
938 }
939 else
940 {
941 chan->state |= HSCX_TX_ACTIVE;
942 chan->out_mbuf_cur = chan->out_mbuf_head;
943 chan->out_mbuf_cur_ptr = chan->out_mbuf_cur->m_data;
944 chan->out_mbuf_cur_len = chan->out_mbuf_cur->m_len;
945
946 if(sc->sc_trace & TRACE_B_TX)
947 {
948 i4b_trace_hdr_t hdr;
949 hdr.unit = L0IFPIUNIT(sc->sc_unit);
950 hdr.type = (h_chan == HSCX_CH_A ? TRC_CH_B1 : TRC_CH_B2);
951 hdr.dir = FROM_TE;
952 hdr.count = ++sc->sc_trace_bcount;
953 MICROTIME(hdr.time);
954 i4b_l1_trace_ind(&hdr, chan->out_mbuf_cur->m_len, chan->out_mbuf_cur->m_data);
955 }
956
957 if(chan->bprot == BPROT_NONE)
958 {
959 if(!(i4b_l1_bchan_tel_silence(chan->out_mbuf_cur->m_data, chan->out_mbuf_cur->m_len)))
960 activity = ACT_TX;
961 }
962 else
963 {
964 activity = ACT_TX;
965 }
966 }
967 }
968
969 avma1pp_hscx_fifo(chan, sc);
970 }
971
972 /* call timeout handling routine */
973
974 if(activity == ACT_RX || activity == ACT_TX)
975 (*chan->isic_drvr_linktab->bch_activity)(chan->isic_drvr_linktab->unit, activity);
976 }
977
978 /*
979 * this is the main routine which checks each channel and then calls
980 * the real interrupt routine as appropriate
981 */
982 static void
983 avma1pp_hscx_int_handler(struct l1_softc *sc)
984 {
985 u_int stat;
986
987 /* has to be a u_int because the byte count is in the 2nd byte */
988 stat = hscx_read_reg_int(0, HSCX_STAT, sc);
989 if (stat & HSCX_INT_MASK)
990 avma1pp_hscx_intr(0, stat, sc);
991 stat = hscx_read_reg_int(1, HSCX_STAT, sc);
992 if (stat & HSCX_INT_MASK)
993 avma1pp_hscx_intr(1, stat, sc);
994 }
995
996 static void
997 avma1pp_disable(device_t dev)
998 {
999 struct l1_softc *sc = device_get_softc(dev);
1000 bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
1001 bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
1002
1003 bus_space_write_1(btag, bhandle, STAT0_OFFSET, ASL_RESET_ALL|ASL_TIMERDISABLE);
1004 }
1005
1006 static void
1007 avma1pp_intr(void *xsc)
1008 {
1009 u_char stat;
1010 struct l1_softc *sc;
1011 bus_space_handle_t bhandle;
1012 bus_space_tag_t btag;
1013
1014 sc = xsc;
1015 bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
1016 btag = rman_get_bustag(sc->sc_resources.io_base[0]);
1017
1018 stat = bus_space_read_1(btag, bhandle, STAT0_OFFSET);
1019 NDBGL1(L1_H_IRQ, "stat %x", stat);
1020 /* was there an interrupt from this card ? */
1021 if ((stat & ASL_IRQ_Pending) == ASL_IRQ_Pending)
1022 return; /* no */
1023 /* interrupts are low active */
1024 if (!(stat & ASL_IRQ_TIMER))
1025 NDBGL1(L1_H_IRQ, "timer interrupt ???");
1026 if (!(stat & ASL_IRQ_HSCX))
1027 {
1028 NDBGL1(L1_H_IRQ, "HSCX");
1029 avma1pp_hscx_int_handler(sc);
1030 }
1031 if (!(stat & ASL_IRQ_ISAC))
1032 {
1033 NDBGL1(L1_H_IRQ, "ISAC");
1034 ifpi_isac_intr(sc);
1035 }
1036 }
1037
1038 static void
1039 avma1pp_hscx_init(struct l1_softc *sc, int h_chan, int activate)
1040 {
1041 l1_bchan_state_t *chan = &sc->sc_chan[h_chan];
1042 u_int param = 0;
1043
1044 NDBGL1(L1_BCHAN, "unit=%d, channel=%d, %s",
1045 sc->sc_unit, h_chan, activate ? "activate" : "deactivate");
1046
1047 if (activate == 0)
1048 {
1049 /* only deactivate if both channels are idle */
1050 if (sc->sc_chan[HSCX_CH_A].state != HSCX_IDLE ||
1051 sc->sc_chan[HSCX_CH_B].state != HSCX_IDLE)
1052 {
1053 return;
1054 }
1055 sc->avma1pp_cmd = HSCX_CMD_XRS|HSCX_CMD_RRS;
1056 sc->avma1pp_prot = HSCX_MODE_TRANS;
1057 AVMA1PPSETCMDLONG(param);
1058 hscx_write_reg(h_chan, HSCX_STAT, param, sc);
1059 return;
1060 }
1061 if(chan->bprot == BPROT_RHDLC)
1062 {
1063 NDBGL1(L1_BCHAN, "BPROT_RHDLC");
1064
1065 /* HDLC Frames, transparent mode 0 */
1066 sc->avma1pp_cmd = HSCX_CMD_XRS|HSCX_CMD_RRS;
1067 sc->avma1pp_prot = HSCX_MODE_ITF_FLG;
1068 AVMA1PPSETCMDLONG(param);
1069 hscx_write_reg(h_chan, HSCX_STAT, param, sc);
1070 sc->avma1pp_cmd = HSCX_CMD_XRS;
1071 AVMA1PPSETCMDLONG(param);
1072 hscx_write_reg(h_chan, HSCX_STAT, param, sc);
1073 sc->avma1pp_cmd = 0;
1074 }
1075 else
1076 {
1077 NDBGL1(L1_BCHAN, "BPROT_NONE??");
1078
1079 /* Raw Telephony, extended transparent mode 1 */
1080 sc->avma1pp_cmd = HSCX_CMD_XRS|HSCX_CMD_RRS;
1081 sc->avma1pp_prot = HSCX_MODE_TRANS;
1082 AVMA1PPSETCMDLONG(param);
1083 hscx_write_reg(h_chan, HSCX_STAT, param, sc);
1084 sc->avma1pp_cmd = HSCX_CMD_XRS;
1085 AVMA1PPSETCMDLONG(param);
1086 hscx_write_reg(h_chan, HSCX_STAT, param, sc);
1087 sc->avma1pp_cmd = 0;
1088 }
1089 }
1090
1091 static void
1092 avma1pp_bchannel_setup(int unit, int h_chan, int bprot, int activate)
1093 {
1094 struct l1_softc *sc = ifpi_scp[unit];
1095 l1_bchan_state_t *chan = &sc->sc_chan[h_chan];
1096
1097 crit_enter();
1098
1099 if(activate == 0)
1100 {
1101 /* deactivation */
1102 chan->state = HSCX_IDLE;
1103 avma1pp_hscx_init(sc, h_chan, activate);
1104 }
1105
1106 NDBGL1(L1_BCHAN, "unit=%d, channel=%d, %s",
1107 sc->sc_unit, h_chan, activate ? "activate" : "deactivate");
1108
1109 /* general part */
1110
1111 chan->unit = sc->sc_unit; /* unit number */
1112 chan->channel = h_chan; /* B channel */
1113 chan->bprot = bprot; /* B channel protocol */
1114 chan->state = HSCX_IDLE; /* B channel state */
1115
1116 /* receiver part */
1117
1118 chan->rx_queue.ifq_maxlen = IFQ_MAXLEN;
1119
1120 i4b_Bcleanifq(&chan->rx_queue); /* clean rx queue */
1121
1122 chan->rxcount = 0; /* reset rx counter */
1123
1124 i4b_Bfreembuf(chan->in_mbuf); /* clean rx mbuf */
1125
1126 chan->in_mbuf = NULL; /* reset mbuf ptr */
1127 chan->in_cbptr = NULL; /* reset mbuf curr ptr */
1128 chan->in_len = 0; /* reset mbuf data len */
1129
1130 /* transmitter part */
1131
1132 chan->tx_queue.ifq_maxlen = IFQ_MAXLEN;
1133
1134 i4b_Bcleanifq(&chan->tx_queue); /* clean tx queue */
1135
1136 chan->txcount = 0; /* reset tx counter */
1137
1138 i4b_Bfreembuf(chan->out_mbuf_head); /* clean tx mbuf */
1139
1140 chan->out_mbuf_head = NULL; /* reset head mbuf ptr */
1141 chan->out_mbuf_cur = NULL; /* reset current mbuf ptr */
1142 chan->out_mbuf_cur_ptr = NULL; /* reset current mbuf data ptr */
1143 chan->out_mbuf_cur_len = 0; /* reset current mbuf data cnt */
1144
1145 if(activate != 0)
1146 {
1147 /* activation */
1148 avma1pp_hscx_init(sc, h_chan, activate);
1149 chan->state |= HSCX_AVMA1PP_ACTIVE;
1150 }
1151
1152 crit_exit();
1153 }
1154
1155 static void
1156 avma1pp_bchannel_start(int unit, int h_chan)
1157 {
1158 struct l1_softc *sc = ifpi_scp[unit];
1159 l1_bchan_state_t *chan = &sc->sc_chan[h_chan];
1160 int activity = -1;
1161
1162 crit_enter();
1163 if(chan->state & HSCX_TX_ACTIVE) /* already running ? */
1164 {
1165 crit_exit();
1166 return; /* yes, leave */
1167 }
1168
1169 /* get next mbuf from queue */
1170
1171 IF_DEQUEUE(&chan->tx_queue, chan->out_mbuf_head);
1172
1173 if(chan->out_mbuf_head == NULL) /* queue empty ? */
1174 {
1175 crit_exit();
1176 return; /* yes, exit */
1177 }
1178
1179 /* init current mbuf values */
1180
1181 chan->out_mbuf_cur = chan->out_mbuf_head;
1182 chan->out_mbuf_cur_len = chan->out_mbuf_cur->m_len;
1183 chan->out_mbuf_cur_ptr = chan->out_mbuf_cur->m_data;
1184
1185 /* activity indicator for timeout handling */
1186
1187 if(chan->bprot == BPROT_NONE)
1188 {
1189 if(!(i4b_l1_bchan_tel_silence(chan->out_mbuf_cur->m_data, chan->out_mbuf_cur->m_len)))
1190 activity = ACT_TX;
1191 }
1192 else
1193 {
1194 activity = ACT_TX;
1195 }
1196
1197 chan->state |= HSCX_TX_ACTIVE; /* we start transmitting */
1198
1199 if(sc->sc_trace & TRACE_B_TX) /* if trace, send mbuf to trace dev */
1200 {
1201 i4b_trace_hdr_t hdr;
1202 hdr.unit = L0IFPIUNIT(sc->sc_unit);
1203 hdr.type = (h_chan == HSCX_CH_A ? TRC_CH_B1 : TRC_CH_B2);
1204 hdr.dir = FROM_TE;
1205 hdr.count = ++sc->sc_trace_bcount;
1206 MICROTIME(hdr.time);
1207 i4b_l1_trace_ind(&hdr, chan->out_mbuf_cur->m_len, chan->out_mbuf_cur->m_data);
1208 }
1209
1210 avma1pp_hscx_fifo(chan, sc);
1211
1212 /* call timeout handling routine */
1213
1214 if(activity == ACT_RX || activity == ACT_TX)
1215 (*chan->isic_drvr_linktab->bch_activity)(chan->isic_drvr_linktab->unit, activity);
1216
1217 crit_exit();
1218 }
1219
1220 /*---------------------------------------------------------------------------*
1221 * return the address of isic drivers linktab
1222 *---------------------------------------------------------------------------*/
1223 static isdn_link_t *
1224 avma1pp_ret_linktab(int unit, int channel)
1225 {
1226 struct l1_softc *sc = ifpi_scp[unit];
1227 l1_bchan_state_t *chan = &sc->sc_chan[channel];
1228
1229 return(&chan->isic_isdn_linktab);
1230 }
1231
1232 /*---------------------------------------------------------------------------*
1233 * set the driver linktab in the b channel softc
1234 *---------------------------------------------------------------------------*/
1235 static void
1236 avma1pp_set_linktab(int unit, int channel, drvr_link_t *dlt)
1237 {
1238 struct l1_softc *sc = ifpi_scp[unit];
1239 l1_bchan_state_t *chan = &sc->sc_chan[channel];
1240
1241 chan->isic_drvr_linktab = dlt;
1242 }
1243
1244
1245 /*---------------------------------------------------------------------------*
1246 * initialize our local linktab
1247 *---------------------------------------------------------------------------*/
1248 static void
1249 avma1pp_init_linktab(struct l1_softc *sc)
1250 {
1251 l1_bchan_state_t *chan = &sc->sc_chan[HSCX_CH_A];
1252 isdn_link_t *lt = &chan->isic_isdn_linktab;
1253
1254 /* make sure the hardware driver is known to layer 4 */
1255 /* avoid overwriting if already set */
1256 if (ctrl_types[CTRL_PASSIVE].set_linktab == NULL)
1257 {
1258 ctrl_types[CTRL_PASSIVE].set_linktab = avma1pp_set_linktab;
1259 ctrl_types[CTRL_PASSIVE].get_linktab = avma1pp_ret_linktab;
1260 }
1261
1262 /* local setup */
1263 lt->unit = sc->sc_unit;
1264 lt->channel = HSCX_CH_A;
1265 lt->bch_config = avma1pp_bchannel_setup;
1266 lt->bch_tx_start = avma1pp_bchannel_start;
1267 lt->bch_stat = avma1pp_bchannel_stat;
1268 lt->tx_queue = &chan->tx_queue;
1269
1270 /* used by non-HDLC data transfers, i.e. telephony drivers */
1271 lt->rx_queue = &chan->rx_queue;
1272
1273 /* used by HDLC data transfers, i.e. ipr and isp drivers */
1274 lt->rx_mbuf = &chan->in_mbuf;
1275
1276 chan = &sc->sc_chan[HSCX_CH_B];
1277 lt = &chan->isic_isdn_linktab;
1278
1279 lt->unit = sc->sc_unit;
1280 lt->channel = HSCX_CH_B;
1281 lt->bch_config = avma1pp_bchannel_setup;
1282 lt->bch_tx_start = avma1pp_bchannel_start;
1283 lt->bch_stat = avma1pp_bchannel_stat;
1284 lt->tx_queue = &chan->tx_queue;
1285
1286 /* used by non-HDLC data transfers, i.e. telephony drivers */
1287 lt->rx_queue = &chan->rx_queue;
1288
1289 /* used by HDLC data transfers, i.e. ipr and isp drivers */
1290 lt->rx_mbuf = &chan->in_mbuf;
1291 }
1292
1293 /*
1294 * use this instead of isic_bchannel_stat in i4b_bchan.c because it's static
1295 */
1296 static void
1297 avma1pp_bchannel_stat(int unit, int h_chan, bchan_statistics_t *bsp)
1298 {
1299 struct l1_softc *sc = ifpi_scp[unit];
1300 l1_bchan_state_t *chan = &sc->sc_chan[h_chan];
1301
1302 crit_enter();
1303
1304 bsp->outbytes = chan->txcount;
1305 bsp->inbytes = chan->rxcount;
1306
1307 chan->txcount = 0;
1308 chan->rxcount = 0;
1309
1310 crit_exit();
1311 }
1312
1313 /*---------------------------------------------------------------------------*
1314 * fill HSCX fifo with data from the current mbuf
1315 * Put this here until it can go into i4b_hscx.c
1316 *---------------------------------------------------------------------------*/
1317 static int
1318 avma1pp_hscx_fifo(l1_bchan_state_t *chan, struct l1_softc *sc)
1319 {
1320 int len;
1321 int nextlen;
1322 int i;
1323 int cmd = 0;
1324 /* using a scratch buffer simplifies writing to the FIFO */
1325 u_char scrbuf[HSCX_FIFO_LEN];
1326
1327 len = 0;
1328
1329 /*
1330 * fill the HSCX tx fifo with data from the current mbuf. if
1331 * current mbuf holds less data than HSCX fifo length, try to
1332 * get the next mbuf from (a possible) mbuf chain. if there is
1333 * not enough data in a single mbuf or in a chain, then this
1334 * is the last mbuf and we tell the HSCX that it has to send
1335 * CRC and closing flag
1336 */
1337
1338 while(chan->out_mbuf_cur && len != sc->sc_bfifolen)
1339 {
1340 nextlen = min(chan->out_mbuf_cur_len, sc->sc_bfifolen - len);
1341
1342 #ifdef NOTDEF
1343 printf("i:mh=%p, mc=%p, mcp=%p, mcl=%d l=%d nl=%d # ",
1344 chan->out_mbuf_head,
1345 chan->out_mbuf_cur,
1346 chan->out_mbuf_cur_ptr,
1347 chan->out_mbuf_cur_len,
1348 len,
1349 nextlen);
1350 #endif
1351
1352 cmd |= HSCX_CMDR_XTF;
1353 /* collect the data in the scratch buffer */
1354 for (i = 0; i < nextlen; i++)
1355 scrbuf[i + len] = chan->out_mbuf_cur_ptr[i];
1356
1357 len += nextlen;
1358 chan->txcount += nextlen;
1359
1360 chan->out_mbuf_cur_ptr += nextlen;
1361 chan->out_mbuf_cur_len -= nextlen;
1362
1363 if(chan->out_mbuf_cur_len == 0)
1364 {
1365 if((chan->out_mbuf_cur = chan->out_mbuf_cur->m_next) != NULL)
1366 {
1367 chan->out_mbuf_cur_ptr = chan->out_mbuf_cur->m_data;
1368 chan->out_mbuf_cur_len = chan->out_mbuf_cur->m_len;
1369
1370 if(sc->sc_trace & TRACE_B_TX)
1371 {
1372 i4b_trace_hdr_t hdr;
1373 hdr.unit = L0IFPIUNIT(sc->sc_unit);
1374 hdr.type = (chan->channel == HSCX_CH_A ? TRC_CH_B1 : TRC_CH_B2);
1375 hdr.dir = FROM_TE;
1376 hdr.count = ++sc->sc_trace_bcount;
1377 MICROTIME(hdr.time);
1378 i4b_l1_trace_ind(&hdr, chan->out_mbuf_cur->m_len, chan->out_mbuf_cur->m_data);
1379 }
1380 }
1381 else
1382 {
1383 if (chan->bprot != BPROT_NONE)
1384 cmd |= HSCX_CMDR_XME;
1385 i4b_Bfreembuf(chan->out_mbuf_head);
1386 chan->out_mbuf_head = NULL;
1387 }
1388 }
1389 }
1390 /* write what we have from the scratch buf to the HSCX fifo */
1391 if (len != 0)
1392 HSCX_WRFIFO(chan->channel, scrbuf, len);
1393 return(cmd);
1394 }
1395
1396 /*---------------------------------------------------------------------------*
1397 * ifpi - ISAC interrupt routine
1398 *---------------------------------------------------------------------------*/
1399 static void
1400 ifpi_isac_intr(struct l1_softc *sc)
1401 {
1402 u_char isac_irq_stat;
1403
1404 for(;;)
1405 {
1406 /* get isac irq status */
1407 isac_irq_stat = ISAC_READ(I_ISTA);
1408
1409 if(isac_irq_stat)
1410 ifpi_isac_irq(sc, isac_irq_stat); /* isac handler */
1411 else
1412 break;
1413 }
1414
1415 ISAC_WRITE(I_MASK, 0xff);
1416
1417 DELAY(100);
1418
1419 ISAC_WRITE(I_MASK, ISAC_IMASK);
1420 }
1421
1422 /*---------------------------------------------------------------------------*
1423 * ifpi_recover - try to recover from irq lockup
1424 *---------------------------------------------------------------------------*/
1425 void
1426 ifpi_recover(struct l1_softc *sc)
1427 {
1428 u_char byte;
1429
1430 /* get isac irq status */
1431
1432 byte = ISAC_READ(I_ISTA);
1433
1434 NDBGL1(L1_ERROR, " ISAC: ISTA = 0x%x", byte);
1435
1436 if(byte & ISAC_ISTA_EXI)
1437 NDBGL1(L1_ERROR, " ISAC: EXIR = 0x%x", (u_char)ISAC_READ(I_EXIR));
1438
1439 if(byte & ISAC_ISTA_CISQ)
1440 {
1441 byte = ISAC_READ(I_CIRR);
1442
1443 NDBGL1(L1_ERROR, " ISAC: CISQ = 0x%x", byte);
1444
1445 if(byte & ISAC_CIRR_SQC)
1446 NDBGL1(L1_ERROR, " ISAC: SQRR = 0x%x", (u_char)ISAC_READ(I_SQRR));
1447 }
1448
1449 NDBGL1(L1_ERROR, " ISAC: IMASK = 0x%x", ISAC_IMASK);
1450
1451 ISAC_WRITE(I_MASK, 0xff);
1452 DELAY(100);
1453 ISAC_WRITE(I_MASK, ISAC_IMASK);
1454 }
1455
1456
1457 #endif /* NIFPI > 0 */
Port diff from OpenBSD to DragonFly