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- Use firmware(9) for acx(4) and revoke acx(4)'s private ioctls
[dfdiff.git] / sys / dev / netif / acx / acx100.c
blob5fa3df6245a776cbfd8d9541aaf9d6ff1c79834d
1 /*
2 * Copyright (c) 2006 The DragonFly Project. All rights reserved.
3 *
4 * This code is derived from software contributed to The DragonFly Project
5 * by Sepherosa Ziehau <sepherosa@gmail.com>
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 *
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
16 * distribution.
17 * 3. Neither the name of The DragonFly Project nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific, prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
24 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
25 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
27 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
28 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
29 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
31 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 * SUCH DAMAGE.
33 *
34 * $DragonFly: src/sys/dev/netif/acx/acx100.c,v 1.12 2008/02/06 08:21:22 sephe Exp $
35 */
36
37 #include <sys/param.h>
38 #include <sys/bus.h>
39 #include <sys/endian.h>
40 #include <sys/rman.h>
41 #include <sys/socket.h>
42 #include <sys/sysctl.h>
43
44 #include <net/if.h>
45 #include <net/if_arp.h>
46 #include <net/if_media.h>
47
48 #include <netproto/802_11/ieee80211_var.h>
49 #include <netproto/802_11/ieee80211_radiotap.h>
50 #include <netproto/802_11/wlan_ratectl/amrr/ieee80211_amrr_param.h>
51 #include <netproto/802_11/wlan_ratectl/onoe/ieee80211_onoe_param.h>
52
53 #include <bus/pci/pcireg.h>
54
55 #define ACX_DEBUG
56
57 #include <dev/netif/acx/if_acxreg.h>
58 #include <dev/netif/acx/if_acxvar.h>
59 #include <dev/netif/acx/acxcmd.h>
60
61 #define ACX100_CONF_FW_RING 0x0003
62 #define ACX100_CONF_MEMOPT 0x0005
63
64 #define ACX100_INTR_ENABLE (ACXRV_INTR_TX_FINI | ACXRV_INTR_RX_FINI)
65 /*
66 * XXX do we really care about following interrupts?
67 *
68 * ACXRV_INTR_INFO | ACXRV_INTR_SCAN_FINI
69 */
70
71 #define ACX100_INTR_DISABLE (uint16_t)~(ACXRV_INTR_UNKN)
72
73 #define ACX100_RATE(rate) ((rate) * 5)
74
75 #define ACX100_RSSI_CORR 8
76 #define ACX100_TXPOWER 18
77 #define ACX100_GPIO_POWER_LED 0x0800
78 #define ACX100_EE_EADDR_OFS 0x1a
79
80 #define ACX100_FW_TXRING_SIZE (ACX_TX_DESC_CNT * sizeof(struct acx_fw_txdesc))
81 #define ACX100_FW_RXRING_SIZE (ACX_RX_DESC_CNT * sizeof(struct acx_fw_rxdesc))
82
83 /*
84 * NOTE:
85 * Following structs' fields are little endian
86 */
87
88 struct acx100_bss_join {
89 uint8_t dtim_intvl;
90 uint8_t basic_rates;
91 uint8_t op_rates;
92 } __packed;
93
94 struct acx100_conf_fw_ring {
95 struct acx_conf confcom;
96 uint32_t fw_ring_size; /* total size of fw (tx + rx) ring */
97 uint32_t fw_rxring_addr; /* start phyaddr of fw rx desc */
98 uint8_t opt; /* see ACX100_RINGOPT_ */
99 uint8_t fw_txring_num; /* num of TX ring */
100 uint8_t fw_rxdesc_num; /* num of fw rx desc */
101 uint8_t reserved0;
102 uint32_t fw_ring_end[2]; /* see ACX100_SET_RING_END() */
103 uint32_t fw_txring_addr; /* start phyaddr of fw tx desc */
104 uint8_t fw_txring_prio; /* see ACX100_TXRING_PRIO_ */
105 uint8_t fw_txdesc_num; /* num of fw tx desc */
106 uint16_t reserved1;
107 } __packed;
108
109 #define ACX100_RINGOPT_AUTO_RESET 0x1
110 #define ACX100_TXRING_PRIO_DEFAULT 0
111 #define ACX100_SET_RING_END(conf, end) \
112 do { \
113 (conf)->fw_ring_end[0] = htole32(end); \
114 (conf)->fw_ring_end[1] = htole32(end + 8); \
115 } while (0)
116
117 struct acx100_conf_memblk_size {
118 struct acx_conf confcom;
119 uint16_t memblk_size; /* size of each mem block */
120 } __packed;
121
122 struct acx100_conf_mem {
123 struct acx_conf confcom;
124 uint32_t opt; /* see ACX100_MEMOPT_ */
125 uint32_t h_rxring_paddr; /* host rx desc start phyaddr */
126
127 /*
128 * Memory blocks are controled by hardware
129 * once after they are initialized
130 */
131 uint32_t rx_memblk_addr; /* start addr of rx mem blocks */
132 uint32_t tx_memblk_addr; /* start addr of tx mem blocks */
133 uint16_t rx_memblk_num; /* num of RX mem block */
134 uint16_t tx_memblk_num; /* num of TX mem block */
135 } __packed;
136
137 #define ACX100_MEMOPT_MEM_INSTR 0x00000000 /* memory access instruct */
138 #define ACX100_MEMOPT_HOSTDESC 0x00010000 /* host indirect desc */
139 #define ACX100_MEMOPT_MEMBLOCK 0x00020000 /* local mem block list */
140 #define ACX100_MEMOPT_IO_INSTR 0x00040000 /* IO instruct */
141 #define ACX100_MEMOPT_PCICONF 0x00080000 /* PCI conf space */
142
143 #define ACX100_MEMBLK_ALIGN 0x20
144
145 struct acx100_conf_cca_mode {
146 struct acx_conf confcom;
147 uint8_t cca_mode;
148 uint8_t unknown;
149 } __packed;
150
151 struct acx100_conf_ed_thresh {
152 struct acx_conf confcom;
153 uint8_t ed_thresh;
154 uint8_t unknown[3];
155 } __packed;
156
157 struct acx100_conf_wepkey {
158 struct acx_conf confcom;
159 uint8_t action; /* see ACX100_WEPKEY_ACT_ */
160 uint8_t key_len;
161 uint8_t key_idx;
162 #define ACX100_WEPKEY_LEN 29
163 uint8_t key[ACX100_WEPKEY_LEN];
164 } __packed;
165
166 #define ACX100_WEPKEY_ACT_ADD 1
167
168 #define ACX100_CONF_FUNC(sg, name) _ACX_CONF_FUNC(sg, name, 100)
169 #define ACX_CONF_fw_ring ACX100_CONF_FW_RING
170 #define ACX_CONF_memblk_size ACX_CONF_MEMBLK_SIZE
171 #define ACX_CONF_mem ACX100_CONF_MEMOPT
172 #define ACX_CONF_cca_mode ACX_CONF_CCA_MODE
173 #define ACX_CONF_ed_thresh ACX_CONF_ED_THRESH
174 #define ACX_CONF_wepkey ACX_CONF_WEPKEY
175 ACX100_CONF_FUNC(set, fw_ring);
176 ACX100_CONF_FUNC(set, memblk_size);
177 ACX100_CONF_FUNC(set, mem);
178 ACX100_CONF_FUNC(get, cca_mode);
179 ACX100_CONF_FUNC(set, cca_mode);
180 ACX100_CONF_FUNC(get, ed_thresh);
181 ACX100_CONF_FUNC(set, ed_thresh);
182 ACX100_CONF_FUNC(set, wepkey);
183
184 #define ACXCMD_init_mem ACXCMD_INIT_MEM
185 ACX_NOARG_FUNC(init_mem);
186
187 static const uint16_t acx100_reg[ACXREG_MAX] = {
188 ACXREG(SOFT_RESET, 0x0000),
189
190 ACXREG(FWMEM_ADDR, 0x0014),
191 ACXREG(FWMEM_DATA, 0x0018),
192 ACXREG(FWMEM_CTRL, 0x001c),
193 ACXREG(FWMEM_START, 0x0020),
194
195 ACXREG(EVENT_MASK, 0x0034),
196
197 ACXREG(INTR_TRIG, 0x007c),
198 ACXREG(INTR_MASK, 0x0098),
199 ACXREG(INTR_STATUS, 0x00a4),
200 ACXREG(INTR_STATUS_CLR, 0x00a8),
201 ACXREG(INTR_ACK, 0x00ac),
202
203 ACXREG(HINTR_TRIG, 0x00b0),
204 ACXREG(RADIO_ENABLE, 0x0104),
205
206 ACXREG(EEPROM_INIT, 0x02d0),
207 ACXREG(EEPROM_CTRL, 0x0250),
208 ACXREG(EEPROM_ADDR, 0x0254),
209 ACXREG(EEPROM_DATA, 0x0258),
210 ACXREG(EEPROM_CONF, 0x025c),
211 ACXREG(EEPROM_INFO, 0x02ac),
212
213 ACXREG(PHY_ADDR, 0x0268),
214 ACXREG(PHY_DATA, 0x026c),
215 ACXREG(PHY_CTRL, 0x0270),
216
217 ACXREG(GPIO_OUT_ENABLE, 0x0290),
218 ACXREG(GPIO_OUT, 0x0298),
219
220 ACXREG(CMD_REG_OFFSET, 0x02a4),
221 ACXREG(INFO_REG_OFFSET, 0x02a8),
222
223 ACXREG(RESET_SENSE, 0x02d4),
224 ACXREG(ECPU_CTRL, 0x02d8)
225 };
226
227 static const uint8_t acx100_txpower_maxim[21] = {
228 63, 63, 63, 62,
229 61, 61, 60, 60,
230 59, 58, 57, 55,
231 53, 50, 47, 43,
232 38, 31, 23, 13,
233 0
234 };
235
236 static const uint8_t acx100_txpower_rfmd[21] = {
237 0, 0, 0, 1,
238 2, 2, 3, 3,
239 4, 5, 6, 8,
240 10, 13, 16, 20,
241 25, 32, 41, 50,
242 63
243 };
244
245 static const uint8_t acx100_rate_map[45] = {
246 [2] = 0x01,
247 [4] = 0x02,
248 [11] = 0x04,
249 [22] = 0x08,
250 [44] = 0x10
251 };
252
253 static int acx100_init(struct acx_softc *);
254 static int acx100_init_wep(struct acx_softc *);
255 static int acx100_init_tmplt(struct acx_softc *);
256 static int acx100_init_fw_ring(struct acx_softc *);
257 static int acx100_init_memory(struct acx_softc *);
258
259 static void acx100_init_fw_txring(struct acx_softc *, uint32_t);
260 static void acx100_init_fw_rxring(struct acx_softc *, uint32_t);
261
262 static int acx100_read_config(struct acx_softc *, struct acx_config *);
263 static int acx100_write_config(struct acx_softc *, struct acx_config *);
264
265 static void *acx100_ratectl_attach(struct ieee80211com *, u_int);
266
267 static int acx100_set_txpower(struct acx_softc *);
268
269 static uint8_t acx100_set_fw_txdesc_rate(struct acx_softc *,
270 struct acx_txbuf *,
271 struct ieee80211_node *, int);
272 static void acx100_tx_complete(struct acx_softc *, struct acx_txbuf *,
273 int, int);
274 static void acx100_set_bss_join_param(struct acx_softc *, void *, int);
275
276 static int acx100_set_wepkey(struct acx_softc *, struct ieee80211_key *,
277 int);
278
279 static void acx100_proc_wep_rxbuf(struct acx_softc *, struct mbuf *, int *);
280
281 #define ACX100_CHK_RATE(ifp, rate, rate_idx) \
282 acx100_check_rate(ifp, rate, rate_idx, __func__)
283
284 static __inline int
285 acx100_check_rate(struct ifnet *ifp, u_int rate, int rate_idx,
286 const char *fname)
287 {
288 #define N(arr) (sizeof(arr) / sizeof(arr[0]))
289 if (rate >= N(acx100_rate_map)) {
290 if_printf(ifp, "%s rate out of range %u (idx %d)\n",
291 fname, rate, rate_idx);
292 return -1;
293 }
294 #undef N
295
296 if (acx100_rate_map[rate] == 0) {
297 if_printf(ifp, "%s invalid rate %u (idx %d)\n",
298 fname, rate, rate_idx);
299 return -1;
300 }
301 return 0;
302 }
303
304 void
305 acx100_set_param(device_t dev)
306 {
307 struct acx_softc *sc = device_get_softc(dev);
308 struct ieee80211com *ic = &sc->sc_ic;
309 struct acx_firmware *fw = &sc->sc_firmware;
310
311 sc->chip_mem1_rid = PCIR_BAR(1);
312 sc->chip_mem2_rid = PCIR_BAR(2);
313 sc->chip_ioreg = acx100_reg;
314 sc->chip_hw_crypt = 1;
315 sc->chip_intr_enable = ACX100_INTR_ENABLE;
316 sc->chip_intr_disable = ACX100_INTR_DISABLE;
317 sc->chip_gpio_pled = ACX100_GPIO_POWER_LED;
318 sc->chip_ee_eaddr_ofs = ACX100_EE_EADDR_OFS;
319 sc->chip_txdesc1_len = ACX_FRAME_HDRLEN;
320 sc->chip_fw_txdesc_ctrl = DESC_CTRL_AUTODMA |
321 DESC_CTRL_RECLAIM |
322 DESC_CTRL_FIRST_FRAG;
323 sc->chip_short_retry_limit = 7;
324 sc->chip_rssi_corr = ACX100_RSSI_CORR;
325
326 sc->chip_phymode = IEEE80211_MODE_11B;
327 sc->chip_chan_flags = IEEE80211_CHAN_B;
328
329 ic->ic_phytype = IEEE80211_T_DS;
330 ic->ic_sup_rates[IEEE80211_MODE_11B] = acx_rates_11b;
331
332 IEEE80211_ONOE_PARAM_SETUP(&sc->sc_onoe_param);
333
334 ic->ic_ratectl.rc_st_ratectl_cap = IEEE80211_RATECTL_CAP_ONOE;
335 ic->ic_ratectl.rc_st_ratectl = IEEE80211_RATECTL_ONOE;
336 ic->ic_ratectl.rc_st_attach = acx100_ratectl_attach;
337
338 sc->chip_init = acx100_init;
339 sc->chip_set_wepkey = acx100_set_wepkey;
340 sc->chip_read_config = acx100_read_config;
341 sc->chip_write_config = acx100_write_config;
342 sc->chip_set_fw_txdesc_rate = acx100_set_fw_txdesc_rate;
343 sc->chip_tx_complete = acx100_tx_complete;
344 sc->chip_set_bss_join_param = acx100_set_bss_join_param;
345 sc->chip_proc_wep_rxbuf = acx100_proc_wep_rxbuf;
346
347 fw->combined_radio_fw = 0;
348 fw->fwdir = "100";
349 }
350
351 static int
352 acx100_init(struct acx_softc *sc)
353 {
354 /*
355 * NOTE:
356 * Order of initialization:
357 * 1) WEP
358 * 2) Templates
359 * 3) Firmware TX/RX ring
360 * 4) Hardware memory
361 * Above order is critical to get a correct memory map
362 */
363
364 if (acx100_init_wep(sc) != 0) {
365 if_printf(&sc->sc_ic.ic_if, "%s can't initialize wep\n",
366 __func__);
367 return ENXIO;
368 }
369
370 if (acx100_init_tmplt(sc) != 0) {
371 if_printf(&sc->sc_ic.ic_if, "%s can't initialize templates\n",
372 __func__);
373 return ENXIO;
374 }
375
376 if (acx100_init_fw_ring(sc) != 0) {
377 if_printf(&sc->sc_ic.ic_if, "%s can't initialize fw ring\n",
378 __func__);
379 return ENXIO;
380 }
381
382 if (acx100_init_memory(sc) != 0) {
383 if_printf(&sc->sc_ic.ic_if, "%s can't initialize hw memory\n",
384 __func__);
385 return ENXIO;
386 }
387 return 0;
388 }
389
390 static int
391 acx100_init_wep(struct acx_softc *sc)
392 {
393 struct acx_conf_wepopt wep_opt;
394 struct acx_conf_mmap mem_map;
395
396 /* Set WEP cache start/end address */
397 if (acx_get_mmap_conf(sc, &mem_map) != 0) {
398 if_printf(&sc->sc_ic.ic_if, "can't get mmap\n");
399 return 1;
400 }
401
402 mem_map.wep_cache_start = htole32(le32toh(mem_map.code_end) + 4);
403 mem_map.wep_cache_end = htole32(le32toh(mem_map.code_end) + 4);
404 if (acx_set_mmap_conf(sc, &mem_map) != 0) {
405 if_printf(&sc->sc_ic.ic_if, "can't set mmap\n");
406 return 1;
407 }
408
409 /* Set WEP options */
410 wep_opt.nkey = htole16(IEEE80211_WEP_NKID + 10);
411 wep_opt.opt = WEPOPT_HDWEP;
412 if (acx_set_wepopt_conf(sc, &wep_opt) != 0) {
413 if_printf(&sc->sc_ic.ic_if, "can't set wep opt\n");
414 return 1;
415 }
416 return 0;
417 }
418
419 static int
420 acx100_init_tmplt(struct acx_softc *sc)
421 {
422 struct acx_conf_mmap mem_map;
423
424 /* Set templates start address */
425 if (acx_get_mmap_conf(sc, &mem_map) != 0) {
426 if_printf(&sc->sc_ic.ic_if, "can't get mmap\n");
427 return 1;
428 }
429
430 mem_map.pkt_tmplt_start = mem_map.wep_cache_end;
431 if (acx_set_mmap_conf(sc, &mem_map) != 0) {
432 if_printf(&sc->sc_ic.ic_if, "can't set mmap\n");
433 return 1;
434 }
435
436 /* Initialize various packet templates */
437 if (acx_init_tmplt_ordered(sc) != 0) {
438 if_printf(&sc->sc_ic.ic_if, "can't init tmplt\n");
439 return 1;
440 }
441 return 0;
442 }
443
444 static int
445 acx100_init_fw_ring(struct acx_softc *sc)
446 {
447 struct acx100_conf_fw_ring ring;
448 struct acx_conf_mmap mem_map;
449 uint32_t txring_start, rxring_start, ring_end;
450
451 /* Set firmware descriptor ring start address */
452 if (acx_get_mmap_conf(sc, &mem_map) != 0) {
453 if_printf(&sc->sc_ic.ic_if, "can't get mmap\n");
454 return 1;
455 }
456
457 txring_start = le32toh(mem_map.pkt_tmplt_end) + 4;
458 rxring_start = txring_start + ACX100_FW_TXRING_SIZE;
459 ring_end = rxring_start + ACX100_FW_RXRING_SIZE;
460
461 mem_map.fw_desc_start = htole32(txring_start);
462 if (acx_set_mmap_conf(sc, &mem_map) != 0) {
463 if_printf(&sc->sc_ic.ic_if, "can't set mmap\n");
464 return 1;
465 }
466
467 /* Set firmware descriptor ring configure */
468 bzero(&ring, sizeof(ring));
469 ring.fw_ring_size = htole32(ACX100_FW_TXRING_SIZE +
470 ACX100_FW_RXRING_SIZE + 8);
471
472 ring.fw_txring_num = 1;
473 ring.fw_txring_addr = htole32(txring_start);
474 ring.fw_txring_prio = ACX100_TXRING_PRIO_DEFAULT;
475 ring.fw_txdesc_num = 0; /* XXX ignored?? */
476
477 ring.fw_rxring_addr = htole32(rxring_start);
478 ring.fw_rxdesc_num = 0; /* XXX ignored?? */
479
480 ring.opt = ACX100_RINGOPT_AUTO_RESET;
481 ACX100_SET_RING_END(&ring, ring_end);
482 if (acx100_set_fw_ring_conf(sc, &ring) != 0) {
483 if_printf(&sc->sc_ic.ic_if, "can't set fw ring configure\n");
484 return 1;
485 }
486
487 /* Setup firmware TX/RX descriptor ring */
488 acx100_init_fw_txring(sc, txring_start);
489 acx100_init_fw_rxring(sc, rxring_start);
490
491 return 0;
492 }
493
494 #define MEMBLK_ALIGN(addr) \
495 (((addr) + (ACX100_MEMBLK_ALIGN - 1)) & ~(ACX100_MEMBLK_ALIGN - 1))
496
497 static int
498 acx100_init_memory(struct acx_softc *sc)
499 {
500 struct acx100_conf_memblk_size memblk_sz;
501 struct acx100_conf_mem mem;
502 struct acx_conf_mmap mem_map;
503 uint32_t memblk_start, memblk_end;
504 int total_memblk, txblk_num, rxblk_num;
505
506 /* Set memory block start address */
507 if (acx_get_mmap_conf(sc, &mem_map) != 0) {
508 if_printf(&sc->sc_ic.ic_if, "can't get mmap\n");
509 return 1;
510 }
511
512 mem_map.memblk_start =
513 htole32(MEMBLK_ALIGN(le32toh(mem_map.fw_desc_end) + 4));
514
515 if (acx_set_mmap_conf(sc, &mem_map) != 0) {
516 if_printf(&sc->sc_ic.ic_if, "can't set mmap\n");
517 return 1;
518 }
519
520 /* Set memory block size */
521 memblk_sz.memblk_size = htole16(ACX_MEMBLOCK_SIZE);
522 if (acx100_set_memblk_size_conf(sc, &memblk_sz) != 0) {
523 if_printf(&sc->sc_ic.ic_if, "can't set mem block size\n");
524 return 1;
525 }
526
527 /* Get memory map after setting it */
528 if (acx_get_mmap_conf(sc, &mem_map) != 0) {
529 if_printf(&sc->sc_ic.ic_if, "can't get mmap again\n");
530 return 1;
531 }
532 memblk_start = le32toh(mem_map.memblk_start);
533 memblk_end = le32toh(mem_map.memblk_end);
534
535 /* Set memory options */
536 mem.opt = htole32(ACX100_MEMOPT_MEMBLOCK | ACX100_MEMOPT_HOSTDESC);
537 mem.h_rxring_paddr = htole32(sc->sc_ring_data.rx_ring_paddr);
538
539 total_memblk = (memblk_end - memblk_start) / ACX_MEMBLOCK_SIZE;
540
541 rxblk_num = total_memblk / 2; /* 50% */
542 txblk_num = total_memblk - rxblk_num; /* 50% */
543
544 DPRINTF((&sc->sc_ic.ic_if, "\ttotal memory blocks\t%d\n"
545 "\trx memory blocks\t%d\n"
546 "\ttx memory blocks\t%d\n",
547 total_memblk, rxblk_num, txblk_num));
548
549 mem.rx_memblk_num = htole16(rxblk_num);
550 mem.tx_memblk_num = htole16(txblk_num);
551
552 mem.rx_memblk_addr = htole32(MEMBLK_ALIGN(memblk_start));
553 mem.tx_memblk_addr =
554 htole32(MEMBLK_ALIGN(memblk_start +
555 (ACX_MEMBLOCK_SIZE * rxblk_num)));
556
557 if (acx100_set_mem_conf(sc, &mem) != 0) {
558 if_printf(&sc->sc_ic.ic_if, "can't set mem options\n");
559 return 1;
560 }
561
562 /* Initialize memory */
563 if (acx_init_mem(sc) != 0) {
564 if_printf(&sc->sc_ic.ic_if, "can't init mem\n");
565 return 1;
566 }
567 return 0;
568 }
569
570 #undef MEMBLK_ALIGN
571
572 static void
573 acx100_init_fw_txring(struct acx_softc *sc, uint32_t fw_txdesc_start)
574 {
575 struct acx_fw_txdesc fw_desc;
576 struct acx_txbuf *tx_buf;
577 uint32_t desc_paddr, fw_desc_offset;
578 int i;
579
580 bzero(&fw_desc, sizeof(fw_desc));
581 fw_desc.f_tx_ctrl = DESC_CTRL_HOSTOWN |
582 DESC_CTRL_RECLAIM |
583 DESC_CTRL_AUTODMA |
584 DESC_CTRL_FIRST_FRAG;
585
586 tx_buf = sc->sc_buf_data.tx_buf;
587 fw_desc_offset = fw_txdesc_start;
588 desc_paddr = sc->sc_ring_data.tx_ring_paddr;
589
590 for (i = 0; i < ACX_TX_DESC_CNT; ++i) {
591 fw_desc.f_tx_host_desc = htole32(desc_paddr);
592
593 if (i == ACX_TX_DESC_CNT - 1) {
594 fw_desc.f_tx_next_desc = htole32(fw_txdesc_start);
595 } else {
596 fw_desc.f_tx_next_desc =
597 htole32(fw_desc_offset +
598 sizeof(struct acx_fw_txdesc));
599 }
600
601 tx_buf[i].tb_fwdesc_ofs = fw_desc_offset;
602 DESC_WRITE_REGION_1(sc, fw_desc_offset, &fw_desc,
603 sizeof(fw_desc));
604
605 desc_paddr += (2 * sizeof(struct acx_host_desc));
606 fw_desc_offset += sizeof(fw_desc);
607 }
608 }
609
610 static void
611 acx100_init_fw_rxring(struct acx_softc *sc, uint32_t fw_rxdesc_start)
612 {
613 struct acx_fw_rxdesc fw_desc;
614 uint32_t fw_desc_offset;
615 int i;
616
617 bzero(&fw_desc, sizeof(fw_desc));
618 fw_desc.f_rx_ctrl = DESC_CTRL_RECLAIM | DESC_CTRL_AUTODMA;
619
620 fw_desc_offset = fw_rxdesc_start;
621
622 for (i = 0; i < ACX_RX_DESC_CNT; ++i) {
623 if (i == ACX_RX_DESC_CNT - 1) {
624 fw_desc.f_rx_next_desc = htole32(fw_rxdesc_start);
625 } else {
626 fw_desc.f_rx_next_desc =
627 htole32(fw_desc_offset +
628 sizeof(struct acx_fw_rxdesc));
629 }
630
631 DESC_WRITE_REGION_1(sc, fw_desc_offset, &fw_desc,
632 sizeof(fw_desc));
633
634 fw_desc_offset += sizeof(fw_desc);
635 }
636 }
637
638 static int
639 acx100_read_config(struct acx_softc *sc, struct acx_config *conf)
640 {
641 struct acx100_conf_cca_mode cca;
642 struct acx100_conf_ed_thresh ed;
643
644 /*
645 * NOTE:
646 * CCA mode and ED threshold MUST be read during initialization
647 * or the acx100 card won't work as expected
648 */
649
650 /* Get CCA mode */
651 if (acx100_get_cca_mode_conf(sc, &cca) != 0) {
652 if_printf(&sc->sc_ic.ic_if, "%s can't get cca mode\n",
653 __func__);
654 return ENXIO;
655 }
656 conf->cca_mode = cca.cca_mode;
657 DPRINTF((&sc->sc_ic.ic_if, "cca mode %02x\n", cca.cca_mode));
658
659 /* Get ED threshold */
660 if (acx100_get_ed_thresh_conf(sc, &ed) != 0) {
661 if_printf(&sc->sc_ic.ic_if, "%s can't get ed threshold\n",
662 __func__);
663 return ENXIO;
664 }
665 conf->ed_thresh = ed.ed_thresh;
666 DPRINTF((&sc->sc_ic.ic_if, "ed threshold %02x\n", ed.ed_thresh));
667
668 return 0;
669 }
670
671 static int
672 acx100_write_config(struct acx_softc *sc, struct acx_config *conf)
673 {
674 struct acx100_conf_cca_mode cca;
675 struct acx100_conf_ed_thresh ed;
676
677 /* Set CCA mode */
678 cca.cca_mode = conf->cca_mode;
679 if (acx100_set_cca_mode_conf(sc, &cca) != 0) {
680 if_printf(&sc->sc_ic.ic_if, "%s can't set cca mode\n",
681 __func__);
682 return ENXIO;
683 }
684
685 /* Set ED threshold */
686 ed.ed_thresh = conf->ed_thresh;
687 if (acx100_set_ed_thresh_conf(sc, &ed) != 0) {
688 if_printf(&sc->sc_ic.ic_if, "%s can't set ed threshold\n",
689 __func__);
690 return ENXIO;
691 }
692
693 /* Set TX power */
694 acx100_set_txpower(sc); /* ignore return value */
695
696 return 0;
697 }
698
699 static int
700 acx100_set_txpower(struct acx_softc *sc)
701 {
702 const uint8_t *map;
703
704 switch (sc->sc_radio_type) {
705 case ACX_RADIO_TYPE_MAXIM:
706 map = acx100_txpower_maxim;
707 break;
708 case ACX_RADIO_TYPE_RFMD:
709 case ACX_RADIO_TYPE_RALINK:
710 map = acx100_txpower_rfmd;
711 break;
712 default:
713 if_printf(&sc->sc_ic.ic_if, "TX power for radio type 0x%02x "
714 "can't be set yet\n", sc->sc_radio_type);
715 return 1;
716 }
717
718 acx_write_phyreg(sc, ACXRV_PHYREG_TXPOWER, map[ACX100_TXPOWER]);
719 return 0;
720 }
721
722 static uint8_t
723 acx100_set_fw_txdesc_rate(struct acx_softc *sc, struct acx_txbuf *tx_buf,
724 struct ieee80211_node *ni, int data_len)
725 {
726 int rate;
727
728 tx_buf->tb_rateidx_len = 1;
729 if (ni == NULL) {
730 rate = 2; /* 1Mbit/s */
731 tx_buf->tb_rateidx[0] = 0;
732 } else {
733 ieee80211_ratectl_findrate(ni, data_len,
734 tx_buf->tb_rateidx, 1);
735 rate = IEEE80211_RS_RATE(&ni->ni_rates,
736 tx_buf->tb_rateidx[0]);
737 if (ACX100_CHK_RATE(&sc->sc_ic.ic_if, rate,
738 tx_buf->tb_rateidx[0]) < 0)
739 rate = 2;
740 }
741 FW_TXDESC_SETFIELD_1(sc, tx_buf, f_tx_rate100, ACX100_RATE(rate));
742
743 return rate;
744 }
745
746 static void
747 acx100_set_bss_join_param(struct acx_softc *sc, void *param, int dtim_intvl)
748 {
749 struct acx100_bss_join *bj = param;
750 struct ifnet *ifp = &sc->sc_ic.ic_if;
751 const struct ieee80211_rateset *rs = &sc->sc_ic.ic_bss->ni_rates;
752 int i;
753
754 bj->basic_rates = 0;
755 bj->op_rates = 0;
756 for (i = 0; i < rs->rs_nrates; ++i) {
757 u_int map_idx = IEEE80211_RS_RATE(rs, i);
758 uint8_t rate;
759
760 if (ACX100_CHK_RATE(ifp, map_idx, i) < 0)
761 continue;
762
763 rate = acx100_rate_map[map_idx];
764 if (rs->rs_rates[i] & IEEE80211_RATE_BASIC)
765 bj->basic_rates |= rate;
766 bj->op_rates |= rate;
767 }
768 DPRINTF((ifp, "basic rates:0x%02x, op rates:0x%02x\n",
769 bj->basic_rates, bj->op_rates));
770
771 bj->dtim_intvl = dtim_intvl;
772 }
773
774 static int
775 acx100_set_wepkey(struct acx_softc *sc, struct ieee80211_key *wk, int wk_idx)
776 {
777 struct acx100_conf_wepkey conf_wk;
778
779 if (wk->wk_keylen > ACX100_WEPKEY_LEN) {
780 if_printf(&sc->sc_ic.ic_if, "%dth WEP key size beyond %d\n",
781 wk_idx, ACX100_WEPKEY_LEN);
782 return EINVAL;
783 }
784
785 conf_wk.action = ACX100_WEPKEY_ACT_ADD;
786 conf_wk.key_len = wk->wk_keylen;
787 conf_wk.key_idx = wk_idx;
788 bcopy(wk->wk_key, conf_wk.key, wk->wk_keylen);
789 if (acx100_set_wepkey_conf(sc, &conf_wk) != 0) {
790 if_printf(&sc->sc_ic.ic_if, "%s set %dth WEP key failed\n",
791 __func__, wk_idx);
792 return ENXIO;
793 }
794 return 0;
795 }
796
797 static void
798 acx100_proc_wep_rxbuf(struct acx_softc *sc, struct mbuf *m, int *len)
799 {
800 int mac_hdrlen;
801 struct ieee80211_frame *f;
802
803 /*
804 * Strip leading IV and KID, and trailing CRC
805 */
806
807 f = mtod(m, struct ieee80211_frame *);
808
809 if ((f->i_fc[1] & IEEE80211_FC1_DIR_MASK) == IEEE80211_FC1_DIR_DSTODS)
810 mac_hdrlen = sizeof(struct ieee80211_frame_addr4);
811 else
812 mac_hdrlen = sizeof(struct ieee80211_frame);
813
814 #define IEEEWEP_IVLEN (IEEE80211_WEP_IVLEN + IEEE80211_WEP_KIDLEN)
815 #define IEEEWEP_EXLEN (IEEEWEP_IVLEN + IEEE80211_WEP_CRCLEN)
816
817 *len = *len - IEEEWEP_EXLEN;
818
819 /* Move MAC header toward frame body */
820 ovbcopy(f, (uint8_t *)f + IEEEWEP_IVLEN, mac_hdrlen);
821 m_adj(m, IEEEWEP_IVLEN);
822
823 #undef IEEEWEP_EXLEN
824 #undef IEEEWEP_IVLEN
825 }
826
827 static void
828 acx100_tx_complete(struct acx_softc *sc, struct acx_txbuf *tx_buf,
829 int frame_len, int is_fail)
830 {
831 int rts_retries, data_retries;
832 struct ieee80211_ratectl_res rc_res;
833
834 rts_retries = FW_TXDESC_GETFIELD_1(sc, tx_buf, f_tx_rts_nretry);
835 data_retries = FW_TXDESC_GETFIELD_1(sc, tx_buf, f_tx_data_nretry);
836
837 rc_res.rc_res_rateidx = tx_buf->tb_rateidx[0];
838 rc_res.rc_res_tries = data_retries + 1;
839
840 ieee80211_ratectl_tx_complete(tx_buf->tb_node, frame_len,
841 &rc_res, 1, data_retries, rts_retries,
842 is_fail);
843 }
844
845 static void *
846 acx100_ratectl_attach(struct ieee80211com *ic, u_int rc)
847 {
848 struct acx_softc *sc = ic->ic_if.if_softc;
849
850 switch (rc) {
851 case IEEE80211_RATECTL_ONOE:
852 return &sc->sc_onoe_param;
853 case IEEE80211_RATECTL_NONE:
854 /* This could only happen during detaching */
855 return NULL;
856 default:
857 panic("unknown rate control algo %u\n", rc);
858 return NULL;
859 }
860 }
Port diff from OpenBSD to DragonFly