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Rename sprintf -> ksprintf
[dfdiff.git] / sys / dev / disk / ncr / ncr.c
blob642c0afa43d30a4834baa13080a668e433c6c10d
1 /**************************************************************************
2 **
3 ** $FreeBSD: src/sys/pci/ncr.c,v 1.155.2.3 2001/03/05 13:09:10 obrien Exp $
4 ** $DragonFly: src/sys/dev/disk/ncr/ncr.c,v 1.16 2006/12/20 18:14:39 dillon Exp $
5 **
6 ** Device driver for the NCR 53C8XX PCI-SCSI-Controller Family.
7 **
8 **-------------------------------------------------------------------------
9 **
10 ** Written for 386bsd and FreeBSD by
11 ** Wolfgang Stanglmeier <wolf@cologne.de>
12 ** Stefan Esser <se@mi.Uni-Koeln.de>
13 **
14 **-------------------------------------------------------------------------
15 **
16 ** Copyright (c) 1994 Wolfgang Stanglmeier. All rights reserved.
17 **
18 ** Redistribution and use in source and binary forms, with or without
19 ** modification, are permitted provided that the following conditions
20 ** are met:
21 ** 1. Redistributions of source code must retain the above copyright
22 ** notice, this list of conditions and the following disclaimer.
23 ** 2. Redistributions in binary form must reproduce the above copyright
24 ** notice, this list of conditions and the following disclaimer in the
25 ** documentation and/or other materials provided with the distribution.
26 ** 3. The name of the author may not be used to endorse or promote products
27 ** derived from this software without specific prior written permission.
28 **
29 ** THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
30 ** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
31 ** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
32 ** IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
33 ** INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
34 ** NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 ** DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 ** THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
38 ** THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 **
40 ***************************************************************************
41 */
42
43 #define NCR_DATE "pl30 98/1/1"
44
45 #define NCR_VERSION (2)
46 #define MAX_UNITS (16)
47
48 #define NCR_GETCC_WITHMSG
49
50 #if (defined(__DragonFly__) || defined (__FreeBSD__)) && defined(_KERNEL)
51 #include "opt_ncr.h"
52 #endif
53
54 /*==========================================================
55 **
56 ** Configuration and Debugging
57 **
58 ** May be overwritten in <arch/conf/xxxx>
59 **
60 **==========================================================
61 */
62
63 /*
64 ** SCSI address of this device.
65 ** The boot routines should have set it.
66 ** If not, use this.
67 */
68
69 #ifndef SCSI_NCR_MYADDR
70 #define SCSI_NCR_MYADDR (7)
71 #endif /* SCSI_NCR_MYADDR */
72
73 /*
74 ** The default synchronous period factor
75 ** (0=asynchronous)
76 ** If maximum synchronous frequency is defined, use it instead.
77 */
78
79 #ifndef SCSI_NCR_MAX_SYNC
80
81 #ifndef SCSI_NCR_DFLT_SYNC
82 #define SCSI_NCR_DFLT_SYNC (12)
83 #endif /* SCSI_NCR_DFLT_SYNC */
84
85 #else
86
87 #if SCSI_NCR_MAX_SYNC == 0
88 #define SCSI_NCR_DFLT_SYNC 0
89 #else
90 #define SCSI_NCR_DFLT_SYNC (250000 / SCSI_NCR_MAX_SYNC)
91 #endif
92
93 #endif
94
95 /*
96 ** The minimal asynchronous pre-scaler period (ns)
97 ** Shall be 40.
98 */
99
100 #ifndef SCSI_NCR_MIN_ASYNC
101 #define SCSI_NCR_MIN_ASYNC (40)
102 #endif /* SCSI_NCR_MIN_ASYNC */
103
104 /*
105 ** The maximal bus with (in log2 byte)
106 ** (0=8 bit, 1=16 bit)
107 */
108
109 #ifndef SCSI_NCR_MAX_WIDE
110 #define SCSI_NCR_MAX_WIDE (1)
111 #endif /* SCSI_NCR_MAX_WIDE */
112
113 /*==========================================================
114 **
115 ** Configuration and Debugging
116 **
117 **==========================================================
118 */
119
120 /*
121 ** Number of targets supported by the driver.
122 ** n permits target numbers 0..n-1.
123 ** Default is 7, meaning targets #0..#6.
124 ** #7 .. is myself.
125 */
126
127 #define MAX_TARGET (16)
128
129 /*
130 ** Number of logic units supported by the driver.
131 ** n enables logic unit numbers 0..n-1.
132 ** The common SCSI devices require only
133 ** one lun, so take 1 as the default.
134 */
135
136 #ifndef MAX_LUN
137 #define MAX_LUN (8)
138 #endif /* MAX_LUN */
139
140 /*
141 ** The maximum number of jobs scheduled for starting.
142 ** There should be one slot per target, and one slot
143 ** for each tag of each target in use.
144 */
145
146 #define MAX_START (256)
147
148 /*
149 ** The maximum number of segments a transfer is split into.
150 */
151
152 #define MAX_SCATTER (33)
153
154 /*
155 ** The maximum transfer length (should be >= 64k).
156 ** MUST NOT be greater than (MAX_SCATTER-1) * PAGE_SIZE.
157 */
158
159 #define MAX_SIZE ((MAX_SCATTER-1) * (long) PAGE_SIZE)
160
161 /*
162 ** other
163 */
164
165 #define NCR_SNOOP_TIMEOUT (1000000)
166
167 /*==========================================================
168 **
169 ** Include files
170 **
171 **==========================================================
172 */
173
174 #include <sys/param.h>
175 #include <sys/time.h>
176
177 #ifdef _KERNEL
178 #include <sys/systm.h>
179 #include <sys/malloc.h>
180 #include <sys/buf.h>
181 #include <sys/kernel.h>
182 #include <sys/sysctl.h>
183 #include <sys/bus.h>
184 #include <sys/thread2.h>
185 #include <machine/clock.h>
186 #include <machine/md_var.h>
187 #include <sys/rman.h>
188 #include <vm/vm.h>
189 #include <vm/pmap.h>
190 #include <vm/vm_extern.h>
191 #endif
192
193 #include <bus/pci/pcivar.h>
194 #include <bus/pci/pcireg.h>
195 #include "ncrreg.h"
196
197 #include <bus/cam/cam.h>
198 #include <bus/cam/cam_ccb.h>
199 #include <bus/cam/cam_sim.h>
200 #include <bus/cam/cam_xpt_sim.h>
201 #include <bus/cam/cam_debug.h>
202
203 #include <bus/cam/scsi/scsi_all.h>
204 #include <bus/cam/scsi/scsi_message.h>
205
206 /*==========================================================
207 **
208 ** Debugging tags
209 **
210 **==========================================================
211 */
212
213 #define DEBUG_ALLOC (0x0001)
214 #define DEBUG_PHASE (0x0002)
215 #define DEBUG_POLL (0x0004)
216 #define DEBUG_QUEUE (0x0008)
217 #define DEBUG_RESULT (0x0010)
218 #define DEBUG_SCATTER (0x0020)
219 #define DEBUG_SCRIPT (0x0040)
220 #define DEBUG_TINY (0x0080)
221 #define DEBUG_TIMING (0x0100)
222 #define DEBUG_NEGO (0x0200)
223 #define DEBUG_TAGS (0x0400)
224 #define DEBUG_FREEZE (0x0800)
225 #define DEBUG_RESTART (0x1000)
226
227 /*
228 ** Enable/Disable debug messages.
229 ** Can be changed at runtime too.
230 */
231 #ifdef SCSI_NCR_DEBUG
232 #define DEBUG_FLAGS ncr_debug
233 #else /* SCSI_NCR_DEBUG */
234 #define SCSI_NCR_DEBUG 0
235 #define DEBUG_FLAGS 0
236 #endif /* SCSI_NCR_DEBUG */
237
238
239
240 /*==========================================================
241 **
242 ** assert ()
243 **
244 **==========================================================
245 **
246 ** modified copy from 386bsd:/usr/include/sys/assert.h
247 **
248 **----------------------------------------------------------
249 */
250
251 #ifdef DIAGNOSTIC
252 #define assert(expression) { \
253 if (!(expression)) { \
254 (void)printf("assertion \"%s\" failed: " \
255 "file \"%s\", line %d\n", \
256 #expression, __FILE__, __LINE__); \
257 Debugger(""); \
258 } \
259 }
260 #else
261 #define assert(expression) { \
262 if (!(expression)) { \
263 (void)printf("assertion \"%s\" failed: " \
264 "file \"%s\", line %d\n", \
265 #expression, __FILE__, __LINE__); \
266 } \
267 }
268 #endif
269
270 /*==========================================================
271 **
272 ** Access to the controller chip.
273 **
274 **==========================================================
275 */
276
277 #define INB(r) bus_space_read_1(np->bst, np->bsh, offsetof(struct ncr_reg, r))
278 #define INW(r) bus_space_read_2(np->bst, np->bsh, offsetof(struct ncr_reg, r))
279 #define INL(r) bus_space_read_4(np->bst, np->bsh, offsetof(struct ncr_reg, r))
280
281 #define OUTB(r, val) bus_space_write_1(np->bst, np->bsh, \
282 offsetof(struct ncr_reg, r), val)
283 #define OUTW(r, val) bus_space_write_2(np->bst, np->bsh, \
284 offsetof(struct ncr_reg, r), val)
285 #define OUTL(r, val) bus_space_write_4(np->bst, np->bsh, \
286 offsetof(struct ncr_reg, r), val)
287 #define OUTL_OFF(o, val) bus_space_write_4(np->bst, np->bsh, o, val)
288
289 #define INB_OFF(o) bus_space_read_1(np->bst, np->bsh, o)
290 #define INW_OFF(o) bus_space_read_2(np->bst, np->bsh, o)
291 #define INL_OFF(o) bus_space_read_4(np->bst, np->bsh, o)
292
293 #define READSCRIPT_OFF(base, off) \
294 (base ? *((volatile u_int32_t *)((volatile char *)base + (off))) : \
295 bus_space_read_4(np->bst2, np->bsh2, off))
296
297 #define WRITESCRIPT_OFF(base, off, val) \
298 do { \
299 if (base) \
300 *((volatile u_int32_t *) \
301 ((volatile char *)base + (off))) = (val); \
302 else \
303 bus_space_write_4(np->bst2, np->bsh2, off, val); \
304 } while (0)
305
306 #define READSCRIPT(r) \
307 READSCRIPT_OFF(np->script, offsetof(struct script, r))
308
309 #define WRITESCRIPT(r, val) \
310 WRITESCRIPT_OFF(np->script, offsetof(struct script, r), val)
311
312 /*
313 ** Set bit field ON, OFF
314 */
315
316 #define OUTONB(r, m) OUTB(r, INB(r) | (m))
317 #define OUTOFFB(r, m) OUTB(r, INB(r) & ~(m))
318 #define OUTONW(r, m) OUTW(r, INW(r) | (m))
319 #define OUTOFFW(r, m) OUTW(r, INW(r) & ~(m))
320 #define OUTONL(r, m) OUTL(r, INL(r) | (m))
321 #define OUTOFFL(r, m) OUTL(r, INL(r) & ~(m))
322
323 /*==========================================================
324 **
325 ** Command control block states.
326 **
327 **==========================================================
328 */
329
330 #define HS_IDLE (0)
331 #define HS_BUSY (1)
332 #define HS_NEGOTIATE (2) /* sync/wide data transfer*/
333 #define HS_DISCONNECT (3) /* Disconnected by target */
334
335 #define HS_COMPLETE (4)
336 #define HS_SEL_TIMEOUT (5) /* Selection timeout */
337 #define HS_RESET (6) /* SCSI reset */
338 #define HS_ABORTED (7) /* Transfer aborted */
339 #define HS_TIMEOUT (8) /* Software timeout */
340 #define HS_FAIL (9) /* SCSI or PCI bus errors */
341 #define HS_UNEXPECTED (10) /* Unexpected disconnect */
342 #define HS_STALL (11) /* QUEUE FULL or BUSY */
343
344 #define HS_DONEMASK (0xfc)
345
346 /*==========================================================
347 **
348 ** Software Interrupt Codes
349 **
350 **==========================================================
351 */
352
353 #define SIR_SENSE_RESTART (1)
354 #define SIR_SENSE_FAILED (2)
355 #define SIR_STALL_RESTART (3)
356 #define SIR_STALL_QUEUE (4)
357 #define SIR_NEGO_SYNC (5)
358 #define SIR_NEGO_WIDE (6)
359 #define SIR_NEGO_FAILED (7)
360 #define SIR_NEGO_PROTO (8)
361 #define SIR_REJECT_RECEIVED (9)
362 #define SIR_REJECT_SENT (10)
363 #define SIR_IGN_RESIDUE (11)
364 #define SIR_MISSING_SAVE (12)
365 #define SIR_MAX (12)
366
367 /*==========================================================
368 **
369 ** Extended error codes.
370 ** xerr_status field of struct nccb.
371 **
372 **==========================================================
373 */
374
375 #define XE_OK (0)
376 #define XE_EXTRA_DATA (1) /* unexpected data phase */
377 #define XE_BAD_PHASE (2) /* illegal phase (4/5) */
378
379 /*==========================================================
380 **
381 ** Negotiation status.
382 ** nego_status field of struct nccb.
383 **
384 **==========================================================
385 */
386
387 #define NS_SYNC (1)
388 #define NS_WIDE (2)
389
390 /*==========================================================
391 **
392 ** XXX These are no longer used. Remove once the
393 ** script is updated.
394 ** "Special features" of targets.
395 ** quirks field of struct tcb.
396 ** actualquirks field of struct nccb.
397 **
398 **==========================================================
399 */
400
401 #define QUIRK_AUTOSAVE (0x01)
402 #define QUIRK_NOMSG (0x02)
403 #define QUIRK_NOSYNC (0x10)
404 #define QUIRK_NOWIDE16 (0x20)
405 #define QUIRK_NOTAGS (0x40)
406 #define QUIRK_UPDATE (0x80)
407
408 /*==========================================================
409 **
410 ** Misc.
411 **
412 **==========================================================
413 */
414
415 #define CCB_MAGIC (0xf2691ad2)
416 #define MAX_TAGS (32) /* hard limit */
417
418 /*==========================================================
419 **
420 ** OS dependencies.
421 **
422 **==========================================================
423 */
424
425 #define PRINT_ADDR(ccb) xpt_print_path((ccb)->ccb_h.path)
426
427 /*==========================================================
428 **
429 ** Declaration of structs.
430 **
431 **==========================================================
432 */
433
434 struct tcb;
435 struct lcb;
436 struct nccb;
437 struct ncb;
438 struct script;
439
440 typedef struct ncb * ncb_p;
441 typedef struct tcb * tcb_p;
442 typedef struct lcb * lcb_p;
443 typedef struct nccb * nccb_p;
444
445 struct link {
446 ncrcmd l_cmd;
447 ncrcmd l_paddr;
448 };
449
450 struct usrcmd {
451 u_long target;
452 u_long lun;
453 u_long data;
454 u_long cmd;
455 };
456
457 #define UC_SETSYNC 10
458 #define UC_SETTAGS 11
459 #define UC_SETDEBUG 12
460 #define UC_SETORDER 13
461 #define UC_SETWIDE 14
462 #define UC_SETFLAG 15
463
464 #define UF_TRACE (0x01)
465
466 /*---------------------------------------
467 **
468 ** Timestamps for profiling
469 **
470 **---------------------------------------
471 */
472
473 /* Type of the kernel variable `ticks'. XXX should be declared with the var. */
474 typedef int ticks_t;
475
476 struct tstamp {
477 ticks_t start;
478 ticks_t end;
479 ticks_t select;
480 ticks_t command;
481 ticks_t data;
482 ticks_t status;
483 ticks_t disconnect;
484 };
485
486 /*
487 ** profiling data (per device)
488 */
489
490 struct profile {
491 u_long num_trans;
492 u_long num_bytes;
493 u_long num_disc;
494 u_long num_break;
495 u_long num_int;
496 u_long num_fly;
497 u_long ms_setup;
498 u_long ms_data;
499 u_long ms_disc;
500 u_long ms_post;
501 };
502
503 /*==========================================================
504 **
505 ** Declaration of structs: target control block
506 **
507 **==========================================================
508 */
509
510 #define NCR_TRANS_CUR 0x01 /* Modify current neogtiation status */
511 #define NCR_TRANS_ACTIVE 0x03 /* Assume this is the active target */
512 #define NCR_TRANS_GOAL 0x04 /* Modify negotiation goal */
513 #define NCR_TRANS_USER 0x08 /* Modify user negotiation settings */
514
515 struct ncr_transinfo {
516 u_int8_t width;
517 u_int8_t period;
518 u_int8_t offset;
519 };
520
521 struct ncr_target_tinfo {
522 /* Hardware version of our sync settings */
523 u_int8_t disc_tag;
524 #define NCR_CUR_DISCENB 0x01
525 #define NCR_CUR_TAGENB 0x02
526 #define NCR_USR_DISCENB 0x04
527 #define NCR_USR_TAGENB 0x08
528 u_int8_t sval;
529 struct ncr_transinfo current;
530 struct ncr_transinfo goal;
531 struct ncr_transinfo user;
532 /* Hardware version of our wide settings */
533 u_int8_t wval;
534 };
535
536 struct tcb {
537 /*
538 ** during reselection the ncr jumps to this point
539 ** with SFBR set to the encoded target number
540 ** with bit 7 set.
541 ** if it's not this target, jump to the next.
542 **
543 ** JUMP IF (SFBR != #target#)
544 ** @(next tcb)
545 */
546
547 struct link jump_tcb;
548
549 /*
550 ** load the actual values for the sxfer and the scntl3
551 ** register (sync/wide mode).
552 **
553 ** SCR_COPY (1);
554 ** @(sval field of this tcb)
555 ** @(sxfer register)
556 ** SCR_COPY (1);
557 ** @(wval field of this tcb)
558 ** @(scntl3 register)
559 */
560
561 ncrcmd getscr[6];
562
563 /*
564 ** if next message is "identify"
565 ** then load the message to SFBR,
566 ** else load 0 to SFBR.
567 **
568 ** CALL
569 ** <RESEL_LUN>
570 */
571
572 struct link call_lun;
573
574 /*
575 ** now look for the right lun.
576 **
577 ** JUMP
578 ** @(first nccb of this lun)
579 */
580
581 struct link jump_lcb;
582
583 /*
584 ** pointer to interrupted getcc nccb
585 */
586
587 nccb_p hold_cp;
588
589 /*
590 ** pointer to nccb used for negotiating.
591 ** Avoid to start a nego for all queued commands
592 ** when tagged command queuing is enabled.
593 */
594
595 nccb_p nego_cp;
596
597 /*
598 ** statistical data
599 */
600
601 u_long transfers;
602 u_long bytes;
603
604 /*
605 ** user settable limits for sync transfer
606 ** and tagged commands.
607 */
608
609 struct ncr_target_tinfo tinfo;
610
611 /*
612 ** the lcb's of this tcb
613 */
614
615 lcb_p lp[MAX_LUN];
616 };
617
618 /*==========================================================
619 **
620 ** Declaration of structs: lun control block
621 **
622 **==========================================================
623 */
624
625 struct lcb {
626 /*
627 ** during reselection the ncr jumps to this point
628 ** with SFBR set to the "Identify" message.
629 ** if it's not this lun, jump to the next.
630 **
631 ** JUMP IF (SFBR != #lun#)
632 ** @(next lcb of this target)
633 */
634
635 struct link jump_lcb;
636
637 /*
638 ** if next message is "simple tag",
639 ** then load the tag to SFBR,
640 ** else load 0 to SFBR.
641 **
642 ** CALL
643 ** <RESEL_TAG>
644 */
645
646 struct link call_tag;
647
648 /*
649 ** now look for the right nccb.
650 **
651 ** JUMP
652 ** @(first nccb of this lun)
653 */
654
655 struct link jump_nccb;
656
657 /*
658 ** start of the nccb chain
659 */
660
661 nccb_p next_nccb;
662
663 /*
664 ** Control of tagged queueing
665 */
666
667 u_char reqnccbs;
668 u_char reqlink;
669 u_char actlink;
670 u_char usetags;
671 u_char lasttag;
672 };
673
674 /*==========================================================
675 **
676 ** Declaration of structs: COMMAND control block
677 **
678 **==========================================================
679 **
680 ** This substructure is copied from the nccb to a
681 ** global address after selection (or reselection)
682 ** and copied back before disconnect.
683 **
684 ** These fields are accessible to the script processor.
685 **
686 **----------------------------------------------------------
687 */
688
689 struct head {
690 /*
691 ** Execution of a nccb starts at this point.
692 ** It's a jump to the "SELECT" label
693 ** of the script.
694 **
695 ** After successful selection the script
696 ** processor overwrites it with a jump to
697 ** the IDLE label of the script.
698 */
699
700 struct link launch;
701
702 /*
703 ** Saved data pointer.
704 ** Points to the position in the script
705 ** responsible for the actual transfer
706 ** of data.
707 ** It's written after reception of a
708 ** "SAVE_DATA_POINTER" message.
709 ** The goalpointer points after
710 ** the last transfer command.
711 */
712
713 u_int32_t savep;
714 u_int32_t lastp;
715 u_int32_t goalp;
716
717 /*
718 ** The virtual address of the nccb
719 ** containing this header.
720 */
721
722 nccb_p cp;
723
724 /*
725 ** space for some timestamps to gather
726 ** profiling data about devices and this driver.
727 */
728
729 struct tstamp stamp;
730
731 /*
732 ** status fields.
733 */
734
735 u_char status[8];
736 };
737
738 /*
739 ** The status bytes are used by the host and the script processor.
740 **
741 ** The first four byte are copied to the scratchb register
742 ** (declared as scr0..scr3 in ncr_reg.h) just after the select/reselect,
743 ** and copied back just after disconnecting.
744 ** Inside the script the XX_REG are used.
745 **
746 ** The last four bytes are used inside the script by "COPY" commands.
747 ** Because source and destination must have the same alignment
748 ** in a longword, the fields HAVE to be at the choosen offsets.
749 ** xerr_st (4) 0 (0x34) scratcha
750 ** sync_st (5) 1 (0x05) sxfer
751 ** wide_st (7) 3 (0x03) scntl3
752 */
753
754 /*
755 ** First four bytes (script)
756 */
757 #define QU_REG scr0
758 #define HS_REG scr1
759 #define HS_PRT nc_scr1
760 #define SS_REG scr2
761 #define PS_REG scr3
762
763 /*
764 ** First four bytes (host)
765 */
766 #define actualquirks phys.header.status[0]
767 #define host_status phys.header.status[1]
768 #define s_status phys.header.status[2]
769 #define parity_status phys.header.status[3]
770
771 /*
772 ** Last four bytes (script)
773 */
774 #define xerr_st header.status[4] /* MUST be ==0 mod 4 */
775 #define sync_st header.status[5] /* MUST be ==1 mod 4 */
776 #define nego_st header.status[6]
777 #define wide_st header.status[7] /* MUST be ==3 mod 4 */
778
779 /*
780 ** Last four bytes (host)
781 */
782 #define xerr_status phys.xerr_st
783 #define sync_status phys.sync_st
784 #define nego_status phys.nego_st
785 #define wide_status phys.wide_st
786
787 /*==========================================================
788 **
789 ** Declaration of structs: Data structure block
790 **
791 **==========================================================
792 **
793 ** During execution of a nccb by the script processor,
794 ** the DSA (data structure address) register points
795 ** to this substructure of the nccb.
796 ** This substructure contains the header with
797 ** the script-processor-changable data and
798 ** data blocks for the indirect move commands.
799 **
800 **----------------------------------------------------------
801 */
802
803 struct dsb {
804
805 /*
806 ** Header.
807 ** Has to be the first entry,
808 ** because it's jumped to by the
809 ** script processor
810 */
811
812 struct head header;
813
814 /*
815 ** Table data for Script
816 */
817
818 struct scr_tblsel select;
819 struct scr_tblmove smsg ;
820 struct scr_tblmove smsg2 ;
821 struct scr_tblmove cmd ;
822 struct scr_tblmove scmd ;
823 struct scr_tblmove sense ;
824 struct scr_tblmove data [MAX_SCATTER];
825 };
826
827 /*==========================================================
828 **
829 ** Declaration of structs: Command control block.
830 **
831 **==========================================================
832 **
833 ** During execution of a nccb by the script processor,
834 ** the DSA (data structure address) register points
835 ** to this substructure of the nccb.
836 ** This substructure contains the header with
837 ** the script-processor-changable data and then
838 ** data blocks for the indirect move commands.
839 **
840 **----------------------------------------------------------
841 */
842
843
844 struct nccb {
845 /*
846 ** This filler ensures that the global header is
847 ** cache line size aligned.
848 */
849 ncrcmd filler[4];
850
851 /*
852 ** during reselection the ncr jumps to this point.
853 ** If a "SIMPLE_TAG" message was received,
854 ** then SFBR is set to the tag.
855 ** else SFBR is set to 0
856 ** If looking for another tag, jump to the next nccb.
857 **
858 ** JUMP IF (SFBR != #TAG#)
859 ** @(next nccb of this lun)
860 */
861
862 struct link jump_nccb;
863
864 /*
865 ** After execution of this call, the return address
866 ** (in the TEMP register) points to the following
867 ** data structure block.
868 ** So copy it to the DSA register, and start
869 ** processing of this data structure.
870 **
871 ** CALL
872 ** <RESEL_TMP>
873 */
874
875 struct link call_tmp;
876
877 /*
878 ** This is the data structure which is
879 ** to be executed by the script processor.
880 */
881
882 struct dsb phys;
883
884 /*
885 ** If a data transfer phase is terminated too early
886 ** (after reception of a message (i.e. DISCONNECT)),
887 ** we have to prepare a mini script to transfer
888 ** the rest of the data.
889 */
890
891 ncrcmd patch[8];
892
893 /*
894 ** The general SCSI driver provides a
895 ** pointer to a control block.
896 */
897
898 union ccb *ccb;
899
900 /*
901 ** We prepare a message to be sent after selection,
902 ** and a second one to be sent after getcc selection.
903 ** Contents are IDENTIFY and SIMPLE_TAG.
904 ** While negotiating sync or wide transfer,
905 ** a SDTM or WDTM message is appended.
906 */
907
908 u_char scsi_smsg [8];
909 u_char scsi_smsg2[8];
910
911 /*
912 ** Lock this nccb.
913 ** Flag is used while looking for a free nccb.
914 */
915
916 u_long magic;
917
918 /*
919 ** Physical address of this instance of nccb
920 */
921
922 u_long p_nccb;
923
924 /*
925 ** Completion time out for this job.
926 ** It's set to time of start + allowed number of seconds.
927 */
928
929 time_t tlimit;
930
931 /*
932 ** All nccbs of one hostadapter are chained.
933 */
934
935 nccb_p link_nccb;
936
937 /*
938 ** All nccbs of one target/lun are chained.
939 */
940
941 nccb_p next_nccb;
942
943 /*
944 ** Sense command
945 */
946
947 u_char sensecmd[6];
948
949 /*
950 ** Tag for this transfer.
951 ** It's patched into jump_nccb.
952 ** If it's not zero, a SIMPLE_TAG
953 ** message is included in smsg.
954 */
955
956 u_char tag;
957 };
958
959 #define CCB_PHYS(cp,lbl) (cp->p_nccb + offsetof(struct nccb, lbl))
960
961 /*==========================================================
962 **
963 ** Declaration of structs: NCR device descriptor
964 **
965 **==========================================================
966 */
967
968 struct ncb {
969 /*
970 ** The global header.
971 ** Accessible to both the host and the
972 ** script-processor.
973 ** We assume it is cache line size aligned.
974 */
975 struct head header;
976
977 int unit;
978
979 /*-----------------------------------------------
980 ** Scripts ..
981 **-----------------------------------------------
982 **
983 ** During reselection the ncr jumps to this point.
984 ** The SFBR register is loaded with the encoded target id.
985 **
986 ** Jump to the first target.
987 **
988 ** JUMP
989 ** @(next tcb)
990 */
991 struct link jump_tcb;
992
993 /*-----------------------------------------------
994 ** Configuration ..
995 **-----------------------------------------------
996 **
997 ** virtual and physical addresses
998 ** of the 53c810 chip.
999 */
1000 int reg_rid;
1001 struct resource *reg_res;
1002 bus_space_tag_t bst;
1003 bus_space_handle_t bsh;
1004
1005 int sram_rid;
1006 struct resource *sram_res;
1007 bus_space_tag_t bst2;
1008 bus_space_handle_t bsh2;
1009
1010 struct resource *irq_res;
1011 void *irq_handle;
1012
1013 /*
1014 ** Scripts instance virtual address.
1015 */
1016 struct script *script;
1017 struct scripth *scripth;
1018
1019 /*
1020 ** Scripts instance physical address.
1021 */
1022 u_long p_script;
1023 u_long p_scripth;
1024
1025 /*
1026 ** The SCSI address of the host adapter.
1027 */
1028 u_char myaddr;
1029
1030 /*
1031 ** timing parameters
1032 */
1033 u_char minsync; /* Minimum sync period factor */
1034 u_char maxsync; /* Maximum sync period factor */
1035 u_char maxoffs; /* Max scsi offset */
1036 u_char clock_divn; /* Number of clock divisors */
1037 u_long clock_khz; /* SCSI clock frequency in KHz */
1038 u_long features; /* Chip features map */
1039 u_char multiplier; /* Clock multiplier (1,2,4) */
1040
1041 u_char maxburst; /* log base 2 of dwords burst */
1042
1043 /*
1044 ** BIOS supplied PCI bus options
1045 */
1046 u_char rv_scntl3;
1047 u_char rv_dcntl;
1048 u_char rv_dmode;
1049 u_char rv_ctest3;
1050 u_char rv_ctest4;
1051 u_char rv_ctest5;
1052 u_char rv_gpcntl;
1053 u_char rv_stest2;
1054
1055 /*-----------------------------------------------
1056 ** CAM SIM information for this instance
1057 **-----------------------------------------------
1058 */
1059
1060 struct cam_sim *sim;
1061 struct cam_path *path;
1062
1063 /*-----------------------------------------------
1064 ** Job control
1065 **-----------------------------------------------
1066 **
1067 ** Commands from user
1068 */
1069 struct usrcmd user;
1070
1071 /*
1072 ** Target data
1073 */
1074 struct tcb target[MAX_TARGET];
1075
1076 /*
1077 ** Start queue.
1078 */
1079 u_int32_t squeue [MAX_START];
1080 u_short squeueput;
1081
1082 /*
1083 ** Timeout handler
1084 */
1085 time_t heartbeat;
1086 u_short ticks;
1087 u_short latetime;
1088 time_t lasttime;
1089 struct callout timeout_ch;
1090
1091 /*-----------------------------------------------
1092 ** Debug and profiling
1093 **-----------------------------------------------
1094 **
1095 ** register dump
1096 */
1097 struct ncr_reg regdump;
1098 time_t regtime;
1099
1100 /*
1101 ** Profiling data
1102 */
1103 struct profile profile;
1104 u_long disc_phys;
1105 u_long disc_ref;
1106
1107 /*
1108 ** Head of list of all nccbs for this controller.
1109 */
1110 nccb_p link_nccb;
1111
1112 /*
1113 ** message buffers.
1114 ** Should be longword aligned,
1115 ** because they're written with a
1116 ** COPY script command.
1117 */
1118 u_char msgout[8];
1119 u_char msgin [8];
1120 u_int32_t lastmsg;
1121
1122 /*
1123 ** Buffer for STATUS_IN phase.
1124 */
1125 u_char scratch;
1126
1127 /*
1128 ** controller chip dependent maximal transfer width.
1129 */
1130 u_char maxwide;
1131
1132 #ifdef NCR_IOMAPPED
1133 /*
1134 ** address of the ncr control registers in io space
1135 */
1136 pci_port_t port;
1137 #endif
1138 };
1139
1140 #define NCB_SCRIPT_PHYS(np,lbl) (np->p_script + offsetof (struct script, lbl))
1141 #define NCB_SCRIPTH_PHYS(np,lbl) (np->p_scripth + offsetof (struct scripth,lbl))
1142
1143 /*==========================================================
1144 **
1145 **
1146 ** Script for NCR-Processor.
1147 **
1148 ** Use ncr_script_fill() to create the variable parts.
1149 ** Use ncr_script_copy_and_bind() to make a copy and
1150 ** bind to physical addresses.
1151 **
1152 **
1153 **==========================================================
1154 **
1155 ** We have to know the offsets of all labels before
1156 ** we reach them (for forward jumps).
1157 ** Therefore we declare a struct here.
1158 ** If you make changes inside the script,
1159 ** DONT FORGET TO CHANGE THE LENGTHS HERE!
1160 **
1161 **----------------------------------------------------------
1162 */
1163
1164 /*
1165 ** Script fragments which are loaded into the on-board RAM
1166 ** of 825A, 875 and 895 chips.
1167 */
1168 struct script {
1169 ncrcmd start [ 7];
1170 ncrcmd start0 [ 2];
1171 ncrcmd start1 [ 3];
1172 ncrcmd startpos [ 1];
1173 ncrcmd trysel [ 8];
1174 ncrcmd skip [ 8];
1175 ncrcmd skip2 [ 3];
1176 ncrcmd idle [ 2];
1177 ncrcmd select [ 18];
1178 ncrcmd prepare [ 4];
1179 ncrcmd loadpos [ 14];
1180 ncrcmd prepare2 [ 24];
1181 ncrcmd setmsg [ 5];
1182 ncrcmd clrack [ 2];
1183 ncrcmd dispatch [ 33];
1184 ncrcmd no_data [ 17];
1185 ncrcmd checkatn [ 10];
1186 ncrcmd command [ 15];
1187 ncrcmd status [ 27];
1188 ncrcmd msg_in [ 26];
1189 ncrcmd msg_bad [ 6];
1190 ncrcmd complete [ 13];
1191 ncrcmd cleanup [ 12];
1192 ncrcmd cleanup0 [ 9];
1193 ncrcmd signal [ 12];
1194 ncrcmd save_dp [ 5];
1195 ncrcmd restore_dp [ 5];
1196 ncrcmd disconnect [ 12];
1197 ncrcmd disconnect0 [ 5];
1198 ncrcmd disconnect1 [ 23];
1199 ncrcmd msg_out [ 9];
1200 ncrcmd msg_out_done [ 7];
1201 ncrcmd badgetcc [ 6];
1202 ncrcmd reselect [ 8];
1203 ncrcmd reselect1 [ 8];
1204 ncrcmd reselect2 [ 8];
1205 ncrcmd resel_tmp [ 5];
1206 ncrcmd resel_lun [ 18];
1207 ncrcmd resel_tag [ 24];
1208 ncrcmd data_in [MAX_SCATTER * 4 + 7];
1209 ncrcmd data_out [MAX_SCATTER * 4 + 7];
1210 };
1211
1212 /*
1213 ** Script fragments which stay in main memory for all chips.
1214 */
1215 struct scripth {
1216 ncrcmd tryloop [MAX_START*5+2];
1217 ncrcmd msg_parity [ 6];
1218 ncrcmd msg_reject [ 8];
1219 ncrcmd msg_ign_residue [ 32];
1220 ncrcmd msg_extended [ 18];
1221 ncrcmd msg_ext_2 [ 18];
1222 ncrcmd msg_wdtr [ 27];
1223 ncrcmd msg_ext_3 [ 18];
1224 ncrcmd msg_sdtr [ 27];
1225 ncrcmd msg_out_abort [ 10];
1226 ncrcmd getcc [ 4];
1227 ncrcmd getcc1 [ 5];
1228 #ifdef NCR_GETCC_WITHMSG
1229 ncrcmd getcc2 [ 29];
1230 #else
1231 ncrcmd getcc2 [ 14];
1232 #endif
1233 ncrcmd getcc3 [ 6];
1234 ncrcmd aborttag [ 4];
1235 ncrcmd abort [ 22];
1236 ncrcmd snooptest [ 9];
1237 ncrcmd snoopend [ 2];
1238 };
1239
1240 /*==========================================================
1241 **
1242 **
1243 ** Function headers.
1244 **
1245 **
1246 **==========================================================
1247 */
1248
1249 #ifdef _KERNEL
1250 static nccb_p ncr_alloc_nccb (ncb_p np, u_long target, u_long lun);
1251 static void ncr_complete (ncb_p np, nccb_p cp);
1252 static int ncr_delta (int * from, int * to);
1253 static void ncr_exception (ncb_p np);
1254 static void ncr_free_nccb (ncb_p np, nccb_p cp);
1255 static void ncr_freeze_devq (ncb_p np, struct cam_path *path);
1256 static void ncr_selectclock (ncb_p np, u_char scntl3);
1257 static void ncr_getclock (ncb_p np, u_char multiplier);
1258 static nccb_p ncr_get_nccb (ncb_p np, u_long t,u_long l);
1259 #if 0
1260 static u_int32_t ncr_info (int unit);
1261 #endif
1262 static void ncr_init (ncb_p np, char * msg, u_long code);
1263 static void ncr_intr (void *vnp);
1264 static void ncr_int_ma (ncb_p np, u_char dstat);
1265 static void ncr_int_sir (ncb_p np);
1266 static void ncr_int_sto (ncb_p np);
1267 #if 0
1268 static void ncr_min_phys (struct buf *bp);
1269 #endif
1270 static void ncr_poll (struct cam_sim *sim);
1271 static void ncb_profile (ncb_p np, nccb_p cp);
1272 static void ncr_script_copy_and_bind
1273 (ncb_p np, ncrcmd *src, ncrcmd *dst, int len);
1274 static void ncr_script_fill (struct script * scr, struct scripth *scrh);
1275 static int ncr_scatter (struct dsb* phys, vm_offset_t vaddr,
1276 vm_size_t datalen);
1277 static void ncr_getsync (ncb_p np, u_char sfac, u_char *fakp,
1278 u_char *scntl3p);
1279 static void ncr_setsync (ncb_p np, nccb_p cp,u_char scntl3,u_char sxfer,
1280 u_char period);
1281 static void ncr_setwide (ncb_p np, nccb_p cp, u_char wide, u_char ack);
1282 static int ncr_show_msg (u_char * msg);
1283 static int ncr_snooptest (ncb_p np);
1284 static void ncr_action (struct cam_sim *sim, union ccb *ccb);
1285 static void ncr_timeout (void *arg);
1286 static void ncr_wakeup (ncb_p np, u_long code);
1287
1288 static int ncr_probe (device_t dev);
1289 static int ncr_attach (device_t dev);
1290
1291 #endif /* _KERNEL */
1292
1293 /*==========================================================
1294 **
1295 **
1296 ** Global static data.
1297 **
1298 **
1299 **==========================================================
1300 */
1301
1302
1303 /*
1304 * $FreeBSD: src/sys/pci/ncr.c,v 1.155.2.3 2001/03/05 13:09:10 obrien Exp $
1305 */
1306 static const u_long ncr_version = NCR_VERSION * 11
1307 + (u_long) sizeof (struct ncb) * 7
1308 + (u_long) sizeof (struct nccb) * 5
1309 + (u_long) sizeof (struct lcb) * 3
1310 + (u_long) sizeof (struct tcb) * 2;
1311
1312 #ifdef _KERNEL
1313
1314 static int ncr_debug = SCSI_NCR_DEBUG;
1315 SYSCTL_INT(_debug, OID_AUTO, ncr_debug, CTLFLAG_RW, &ncr_debug, 0, "");
1316
1317 static int ncr_cache; /* to be aligned _NOT_ static */
1318
1319 /*==========================================================
1320 **
1321 **
1322 ** Global static data: auto configure
1323 **
1324 **
1325 **==========================================================
1326 */
1327
1328 #define NCR_810_ID (0x00011000ul)
1329 #define NCR_815_ID (0x00041000ul)
1330 #define NCR_820_ID (0x00021000ul)
1331 #define NCR_825_ID (0x00031000ul)
1332 #define NCR_860_ID (0x00061000ul)
1333 #define NCR_875_ID (0x000f1000ul)
1334 #define NCR_875_ID2 (0x008f1000ul)
1335 #define NCR_885_ID (0x000d1000ul)
1336 #define NCR_895_ID (0x000c1000ul)
1337 #define NCR_896_ID (0x000b1000ul)
1338 #define NCR_895A_ID (0x00121000ul)
1339 #define NCR_1510D_ID (0x000a1000ul)
1340
1341
1342 static char *ncr_name (ncb_p np)
1343 {
1344 static char name[10];
1345 ksnprintf(name, sizeof(name), "ncr%d", np->unit);
1346 return (name);
1347 }
1348
1349 /*==========================================================
1350 **
1351 **
1352 ** Scripts for NCR-Processor.
1353 **
1354 ** Use ncr_script_bind for binding to physical addresses.
1355 **
1356 **
1357 **==========================================================
1358 **
1359 ** NADDR generates a reference to a field of the controller data.
1360 ** PADDR generates a reference to another part of the script.
1361 ** RADDR generates a reference to a script processor register.
1362 ** FADDR generates a reference to a script processor register
1363 ** with offset.
1364 **
1365 **----------------------------------------------------------
1366 */
1367
1368 #define RELOC_SOFTC 0x40000000
1369 #define RELOC_LABEL 0x50000000
1370 #define RELOC_REGISTER 0x60000000
1371 #define RELOC_KVAR 0x70000000
1372 #define RELOC_LABELH 0x80000000
1373 #define RELOC_MASK 0xf0000000
1374
1375 #define NADDR(label) (RELOC_SOFTC | offsetof(struct ncb, label))
1376 #define PADDR(label) (RELOC_LABEL | offsetof(struct script, label))
1377 #define PADDRH(label) (RELOC_LABELH | offsetof(struct scripth, label))
1378 #define RADDR(label) (RELOC_REGISTER | REG(label))
1379 #define FADDR(label,ofs)(RELOC_REGISTER | ((REG(label))+(ofs)))
1380 #define KVAR(which) (RELOC_KVAR | (which))
1381
1382 #define KVAR_SECOND (0)
1383 #define KVAR_TICKS (1)
1384 #define KVAR_NCR_CACHE (2)
1385
1386 #define SCRIPT_KVAR_FIRST (0)
1387 #define SCRIPT_KVAR_LAST (3)
1388
1389 /*
1390 * Kernel variables referenced in the scripts.
1391 * THESE MUST ALL BE ALIGNED TO A 4-BYTE BOUNDARY.
1392 */
1393 static void *script_kvars[] =
1394 { &time_second, &ticks, &ncr_cache };
1395
1396 static struct script script0 = {
1397 /*--------------------------< START >-----------------------*/ {
1398 /*
1399 ** Claim to be still alive ...
1400 */
1401 SCR_COPY (sizeof (((struct ncb *)0)->heartbeat)),
1402 KVAR (KVAR_SECOND),
1403 NADDR (heartbeat),
1404 /*
1405 ** Make data structure address invalid.
1406 ** clear SIGP.
1407 */
1408 SCR_LOAD_REG (dsa, 0xff),
1409 0,
1410 SCR_FROM_REG (ctest2),
1411 0,
1412 }/*-------------------------< START0 >----------------------*/,{
1413 /*
1414 ** Hook for interrupted GetConditionCode.
1415 ** Will be patched to ... IFTRUE by
1416 ** the interrupt handler.
1417 */
1418 SCR_INT ^ IFFALSE (0),
1419 SIR_SENSE_RESTART,
1420
1421 }/*-------------------------< START1 >----------------------*/,{
1422 /*
1423 ** Hook for stalled start queue.
1424 ** Will be patched to IFTRUE by the interrupt handler.
1425 */
1426 SCR_INT ^ IFFALSE (0),
1427 SIR_STALL_RESTART,
1428 /*
1429 ** Then jump to a certain point in tryloop.
1430 ** Due to the lack of indirect addressing the code
1431 ** is self modifying here.
1432 */
1433 SCR_JUMP,
1434 }/*-------------------------< STARTPOS >--------------------*/,{
1435 PADDRH(tryloop),
1436
1437 }/*-------------------------< TRYSEL >----------------------*/,{
1438 /*
1439 ** Now:
1440 ** DSA: Address of a Data Structure
1441 ** or Address of the IDLE-Label.
1442 **
1443 ** TEMP: Address of a script, which tries to
1444 ** start the NEXT entry.
1445 **
1446 ** Save the TEMP register into the SCRATCHA register.
1447 ** Then copy the DSA to TEMP and RETURN.
1448 ** This is kind of an indirect jump.
1449 ** (The script processor has NO stack, so the
1450 ** CALL is actually a jump and link, and the
1451 ** RETURN is an indirect jump.)
1452 **
1453 ** If the slot was empty, DSA contains the address
1454 ** of the IDLE part of this script. The processor
1455 ** jumps to IDLE and waits for a reselect.
1456 ** It will wake up and try the same slot again
1457 ** after the SIGP bit becomes set by the host.
1458 **
1459 ** If the slot was not empty, DSA contains
1460 ** the address of the phys-part of a nccb.
1461 ** The processor jumps to this address.
1462 ** phys starts with head,
1463 ** head starts with launch,
1464 ** so actually the processor jumps to
1465 ** the lauch part.
1466 ** If the entry is scheduled for execution,
1467 ** then launch contains a jump to SELECT.
1468 ** If it's not scheduled, it contains a jump to IDLE.
1469 */
1470 SCR_COPY (4),
1471 RADDR (temp),
1472 RADDR (scratcha),
1473 SCR_COPY (4),
1474 RADDR (dsa),
1475 RADDR (temp),
1476 SCR_RETURN,
1477 0
1478
1479 }/*-------------------------< SKIP >------------------------*/,{
1480 /*
1481 ** This entry has been canceled.
1482 ** Next time use the next slot.
1483 */
1484 SCR_COPY (4),
1485 RADDR (scratcha),
1486 PADDR (startpos),
1487 /*
1488 ** patch the launch field.
1489 ** should look like an idle process.
1490 */
1491 SCR_COPY_F (4),
1492 RADDR (dsa),
1493 PADDR (skip2),
1494 SCR_COPY (8),
1495 PADDR (idle),
1496 }/*-------------------------< SKIP2 >-----------------------*/,{
1497 0,
1498 SCR_JUMP,
1499 PADDR(start),
1500 }/*-------------------------< IDLE >------------------------*/,{
1501 /*
1502 ** Nothing to do?
1503 ** Wait for reselect.
1504 */
1505 SCR_JUMP,
1506 PADDR(reselect),
1507
1508 }/*-------------------------< SELECT >----------------------*/,{
1509 /*
1510 ** DSA contains the address of a scheduled
1511 ** data structure.
1512 **
1513 ** SCRATCHA contains the address of the script,
1514 ** which starts the next entry.
1515 **
1516 ** Set Initiator mode.
1517 **
1518 ** (Target mode is left as an exercise for the reader)
1519 */
1520
1521 SCR_CLR (SCR_TRG),
1522 0,
1523 SCR_LOAD_REG (HS_REG, 0xff),
1524 0,
1525
1526 /*
1527 ** And try to select this target.
1528 */
1529 SCR_SEL_TBL_ATN ^ offsetof (struct dsb, select),
1530 PADDR (reselect),
1531
1532 /*
1533 ** Now there are 4 possibilities:
1534 **
1535 ** (1) The ncr looses arbitration.
1536 ** This is ok, because it will try again,
1537 ** when the bus becomes idle.
1538 ** (But beware of the timeout function!)
1539 **
1540 ** (2) The ncr is reselected.
1541 ** Then the script processor takes the jump
1542 ** to the RESELECT label.
1543 **
1544 ** (3) The ncr completes the selection.
1545 ** Then it will execute the next statement.
1546 **
1547 ** (4) There is a selection timeout.
1548 ** Then the ncr should interrupt the host and stop.
1549 ** Unfortunately, it seems to continue execution
1550 ** of the script. But it will fail with an
1551 ** IID-interrupt on the next WHEN.
1552 */
1553
1554 SCR_JUMPR ^ IFTRUE (WHEN (SCR_MSG_IN)),
1555 0,
1556
1557 /*
1558 ** Send the IDENTIFY and SIMPLE_TAG messages
1559 ** (and the MSG_EXT_SDTR message)
1560 */
1561 SCR_MOVE_TBL ^ SCR_MSG_OUT,
1562 offsetof (struct dsb, smsg),
1563 #ifdef undef /* XXX better fail than try to deal with this ... */
1564 SCR_JUMPR ^ IFTRUE (WHEN (SCR_MSG_OUT)),
1565 -16,
1566 #endif
1567 SCR_CLR (SCR_ATN),
1568 0,
1569 SCR_COPY (1),
1570 RADDR (sfbr),
1571 NADDR (lastmsg),
1572 /*
1573 ** Selection complete.
1574 ** Next time use the next slot.
1575 */
1576 SCR_COPY (4),
1577 RADDR (scratcha),
1578 PADDR (startpos),
1579 }/*-------------------------< PREPARE >----------------------*/,{
1580 /*
1581 ** The ncr doesn't have an indirect load
1582 ** or store command. So we have to
1583 ** copy part of the control block to a
1584 ** fixed place, where we can access it.
1585 **
1586 ** We patch the address part of a
1587 ** COPY command with the DSA-register.
1588 */
1589 SCR_COPY_F (4),
1590 RADDR (dsa),
1591 PADDR (loadpos),
1592 /*
1593 ** then we do the actual copy.
1594 */
1595 SCR_COPY (sizeof (struct head)),
1596 /*
1597 ** continued after the next label ...
1598 */
1599
1600 }/*-------------------------< LOADPOS >---------------------*/,{
1601 0,
1602 NADDR (header),
1603 /*
1604 ** Mark this nccb as not scheduled.
1605 */
1606 SCR_COPY (8),
1607 PADDR (idle),
1608 NADDR (header.launch),
1609 /*
1610 ** Set a time stamp for this selection
1611 */
1612 SCR_COPY (sizeof (ticks)),
1613 KVAR (KVAR_TICKS),
1614 NADDR (header.stamp.select),
1615 /*
1616 ** load the savep (saved pointer) into
1617 ** the TEMP register (actual pointer)
1618 */
1619 SCR_COPY (4),
1620 NADDR (header.savep),
1621 RADDR (temp),
1622 /*
1623 ** Initialize the status registers
1624 */
1625 SCR_COPY (4),
1626 NADDR (header.status),
1627 RADDR (scr0),
1628
1629 }/*-------------------------< PREPARE2 >---------------------*/,{
1630 /*
1631 ** Load the synchronous mode register
1632 */
1633 SCR_COPY (1),
1634 NADDR (sync_st),
1635 RADDR (sxfer),
1636 /*
1637 ** Load the wide mode and timing register
1638 */
1639 SCR_COPY (1),
1640 NADDR (wide_st),
1641 RADDR (scntl3),
1642 /*
1643 ** Initialize the msgout buffer with a NOOP message.
1644 */
1645 SCR_LOAD_REG (scratcha, MSG_NOOP),
1646 0,
1647 SCR_COPY (1),
1648 RADDR (scratcha),
1649 NADDR (msgout),
1650 SCR_COPY (1),
1651 RADDR (scratcha),
1652 NADDR (msgin),
1653 /*
1654 ** Message in phase ?
1655 */
1656 SCR_JUMP ^ IFFALSE (WHEN (SCR_MSG_IN)),
1657 PADDR (dispatch),
1658 /*
1659 ** Extended or reject message ?
1660 */
1661 SCR_FROM_REG (sbdl),
1662 0,
1663 SCR_JUMP ^ IFTRUE (DATA (MSG_EXTENDED)),
1664 PADDR (msg_in),
1665 SCR_JUMP ^ IFTRUE (DATA (MSG_MESSAGE_REJECT)),
1666 PADDRH (msg_reject),
1667 /*
1668 ** normal processing
1669 */
1670 SCR_JUMP,
1671 PADDR (dispatch),
1672 }/*-------------------------< SETMSG >----------------------*/,{
1673 SCR_COPY (1),
1674 RADDR (scratcha),
1675 NADDR (msgout),
1676 SCR_SET (SCR_ATN),
1677 0,
1678 }/*-------------------------< CLRACK >----------------------*/,{
1679 /*
1680 ** Terminate possible pending message phase.
1681 */
1682 SCR_CLR (SCR_ACK),
1683 0,
1684
1685 }/*-----------------------< DISPATCH >----------------------*/,{
1686 SCR_FROM_REG (HS_REG),
1687 0,
1688 SCR_INT ^ IFTRUE (DATA (HS_NEGOTIATE)),
1689 SIR_NEGO_FAILED,
1690 /*
1691 ** remove bogus output signals
1692 */
1693 SCR_REG_REG (socl, SCR_AND, CACK|CATN),
1694 0,
1695 SCR_RETURN ^ IFTRUE (WHEN (SCR_DATA_OUT)),
1696 0,
1697 SCR_RETURN ^ IFTRUE (IF (SCR_DATA_IN)),
1698 0,
1699 SCR_JUMP ^ IFTRUE (IF (SCR_MSG_OUT)),
1700 PADDR (msg_out),
1701 SCR_JUMP ^ IFTRUE (IF (SCR_MSG_IN)),
1702 PADDR (msg_in),
1703 SCR_JUMP ^ IFTRUE (IF (SCR_COMMAND)),
1704 PADDR (command),
1705 SCR_JUMP ^ IFTRUE (IF (SCR_STATUS)),
1706 PADDR (status),
1707 /*
1708 ** Discard one illegal phase byte, if required.
1709 */
1710 SCR_LOAD_REG (scratcha, XE_BAD_PHASE),
1711 0,
1712 SCR_COPY (1),
1713 RADDR (scratcha),
1714 NADDR (xerr_st),
1715 SCR_JUMPR ^ IFFALSE (IF (SCR_ILG_OUT)),
1716 8,
1717 SCR_MOVE_ABS (1) ^ SCR_ILG_OUT,
1718 NADDR (scratch),
1719 SCR_JUMPR ^ IFFALSE (IF (SCR_ILG_IN)),
1720 8,
1721 SCR_MOVE_ABS (1) ^ SCR_ILG_IN,
1722 NADDR (scratch),
1723 SCR_JUMP,
1724 PADDR (dispatch),
1725
1726 }/*-------------------------< NO_DATA >--------------------*/,{
1727 /*
1728 ** The target wants to tranfer too much data
1729 ** or in the wrong direction.
1730 ** Remember that in extended error.
1731 */
1732 SCR_LOAD_REG (scratcha, XE_EXTRA_DATA),
1733 0,
1734 SCR_COPY (1),
1735 RADDR (scratcha),
1736 NADDR (xerr_st),
1737 /*
1738 ** Discard one data byte, if required.
1739 */
1740 SCR_JUMPR ^ IFFALSE (WHEN (SCR_DATA_OUT)),
1741 8,
1742 SCR_MOVE_ABS (1) ^ SCR_DATA_OUT,
1743 NADDR (scratch),
1744 SCR_JUMPR ^ IFFALSE (IF (SCR_DATA_IN)),
1745 8,
1746 SCR_MOVE_ABS (1) ^ SCR_DATA_IN,
1747 NADDR (scratch),
1748 /*
1749 ** .. and repeat as required.
1750 */
1751 SCR_CALL,
1752 PADDR (dispatch),
1753 SCR_JUMP,
1754 PADDR (no_data),
1755 }/*-------------------------< CHECKATN >--------------------*/,{
1756 /*
1757 ** If AAP (bit 1 of scntl0 register) is set
1758 ** and a parity error is detected,
1759 ** the script processor asserts ATN.
1760 **
1761 ** The target should switch to a MSG_OUT phase
1762 ** to get the message.
1763 */
1764 SCR_FROM_REG (socl),
1765 0,
1766 SCR_JUMP ^ IFFALSE (MASK (CATN, CATN)),
1767 PADDR (dispatch),
1768 /*
1769 ** count it
1770 */
1771 SCR_REG_REG (PS_REG, SCR_ADD, 1),
1772 0,
1773 /*
1774 ** Prepare a MSG_INITIATOR_DET_ERR message
1775 ** (initiator detected error).
1776 ** The target should retry the transfer.
1777 */
1778 SCR_LOAD_REG (scratcha, MSG_INITIATOR_DET_ERR),
1779 0,
1780 SCR_JUMP,
1781 PADDR (setmsg),
1782
1783 }/*-------------------------< COMMAND >--------------------*/,{
1784 /*
1785 ** If this is not a GETCC transfer ...
1786 */
1787 SCR_FROM_REG (SS_REG),
1788 0,
1789 /*<<<*/ SCR_JUMPR ^ IFTRUE (DATA (SCSI_STATUS_CHECK_COND)),
1790 28,
1791 /*
1792 ** ... set a timestamp ...
1793 */
1794 SCR_COPY (sizeof (ticks)),
1795 KVAR (KVAR_TICKS),
1796 NADDR (header.stamp.command),
1797 /*
1798 ** ... and send the command
1799 */
1800 SCR_MOVE_TBL ^ SCR_COMMAND,
1801 offsetof (struct dsb, cmd),
1802 SCR_JUMP,
1803 PADDR (dispatch),
1804 /*
1805 ** Send the GETCC command
1806 */
1807 /*>>>*/ SCR_MOVE_TBL ^ SCR_COMMAND,
1808 offsetof (struct dsb, scmd),
1809 SCR_JUMP,
1810 PADDR (dispatch),
1811
1812 }/*-------------------------< STATUS >--------------------*/,{
1813 /*
1814 ** set the timestamp.
1815 */
1816 SCR_COPY (sizeof (ticks)),
1817 KVAR (KVAR_TICKS),
1818 NADDR (header.stamp.status),
1819 /*
1820 ** If this is a GETCC transfer,
1821 */
1822 SCR_FROM_REG (SS_REG),
1823 0,
1824 /*<<<*/ SCR_JUMPR ^ IFFALSE (DATA (SCSI_STATUS_CHECK_COND)),
1825 40,
1826 /*
1827 ** get the status
1828 */
1829 SCR_MOVE_ABS (1) ^ SCR_STATUS,
1830 NADDR (scratch),
1831 /*
1832 ** Save status to scsi_status.
1833 ** Mark as complete.
1834 ** And wait for disconnect.
1835 */
1836 SCR_TO_REG (SS_REG),
1837 0,
1838 SCR_REG_REG (SS_REG, SCR_OR, SCSI_STATUS_SENSE),
1839 0,
1840 SCR_LOAD_REG (HS_REG, HS_COMPLETE),
1841 0,
1842 SCR_JUMP,
1843 PADDR (checkatn),
1844 /*
1845 ** If it was no GETCC transfer,
1846 ** save the status to scsi_status.
1847 */
1848 /*>>>*/ SCR_MOVE_ABS (1) ^ SCR_STATUS,
1849 NADDR (scratch),
1850 SCR_TO_REG (SS_REG),
1851 0,
1852 /*
1853 ** if it was no check condition ...
1854 */
1855 SCR_JUMP ^ IFTRUE (DATA (SCSI_STATUS_CHECK_COND)),
1856 PADDR (checkatn),
1857 /*
1858 ** ... mark as complete.
1859 */
1860 SCR_LOAD_REG (HS_REG, HS_COMPLETE),
1861 0,
1862 SCR_JUMP,
1863 PADDR (checkatn),
1864
1865 }/*-------------------------< MSG_IN >--------------------*/,{
1866 /*
1867 ** Get the first byte of the message
1868 ** and save it to SCRATCHA.
1869 **
1870 ** The script processor doesn't negate the
1871 ** ACK signal after this transfer.
1872 */
1873 SCR_MOVE_ABS (1) ^ SCR_MSG_IN,
1874 NADDR (msgin[0]),
1875 /*
1876 ** Check for message parity error.
1877 */
1878 SCR_TO_REG (scratcha),
1879 0,
1880 SCR_FROM_REG (socl),
1881 0,
1882 SCR_JUMP ^ IFTRUE (MASK (CATN, CATN)),
1883 PADDRH (msg_parity),
1884 SCR_FROM_REG (scratcha),
1885 0,
1886 /*
1887 ** Parity was ok, handle this message.
1888 */
1889 SCR_JUMP ^ IFTRUE (DATA (MSG_CMDCOMPLETE)),
1890 PADDR (complete),
1891 SCR_JUMP ^ IFTRUE (DATA (MSG_SAVEDATAPOINTER)),
1892 PADDR (save_dp),
1893 SCR_JUMP ^ IFTRUE (DATA (MSG_RESTOREPOINTERS)),
1894 PADDR (restore_dp),
1895 SCR_JUMP ^ IFTRUE (DATA (MSG_DISCONNECT)),
1896 PADDR (disconnect),
1897 SCR_JUMP ^ IFTRUE (DATA (MSG_EXTENDED)),
1898 PADDRH (msg_extended),
1899 SCR_JUMP ^ IFTRUE (DATA (MSG_NOOP)),
1900 PADDR (clrack),
1901 SCR_JUMP ^ IFTRUE (DATA (MSG_MESSAGE_REJECT)),
1902 PADDRH (msg_reject),
1903 SCR_JUMP ^ IFTRUE (DATA (MSG_IGN_WIDE_RESIDUE)),
1904 PADDRH (msg_ign_residue),
1905 /*
1906 ** Rest of the messages left as
1907 ** an exercise ...
1908 **
1909 ** Unimplemented messages:
1910 ** fall through to MSG_BAD.
1911 */
1912 }/*-------------------------< MSG_BAD >------------------*/,{
1913 /*
1914 ** unimplemented message - reject it.
1915 */
1916 SCR_INT,
1917 SIR_REJECT_SENT,
1918 SCR_LOAD_REG (scratcha, MSG_MESSAGE_REJECT),
1919 0,
1920 SCR_JUMP,
1921 PADDR (setmsg),
1922
1923 }/*-------------------------< COMPLETE >-----------------*/,{
1924 /*
1925 ** Complete message.
1926 **
1927 ** If it's not the get condition code,
1928 ** copy TEMP register to LASTP in header.
1929 */
1930 SCR_FROM_REG (SS_REG),
1931 0,
1932 /*<<<*/ SCR_JUMPR ^ IFTRUE (MASK (SCSI_STATUS_SENSE, SCSI_STATUS_SENSE)),
1933 12,
1934 SCR_COPY (4),
1935 RADDR (temp),
1936 NADDR (header.lastp),
1937 /*>>>*/ /*
1938 ** When we terminate the cycle by clearing ACK,
1939 ** the target may disconnect immediately.
1940 **
1941 ** We don't want to be told of an
1942 ** "unexpected disconnect",
1943 ** so we disable this feature.
1944 */
1945 SCR_REG_REG (scntl2, SCR_AND, 0x7f),
1946 0,
1947 /*
1948 ** Terminate cycle ...
1949 */
1950 SCR_CLR (SCR_ACK|SCR_ATN),
1951 0,
1952 /*
1953 ** ... and wait for the disconnect.
1954 */
1955 SCR_WAIT_DISC,
1956 0,
1957 }/*-------------------------< CLEANUP >-------------------*/,{
1958 /*
1959 ** dsa: Pointer to nccb
1960 ** or xxxxxxFF (no nccb)
1961 **
1962 ** HS_REG: Host-Status (<>0!)
1963 */
1964 SCR_FROM_REG (dsa),
1965 0,
1966 SCR_JUMP ^ IFTRUE (DATA (0xff)),
1967 PADDR (signal),
1968 /*
1969 ** dsa is valid.
1970 ** save the status registers
1971 */
1972 SCR_COPY (4),
1973 RADDR (scr0),
1974 NADDR (header.status),
1975 /*
1976 ** and copy back the header to the nccb.
1977 */
1978 SCR_COPY_F (4),
1979 RADDR (dsa),
1980 PADDR (cleanup0),
1981 SCR_COPY (sizeof (struct head)),
1982 NADDR (header),
1983 }/*-------------------------< CLEANUP0 >--------------------*/,{
1984 0,
1985
1986 /*
1987 ** If command resulted in "check condition"
1988 ** status and is not yet completed,
1989 ** try to get the condition code.
1990 */
1991 SCR_FROM_REG (HS_REG),
1992 0,
1993 /*<<<*/ SCR_JUMPR ^ IFFALSE (MASK (0, HS_DONEMASK)),
1994 16,
1995 SCR_FROM_REG (SS_REG),
1996 0,
1997 SCR_JUMP ^ IFTRUE (DATA (SCSI_STATUS_CHECK_COND)),
1998 PADDRH(getcc2),
1999 }/*-------------------------< SIGNAL >----------------------*/,{
2000 /*
2001 ** if status = queue full,
2002 ** reinsert in startqueue and stall queue.
2003 */
2004 /*>>>*/ SCR_FROM_REG (SS_REG),
2005 0,
2006 SCR_INT ^ IFTRUE (DATA (SCSI_STATUS_QUEUE_FULL)),
2007 SIR_STALL_QUEUE,
2008 /*
2009 ** And make the DSA register invalid.
2010 */
2011 SCR_LOAD_REG (dsa, 0xff), /* invalid */
2012 0,
2013 /*
2014 ** if job completed ...
2015 */
2016 SCR_FROM_REG (HS_REG),
2017 0,
2018 /*
2019 ** ... signal completion to the host
2020 */
2021 SCR_INT_FLY ^ IFFALSE (MASK (0, HS_DONEMASK)),
2022 0,
2023 /*
2024 ** Auf zu neuen Schandtaten!
2025 */
2026 SCR_JUMP,
2027 PADDR(start),
2028
2029 }/*-------------------------< SAVE_DP >------------------*/,{
2030 /*
2031 ** SAVE_DP message:
2032 ** Copy TEMP register to SAVEP in header.
2033 */
2034 SCR_COPY (4),
2035 RADDR (temp),
2036 NADDR (header.savep),
2037 SCR_JUMP,
2038 PADDR (clrack),
2039 }/*-------------------------< RESTORE_DP >---------------*/,{
2040 /*
2041 ** RESTORE_DP message:
2042 ** Copy SAVEP in header to TEMP register.
2043 */
2044 SCR_COPY (4),
2045 NADDR (header.savep),
2046 RADDR (temp),
2047 SCR_JUMP,
2048 PADDR (clrack),
2049
2050 }/*-------------------------< DISCONNECT >---------------*/,{
2051 /*
2052 ** If QUIRK_AUTOSAVE is set,
2053 ** do an "save pointer" operation.
2054 */
2055 SCR_FROM_REG (QU_REG),
2056 0,
2057 /*<<<*/ SCR_JUMPR ^ IFFALSE (MASK (QUIRK_AUTOSAVE, QUIRK_AUTOSAVE)),
2058 12,
2059 /*
2060 ** like SAVE_DP message:
2061 ** Copy TEMP register to SAVEP in header.
2062 */
2063 SCR_COPY (4),
2064 RADDR (temp),
2065 NADDR (header.savep),
2066 /*>>>*/ /*
2067 ** Check if temp==savep or temp==goalp:
2068 ** if not, log a missing save pointer message.
2069 ** In fact, it's a comparison mod 256.
2070 **
2071 ** Hmmm, I hadn't thought that I would be urged to
2072 ** write this kind of ugly self modifying code.
2073 **
2074 ** It's unbelievable, but the ncr53c8xx isn't able
2075 ** to subtract one register from another.
2076 */
2077 SCR_FROM_REG (temp),
2078 0,
2079 /*
2080 ** You are not expected to understand this ..
2081 **
2082 ** CAUTION: only little endian architectures supported! XXX
2083 */
2084 SCR_COPY_F (1),
2085 NADDR (header.savep),
2086 PADDR (disconnect0),
2087 }/*-------------------------< DISCONNECT0 >--------------*/,{
2088 /*<<<*/ SCR_JUMPR ^ IFTRUE (DATA (1)),
2089 20,
2090 /*
2091 ** neither this
2092 */
2093 SCR_COPY_F (1),
2094 NADDR (header.goalp),
2095 PADDR (disconnect1),
2096 }/*-------------------------< DISCONNECT1 >--------------*/,{
2097 SCR_INT ^ IFFALSE (DATA (1)),
2098 SIR_MISSING_SAVE,
2099 /*>>>*/
2100
2101 /*
2102 ** DISCONNECTing ...
2103 **
2104 ** disable the "unexpected disconnect" feature,
2105 ** and remove the ACK signal.
2106 */
2107 SCR_REG_REG (scntl2, SCR_AND, 0x7f),
2108 0,
2109 SCR_CLR (SCR_ACK|SCR_ATN),
2110 0,
2111 /*
2112 ** Wait for the disconnect.
2113 */
2114 SCR_WAIT_DISC,
2115 0,
2116 /*
2117 ** Profiling:
2118 ** Set a time stamp,
2119 ** and count the disconnects.
2120 */
2121 SCR_COPY (sizeof (ticks)),
2122 KVAR (KVAR_TICKS),
2123 NADDR (header.stamp.disconnect),
2124 SCR_COPY (4),
2125 NADDR (disc_phys),
2126 RADDR (temp),
2127 SCR_REG_REG (temp, SCR_ADD, 0x01),
2128 0,
2129 SCR_COPY (4),
2130 RADDR (temp),
2131 NADDR (disc_phys),
2132 /*
2133 ** Status is: DISCONNECTED.
2134 */
2135 SCR_LOAD_REG (HS_REG, HS_DISCONNECT),
2136 0,
2137 SCR_JUMP,
2138 PADDR (cleanup),
2139
2140 }/*-------------------------< MSG_OUT >-------------------*/,{
2141 /*
2142 ** The target requests a message.
2143 */
2144 SCR_MOVE_ABS (1) ^ SCR_MSG_OUT,
2145 NADDR (msgout),
2146 SCR_COPY (1),
2147 RADDR (sfbr),
2148 NADDR (lastmsg),
2149 /*
2150 ** If it was no ABORT message ...
2151 */
2152 SCR_JUMP ^ IFTRUE (DATA (MSG_ABORT)),
2153 PADDRH (msg_out_abort),
2154 /*
2155 ** ... wait for the next phase
2156 ** if it's a message out, send it again, ...
2157 */
2158 SCR_JUMP ^ IFTRUE (WHEN (SCR_MSG_OUT)),
2159 PADDR (msg_out),
2160 }/*-------------------------< MSG_OUT_DONE >--------------*/,{
2161 /*
2162 ** ... else clear the message ...
2163 */
2164 SCR_LOAD_REG (scratcha, MSG_NOOP),
2165 0,
2166 SCR_COPY (4),
2167 RADDR (scratcha),
2168 NADDR (msgout),
2169 /*
2170 ** ... and process the next phase
2171 */
2172 SCR_JUMP,
2173 PADDR (dispatch),
2174
2175 }/*------------------------< BADGETCC >---------------------*/,{
2176 /*
2177 ** If SIGP was set, clear it and try again.
2178 */
2179 SCR_FROM_REG (ctest2),
2180 0,
2181 SCR_JUMP ^ IFTRUE (MASK (CSIGP,CSIGP)),
2182 PADDRH (getcc2),
2183 SCR_INT,
2184 SIR_SENSE_FAILED,
2185 }/*-------------------------< RESELECT >--------------------*/,{
2186 /*
2187 ** This NOP will be patched with LED OFF
2188 ** SCR_REG_REG (gpreg, SCR_OR, 0x01)
2189 */
2190 SCR_NO_OP,
2191 0,
2192
2193 /*
2194 ** make the DSA invalid.
2195 */
2196 SCR_LOAD_REG (dsa, 0xff),
2197 0,
2198 SCR_CLR (SCR_TRG),
2199 0,
2200 /*
2201 ** Sleep waiting for a reselection.
2202 ** If SIGP is set, special treatment.
2203 **
2204 ** Zu allem bereit ..
2205 */
2206 SCR_WAIT_RESEL,
2207 PADDR(reselect2),
2208 }/*-------------------------< RESELECT1 >--------------------*/,{
2209 /*
2210 ** This NOP will be patched with LED ON
2211 ** SCR_REG_REG (gpreg, SCR_AND, 0xfe)
2212 */
2213 SCR_NO_OP,
2214 0,
2215 /*
2216 ** ... zu nichts zu gebrauchen ?
2217 **
2218 ** load the target id into the SFBR
2219 ** and jump to the control block.
2220 **
2221 ** Look at the declarations of
2222 ** - struct ncb
2223 ** - struct tcb
2224 ** - struct lcb
2225 ** - struct nccb
2226 ** to understand what's going on.
2227 */
2228 SCR_REG_SFBR (ssid, SCR_AND, 0x8F),
2229 0,
2230 SCR_TO_REG (sdid),
2231 0,
2232 SCR_JUMP,
2233 NADDR (jump_tcb),
2234 }/*-------------------------< RESELECT2 >-------------------*/,{
2235 /*
2236 ** This NOP will be patched with LED ON
2237 ** SCR_REG_REG (gpreg, SCR_AND, 0xfe)
2238 */
2239 SCR_NO_OP,
2240 0,
2241 /*
2242 ** If it's not connected :(
2243 ** -> interrupted by SIGP bit.
2244 ** Jump to start.
2245 */
2246 SCR_FROM_REG (ctest2),
2247 0,
2248 SCR_JUMP ^ IFTRUE (MASK (CSIGP,CSIGP)),
2249 PADDR (start),
2250 SCR_JUMP,
2251 PADDR (reselect),
2252
2253 }/*-------------------------< RESEL_TMP >-------------------*/,{
2254 /*
2255 ** The return address in TEMP
2256 ** is in fact the data structure address,
2257 ** so copy it to the DSA register.
2258 */
2259 SCR_COPY (4),
2260 RADDR (temp),
2261 RADDR (dsa),
2262 SCR_JUMP,
2263 PADDR (prepare),
2264
2265 }/*-------------------------< RESEL_LUN >-------------------*/,{
2266 /*
2267 ** come back to this point
2268 ** to get an IDENTIFY message
2269 ** Wait for a msg_in phase.
2270 */
2271 /*<<<*/ SCR_JUMPR ^ IFFALSE (WHEN (SCR_MSG_IN)),
2272 48,
2273 /*
2274 ** message phase
2275 ** It's not a sony, it's a trick:
2276 ** read the data without acknowledging it.
2277 */
2278 SCR_FROM_REG (sbdl),
2279 0,
2280 /*<<<*/ SCR_JUMPR ^ IFFALSE (MASK (MSG_IDENTIFYFLAG, 0x98)),
2281 32,
2282 /*
2283 ** It WAS an Identify message.
2284 ** get it and ack it!
2285 */
2286 SCR_MOVE_ABS (1) ^ SCR_MSG_IN,
2287 NADDR (msgin),
2288 SCR_CLR (SCR_ACK),
2289 0,
2290 /*
2291 ** Mask out the lun.
2292 */
2293 SCR_REG_REG (sfbr, SCR_AND, 0x07),
2294 0,
2295 SCR_RETURN,
2296 0,
2297 /*
2298 ** No message phase or no IDENTIFY message:
2299 ** return 0.
2300 */
2301 /*>>>*/ SCR_LOAD_SFBR (0),
2302 0,
2303 SCR_RETURN,
2304 0,
2305
2306 }/*-------------------------< RESEL_TAG >-------------------*/,{
2307 /*
2308 ** come back to this point
2309 ** to get a SIMPLE_TAG message
2310 ** Wait for a MSG_IN phase.
2311 */
2312 /*<<<*/ SCR_JUMPR ^ IFFALSE (WHEN (SCR_MSG_IN)),
2313 64,
2314 /*
2315 ** message phase
2316 ** It's a trick - read the data
2317 ** without acknowledging it.
2318 */
2319 SCR_FROM_REG (sbdl),
2320 0,
2321 /*<<<*/ SCR_JUMPR ^ IFFALSE (DATA (MSG_SIMPLE_Q_TAG)),
2322 48,
2323 /*
2324 ** It WAS a SIMPLE_TAG message.
2325 ** get it and ack it!
2326 */
2327 SCR_MOVE_ABS (1) ^ SCR_MSG_IN,
2328 NADDR (msgin),
2329 SCR_CLR (SCR_ACK),
2330 0,
2331 /*
2332 ** Wait for the second byte (the tag)
2333 */
2334 /*<<<*/ SCR_JUMPR ^ IFFALSE (WHEN (SCR_MSG_IN)),
2335 24,
2336 /*
2337 ** Get it and ack it!
2338 */
2339 SCR_MOVE_ABS (1) ^ SCR_MSG_IN,
2340 NADDR (msgin),
2341 SCR_CLR (SCR_ACK|SCR_CARRY),
2342 0,
2343 SCR_RETURN,
2344 0,
2345 /*
2346 ** No message phase or no SIMPLE_TAG message
2347 ** or no second byte: return 0.
2348 */
2349 /*>>>*/ SCR_LOAD_SFBR (0),
2350 0,
2351 SCR_SET (SCR_CARRY),
2352 0,
2353 SCR_RETURN,
2354 0,
2355
2356 }/*-------------------------< DATA_IN >--------------------*/,{
2357 /*
2358 ** Because the size depends on the
2359 ** #define MAX_SCATTER parameter,
2360 ** it is filled in at runtime.
2361 **
2362 ** SCR_JUMP ^ IFFALSE (WHEN (SCR_DATA_IN)),
2363 ** PADDR (no_data),
2364 ** SCR_COPY (sizeof (ticks)),
2365 ** KVAR (KVAR_TICKS),
2366 ** NADDR (header.stamp.data),
2367 ** SCR_MOVE_TBL ^ SCR_DATA_IN,
2368 ** offsetof (struct dsb, data[ 0]),
2369 **
2370 ** ##===========< i=1; i<MAX_SCATTER >=========
2371 ** || SCR_CALL ^ IFFALSE (WHEN (SCR_DATA_IN)),
2372 ** || PADDR (checkatn),
2373 ** || SCR_MOVE_TBL ^ SCR_DATA_IN,
2374 ** || offsetof (struct dsb, data[ i]),
2375 ** ##==========================================
2376 **
2377 ** SCR_CALL,
2378 ** PADDR (checkatn),
2379 ** SCR_JUMP,
2380 ** PADDR (no_data),
2381 */
2382 0
2383 }/*-------------------------< DATA_OUT >-------------------*/,{
2384 /*
2385 ** Because the size depends on the
2386 ** #define MAX_SCATTER parameter,
2387 ** it is filled in at runtime.
2388 **
2389 ** SCR_JUMP ^ IFFALSE (WHEN (SCR_DATA_OUT)),
2390 ** PADDR (no_data),
2391 ** SCR_COPY (sizeof (ticks)),
2392 ** KVAR (KVAR_TICKS),
2393 ** NADDR (header.stamp.data),
2394 ** SCR_MOVE_TBL ^ SCR_DATA_OUT,
2395 ** offsetof (struct dsb, data[ 0]),
2396 **
2397 ** ##===========< i=1; i<MAX_SCATTER >=========
2398 ** || SCR_CALL ^ IFFALSE (WHEN (SCR_DATA_OUT)),
2399 ** || PADDR (dispatch),
2400 ** || SCR_MOVE_TBL ^ SCR_DATA_OUT,
2401 ** || offsetof (struct dsb, data[ i]),
2402 ** ##==========================================
2403 **
2404 ** SCR_CALL,
2405 ** PADDR (dispatch),
2406 ** SCR_JUMP,
2407 ** PADDR (no_data),
2408 **
2409 **---------------------------------------------------------
2410 */
2411 (u_long)0
2412
2413 }/*--------------------------------------------------------*/
2414 };
2415
2416
2417 static struct scripth scripth0 = {
2418 /*-------------------------< TRYLOOP >---------------------*/{
2419 /*
2420 ** Load an entry of the start queue into dsa
2421 ** and try to start it by jumping to TRYSEL.
2422 **
2423 ** Because the size depends on the
2424 ** #define MAX_START parameter, it is filled
2425 ** in at runtime.
2426 **
2427 **-----------------------------------------------------------
2428 **
2429 ** ##===========< I=0; i<MAX_START >===========
2430 ** || SCR_COPY (4),
2431 ** || NADDR (squeue[i]),
2432 ** || RADDR (dsa),
2433 ** || SCR_CALL,
2434 ** || PADDR (trysel),
2435 ** ##==========================================
2436 **
2437 ** SCR_JUMP,
2438 ** PADDRH(tryloop),
2439 **
2440 **-----------------------------------------------------------
2441 */
2442 0
2443 }/*-------------------------< MSG_PARITY >---------------*/,{
2444 /*
2445 ** count it
2446 */
2447 SCR_REG_REG (PS_REG, SCR_ADD, 0x01),
2448 0,
2449 /*
2450 ** send a "message parity error" message.
2451 */
2452 SCR_LOAD_REG (scratcha, MSG_PARITY_ERROR),
2453 0,
2454 SCR_JUMP,
2455 PADDR (setmsg),
2456 }/*-------------------------< MSG_MESSAGE_REJECT >---------------*/,{
2457 /*
2458 ** If a negotiation was in progress,
2459 ** negotiation failed.
2460 */
2461 SCR_FROM_REG (HS_REG),
2462 0,
2463 SCR_INT ^ IFTRUE (DATA (HS_NEGOTIATE)),
2464 SIR_NEGO_FAILED,
2465 /*
2466 ** else make host log this message
2467 */
2468 SCR_INT ^ IFFALSE (DATA (HS_NEGOTIATE)),
2469 SIR_REJECT_RECEIVED,
2470 SCR_JUMP,
2471 PADDR (clrack),
2472
2473 }/*-------------------------< MSG_IGN_RESIDUE >----------*/,{
2474 /*
2475 ** Terminate cycle
2476 */
2477 SCR_CLR (SCR_ACK),
2478 0,
2479 SCR_JUMP ^ IFFALSE (WHEN (SCR_MSG_IN)),
2480 PADDR (dispatch),
2481 /*
2482 ** get residue size.
2483 */
2484 SCR_MOVE_ABS (1) ^ SCR_MSG_IN,
2485 NADDR (msgin[1]),
2486 /*
2487 ** Check for message parity error.
2488 */
2489 SCR_TO_REG (scratcha),
2490 0,
2491 SCR_FROM_REG (socl),
2492 0,
2493 SCR_JUMP ^ IFTRUE (MASK (CATN, CATN)),
2494 PADDRH (msg_parity),
2495 SCR_FROM_REG (scratcha),
2496 0,
2497 /*
2498 ** Size is 0 .. ignore message.
2499 */
2500 SCR_JUMP ^ IFTRUE (DATA (0)),
2501 PADDR (clrack),
2502 /*
2503 ** Size is not 1 .. have to interrupt.
2504 */
2505 /*<<<*/ SCR_JUMPR ^ IFFALSE (DATA (1)),
2506 40,
2507 /*
2508 ** Check for residue byte in swide register
2509 */
2510 SCR_FROM_REG (scntl2),
2511 0,
2512 /*<<<*/ SCR_JUMPR ^ IFFALSE (MASK (WSR, WSR)),
2513 16,
2514 /*
2515 ** There IS data in the swide register.
2516 ** Discard it.
2517 */
2518 SCR_REG_REG (scntl2, SCR_OR, WSR),
2519 0,
2520 SCR_JUMP,
2521 PADDR (clrack),
2522 /*
2523 ** Load again the size to the sfbr register.
2524 */
2525 /*>>>*/ SCR_FROM_REG (scratcha),
2526 0,
2527 /*>>>*/ SCR_INT,
2528 SIR_IGN_RESIDUE,
2529 SCR_JUMP,
2530 PADDR (clrack),
2531
2532 }/*-------------------------< MSG_EXTENDED >-------------*/,{
2533 /*
2534 ** Terminate cycle
2535 */
2536 SCR_CLR (SCR_ACK),
2537 0,
2538 SCR_JUMP ^ IFFALSE (WHEN (SCR_MSG_IN)),
2539 PADDR (dispatch),
2540 /*
2541 ** get length.
2542 */
2543 SCR_MOVE_ABS (1) ^ SCR_MSG_IN,
2544 NADDR (msgin[1]),
2545 /*
2546 ** Check for message parity error.
2547 */
2548 SCR_TO_REG (scratcha),
2549 0,
2550 SCR_FROM_REG (socl),
2551 0,
2552 SCR_JUMP ^ IFTRUE (MASK (CATN, CATN)),
2553 PADDRH (msg_parity),
2554 SCR_FROM_REG (scratcha),
2555 0,
2556 /*
2557 */
2558 SCR_JUMP ^ IFTRUE (DATA (3)),
2559 PADDRH (msg_ext_3),
2560 SCR_JUMP ^ IFFALSE (DATA (2)),
2561 PADDR (msg_bad),
2562 }/*-------------------------< MSG_EXT_2 >----------------*/,{
2563 SCR_CLR (SCR_ACK),
2564 0,
2565 SCR_JUMP ^ IFFALSE (WHEN (SCR_MSG_IN)),
2566 PADDR (dispatch),
2567 /*
2568 ** get extended message code.
2569 */
2570 SCR_MOVE_ABS (1) ^ SCR_MSG_IN,
2571 NADDR (msgin[2]),
2572 /*
2573 ** Check for message parity error.
2574 */
2575 SCR_TO_REG (scratcha),
2576 0,
2577 SCR_FROM_REG (socl),
2578 0,
2579 SCR_JUMP ^ IFTRUE (MASK (CATN, CATN)),
2580 PADDRH (msg_parity),
2581 SCR_FROM_REG (scratcha),
2582 0,
2583 SCR_JUMP ^ IFTRUE (DATA (MSG_EXT_WDTR)),
2584 PADDRH (msg_wdtr),
2585 /*
2586 ** unknown extended message
2587 */
2588 SCR_JUMP,
2589 PADDR (msg_bad)
2590 }/*-------------------------< MSG_WDTR >-----------------*/,{
2591 SCR_CLR (SCR_ACK),
2592 0,
2593 SCR_JUMP ^ IFFALSE (WHEN (SCR_MSG_IN)),
2594 PADDR (dispatch),
2595 /*
2596 ** get data bus width
2597 */
2598 SCR_MOVE_ABS (1) ^ SCR_MSG_IN,
2599 NADDR (msgin[3]),
2600 SCR_FROM_REG (socl),
2601 0,
2602 SCR_JUMP ^ IFTRUE (MASK (CATN, CATN)),
2603 PADDRH (msg_parity),
2604 /*
2605 ** let the host do the real work.
2606 */
2607 SCR_INT,
2608 SIR_NEGO_WIDE,
2609 /*
2610 ** let the target fetch our answer.
2611 */
2612 SCR_SET (SCR_ATN),
2613 0,
2614 SCR_CLR (SCR_ACK),
2615 0,
2616
2617 SCR_INT ^ IFFALSE (WHEN (SCR_MSG_OUT)),
2618 SIR_NEGO_PROTO,
2619 /*
2620 ** Send the MSG_EXT_WDTR
2621 */
2622 SCR_MOVE_ABS (4) ^ SCR_MSG_OUT,
2623 NADDR (msgout),
2624 SCR_CLR (SCR_ATN),
2625 0,
2626 SCR_COPY (1),
2627 RADDR (sfbr),
2628 NADDR (lastmsg),
2629 SCR_JUMP,
2630 PADDR (msg_out_done),
2631
2632 }/*-------------------------< MSG_EXT_3 >----------------*/,{
2633 SCR_CLR (SCR_ACK),
2634 0,
2635 SCR_JUMP ^ IFFALSE (WHEN (SCR_MSG_IN)),
2636 PADDR (dispatch),
2637 /*
2638 ** get extended message code.
2639 */
2640 SCR_MOVE_ABS (1) ^ SCR_MSG_IN,
2641 NADDR (msgin[2]),
2642 /*
2643 ** Check for message parity error.
2644 */
2645 SCR_TO_REG (scratcha),
2646 0,
2647 SCR_FROM_REG (socl),
2648 0,
2649 SCR_JUMP ^ IFTRUE (MASK (CATN, CATN)),
2650 PADDRH (msg_parity),
2651 SCR_FROM_REG (scratcha),
2652 0,
2653 SCR_JUMP ^ IFTRUE (DATA (MSG_EXT_SDTR)),
2654 PADDRH (msg_sdtr),
2655 /*
2656 ** unknown extended message
2657 */
2658 SCR_JUMP,
2659 PADDR (msg_bad)
2660
2661 }/*-------------------------< MSG_SDTR >-----------------*/,{
2662 SCR_CLR (SCR_ACK),
2663 0,
2664 SCR_JUMP ^ IFFALSE (WHEN (SCR_MSG_IN)),
2665 PADDR (dispatch),
2666 /*
2667 ** get period and offset
2668 */
2669 SCR_MOVE_ABS (2) ^ SCR_MSG_IN,
2670 NADDR (msgin[3]),
2671 SCR_FROM_REG (socl),
2672 0,
2673 SCR_JUMP ^ IFTRUE (MASK (CATN, CATN)),
2674 PADDRH (msg_parity),
2675 /*
2676 ** let the host do the real work.
2677 */
2678 SCR_INT,
2679 SIR_NEGO_SYNC,
2680 /*
2681 ** let the target fetch our answer.
2682 */
2683 SCR_SET (SCR_ATN),
2684 0,
2685 SCR_CLR (SCR_ACK),
2686 0,
2687
2688 SCR_INT ^ IFFALSE (WHEN (SCR_MSG_OUT)),
2689 SIR_NEGO_PROTO,
2690 /*
2691 ** Send the MSG_EXT_SDTR
2692 */
2693 SCR_MOVE_ABS (5) ^ SCR_MSG_OUT,
2694 NADDR (msgout),
2695 SCR_CLR (SCR_ATN),
2696 0,
2697 SCR_COPY (1),
2698 RADDR (sfbr),
2699 NADDR (lastmsg),
2700 SCR_JUMP,
2701 PADDR (msg_out_done),
2702
2703 }/*-------------------------< MSG_OUT_ABORT >-------------*/,{
2704 /*
2705 ** After ABORT message,
2706 **
2707 ** expect an immediate disconnect, ...
2708 */
2709 SCR_REG_REG (scntl2, SCR_AND, 0x7f),
2710 0,
2711 SCR_CLR (SCR_ACK|SCR_ATN),
2712 0,
2713 SCR_WAIT_DISC,
2714 0,
2715 /*
2716 ** ... and set the status to "ABORTED"
2717 */
2718 SCR_LOAD_REG (HS_REG, HS_ABORTED),
2719 0,
2720 SCR_JUMP,
2721 PADDR (cleanup),
2722
2723 }/*-------------------------< GETCC >-----------------------*/,{
2724 /*
2725 ** The ncr doesn't have an indirect load
2726 ** or store command. So we have to
2727 ** copy part of the control block to a
2728 ** fixed place, where we can modify it.
2729 **
2730 ** We patch the address part of a COPY command
2731 ** with the address of the dsa register ...
2732 */
2733 SCR_COPY_F (4),
2734 RADDR (dsa),
2735 PADDRH (getcc1),
2736 /*
2737 ** ... then we do the actual copy.
2738 */
2739 SCR_COPY (sizeof (struct head)),
2740 }/*-------------------------< GETCC1 >----------------------*/,{
2741 0,
2742 NADDR (header),
2743 /*
2744 ** Initialize the status registers
2745 */
2746 SCR_COPY (4),
2747 NADDR (header.status),
2748 RADDR (scr0),
2749 }/*-------------------------< GETCC2 >----------------------*/,{
2750 /*
2751 ** Get the condition code from a target.
2752 **
2753 ** DSA points to a data structure.
2754 ** Set TEMP to the script location
2755 ** that receives the condition code.
2756 **
2757 ** Because there is no script command
2758 ** to load a longword into a register,
2759 ** we use a CALL command.
2760 */
2761 /*<<<*/ SCR_CALLR,
2762 24,
2763 /*
2764 ** Get the condition code.
2765 */
2766 SCR_MOVE_TBL ^ SCR_DATA_IN,
2767 offsetof (struct dsb, sense),
2768 /*
2769 ** No data phase may follow!
2770 */
2771 SCR_CALL,
2772 PADDR (checkatn),
2773 SCR_JUMP,
2774 PADDR (no_data),
2775 /*>>>*/
2776
2777 /*
2778 ** The CALL jumps to this point.
2779 ** Prepare for a RESTORE_POINTER message.
2780 ** Save the TEMP register into the saved pointer.
2781 */
2782 SCR_COPY (4),
2783 RADDR (temp),
2784 NADDR (header.savep),
2785 /*
2786 ** Load scratcha, because in case of a selection timeout,
2787 ** the host will expect a new value for startpos in
2788 ** the scratcha register.
2789 */
2790 SCR_COPY (4),
2791 PADDR (startpos),
2792 RADDR (scratcha),
2793 #ifdef NCR_GETCC_WITHMSG
2794 /*
2795 ** If QUIRK_NOMSG is set, select without ATN.
2796 ** and don't send a message.
2797 */
2798 SCR_FROM_REG (QU_REG),
2799 0,
2800 SCR_JUMP ^ IFTRUE (MASK (QUIRK_NOMSG, QUIRK_NOMSG)),
2801 PADDRH(getcc3),
2802 /*
2803 ** Then try to connect to the target.
2804 ** If we are reselected, special treatment
2805 ** of the current job is required before
2806 ** accepting the reselection.
2807 */
2808 SCR_SEL_TBL_ATN ^ offsetof (struct dsb, select),
2809 PADDR(badgetcc),
2810 /*
2811 ** Send the IDENTIFY message.
2812 ** In case of short transfer, remove ATN.
2813 */
2814 SCR_MOVE_TBL ^ SCR_MSG_OUT,
2815 offsetof (struct dsb, smsg2),
2816 SCR_CLR (SCR_ATN),
2817 0,
2818 /*
2819 ** save the first byte of the message.
2820 */
2821 SCR_COPY (1),
2822 RADDR (sfbr),
2823 NADDR (lastmsg),
2824 SCR_JUMP,
2825 PADDR (prepare2),
2826
2827 #endif
2828 }/*-------------------------< GETCC3 >----------------------*/,{
2829 /*
2830 ** Try to connect to the target.
2831 ** If we are reselected, special treatment
2832 ** of the current job is required before
2833 ** accepting the reselection.
2834 **
2835 ** Silly target won't accept a message.
2836 ** Select without ATN.
2837 */
2838 SCR_SEL_TBL ^ offsetof (struct dsb, select),
2839 PADDR(badgetcc),
2840 /*
2841 ** Force error if selection timeout
2842 */
2843 SCR_JUMPR ^ IFTRUE (WHEN (SCR_MSG_IN)),
2844 0,
2845 /*
2846 ** don't negotiate.
2847 */
2848 SCR_JUMP,
2849 PADDR (prepare2),
2850 }/*-------------------------< ABORTTAG >-------------------*/,{
2851 /*
2852 ** Abort a bad reselection.
2853 ** Set the message to ABORT vs. ABORT_TAG
2854 */
2855 SCR_LOAD_REG (scratcha, MSG_ABORT_TAG),
2856 0,
2857 SCR_JUMPR ^ IFFALSE (CARRYSET),
2858 8,
2859 }/*-------------------------< ABORT >----------------------*/,{
2860 SCR_LOAD_REG (scratcha, MSG_ABORT),
2861 0,
2862 SCR_COPY (1),
2863 RADDR (scratcha),
2864 NADDR (msgout),
2865 SCR_SET (SCR_ATN),
2866 0,
2867 SCR_CLR (SCR_ACK),
2868 0,
2869 /*
2870 ** and send it.
2871 ** we expect an immediate disconnect
2872 */
2873 SCR_REG_REG (scntl2, SCR_AND, 0x7f),
2874 0,
2875 SCR_MOVE_ABS (1) ^ SCR_MSG_OUT,
2876 NADDR (msgout),
2877 SCR_COPY (1),
2878 RADDR (sfbr),
2879 NADDR (lastmsg),
2880 SCR_CLR (SCR_ACK|SCR_ATN),
2881 0,
2882 SCR_WAIT_DISC,
2883 0,
2884 SCR_JUMP,
2885 PADDR (start),
2886 }/*-------------------------< SNOOPTEST >-------------------*/,{
2887 /*
2888 ** Read the variable.
2889 */
2890 SCR_COPY (4),
2891 KVAR (KVAR_NCR_CACHE),
2892 RADDR (scratcha),
2893 /*
2894 ** Write the variable.
2895 */
2896 SCR_COPY (4),
2897 RADDR (temp),
2898 KVAR (KVAR_NCR_CACHE),
2899 /*
2900 ** Read back the variable.
2901 */
2902 SCR_COPY (4),
2903 KVAR (KVAR_NCR_CACHE),
2904 RADDR (temp),
2905 }/*-------------------------< SNOOPEND >-------------------*/,{
2906 /*
2907 ** And stop.
2908 */
2909 SCR_INT,
2910 99,
2911 }/*--------------------------------------------------------*/
2912 };
2913
2914
2915 /*==========================================================
2916 **
2917 **
2918 ** Fill in #define dependent parts of the script
2919 **
2920 **
2921 **==========================================================
2922 */
2923
2924 void ncr_script_fill (struct script * scr, struct scripth * scrh)
2925 {
2926 int i;
2927 ncrcmd *p;
2928
2929 p = scrh->tryloop;
2930 for (i=0; i<MAX_START; i++) {
2931 *p++ =SCR_COPY (4);
2932 *p++ =NADDR (squeue[i]);
2933 *p++ =RADDR (dsa);
2934 *p++ =SCR_CALL;
2935 *p++ =PADDR (trysel);
2936 };
2937 *p++ =SCR_JUMP;
2938 *p++ =PADDRH(tryloop);
2939
2940 assert ((char *)p == (char *)&scrh->tryloop + sizeof (scrh->tryloop));
2941
2942 p = scr->data_in;
2943
2944 *p++ =SCR_JUMP ^ IFFALSE (WHEN (SCR_DATA_IN));
2945 *p++ =PADDR (no_data);
2946 *p++ =SCR_COPY (sizeof (ticks));
2947 *p++ =(ncrcmd) KVAR (KVAR_TICKS);
2948 *p++ =NADDR (header.stamp.data);
2949 *p++ =SCR_MOVE_TBL ^ SCR_DATA_IN;
2950 *p++ =offsetof (struct dsb, data[ 0]);
2951
2952 for (i=1; i<MAX_SCATTER; i++) {
2953 *p++ =SCR_CALL ^ IFFALSE (WHEN (SCR_DATA_IN));
2954 *p++ =PADDR (checkatn);
2955 *p++ =SCR_MOVE_TBL ^ SCR_DATA_IN;
2956 *p++ =offsetof (struct dsb, data[i]);
2957 };
2958
2959 *p++ =SCR_CALL;
2960 *p++ =PADDR (checkatn);
2961 *p++ =SCR_JUMP;
2962 *p++ =PADDR (no_data);
2963
2964 assert ((char *)p == (char *)&scr->data_in + sizeof (scr->data_in));
2965
2966 p = scr->data_out;
2967
2968 *p++ =SCR_JUMP ^ IFFALSE (WHEN (SCR_DATA_OUT));
2969 *p++ =PADDR (no_data);
2970 *p++ =SCR_COPY (sizeof (ticks));
2971 *p++ =(ncrcmd) KVAR (KVAR_TICKS);
2972 *p++ =NADDR (header.stamp.data);
2973 *p++ =SCR_MOVE_TBL ^ SCR_DATA_OUT;
2974 *p++ =offsetof (struct dsb, data[ 0]);
2975
2976 for (i=1; i<MAX_SCATTER; i++) {
2977 *p++ =SCR_CALL ^ IFFALSE (WHEN (SCR_DATA_OUT));
2978 *p++ =PADDR (dispatch);
2979 *p++ =SCR_MOVE_TBL ^ SCR_DATA_OUT;
2980 *p++ =offsetof (struct dsb, data[i]);
2981 };
2982
2983 *p++ =SCR_CALL;
2984 *p++ =PADDR (dispatch);
2985 *p++ =SCR_JUMP;
2986 *p++ =PADDR (no_data);
2987
2988 assert ((char *)p == (char *)&scr->data_out + sizeof (scr->data_out));
2989 }
2990
2991 /*==========================================================
2992 **
2993 **
2994 ** Copy and rebind a script.
2995 **
2996 **
2997 **==========================================================
2998 */
2999
3000 static void ncr_script_copy_and_bind (ncb_p np, ncrcmd *src, ncrcmd *dst, int len)
3001 {
3002 ncrcmd opcode, new, old, tmp1, tmp2;
3003 ncrcmd *start, *end;
3004 int relocs, offset;
3005
3006 start = src;
3007 end = src + len/4;
3008 offset = 0;
3009
3010 while (src < end) {
3011
3012 opcode = *src++;
3013 WRITESCRIPT_OFF(dst, offset, opcode);
3014 offset += 4;
3015
3016 /*
3017 ** If we forget to change the length
3018 ** in struct script, a field will be
3019 ** padded with 0. This is an illegal
3020 ** command.
3021 */
3022
3023 if (opcode == 0) {
3024 printf ("%s: ERROR0 IN SCRIPT at %d.\n",
3025 ncr_name(np), (int) (src-start-1));
3026 DELAY (1000000);
3027 };
3028
3029 if (DEBUG_FLAGS & DEBUG_SCRIPT)
3030 printf ("%p: <%x>\n",
3031 (src-1), (unsigned)opcode);
3032
3033 /*
3034 ** We don't have to decode ALL commands
3035 */
3036 switch (opcode >> 28) {
3037
3038 case 0xc:
3039 /*
3040 ** COPY has TWO arguments.
3041 */
3042 relocs = 2;
3043 tmp1 = src[0];
3044 if ((tmp1 & RELOC_MASK) == RELOC_KVAR)
3045 tmp1 = 0;
3046 tmp2 = src[1];
3047 if ((tmp2 & RELOC_MASK) == RELOC_KVAR)
3048 tmp2 = 0;
3049 if ((tmp1 ^ tmp2) & 3) {
3050 printf ("%s: ERROR1 IN SCRIPT at %d.\n",
3051 ncr_name(np), (int) (src-start-1));
3052 DELAY (1000000);
3053 }
3054 /*
3055 ** If PREFETCH feature not enabled, remove
3056 ** the NO FLUSH bit if present.
3057 */
3058 if ((opcode & SCR_NO_FLUSH) && !(np->features&FE_PFEN))
3059 WRITESCRIPT_OFF(dst, offset - 4,
3060 (opcode & ~SCR_NO_FLUSH));
3061 break;
3062
3063 case 0x0:
3064 /*
3065 ** MOVE (absolute address)
3066 */
3067 relocs = 1;
3068 break;
3069
3070 case 0x8:
3071 /*
3072 ** JUMP / CALL
3073 ** dont't relocate if relative :-)
3074 */
3075 if (opcode & 0x00800000)
3076 relocs = 0;
3077 else
3078 relocs = 1;
3079 break;
3080
3081 case 0x4:
3082 case 0x5:
3083 case 0x6:
3084 case 0x7:
3085 relocs = 1;
3086 break;
3087
3088 default:
3089 relocs = 0;
3090 break;
3091 };
3092
3093 if (relocs) {
3094 while (relocs--) {
3095 old = *src++;
3096
3097 switch (old & RELOC_MASK) {
3098 case RELOC_REGISTER:
3099 new = (old & ~RELOC_MASK) + rman_get_start(np->reg_res);
3100 break;
3101 case RELOC_LABEL:
3102 new = (old & ~RELOC_MASK) + np->p_script;
3103 break;
3104 case RELOC_LABELH:
3105 new = (old & ~RELOC_MASK) + np->p_scripth;
3106 break;
3107 case RELOC_SOFTC:
3108 new = (old & ~RELOC_MASK) + vtophys(np);
3109 break;
3110 case RELOC_KVAR:
3111 if (((old & ~RELOC_MASK) <
3112 SCRIPT_KVAR_FIRST) ||
3113 ((old & ~RELOC_MASK) >
3114 SCRIPT_KVAR_LAST))
3115 panic("ncr KVAR out of range");
3116 new = vtophys(script_kvars[old &
3117 ~RELOC_MASK]);
3118 break;
3119 case 0:
3120 /* Don't relocate a 0 address. */
3121 if (old == 0) {
3122 new = old;
3123 break;
3124 }
3125 /* fall through */
3126 default:
3127 panic("ncr_script_copy_and_bind: weird relocation %x @ %d\n", old, (int)(src - start));
3128 break;
3129 }
3130
3131 WRITESCRIPT_OFF(dst, offset, new);
3132 offset += 4;
3133 }
3134 } else {
3135 WRITESCRIPT_OFF(dst, offset, *src++);
3136 offset += 4;
3137 }
3138
3139 };
3140 }
3141
3142 /*==========================================================
3143 **
3144 **
3145 ** Auto configuration.
3146 **
3147 **
3148 **==========================================================
3149 */
3150
3151 #if 0
3152 /*----------------------------------------------------------
3153 **
3154 ** Reduce the transfer length to the max value
3155 ** we can transfer safely.
3156 **
3157 ** Reading a block greater then MAX_SIZE from the
3158 ** raw (character) device exercises a memory leak
3159 ** in the vm subsystem. This is common to ALL devices.
3160 ** We have submitted a description of this bug to
3161 ** <FreeBSD-bugs@freefall.cdrom.com>.
3162 ** It should be fixed in the current release.
3163 **
3164 **----------------------------------------------------------
3165 */
3166
3167 void ncr_min_phys (struct buf *bp)
3168 {
3169 if ((unsigned long)bp->b_bcount > MAX_SIZE) bp->b_bcount = MAX_SIZE;
3170 }
3171
3172 #endif
3173
3174 #if 0
3175 /*----------------------------------------------------------
3176 **
3177 ** Maximal number of outstanding requests per target.
3178 **
3179 **----------------------------------------------------------
3180 */
3181
3182 u_int32_t ncr_info (int unit)
3183 {
3184 return (1); /* may be changed later */
3185 }
3186
3187 #endif
3188
3189 /*----------------------------------------------------------
3190 **
3191 ** NCR chip devices table and chip look up function.
3192 ** Features bit are defined in ncrreg.h. Is it the
3193 ** right place?
3194 **
3195 **----------------------------------------------------------
3196 */
3197 typedef struct {
3198 unsigned long device_id;
3199 unsigned short minrevid;
3200 char *name;
3201 unsigned char maxburst;
3202 unsigned char maxoffs;
3203 unsigned char clock_divn;
3204 unsigned int features;
3205 } ncr_chip;
3206
3207 static ncr_chip ncr_chip_table[] = {
3208 {NCR_810_ID, 0x00, "ncr 53c810 fast10 scsi", 4, 8, 4,
3209 FE_ERL}
3210 ,
3211 {NCR_810_ID, 0x10, "ncr 53c810a fast10 scsi", 4, 8, 4,
3212 FE_ERL|FE_LDSTR|FE_PFEN|FE_BOF}
3213 ,
3214 {NCR_815_ID, 0x00, "ncr 53c815 fast10 scsi", 4, 8, 4,
3215 FE_ERL|FE_BOF}
3216 ,
3217 {NCR_820_ID, 0x00, "ncr 53c820 fast10 wide scsi", 4, 8, 4,
3218 FE_WIDE|FE_ERL}
3219 ,
3220 {NCR_825_ID, 0x00, "ncr 53c825 fast10 wide scsi", 4, 8, 4,
3221 FE_WIDE|FE_ERL|FE_BOF}
3222 ,
3223 {NCR_825_ID, 0x10, "ncr 53c825a fast10 wide scsi", 7, 8, 4,
3224 FE_WIDE|FE_CACHE_SET|FE_DFS|FE_LDSTR|FE_PFEN|FE_RAM}
3225 ,
3226 {NCR_860_ID, 0x00, "ncr 53c860 fast20 scsi", 4, 8, 5,
3227 FE_ULTRA|FE_CLK80|FE_CACHE_SET|FE_LDSTR|FE_PFEN}
3228 ,
3229 {NCR_875_ID, 0x00, "ncr 53c875 fast20 wide scsi", 7, 16, 5,
3230 FE_WIDE|FE_ULTRA|FE_CLK80|FE_CACHE_SET|FE_DFS|FE_LDSTR|FE_PFEN|FE_RAM}
3231 ,
3232 {NCR_875_ID, 0x02, "ncr 53c875 fast20 wide scsi", 7, 16, 5,
3233 FE_WIDE|FE_ULTRA|FE_DBLR|FE_CACHE_SET|FE_DFS|FE_LDSTR|FE_PFEN|FE_RAM}
3234 ,
3235 {NCR_875_ID2, 0x00, "ncr 53c875j fast20 wide scsi", 7, 16, 5,
3236 FE_WIDE|FE_ULTRA|FE_DBLR|FE_CACHE_SET|FE_DFS|FE_LDSTR|FE_PFEN|FE_RAM}
3237 ,
3238 {NCR_885_ID, 0x00, "ncr 53c885 fast20 wide scsi", 7, 16, 5,
3239 FE_WIDE|FE_ULTRA|FE_DBLR|FE_CACHE_SET|FE_DFS|FE_LDSTR|FE_PFEN|FE_RAM}
3240 ,
3241 {NCR_895_ID, 0x00, "ncr 53c895 fast40 wide scsi", 7, 31, 7,
3242 FE_WIDE|FE_ULTRA2|FE_QUAD|FE_CACHE_SET|FE_DFS|FE_LDSTR|FE_PFEN|FE_RAM}
3243 ,
3244 {NCR_896_ID, 0x00, "ncr 53c896 fast40 wide scsi", 7, 31, 7,
3245 FE_WIDE|FE_ULTRA2|FE_QUAD|FE_CACHE_SET|FE_DFS|FE_LDSTR|FE_PFEN|FE_RAM}
3246 ,
3247 {NCR_895A_ID, 0x00, "ncr 53c895a fast40 wide scsi", 7, 31, 7,
3248 FE_WIDE|FE_ULTRA2|FE_QUAD|FE_CACHE_SET|FE_DFS|FE_LDSTR|FE_PFEN|FE_RAM}
3249 ,
3250 {NCR_1510D_ID, 0x00, "ncr 53c1510d fast40 wide scsi", 7, 31, 7,
3251 FE_WIDE|FE_ULTRA2|FE_QUAD|FE_CACHE_SET|FE_DFS|FE_LDSTR|FE_PFEN|FE_RAM}
3252 };
3253
3254 static int ncr_chip_lookup(u_long device_id, u_char revision_id)
3255 {
3256 int i, found;
3257
3258 found = -1;
3259 for (i = 0; i < sizeof(ncr_chip_table)/sizeof(ncr_chip_table[0]); i++) {
3260 if (device_id == ncr_chip_table[i].device_id &&
3261 ncr_chip_table[i].minrevid <= revision_id) {
3262 if (found < 0 ||
3263 ncr_chip_table[found].minrevid
3264 < ncr_chip_table[i].minrevid) {
3265 found = i;
3266 }
3267 }
3268 }
3269 return found;
3270 }
3271
3272 /*----------------------------------------------------------
3273 **
3274 ** Probe the hostadapter.
3275 **
3276 **----------------------------------------------------------
3277 */
3278
3279
3280
3281 static int ncr_probe (device_t dev)
3282 {
3283 int i;
3284
3285 i = ncr_chip_lookup(pci_get_devid(dev), pci_get_revid(dev));
3286 if (i >= 0) {
3287 device_set_desc(dev, ncr_chip_table[i].name);
3288 return (-1000); /* Allows to use both ncr and sym */
3289 }
3290
3291 return (ENXIO);
3292 }
3293
3294
3295
3296 /*==========================================================
3297 **
3298 ** NCR chip clock divisor table.
3299 ** Divisors are multiplied by 10,000,000 in order to make
3300 ** calculations more simple.
3301 **
3302 **==========================================================
3303 */
3304
3305 #define _5M 5000000
3306 static u_long div_10M[] =
3307 {2*_5M, 3*_5M, 4*_5M, 6*_5M, 8*_5M, 12*_5M, 16*_5M};
3308
3309 /*===============================================================
3310 **
3311 ** NCR chips allow burst lengths of 2, 4, 8, 16, 32, 64, 128
3312 ** transfers. 32,64,128 are only supported by 875 and 895 chips.
3313 ** We use log base 2 (burst length) as internal code, with
3314 ** value 0 meaning "burst disabled".
3315 **
3316 **===============================================================
3317 */
3318
3319 /*
3320 * Burst length from burst code.
3321 */
3322 #define burst_length(bc) (!(bc))? 0 : 1 << (bc)
3323
3324 /*
3325 * Burst code from io register bits.
3326 */
3327 #define burst_code(dmode, ctest4, ctest5) \
3328 (ctest4) & 0x80? 0 : (((dmode) & 0xc0) >> 6) + ((ctest5) & 0x04) + 1
3329
3330 /*
3331 * Set initial io register bits from burst code.
3332 */
3333 static void
3334 ncr_init_burst(ncb_p np, u_char bc)
3335 {
3336 np->rv_ctest4 &= ~0x80;
3337 np->rv_dmode &= ~(0x3 << 6);
3338 np->rv_ctest5 &= ~0x4;
3339
3340 if (!bc) {
3341 np->rv_ctest4 |= 0x80;
3342 }
3343 else {
3344 --bc;
3345 np->rv_dmode |= ((bc & 0x3) << 6);
3346 np->rv_ctest5 |= (bc & 0x4);
3347 }
3348 }
3349
3350 /*==========================================================
3351 **
3352 **
3353 ** Auto configuration: attach and init a host adapter.
3354 **
3355 **
3356 **==========================================================
3357 */
3358
3359
3360 static int
3361 ncr_attach (device_t dev)
3362 {
3363 ncb_p np = (struct ncb*) device_get_softc(dev);
3364 u_char rev = 0;
3365 u_long period;
3366 int i, rid;
3367 u_int8_t usrsync;
3368 u_int8_t usrwide;
3369 struct cam_devq *devq;
3370
3371 /*
3372 ** allocate and initialize structures.
3373 */
3374
3375 np->unit = device_get_unit(dev);
3376
3377 /*
3378 ** Try to map the controller chip to
3379 ** virtual and physical memory.
3380 */
3381
3382 np->reg_rid = 0x14;
3383 np->reg_res = bus_alloc_resource(dev, SYS_RES_MEMORY, &np->reg_rid,
3384 0, ~0, 1, RF_ACTIVE);
3385 if (!np->reg_res) {
3386 device_printf(dev, "could not map memory\n");
3387 return ENXIO;
3388 }
3389
3390 /*
3391 ** Make the controller's registers available.
3392 ** Now the INB INW INL OUTB OUTW OUTL macros
3393 ** can be used safely.
3394 */
3395
3396 np->bst = rman_get_bustag(np->reg_res);
3397 np->bsh = rman_get_bushandle(np->reg_res);
3398
3399
3400 #ifdef NCR_IOMAPPED
3401 /*
3402 ** Try to map the controller chip into iospace.
3403 */
3404
3405 if (!pci_map_port (config_id, 0x10, &np->port))
3406 return;
3407 #endif
3408
3409
3410 /*
3411 ** Save some controller register default values
3412 */
3413
3414 np->rv_scntl3 = INB(nc_scntl3) & 0x77;
3415 np->rv_dmode = INB(nc_dmode) & 0xce;
3416 np->rv_dcntl = INB(nc_dcntl) & 0xa9;
3417 np->rv_ctest3 = INB(nc_ctest3) & 0x01;
3418 np->rv_ctest4 = INB(nc_ctest4) & 0x88;
3419 np->rv_ctest5 = INB(nc_ctest5) & 0x24;
3420 np->rv_gpcntl = INB(nc_gpcntl);
3421 np->rv_stest2 = INB(nc_stest2) & 0x20;
3422
3423 if (bootverbose >= 2) {
3424 printf ("\tBIOS values: SCNTL3:%02x DMODE:%02x DCNTL:%02x\n",
3425 np->rv_scntl3, np->rv_dmode, np->rv_dcntl);
3426 printf ("\t CTEST3:%02x CTEST4:%02x CTEST5:%02x\n",
3427 np->rv_ctest3, np->rv_ctest4, np->rv_ctest5);
3428 }
3429
3430 np->rv_dcntl |= NOCOM;
3431
3432 /*
3433 ** Do chip dependent initialization.
3434 */
3435
3436 rev = pci_get_revid(dev);
3437
3438 /*
3439 ** Get chip features from chips table.
3440 */
3441 i = ncr_chip_lookup(pci_get_devid(dev), rev);
3442
3443 if (i >= 0) {
3444 np->maxburst = ncr_chip_table[i].maxburst;
3445 np->maxoffs = ncr_chip_table[i].maxoffs;
3446 np->clock_divn = ncr_chip_table[i].clock_divn;
3447 np->features = ncr_chip_table[i].features;
3448 } else { /* Should'nt happen if probe() is ok */
3449 np->maxburst = 4;
3450 np->maxoffs = 8;
3451 np->clock_divn = 4;
3452 np->features = FE_ERL;
3453 }
3454
3455 np->maxwide = np->features & FE_WIDE ? 1 : 0;
3456 np->clock_khz = np->features & FE_CLK80 ? 80000 : 40000;
3457 if (np->features & FE_QUAD) np->multiplier = 4;
3458 else if (np->features & FE_DBLR) np->multiplier = 2;
3459 else np->multiplier = 1;
3460
3461 /*
3462 ** Get the frequency of the chip's clock.
3463 ** Find the right value for scntl3.
3464 */
3465 if (np->features & (FE_ULTRA|FE_ULTRA2))
3466 ncr_getclock(np, np->multiplier);
3467
3468 #ifdef NCR_TEKRAM_EEPROM
3469 if (bootverbose) {
3470 printf ("%s: Tekram EEPROM read %s\n",
3471 ncr_name(np),
3472 read_tekram_eeprom (np, NULL) ?
3473 "succeeded" : "failed");
3474 }
3475 #endif /* NCR_TEKRAM_EEPROM */
3476
3477 /*
3478 * If scntl3 != 0, we assume BIOS is present.
3479 */
3480 if (np->rv_scntl3)
3481 np->features |= FE_BIOS;
3482
3483 /*
3484 * Divisor to be used for async (timer pre-scaler).
3485 */
3486 i = np->clock_divn - 1;
3487 while (i >= 0) {
3488 --i;
3489 if (10ul * SCSI_NCR_MIN_ASYNC * np->clock_khz > div_10M[i]) {
3490 ++i;
3491 break;
3492 }
3493 }
3494 np->rv_scntl3 = i+1;
3495
3496 /*
3497 * Minimum synchronous period factor supported by the chip.
3498 * Btw, 'period' is in tenths of nanoseconds.
3499 */
3500
3501 period = (4 * div_10M[0] + np->clock_khz - 1) / np->clock_khz;
3502 if (period <= 250) np->minsync = 10;
3503 else if (period <= 303) np->minsync = 11;
3504 else if (period <= 500) np->minsync = 12;
3505 else np->minsync = (period + 40 - 1) / 40;
3506
3507 /*
3508 * Check against chip SCSI standard support (SCSI-2,ULTRA,ULTRA2).
3509 */
3510
3511 if (np->minsync < 25 && !(np->features & (FE_ULTRA|FE_ULTRA2)))
3512 np->minsync = 25;
3513 else if (np->minsync < 12 && !(np->features & FE_ULTRA2))
3514 np->minsync = 12;
3515
3516 /*
3517 * Maximum synchronous period factor supported by the chip.
3518 */
3519
3520 period = (11 * div_10M[np->clock_divn - 1]) / (4 * np->clock_khz);
3521 np->maxsync = period > 2540 ? 254 : period / 10;
3522
3523 /*
3524 * Now, some features available with Symbios compatible boards.
3525 * LED support through GPIO0 and DIFF support.
3526 */
3527
3528 #ifdef SCSI_NCR_SYMBIOS_COMPAT
3529 if (!(np->rv_gpcntl & 0x01))
3530 np->features |= FE_LED0;
3531 #if 0 /* Not safe enough without NVRAM support or user settable option */
3532 if (!(INB(nc_gpreg) & 0x08))
3533 np->features |= FE_DIFF;
3534 #endif
3535 #endif /* SCSI_NCR_SYMBIOS_COMPAT */
3536
3537 /*
3538 * Prepare initial IO registers settings.
3539 * Trust BIOS only if we believe we have one and if we want to.
3540 */
3541 #ifdef SCSI_NCR_TRUST_BIOS
3542 if (!(np->features & FE_BIOS)) {
3543 #else
3544 if (1) {
3545 #endif
3546 np->rv_dmode = 0;
3547 np->rv_dcntl = NOCOM;
3548 np->rv_ctest3 = 0;
3549 np->rv_ctest4 = MPEE;
3550 np->rv_ctest5 = 0;
3551 np->rv_stest2 = 0;
3552
3553 if (np->features & FE_ERL)
3554 np->rv_dmode |= ERL; /* Enable Read Line */
3555 if (np->features & FE_BOF)
3556 np->rv_dmode |= BOF; /* Burst Opcode Fetch */
3557 if (np->features & FE_ERMP)
3558 np->rv_dmode |= ERMP; /* Enable Read Multiple */
3559 if (np->features & FE_CLSE)
3560 np->rv_dcntl |= CLSE; /* Cache Line Size Enable */
3561 if (np->features & FE_WRIE)
3562 np->rv_ctest3 |= WRIE; /* Write and Invalidate */
3563 if (np->features & FE_PFEN)
3564 np->rv_dcntl |= PFEN; /* Prefetch Enable */
3565 if (np->features & FE_DFS)
3566 np->rv_ctest5 |= DFS; /* Dma Fifo Size */
3567 if (np->features & FE_DIFF)
3568 np->rv_stest2 |= 0x20; /* Differential mode */
3569 ncr_init_burst(np, np->maxburst); /* Max dwords burst length */
3570 } else {
3571 np->maxburst =
3572 burst_code(np->rv_dmode, np->rv_ctest4, np->rv_ctest5);
3573 }
3574
3575 /*
3576 ** Get on-chip SRAM address, if supported
3577 */
3578 if ((np->features & FE_RAM) && sizeof(struct script) <= 4096) {
3579 np->sram_rid = 0x18;
3580 np->sram_res = bus_alloc_resource(dev, SYS_RES_MEMORY,
3581 &np->sram_rid,
3582 0, ~0, 1, RF_ACTIVE);
3583 }
3584
3585 /*
3586 ** Allocate structure for script relocation.
3587 */
3588 if (np->sram_res != NULL) {
3589 np->script = NULL;
3590 np->p_script = rman_get_start(np->sram_res);
3591 np->bst2 = rman_get_bustag(np->sram_res);
3592 np->bsh2 = rman_get_bushandle(np->sram_res);
3593 } else if (sizeof (struct script) > PAGE_SIZE) {
3594 np->script = (struct script*) vm_page_alloc_contig
3595 (round_page(sizeof (struct script)),
3596 0, 0xffffffff, PAGE_SIZE);
3597 } else {
3598 np->script = (struct script *)
3599 kmalloc (sizeof (struct script), M_DEVBUF, M_WAITOK);
3600 }
3601
3602 /* XXX JGibbs - Use contigmalloc */
3603 if (sizeof (struct scripth) > PAGE_SIZE) {
3604 np->scripth = (struct scripth*) vm_page_alloc_contig
3605 (round_page(sizeof (struct scripth)),
3606 0, 0xffffffff, PAGE_SIZE);
3607 } else
3608 {
3609 np->scripth = (struct scripth *)
3610 kmalloc (sizeof (struct scripth), M_DEVBUF, M_WAITOK);
3611 }
3612
3613 #ifdef SCSI_NCR_PCI_CONFIG_FIXUP
3614 /*
3615 ** If cache line size is enabled, check PCI config space and
3616 ** try to fix it up if necessary.
3617 */
3618 #ifdef PCIR_CACHELNSZ /* To be sure that new PCI stuff is present */
3619 {
3620 u_char cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1);
3621 u_short command = pci_read_config(dev, PCIR_COMMAND, 2);
3622
3623 if (!cachelnsz) {
3624 cachelnsz = 8;
3625 printf("%s: setting PCI cache line size register to %d.\n",
3626 ncr_name(np), (int)cachelnsz);
3627 pci_write_config(dev, PCIR_CACHELNSZ, cachelnsz, 1);
3628 }
3629
3630 if (!(command & (1<<4))) {
3631 command |= (1<<4);
3632 printf("%s: setting PCI command write and invalidate.\n",
3633 ncr_name(np));
3634 pci_write_config(dev, PCIR_COMMAND, command, 2);
3635 }
3636 }
3637 #endif /* PCIR_CACHELNSZ */
3638
3639 #endif /* SCSI_NCR_PCI_CONFIG_FIXUP */
3640
3641 /* Initialize per-target user settings */
3642 usrsync = 0;
3643 if (SCSI_NCR_DFLT_SYNC) {
3644 usrsync = SCSI_NCR_DFLT_SYNC;
3645 if (usrsync > np->maxsync)
3646 usrsync = np->maxsync;
3647 if (usrsync < np->minsync)
3648 usrsync = np->minsync;
3649 };
3650
3651 usrwide = (SCSI_NCR_MAX_WIDE);
3652 if (usrwide > np->maxwide) usrwide=np->maxwide;
3653
3654 for (i=0;i<MAX_TARGET;i++) {
3655 tcb_p tp = &np->target[i];
3656
3657 tp->tinfo.user.period = usrsync;
3658 tp->tinfo.user.offset = usrsync != 0 ? np->maxoffs : 0;
3659 tp->tinfo.user.width = usrwide;
3660 tp->tinfo.disc_tag = NCR_CUR_DISCENB
3661 | NCR_CUR_TAGENB
3662 | NCR_USR_DISCENB
3663 | NCR_USR_TAGENB;
3664 }
3665
3666 /*
3667 ** Bells and whistles ;-)
3668 */
3669 if (bootverbose)
3670 printf("%s: minsync=%d, maxsync=%d, maxoffs=%d, %d dwords burst, %s dma fifo\n",
3671 ncr_name(np), np->minsync, np->maxsync, np->maxoffs,
3672 burst_length(np->maxburst),
3673 (np->rv_ctest5 & DFS) ? "large" : "normal");
3674
3675 /*
3676 ** Print some complementary information that can be helpfull.
3677 */
3678 if (bootverbose)
3679 printf("%s: %s, %s IRQ driver%s\n",
3680 ncr_name(np),
3681 np->rv_stest2 & 0x20 ? "differential" : "single-ended",
3682 np->rv_dcntl & IRQM ? "totem pole" : "open drain",
3683 np->sram_res ? ", using on-chip SRAM" : "");
3684
3685 /*
3686 ** Patch scripts to physical addresses
3687 */
3688 ncr_script_fill (&script0, &scripth0);
3689
3690 if (np->script)
3691 np->p_script = vtophys(np->script);
3692 np->p_scripth = vtophys(np->scripth);
3693
3694 ncr_script_copy_and_bind (np, (ncrcmd *) &script0,
3695 (ncrcmd *) np->script, sizeof(struct script));
3696
3697 ncr_script_copy_and_bind (np, (ncrcmd *) &scripth0,
3698 (ncrcmd *) np->scripth, sizeof(struct scripth));
3699
3700 /*
3701 ** Patch the script for LED support.
3702 */
3703
3704 if (np->features & FE_LED0) {
3705 WRITESCRIPT(reselect[0], SCR_REG_REG(gpreg, SCR_OR, 0x01));
3706 WRITESCRIPT(reselect1[0], SCR_REG_REG(gpreg, SCR_AND, 0xfe));
3707 WRITESCRIPT(reselect2[0], SCR_REG_REG(gpreg, SCR_AND, 0xfe));
3708 }
3709
3710 /*
3711 ** init data structure
3712 */
3713
3714 np->jump_tcb.l_cmd = SCR_JUMP;
3715 np->jump_tcb.l_paddr = NCB_SCRIPTH_PHYS (np, abort);
3716
3717 /*
3718 ** Get SCSI addr of host adapter (set by bios?).
3719 */
3720
3721 np->myaddr = INB(nc_scid) & 0x07;
3722 if (!np->myaddr) np->myaddr = SCSI_NCR_MYADDR;
3723
3724 #ifdef NCR_DUMP_REG
3725 /*
3726 ** Log the initial register contents
3727 */
3728 {
3729 int reg;
3730 for (reg=0; reg<256; reg+=4) {
3731 if (reg%16==0) printf ("reg[%2x]", reg);
3732 printf (" %08x", (int)pci_conf_read (config_id, reg));
3733 if (reg%16==12) printf ("\n");
3734 }
3735 }
3736 #endif /* NCR_DUMP_REG */
3737
3738 /*
3739 ** Reset chip.
3740 */
3741
3742 OUTB (nc_istat, SRST);
3743 DELAY (1000);
3744 OUTB (nc_istat, 0 );
3745
3746
3747 /*
3748 ** Now check the cache handling of the pci chipset.
3749 */
3750
3751 if (ncr_snooptest (np)) {
3752 printf ("CACHE INCORRECTLY CONFIGURED.\n");
3753 return EINVAL;
3754 };
3755
3756 /*
3757 ** Install the interrupt handler.
3758 */
3759
3760 rid = 0;
3761 np->irq_res = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
3762 RF_SHAREABLE | RF_ACTIVE);
3763 if (np->irq_res == NULL) {
3764 device_printf(dev,
3765 "interruptless mode: reduced performance.\n");
3766 } else {
3767 bus_setup_intr(dev, np->irq_res, 0,
3768 ncr_intr, np, &np->irq_handle, NULL);
3769 }
3770
3771 /*
3772 ** Create the device queue. We only allow MAX_START-1 concurrent
3773 ** transactions so we can be sure to have one element free in our
3774 ** start queue to reset to the idle loop.
3775 */
3776 devq = cam_simq_alloc(MAX_START - 1);
3777 if (devq == NULL)
3778 return ENOMEM;
3779
3780 /*
3781 ** Now tell the generic SCSI layer
3782 ** about our bus.
3783 */
3784 np->sim = cam_sim_alloc(ncr_action, ncr_poll, "ncr", np, np->unit,
3785 1, MAX_TAGS, devq);
3786 cam_simq_release(devq);
3787 if (np->sim == NULL)
3788 return ENOMEM;
3789
3790
3791 if (xpt_bus_register(np->sim, 0) != CAM_SUCCESS) {
3792 cam_sim_free(np->sim);
3793 return ENOMEM;
3794 }
3795
3796 if (xpt_create_path(&np->path, /*periph*/NULL,
3797 cam_sim_path(np->sim), CAM_TARGET_WILDCARD,
3798 CAM_LUN_WILDCARD) != CAM_REQ_CMP) {
3799 xpt_bus_deregister(cam_sim_path(np->sim));
3800 cam_sim_free(np->sim);
3801 return ENOMEM;
3802 }
3803
3804 /*
3805 ** start the timeout daemon
3806 */
3807 callout_init(&np->timeout_ch);
3808 ncr_timeout (np);
3809 np->lasttime=0;
3810
3811 return 0;
3812 }
3813
3814 /*==========================================================
3815 **
3816 **
3817 ** Process pending device interrupts.
3818 **
3819 **
3820 **==========================================================
3821 */
3822
3823 static void
3824 ncr_intr(vnp)
3825 void *vnp;
3826 {
3827 ncb_p np = vnp;
3828 crit_enter();
3829
3830 if (DEBUG_FLAGS & DEBUG_TINY) printf ("[");
3831
3832 if (INB(nc_istat) & (INTF|SIP|DIP)) {
3833 /*
3834 ** Repeat until no outstanding ints
3835 */
3836 do {
3837 ncr_exception (np);
3838 } while (INB(nc_istat) & (INTF|SIP|DIP));
3839
3840 np->ticks = 100;
3841 };
3842
3843 if (DEBUG_FLAGS & DEBUG_TINY) printf ("]\n");
3844
3845 crit_exit();
3846 }
3847
3848 /*==========================================================
3849 **
3850 **
3851 ** Start execution of a SCSI command.
3852 ** This is called from the generic SCSI driver.
3853 **
3854 **
3855 **==========================================================
3856 */
3857
3858 static void
3859 ncr_action (struct cam_sim *sim, union ccb *ccb)
3860 {
3861 ncb_p np;
3862
3863 np = (ncb_p) cam_sim_softc(sim);
3864
3865 switch (ccb->ccb_h.func_code) {
3866 /* Common cases first */
3867 case XPT_SCSI_IO: /* Execute the requested I/O operation */
3868 {
3869 nccb_p cp;
3870 lcb_p lp;
3871 tcb_p tp;
3872 struct ccb_scsiio *csio;
3873 u_int8_t *msgptr;
3874 u_int msglen;
3875 u_int msglen2;
3876 int segments;
3877 u_int8_t nego;
3878 u_int8_t idmsg;
3879 int qidx;
3880
3881 tp = &np->target[ccb->ccb_h.target_id];
3882 csio = &ccb->csio;
3883
3884 crit_enter();
3885
3886 /*
3887 * Last time we need to check if this CCB needs to
3888 * be aborted.
3889 */
3890 if ((ccb->ccb_h.status & CAM_STATUS_MASK) != CAM_REQ_INPROG) {
3891 xpt_done(ccb);
3892 crit_exit();
3893 return;
3894 }
3895 ccb->ccb_h.status |= CAM_SIM_QUEUED;
3896
3897 /*---------------------------------------------------
3898 **
3899 ** Assign an nccb / bind ccb
3900 **
3901 **----------------------------------------------------
3902 */
3903 cp = ncr_get_nccb (np, ccb->ccb_h.target_id,
3904 ccb->ccb_h.target_lun);
3905 if (cp == NULL) {
3906 /* XXX JGibbs - Freeze SIMQ */
3907 ccb->ccb_h.status = CAM_RESRC_UNAVAIL;
3908 xpt_done(ccb);
3909 return;
3910 };
3911
3912 cp->ccb = ccb;
3913
3914 /*---------------------------------------------------
3915 **
3916 ** timestamp
3917 **
3918 **----------------------------------------------------
3919 */
3920 /*
3921 ** XXX JGibbs - Isn't this expensive
3922 ** enough to be conditionalized??
3923 */
3924
3925 bzero (&cp->phys.header.stamp, sizeof (struct tstamp));
3926 cp->phys.header.stamp.start = ticks;
3927
3928 nego = 0;
3929 if (tp->nego_cp == NULL) {
3930
3931 if (tp->tinfo.current.width
3932 != tp->tinfo.goal.width) {
3933 tp->nego_cp = cp;
3934 nego = NS_WIDE;
3935 } else if ((tp->tinfo.current.period
3936 != tp->tinfo.goal.period)
3937 || (tp->tinfo.current.offset
3938 != tp->tinfo.goal.offset)) {
3939 tp->nego_cp = cp;
3940 nego = NS_SYNC;
3941 };
3942 };
3943
3944 /*---------------------------------------------------
3945 **
3946 ** choose a new tag ...
3947 **
3948 **----------------------------------------------------
3949 */
3950 lp = tp->lp[ccb->ccb_h.target_lun];
3951
3952 if ((ccb->ccb_h.flags & CAM_TAG_ACTION_VALID) != 0
3953 && (ccb->csio.tag_action != CAM_TAG_ACTION_NONE)
3954 && (nego == 0)) {
3955 /*
3956 ** assign a tag to this nccb
3957 */
3958 while (!cp->tag) {
3959 nccb_p cp2 = lp->next_nccb;
3960 lp->lasttag = lp->lasttag % 255 + 1;
3961 while (cp2 && cp2->tag != lp->lasttag)
3962 cp2 = cp2->next_nccb;
3963 if (cp2) continue;
3964 cp->tag=lp->lasttag;
3965 if (DEBUG_FLAGS & DEBUG_TAGS) {
3966 PRINT_ADDR(ccb);
3967 printf ("using tag #%d.\n", cp->tag);
3968 };
3969 };
3970 } else {
3971 cp->tag=0;
3972 };
3973
3974 /*----------------------------------------------------
3975 **
3976 ** Build the identify / tag / sdtr message
3977 **
3978 **----------------------------------------------------
3979 */
3980 idmsg = MSG_IDENTIFYFLAG | ccb->ccb_h.target_lun;
3981 if (tp->tinfo.disc_tag & NCR_CUR_DISCENB)
3982 idmsg |= MSG_IDENTIFY_DISCFLAG;
3983
3984 msgptr = cp->scsi_smsg;
3985 msglen = 0;
3986 msgptr[msglen++] = idmsg;
3987
3988 if (cp->tag) {
3989 msgptr[msglen++] = ccb->csio.tag_action;
3990 msgptr[msglen++] = cp->tag;
3991 }
3992
3993 switch (nego) {
3994 case NS_SYNC:
3995 msgptr[msglen++] = MSG_EXTENDED;
3996 msgptr[msglen++] = MSG_EXT_SDTR_LEN;
3997 msgptr[msglen++] = MSG_EXT_SDTR;
3998 msgptr[msglen++] = tp->tinfo.goal.period;
3999 msgptr[msglen++] = tp->tinfo.goal.offset;
4000 if (DEBUG_FLAGS & DEBUG_NEGO) {
4001 PRINT_ADDR(ccb);
4002 printf ("sync msgout: ");
4003 ncr_show_msg (&cp->scsi_smsg [msglen-5]);
4004 printf (".\n");
4005 };
4006 break;
4007 case NS_WIDE:
4008 msgptr[msglen++] = MSG_EXTENDED;
4009 msgptr[msglen++] = MSG_EXT_WDTR_LEN;
4010 msgptr[msglen++] = MSG_EXT_WDTR;
4011 msgptr[msglen++] = tp->tinfo.goal.width;
4012 if (DEBUG_FLAGS & DEBUG_NEGO) {
4013 PRINT_ADDR(ccb);
4014 printf ("wide msgout: ");
4015 ncr_show_msg (&cp->scsi_smsg [msglen-4]);
4016 printf (".\n");
4017 };
4018 break;
4019 };
4020
4021 /*----------------------------------------------------
4022 **
4023 ** Build the identify message for getcc.
4024 **
4025 **----------------------------------------------------
4026 */
4027
4028 cp->scsi_smsg2 [0] = idmsg;
4029 msglen2 = 1;
4030
4031 /*----------------------------------------------------
4032 **
4033 ** Build the data descriptors
4034 **
4035 **----------------------------------------------------
4036 */
4037
4038 /* XXX JGibbs - Handle other types of I/O */
4039 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) {
4040 segments = ncr_scatter(&cp->phys,
4041 (vm_offset_t)csio->data_ptr,
4042 (vm_size_t)csio->dxfer_len);
4043
4044 if (segments < 0) {
4045 ccb->ccb_h.status = CAM_REQ_TOO_BIG;
4046 ncr_free_nccb(np, cp);
4047 crit_exit();
4048 xpt_done(ccb);
4049 return;
4050 }
4051 if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) {
4052 cp->phys.header.savep = NCB_SCRIPT_PHYS (np, data_in);
4053 cp->phys.header.goalp = cp->phys.header.savep +20 +segments*16;
4054 } else { /* CAM_DIR_OUT */
4055 cp->phys.header.savep = NCB_SCRIPT_PHYS (np, data_out);
4056 cp->phys.header.goalp = cp->phys.header.savep +20 +segments*16;
4057 }
4058 } else {
4059 cp->phys.header.savep = NCB_SCRIPT_PHYS (np, no_data);
4060 cp->phys.header.goalp = cp->phys.header.savep;
4061 }
4062
4063 cp->phys.header.lastp = cp->phys.header.savep;
4064
4065
4066 /*----------------------------------------------------
4067 **
4068 ** fill in nccb
4069 **
4070 **----------------------------------------------------
4071 **
4072 **
4073 ** physical -> virtual backlink
4074 ** Generic SCSI command
4075 */
4076 cp->phys.header.cp = cp;
4077 /*
4078 ** Startqueue
4079 */
4080 cp->phys.header.launch.l_paddr = NCB_SCRIPT_PHYS (np, select);
4081 cp->phys.header.launch.l_cmd = SCR_JUMP;
4082 /*
4083 ** select
4084 */
4085 cp->phys.select.sel_id = ccb->ccb_h.target_id;
4086 cp->phys.select.sel_scntl3 = tp->tinfo.wval;
4087 cp->phys.select.sel_sxfer = tp->tinfo.sval;
4088 /*
4089 ** message
4090 */
4091 cp->phys.smsg.addr = CCB_PHYS (cp, scsi_smsg);
4092 cp->phys.smsg.size = msglen;
4093
4094 cp->phys.smsg2.addr = CCB_PHYS (cp, scsi_smsg2);
4095 cp->phys.smsg2.size = msglen2;
4096 /*
4097 ** command
4098 */
4099 /* XXX JGibbs - Support other command types */
4100 cp->phys.cmd.addr = vtophys (csio->cdb_io.cdb_bytes);
4101 cp->phys.cmd.size = csio->cdb_len;
4102 /*
4103 ** sense command
4104 */
4105 cp->phys.scmd.addr = CCB_PHYS (cp, sensecmd);
4106 cp->phys.scmd.size = 6;
4107 /*
4108 ** patch requested size into sense command
4109 */
4110 cp->sensecmd[0] = 0x03;
4111 cp->sensecmd[1] = ccb->ccb_h.target_lun << 5;
4112 cp->sensecmd[4] = sizeof(struct scsi_sense_data);
4113 cp->sensecmd[4] = csio->sense_len;
4114 /*
4115 ** sense data
4116 */
4117 cp->phys.sense.addr = vtophys (&csio->sense_data);
4118 cp->phys.sense.size = csio->sense_len;
4119 /*
4120 ** status
4121 */
4122 cp->actualquirks = QUIRK_NOMSG;
4123 cp->host_status = nego ? HS_NEGOTIATE : HS_BUSY;
4124 cp->s_status = SCSI_STATUS_ILLEGAL;
4125 cp->parity_status = 0;
4126
4127 cp->xerr_status = XE_OK;
4128 cp->sync_status = tp->tinfo.sval;
4129 cp->nego_status = nego;
4130 cp->wide_status = tp->tinfo.wval;
4131
4132 /*----------------------------------------------------
4133 **
4134 ** Critical region: start this job.
4135 **
4136 **----------------------------------------------------
4137 */
4138
4139 /*
4140 ** reselect pattern and activate this job.
4141 */
4142
4143 cp->jump_nccb.l_cmd = (SCR_JUMP ^ IFFALSE (DATA (cp->tag)));
4144 cp->tlimit = time_second
4145 + ccb->ccb_h.timeout / 1000 + 2;
4146 cp->magic = CCB_MAGIC;
4147
4148 /*
4149 ** insert into start queue.
4150 */
4151
4152 qidx = np->squeueput + 1;
4153 if (qidx >= MAX_START)
4154 qidx = 0;
4155 np->squeue [qidx ] = NCB_SCRIPT_PHYS (np, idle);
4156 np->squeue [np->squeueput] = CCB_PHYS (cp, phys);
4157 np->squeueput = qidx;
4158
4159 if(DEBUG_FLAGS & DEBUG_QUEUE)
4160 printf("%s: queuepos=%d tryoffset=%d.\n",
4161 ncr_name (np), np->squeueput,
4162 (unsigned)(READSCRIPT(startpos[0]) -
4163 (NCB_SCRIPTH_PHYS (np, tryloop))));
4164
4165 /*
4166 ** Script processor may be waiting for reselect.
4167 ** Wake it up.
4168 */
4169 OUTB (nc_istat, SIGP);
4170
4171 /*
4172 ** and reenable interrupts
4173 */
4174 crit_exit();
4175 break;
4176 }
4177 case XPT_RESET_DEV: /* Bus Device Reset the specified SCSI device */
4178 case XPT_EN_LUN: /* Enable LUN as a target */
4179 case XPT_TARGET_IO: /* Execute target I/O request */
4180 case XPT_ACCEPT_TARGET_IO: /* Accept Host Target Mode CDB */
4181 case XPT_CONT_TARGET_IO: /* Continue Host Target I/O Connection*/
4182 case XPT_ABORT: /* Abort the specified CCB */
4183 /* XXX Implement */
4184 ccb->ccb_h.status = CAM_REQ_INVALID;
4185 xpt_done(ccb);
4186 break;
4187 case XPT_SET_TRAN_SETTINGS:
4188 {
4189 struct ccb_trans_settings *cts;
4190 tcb_p tp;
4191 u_int update_type;
4192
4193 cts = &ccb->cts;
4194 update_type = 0;
4195 if ((cts->flags & CCB_TRANS_CURRENT_SETTINGS) != 0)
4196 update_type |= NCR_TRANS_GOAL;
4197 if ((cts->flags & CCB_TRANS_USER_SETTINGS) != 0)
4198 update_type |= NCR_TRANS_USER;
4199
4200 crit_enter();
4201 tp = &np->target[ccb->ccb_h.target_id];
4202 /* Tag and disc enables */
4203 if ((cts->valid & CCB_TRANS_DISC_VALID) != 0) {
4204 if (update_type & NCR_TRANS_GOAL) {
4205 if ((cts->flags & CCB_TRANS_DISC_ENB) != 0)
4206 tp->tinfo.disc_tag |= NCR_CUR_DISCENB;
4207 else
4208 tp->tinfo.disc_tag &= ~NCR_CUR_DISCENB;
4209 }
4210
4211 if (update_type & NCR_TRANS_USER) {
4212 if ((cts->flags & CCB_TRANS_DISC_ENB) != 0)
4213 tp->tinfo.disc_tag |= NCR_USR_DISCENB;
4214 else
4215 tp->tinfo.disc_tag &= ~NCR_USR_DISCENB;
4216 }
4217
4218 }
4219
4220 if ((cts->valid & CCB_TRANS_TQ_VALID) != 0) {
4221 if (update_type & NCR_TRANS_GOAL) {
4222 if ((cts->flags & CCB_TRANS_TAG_ENB) != 0)
4223 tp->tinfo.disc_tag |= NCR_CUR_TAGENB;
4224 else
4225 tp->tinfo.disc_tag &= ~NCR_CUR_TAGENB;
4226 }
4227
4228 if (update_type & NCR_TRANS_USER) {
4229 if ((cts->flags & CCB_TRANS_TAG_ENB) != 0)
4230 tp->tinfo.disc_tag |= NCR_USR_TAGENB;
4231 else
4232 tp->tinfo.disc_tag &= ~NCR_USR_TAGENB;
4233 }
4234 }
4235
4236 /* Filter bus width and sync negotiation settings */
4237 if ((cts->valid & CCB_TRANS_BUS_WIDTH_VALID) != 0) {
4238 if (cts->bus_width > np->maxwide)
4239 cts->bus_width = np->maxwide;
4240 }
4241
4242 if (((cts->valid & CCB_TRANS_SYNC_RATE_VALID) != 0)
4243 || ((cts->valid & CCB_TRANS_SYNC_OFFSET_VALID) != 0)) {
4244 if ((cts->valid & CCB_TRANS_SYNC_RATE_VALID) != 0) {
4245 if (cts->sync_period != 0
4246 && (cts->sync_period < np->minsync))
4247 cts->sync_period = np->minsync;
4248 }
4249 if ((cts->valid & CCB_TRANS_SYNC_OFFSET_VALID) != 0) {
4250 if (cts->sync_offset == 0)
4251 cts->sync_period = 0;
4252 if (cts->sync_offset > np->maxoffs)
4253 cts->sync_offset = np->maxoffs;
4254 }
4255 }
4256 if ((update_type & NCR_TRANS_USER) != 0) {
4257 if ((cts->valid & CCB_TRANS_SYNC_RATE_VALID) != 0)
4258 tp->tinfo.user.period = cts->sync_period;
4259 if ((cts->valid & CCB_TRANS_SYNC_OFFSET_VALID) != 0)
4260 tp->tinfo.user.offset = cts->sync_offset;
4261 if ((cts->valid & CCB_TRANS_BUS_WIDTH_VALID) != 0)
4262 tp->tinfo.user.width = cts->bus_width;
4263 }
4264 if ((update_type & NCR_TRANS_GOAL) != 0) {
4265 if ((cts->valid & CCB_TRANS_SYNC_RATE_VALID) != 0)
4266 tp->tinfo.goal.period = cts->sync_period;
4267
4268 if ((cts->valid & CCB_TRANS_SYNC_OFFSET_VALID) != 0)
4269 tp->tinfo.goal.offset = cts->sync_offset;
4270
4271 if ((cts->valid & CCB_TRANS_BUS_WIDTH_VALID) != 0)
4272 tp->tinfo.goal.width = cts->bus_width;
4273 }
4274 crit_exit();
4275 ccb->ccb_h.status = CAM_REQ_CMP;
4276 xpt_done(ccb);
4277 break;
4278 }
4279 case XPT_GET_TRAN_SETTINGS:
4280 /* Get default/user set transfer settings for the target */
4281 {
4282 struct ccb_trans_settings *cts;
4283 struct ncr_transinfo *tinfo;
4284 tcb_p tp;
4285
4286 cts = &ccb->cts;
4287 tp = &np->target[ccb->ccb_h.target_id];
4288
4289 crit_enter();
4290 if ((cts->flags & CCB_TRANS_CURRENT_SETTINGS) != 0) {
4291 tinfo = &tp->tinfo.current;
4292 if (tp->tinfo.disc_tag & NCR_CUR_DISCENB)
4293 cts->flags |= CCB_TRANS_DISC_ENB;
4294 else
4295 cts->flags &= ~CCB_TRANS_DISC_ENB;
4296
4297 if (tp->tinfo.disc_tag & NCR_CUR_TAGENB)
4298 cts->flags |= CCB_TRANS_TAG_ENB;
4299 else
4300 cts->flags &= ~CCB_TRANS_TAG_ENB;
4301 } else {
4302 tinfo = &tp->tinfo.user;
4303 if (tp->tinfo.disc_tag & NCR_USR_DISCENB)
4304 cts->flags |= CCB_TRANS_DISC_ENB;
4305 else
4306 cts->flags &= ~CCB_TRANS_DISC_ENB;
4307
4308 if (tp->tinfo.disc_tag & NCR_USR_TAGENB)
4309 cts->flags |= CCB_TRANS_TAG_ENB;
4310 else
4311 cts->flags &= ~CCB_TRANS_TAG_ENB;
4312 }
4313
4314 cts->sync_period = tinfo->period;
4315 cts->sync_offset = tinfo->offset;
4316 cts->bus_width = tinfo->width;
4317
4318 crit_exit();
4319
4320 cts->valid = CCB_TRANS_SYNC_RATE_VALID
4321 | CCB_TRANS_SYNC_OFFSET_VALID
4322 | CCB_TRANS_BUS_WIDTH_VALID
4323 | CCB_TRANS_DISC_VALID
4324 | CCB_TRANS_TQ_VALID;
4325
4326 ccb->ccb_h.status = CAM_REQ_CMP;
4327 xpt_done(ccb);
4328 break;
4329 }
4330 case XPT_CALC_GEOMETRY:
4331 {
4332 struct ccb_calc_geometry *ccg;
4333 u_int32_t size_mb;
4334 u_int32_t secs_per_cylinder;
4335 int extended;
4336
4337 /* XXX JGibbs - I'm sure the NCR uses a different strategy,
4338 * but it should be able to deal with Adaptec
4339 * geometry too.
4340 */
4341 extended = 1;
4342 ccg = &ccb->ccg;
4343 size_mb = ccg->volume_size
4344 / ((1024L * 1024L) / ccg->block_size);
4345
4346 if (size_mb > 1024 && extended) {
4347 ccg->heads = 255;
4348 ccg->secs_per_track = 63;
4349 } else {
4350 ccg->heads = 64;
4351 ccg->secs_per_track = 32;
4352 }
4353 secs_per_cylinder = ccg->heads * ccg->secs_per_track;
4354 ccg->cylinders = ccg->volume_size / secs_per_cylinder;
4355 ccb->ccb_h.status = CAM_REQ_CMP;
4356 xpt_done(ccb);
4357 break;
4358 }
4359 case XPT_RESET_BUS: /* Reset the specified SCSI bus */
4360 {
4361 OUTB (nc_scntl1, CRST);
4362 ccb->ccb_h.status = CAM_REQ_CMP;
4363 DELAY(10000); /* Wait until our interrupt handler sees it */
4364 xpt_done(ccb);
4365 break;
4366 }
4367 case XPT_TERM_IO: /* Terminate the I/O process */
4368 /* XXX Implement */
4369 ccb->ccb_h.status = CAM_REQ_INVALID;
4370 xpt_done(ccb);
4371 break;
4372 case XPT_PATH_INQ: /* Path routing inquiry */
4373 {
4374 struct ccb_pathinq *cpi = &ccb->cpi;
4375
4376 cpi->version_num = 1; /* XXX??? */
4377 cpi->hba_inquiry = PI_SDTR_ABLE|PI_TAG_ABLE;
4378 if ((np->features & FE_WIDE) != 0)
4379 cpi->hba_inquiry |= PI_WIDE_16;
4380 cpi->target_sprt = 0;
4381 cpi->hba_misc = 0;
4382 cpi->hba_eng_cnt = 0;
4383 cpi->max_target = (np->features & FE_WIDE) ? 15 : 7;
4384 cpi->max_lun = MAX_LUN - 1;
4385 cpi->initiator_id = np->myaddr;
4386 cpi->bus_id = cam_sim_bus(sim);
4387 cpi->base_transfer_speed = 3300;
4388 strncpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN);
4389 strncpy(cpi->hba_vid, "Symbios", HBA_IDLEN);
4390 strncpy(cpi->dev_name, cam_sim_name(sim), DEV_IDLEN);
4391 cpi->unit_number = cam_sim_unit(sim);
4392 cpi->ccb_h.status = CAM_REQ_CMP;
4393 xpt_done(ccb);
4394 break;
4395 }
4396 default:
4397 ccb->ccb_h.status = CAM_REQ_INVALID;
4398 xpt_done(ccb);
4399 break;
4400 }
4401 }
4402
4403 /*==========================================================
4404 **
4405 **
4406 ** Complete execution of a SCSI command.
4407 ** Signal completion to the generic SCSI driver.
4408 **
4409 **
4410 **==========================================================
4411 */
4412
4413 void
4414 ncr_complete (ncb_p np, nccb_p cp)
4415 {
4416 union ccb *ccb;
4417 tcb_p tp;
4418 lcb_p lp;
4419
4420 /*
4421 ** Sanity check
4422 */
4423
4424 if (!cp || (cp->magic!=CCB_MAGIC) || !cp->ccb) return;
4425 cp->magic = 1;
4426 cp->tlimit= 0;
4427
4428 /*
4429 ** No Reselect anymore.
4430 */
4431 cp->jump_nccb.l_cmd = (SCR_JUMP);
4432
4433 /*
4434 ** No starting.
4435 */
4436 cp->phys.header.launch.l_paddr= NCB_SCRIPT_PHYS (np, idle);
4437
4438 /*
4439 ** timestamp
4440 */
4441 ncb_profile (np, cp);
4442
4443 if (DEBUG_FLAGS & DEBUG_TINY)
4444 printf ("CCB=%x STAT=%x/%x\n", (int)(intptr_t)cp & 0xfff,
4445 cp->host_status,cp->s_status);
4446
4447 ccb = cp->ccb;
4448 cp->ccb = NULL;
4449 tp = &np->target[ccb->ccb_h.target_id];
4450 lp = tp->lp[ccb->ccb_h.target_lun];
4451
4452 /*
4453 ** We do not queue more than 1 nccb per target
4454 ** with negotiation at any time. If this nccb was
4455 ** used for negotiation, clear this info in the tcb.
4456 */
4457
4458 if (cp == tp->nego_cp)
4459 tp->nego_cp = NULL;
4460
4461 /*
4462 ** Check for parity errors.
4463 */
4464 /* XXX JGibbs - What about reporting them??? */
4465
4466 if (cp->parity_status) {
4467 PRINT_ADDR(ccb);
4468 printf ("%d parity error(s), fallback.\n", cp->parity_status);
4469 /*
4470 ** fallback to asynch transfer.
4471 */
4472 tp->tinfo.goal.period = 0;
4473 tp->tinfo.goal.offset = 0;
4474 };
4475
4476 /*
4477 ** Check for extended errors.
4478 */
4479
4480 if (cp->xerr_status != XE_OK) {
4481 PRINT_ADDR(ccb);
4482 switch (cp->xerr_status) {
4483 case XE_EXTRA_DATA:
4484 printf ("extraneous data discarded.\n");
4485 break;
4486 case XE_BAD_PHASE:
4487 printf ("illegal scsi phase (4/5).\n");
4488 break;
4489 default:
4490 printf ("extended error %d.\n", cp->xerr_status);
4491 break;
4492 };
4493 if (cp->host_status==HS_COMPLETE)
4494 cp->host_status = HS_FAIL;
4495 };
4496
4497 /*
4498 ** Check the status.
4499 */
4500 if (cp->host_status == HS_COMPLETE) {
4501
4502 if (cp->s_status == SCSI_STATUS_OK) {
4503
4504 /*
4505 ** All went well.
4506 */
4507 /* XXX JGibbs - Properly calculate residual */
4508
4509 tp->bytes += ccb->csio.dxfer_len;
4510 tp->transfers ++;
4511
4512 ccb->ccb_h.status = CAM_REQ_CMP;
4513 } else if ((cp->s_status & SCSI_STATUS_SENSE) != 0) {
4514
4515 /*
4516 * XXX Could be TERMIO too. Should record
4517 * original status.
4518 */
4519 ccb->csio.scsi_status = SCSI_STATUS_CHECK_COND;
4520 cp->s_status &= ~SCSI_STATUS_SENSE;
4521 if (cp->s_status == SCSI_STATUS_OK) {
4522 ccb->ccb_h.status =
4523 CAM_AUTOSNS_VALID|CAM_SCSI_STATUS_ERROR;
4524 } else {
4525 ccb->ccb_h.status = CAM_AUTOSENSE_FAIL;
4526 }
4527 } else {
4528 ccb->ccb_h.status = CAM_SCSI_STATUS_ERROR;
4529 ccb->csio.scsi_status = cp->s_status;
4530 }
4531
4532
4533 } else if (cp->host_status == HS_SEL_TIMEOUT) {
4534
4535 /*
4536 ** Device failed selection
4537 */
4538 ccb->ccb_h.status = CAM_SEL_TIMEOUT;
4539
4540 } else if (cp->host_status == HS_TIMEOUT) {
4541
4542 /*
4543 ** No response
4544 */
4545 ccb->ccb_h.status = CAM_CMD_TIMEOUT;
4546 } else if (cp->host_status == HS_STALL) {
4547 ccb->ccb_h.status = CAM_REQUEUE_REQ;
4548 } else {
4549
4550 /*
4551 ** Other protocol messes
4552 */
4553 PRINT_ADDR(ccb);
4554 printf ("COMMAND FAILED (%x %x) @%p.\n",
4555 cp->host_status, cp->s_status, cp);
4556
4557 ccb->ccb_h.status = CAM_CMD_TIMEOUT;
4558 }
4559
4560 if ((ccb->ccb_h.status & CAM_STATUS_MASK) != CAM_REQ_CMP) {
4561 xpt_freeze_devq(ccb->ccb_h.path, /*count*/1);
4562 ccb->ccb_h.status |= CAM_DEV_QFRZN;
4563 }
4564
4565 /*
4566 ** Free this nccb
4567 */
4568 ncr_free_nccb (np, cp);
4569
4570 /*
4571 ** signal completion to generic driver.
4572 */
4573 xpt_done (ccb);
4574 }
4575
4576 /*==========================================================
4577 **
4578 **
4579 ** Signal all (or one) control block done.
4580 **
4581 **
4582 **==========================================================
4583 */
4584
4585 void
4586 ncr_wakeup (ncb_p np, u_long code)
4587 {
4588 /*
4589 ** Starting at the default nccb and following
4590 ** the links, complete all jobs with a
4591 ** host_status greater than "disconnect".
4592 **
4593 ** If the "code" parameter is not zero,
4594 ** complete all jobs that are not IDLE.
4595 */
4596
4597 nccb_p cp = np->link_nccb;
4598 while (cp) {
4599 switch (cp->host_status) {
4600
4601 case HS_IDLE:
4602 break;
4603
4604 case HS_DISCONNECT:
4605 if(DEBUG_FLAGS & DEBUG_TINY) printf ("D");
4606 /* fall through */
4607
4608 case HS_BUSY:
4609 case HS_NEGOTIATE:
4610 if (!code) break;
4611 cp->host_status = code;
4612
4613 /* fall through */
4614
4615 default:
4616 ncr_complete (np, cp);
4617 break;
4618 };
4619 cp = cp -> link_nccb;
4620 };
4621 }
4622
4623 static void
4624 ncr_freeze_devq (ncb_p np, struct cam_path *path)
4625 {
4626 nccb_p cp;
4627 int i;
4628 int count;
4629 int firstskip;
4630 /*
4631 ** Starting at the first nccb and following
4632 ** the links, complete all jobs that match
4633 ** the passed in path and are in the start queue.
4634 */
4635
4636 cp = np->link_nccb;
4637 count = 0;
4638 firstskip = 0;
4639 while (cp) {
4640 switch (cp->host_status) {
4641
4642 case HS_BUSY:
4643 case HS_NEGOTIATE:
4644 if ((cp->phys.header.launch.l_paddr
4645 == NCB_SCRIPT_PHYS (np, select))
4646 && (xpt_path_comp(path, cp->ccb->ccb_h.path) >= 0)) {
4647
4648 /* Mark for removal from the start queue */
4649 for (i = 1; i < MAX_START; i++) {
4650 int idx;
4651
4652 idx = np->squeueput - i;
4653
4654 if (idx < 0)
4655 idx = MAX_START + idx;
4656 if (np->squeue[idx]
4657 == CCB_PHYS(cp, phys)) {
4658 np->squeue[idx] =
4659 NCB_SCRIPT_PHYS (np, skip);
4660 if (i > firstskip)
4661 firstskip = i;
4662 break;
4663 }
4664 }
4665 cp->host_status=HS_STALL;
4666 ncr_complete (np, cp);
4667 count++;
4668 }
4669 break;
4670 default:
4671 break;
4672 }
4673 cp = cp->link_nccb;
4674 }
4675
4676 if (count > 0) {
4677 int j;
4678 int bidx;
4679
4680 /* Compress the start queue */
4681 j = 0;
4682 bidx = np->squeueput;
4683 i = np->squeueput - firstskip;
4684 if (i < 0)
4685 i = MAX_START + i;
4686 for (;;) {
4687
4688 bidx = i - j;
4689 if (bidx < 0)
4690 bidx = MAX_START + bidx;
4691
4692 if (np->squeue[i] == NCB_SCRIPT_PHYS (np, skip)) {
4693 j++;
4694 } else if (j != 0) {
4695 np->squeue[bidx] = np->squeue[i];
4696 if (np->squeue[bidx]
4697 == NCB_SCRIPT_PHYS(np, idle))
4698 break;
4699 }
4700 i = (i + 1) % MAX_START;
4701 }
4702 np->squeueput = bidx;
4703 }
4704 }
4705
4706 /*==========================================================
4707 **
4708 **
4709 ** Start NCR chip.
4710 **
4711 **
4712 **==========================================================
4713 */
4714
4715 void
4716 ncr_init(ncb_p np, char * msg, u_long code)
4717 {
4718 int i;
4719
4720 /*
4721 ** Reset chip.
4722 */
4723
4724 OUTB (nc_istat, SRST);
4725 DELAY (1000);
4726 OUTB (nc_istat, 0);
4727
4728 /*
4729 ** Message.
4730 */
4731
4732 if (msg) printf ("%s: restart (%s).\n", ncr_name (np), msg);
4733
4734 /*
4735 ** Clear Start Queue
4736 */
4737
4738 for (i=0;i<MAX_START;i++)
4739 np -> squeue [i] = NCB_SCRIPT_PHYS (np, idle);
4740
4741 /*
4742 ** Start at first entry.
4743 */
4744
4745 np->squeueput = 0;
4746 WRITESCRIPT(startpos[0], NCB_SCRIPTH_PHYS (np, tryloop));
4747 WRITESCRIPT(start0 [0], SCR_INT ^ IFFALSE (0));
4748
4749 /*
4750 ** Wakeup all pending jobs.
4751 */
4752
4753 ncr_wakeup (np, code);
4754
4755 /*
4756 ** Init chip.
4757 */
4758
4759 OUTB (nc_istat, 0x00 ); /* Remove Reset, abort ... */
4760 OUTB (nc_scntl0, 0xca ); /* full arb., ena parity, par->ATN */
4761 OUTB (nc_scntl1, 0x00 ); /* odd parity, and remove CRST!! */
4762 ncr_selectclock(np, np->rv_scntl3); /* Select SCSI clock */
4763 OUTB (nc_scid , RRE|np->myaddr);/* host adapter SCSI address */
4764 OUTW (nc_respid, 1ul<<np->myaddr);/* id to respond to */
4765 OUTB (nc_istat , SIGP ); /* Signal Process */
4766 OUTB (nc_dmode , np->rv_dmode); /* XXX modify burstlen ??? */
4767 OUTB (nc_dcntl , np->rv_dcntl);
4768 OUTB (nc_ctest3, np->rv_ctest3);
4769 OUTB (nc_ctest5, np->rv_ctest5);
4770 OUTB (nc_ctest4, np->rv_ctest4);/* enable master parity checking */
4771 OUTB (nc_stest2, np->rv_stest2|EXT); /* Extended Sreq/Sack filtering */
4772 OUTB (nc_stest3, TE ); /* TolerANT enable */
4773 OUTB (nc_stime0, 0x0b ); /* HTH = disabled, STO = 0.1 sec. */
4774
4775 if (bootverbose >= 2) {
4776 printf ("\tACTUAL values:SCNTL3:%02x DMODE:%02x DCNTL:%02x\n",
4777 np->rv_scntl3, np->rv_dmode, np->rv_dcntl);
4778 printf ("\t CTEST3:%02x CTEST4:%02x CTEST5:%02x\n",
4779 np->rv_ctest3, np->rv_ctest4, np->rv_ctest5);
4780 }
4781
4782 /*
4783 ** Enable GPIO0 pin for writing if LED support.
4784 */
4785
4786 if (np->features & FE_LED0) {
4787 OUTOFFB (nc_gpcntl, 0x01);
4788 }
4789
4790 /*
4791 ** Fill in target structure.
4792 */
4793 for (i=0;i<MAX_TARGET;i++) {
4794 tcb_p tp = &np->target[i];
4795
4796 tp->tinfo.sval = 0;
4797 tp->tinfo.wval = np->rv_scntl3;
4798
4799 tp->tinfo.current.period = 0;
4800 tp->tinfo.current.offset = 0;
4801 tp->tinfo.current.width = MSG_EXT_WDTR_BUS_8_BIT;
4802 }
4803
4804 /*
4805 ** enable ints
4806 */
4807
4808 OUTW (nc_sien , STO|HTH|MA|SGE|UDC|RST);
4809 OUTB (nc_dien , MDPE|BF|ABRT|SSI|SIR|IID);
4810
4811 /*
4812 ** Start script processor.
4813 */
4814
4815 OUTL (nc_dsp, NCB_SCRIPT_PHYS (np, start));
4816
4817 /*
4818 * Notify the XPT of the event
4819 */
4820 if (code == HS_RESET)
4821 xpt_async(AC_BUS_RESET, np->path, NULL);
4822 }
4823
4824 static void
4825 ncr_poll(struct cam_sim *sim)
4826 {
4827 ncr_intr(cam_sim_softc(sim));
4828 }
4829
4830
4831 /*==========================================================
4832 **
4833 ** Get clock factor and sync divisor for a given
4834 ** synchronous factor period.
4835 ** Returns the clock factor (in sxfer) and scntl3
4836 ** synchronous divisor field.
4837 **
4838 **==========================================================
4839 */
4840
4841 static void ncr_getsync(ncb_p np, u_char sfac, u_char *fakp, u_char *scntl3p)
4842 {
4843 u_long clk = np->clock_khz; /* SCSI clock frequency in kHz */
4844 int div = np->clock_divn; /* Number of divisors supported */
4845 u_long fak; /* Sync factor in sxfer */
4846 u_long per; /* Period in tenths of ns */
4847 u_long kpc; /* (per * clk) */
4848
4849 /*
4850 ** Compute the synchronous period in tenths of nano-seconds
4851 */
4852 if (sfac <= 10) per = 250;
4853 else if (sfac == 11) per = 303;
4854 else if (sfac == 12) per = 500;
4855 else per = 40 * sfac;
4856
4857 /*
4858 ** Look for the greatest clock divisor that allows an
4859 ** input speed faster than the period.
4860 */
4861 kpc = per * clk;
4862 while (--div >= 0)
4863 if (kpc >= (div_10M[div] * 4)) break;
4864
4865 /*
4866 ** Calculate the lowest clock factor that allows an output
4867 ** speed not faster than the period.
4868 */
4869 fak = (kpc - 1) / div_10M[div] + 1;
4870
4871 #if 0 /* You can #if 1 if you think this optimization is usefull */
4872
4873 per = (fak * div_10M[div]) / clk;
4874
4875 /*
4876 ** Why not to try the immediate lower divisor and to choose
4877 ** the one that allows the fastest output speed ?
4878 ** We dont want input speed too much greater than output speed.
4879 */
4880 if (div >= 1 && fak < 6) {
4881 u_long fak2, per2;
4882 fak2 = (kpc - 1) / div_10M[div-1] + 1;
4883 per2 = (fak2 * div_10M[div-1]) / clk;
4884 if (per2 < per && fak2 <= 6) {
4885 fak = fak2;
4886 per = per2;
4887 --div;
4888 }
4889 }
4890 #endif
4891
4892 if (fak < 4) fak = 4; /* Should never happen, too bad ... */
4893
4894 /*
4895 ** Compute and return sync parameters for the ncr
4896 */
4897 *fakp = fak - 4;
4898 *scntl3p = ((div+1) << 4) + (sfac < 25 ? 0x80 : 0);
4899 }
4900
4901 /*==========================================================
4902 **
4903 ** Switch sync mode for current job and its target
4904 **
4905 **==========================================================
4906 */
4907
4908 static void
4909 ncr_setsync(ncb_p np, nccb_p cp, u_char scntl3, u_char sxfer, u_char period)
4910 {
4911 union ccb *ccb;
4912 struct ccb_trans_settings neg;
4913 tcb_p tp;
4914 int div;
4915 u_int target = INB (nc_sdid) & 0x0f;
4916 u_int period_10ns;
4917
4918 assert (cp);
4919 if (!cp) return;
4920
4921 ccb = cp->ccb;
4922 assert (ccb);
4923 if (!ccb) return;
4924 assert (target == ccb->ccb_h.target_id);
4925
4926 tp = &np->target[target];
4927
4928 if (!scntl3 || !(sxfer & 0x1f))
4929 scntl3 = np->rv_scntl3;
4930 scntl3 = (scntl3 & 0xf0) | (tp->tinfo.wval & EWS)
4931 | (np->rv_scntl3 & 0x07);
4932
4933 /*
4934 ** Deduce the value of controller sync period from scntl3.
4935 ** period is in tenths of nano-seconds.
4936 */
4937
4938 div = ((scntl3 >> 4) & 0x7);
4939 if ((sxfer & 0x1f) && div)
4940 period_10ns =
4941 (((sxfer>>5)+4)*div_10M[div-1])/np->clock_khz;
4942 else
4943 period_10ns = 0;
4944
4945 tp->tinfo.goal.period = period;
4946 tp->tinfo.goal.offset = sxfer & 0x1f;
4947 tp->tinfo.current.period = period;
4948 tp->tinfo.current.offset = sxfer & 0x1f;
4949
4950 /*
4951 ** Stop there if sync parameters are unchanged
4952 */
4953 if (tp->tinfo.sval == sxfer && tp->tinfo.wval == scntl3) return;
4954 tp->tinfo.sval = sxfer;
4955 tp->tinfo.wval = scntl3;
4956
4957 if (sxfer & 0x1f) {
4958 /*
4959 ** Disable extended Sreq/Sack filtering
4960 */
4961 if (period_10ns <= 2000) OUTOFFB (nc_stest2, EXT);
4962 }
4963
4964 /*
4965 ** Tell the SCSI layer about the
4966 ** new transfer parameters.
4967 */
4968 neg.sync_period = period;
4969 neg.sync_offset = sxfer & 0x1f;
4970 neg.valid = CCB_TRANS_SYNC_RATE_VALID
4971 | CCB_TRANS_SYNC_OFFSET_VALID;
4972 xpt_setup_ccb(&neg.ccb_h, ccb->ccb_h.path,
4973 /*priority*/1);
4974 xpt_async(AC_TRANSFER_NEG, ccb->ccb_h.path, &neg);
4975
4976 /*
4977 ** set actual value and sync_status
4978 */
4979 OUTB (nc_sxfer, sxfer);
4980 np->sync_st = sxfer;
4981 OUTB (nc_scntl3, scntl3);
4982 np->wide_st = scntl3;
4983
4984 /*
4985 ** patch ALL nccbs of this target.
4986 */
4987 for (cp = np->link_nccb; cp; cp = cp->link_nccb) {
4988 if (!cp->ccb) continue;
4989 if (cp->ccb->ccb_h.target_id != target) continue;
4990 cp->sync_status = sxfer;
4991 cp->wide_status = scntl3;
4992 };
4993 }
4994
4995 /*==========================================================
4996 **
4997 ** Switch wide mode for current job and its target
4998 ** SCSI specs say: a SCSI device that accepts a WDTR
4999 ** message shall reset the synchronous agreement to
5000 ** asynchronous mode.
5001 **
5002 **==========================================================
5003 */
5004
5005 static void ncr_setwide (ncb_p np, nccb_p cp, u_char wide, u_char ack)
5006 {
5007 union ccb *ccb;
5008 struct ccb_trans_settings neg;
5009 u_int target = INB (nc_sdid) & 0x0f;
5010 tcb_p tp;
5011 u_char scntl3;
5012 u_char sxfer;
5013
5014 assert (cp);
5015 if (!cp) return;
5016
5017 ccb = cp->ccb;
5018 assert (ccb);
5019 if (!ccb) return;
5020 assert (target == ccb->ccb_h.target_id);
5021
5022 tp = &np->target[target];
5023 tp->tinfo.current.width = wide;
5024 tp->tinfo.goal.width = wide;
5025 tp->tinfo.current.period = 0;
5026 tp->tinfo.current.offset = 0;
5027
5028 scntl3 = (tp->tinfo.wval & (~EWS)) | (wide ? EWS : 0);
5029
5030 sxfer = ack ? 0 : tp->tinfo.sval;
5031
5032 /*
5033 ** Stop there if sync/wide parameters are unchanged
5034 */
5035 if (tp->tinfo.sval == sxfer && tp->tinfo.wval == scntl3) return;
5036 tp->tinfo.sval = sxfer;
5037 tp->tinfo.wval = scntl3;
5038
5039 /* Tell the SCSI layer about the new transfer params */
5040 neg.bus_width = (scntl3 & EWS) ? MSG_EXT_WDTR_BUS_16_BIT
5041 : MSG_EXT_WDTR_BUS_8_BIT;
5042 neg.sync_period = 0;
5043 neg.sync_offset = 0;
5044 neg.valid = CCB_TRANS_BUS_WIDTH_VALID
5045 | CCB_TRANS_SYNC_RATE_VALID
5046 | CCB_TRANS_SYNC_OFFSET_VALID;
5047 xpt_setup_ccb(&neg.ccb_h, ccb->ccb_h.path,
5048 /*priority*/1);
5049 xpt_async(AC_TRANSFER_NEG, ccb->ccb_h.path, &neg);
5050
5051 /*
5052 ** set actual value and sync_status
5053 */
5054 OUTB (nc_sxfer, sxfer);
5055 np->sync_st = sxfer;
5056 OUTB (nc_scntl3, scntl3);
5057 np->wide_st = scntl3;
5058
5059 /*
5060 ** patch ALL nccbs of this target.
5061 */
5062 for (cp = np->link_nccb; cp; cp = cp->link_nccb) {
5063 if (!cp->ccb) continue;
5064 if (cp->ccb->ccb_h.target_id != target) continue;
5065 cp->sync_status = sxfer;
5066 cp->wide_status = scntl3;
5067 };
5068 }
5069
5070 /*==========================================================
5071 **
5072 **
5073 ** ncr timeout handler.
5074 **
5075 **
5076 **==========================================================
5077 **
5078 ** Misused to keep the driver running when
5079 ** interrupts are not configured correctly.
5080 **
5081 **----------------------------------------------------------
5082 */
5083
5084 static void
5085 ncr_timeout (void *arg)
5086 {
5087 ncb_p np = arg;
5088 time_t thistime = time_second;
5089 ticks_t step = np->ticks;
5090 u_long count = 0;
5091 long signed t;
5092 nccb_p cp;
5093
5094 if (np->lasttime != thistime) {
5095 /*
5096 ** block ncr interrupts
5097 */
5098 crit_enter();
5099 np->lasttime = thistime;
5100
5101 /*----------------------------------------------------
5102 **
5103 ** handle ncr chip timeouts
5104 **
5105 ** Assumption:
5106 ** We have a chance to arbitrate for the
5107 ** SCSI bus at least every 10 seconds.
5108 **
5109 **----------------------------------------------------
5110 */
5111
5112 t = thistime - np->heartbeat;
5113
5114 if (t<2) np->latetime=0; else np->latetime++;
5115
5116 if (np->latetime>2) {
5117 /*
5118 ** If there are no requests, the script
5119 ** processor will sleep on SEL_WAIT_RESEL.
5120 ** But we have to check whether it died.
5121 ** Let's try to wake it up.
5122 */
5123 OUTB (nc_istat, SIGP);
5124 };
5125
5126 /*----------------------------------------------------
5127 **
5128 ** handle nccb timeouts
5129 **
5130 **----------------------------------------------------
5131 */
5132
5133 for (cp=np->link_nccb; cp; cp=cp->link_nccb) {
5134 /*
5135 ** look for timed out nccbs.
5136 */
5137 if (!cp->host_status) continue;
5138 count++;
5139 if (cp->tlimit > thistime) continue;
5140
5141 /*
5142 ** Disable reselect.
5143 ** Remove it from startqueue.
5144 */
5145 cp->jump_nccb.l_cmd = (SCR_JUMP);
5146 if (cp->phys.header.launch.l_paddr ==
5147 NCB_SCRIPT_PHYS (np, select)) {
5148 printf ("%s: timeout nccb=%p (skip)\n",
5149 ncr_name (np), cp);
5150 cp->phys.header.launch.l_paddr
5151 = NCB_SCRIPT_PHYS (np, skip);
5152 };
5153
5154 switch (cp->host_status) {
5155
5156 case HS_BUSY:
5157 case HS_NEGOTIATE:
5158 /* fall through */
5159 case HS_DISCONNECT:
5160 cp->host_status=HS_TIMEOUT;
5161 };
5162 cp->tag = 0;
5163
5164 /*
5165 ** wakeup this nccb.
5166 */
5167 ncr_complete (np, cp);
5168 };
5169 crit_exit();
5170 }
5171
5172 callout_reset(&np->timeout_ch, step ? step : 1, ncr_timeout, np);
5173
5174 if (INB(nc_istat) & (INTF|SIP|DIP)) {
5175
5176 /*
5177 ** Process pending interrupts.
5178 */
5179
5180 crit_enter();
5181 if (DEBUG_FLAGS & DEBUG_TINY) printf ("{");
5182 ncr_exception (np);
5183 if (DEBUG_FLAGS & DEBUG_TINY) printf ("}");
5184 crit_exit();
5185 };
5186 }
5187
5188 /*==========================================================
5189 **
5190 ** log message for real hard errors
5191 **
5192 ** "ncr0 targ 0?: ERROR (ds:si) (so-si-sd) (sxfer/scntl3) @ name (dsp:dbc)."
5193 ** " reg: r0 r1 r2 r3 r4 r5 r6 ..... rf."
5194 **
5195 ** exception register:
5196 ** ds: dstat
5197 ** si: sist
5198 **
5199 ** SCSI bus lines:
5200 ** so: control lines as driver by NCR.
5201 ** si: control lines as seen by NCR.
5202 ** sd: scsi data lines as seen by NCR.
5203 **
5204 ** wide/fastmode:
5205 ** sxfer: (see the manual)
5206 ** scntl3: (see the manual)
5207 **
5208 ** current script command:
5209 ** dsp: script adress (relative to start of script).
5210 ** dbc: first word of script command.
5211 **
5212 ** First 16 register of the chip:
5213 ** r0..rf
5214 **
5215 **==========================================================
5216 */
5217
5218 static void ncr_log_hard_error(ncb_p np, u_short sist, u_char dstat)
5219 {
5220 u_int32_t dsp;
5221 int script_ofs;
5222 int script_size;
5223 char *script_name;
5224 u_char *script_base;
5225 int i;
5226
5227 dsp = INL (nc_dsp);
5228
5229 if (np->p_script < dsp &&
5230 dsp <= np->p_script + sizeof(struct script)) {
5231 script_ofs = dsp - np->p_script;
5232 script_size = sizeof(struct script);
5233 script_base = (u_char *) np->script;
5234 script_name = "script";
5235 }
5236 else if (np->p_scripth < dsp &&
5237 dsp <= np->p_scripth + sizeof(struct scripth)) {
5238 script_ofs = dsp - np->p_scripth;
5239 script_size = sizeof(struct scripth);
5240 script_base = (u_char *) np->scripth;
5241 script_name = "scripth";
5242 } else {
5243 script_ofs = dsp;
5244 script_size = 0;
5245 script_base = 0;
5246 script_name = "mem";
5247 }
5248
5249 printf ("%s:%d: ERROR (%x:%x) (%x-%x-%x) (%x/%x) @ (%s %x:%08x).\n",
5250 ncr_name (np), (unsigned)INB (nc_sdid)&0x0f, dstat, sist,
5251 (unsigned)INB (nc_socl), (unsigned)INB (nc_sbcl), (unsigned)INB (nc_sbdl),
5252 (unsigned)INB (nc_sxfer),(unsigned)INB (nc_scntl3), script_name, script_ofs,
5253 (unsigned)INL (nc_dbc));
5254
5255 if (((script_ofs & 3) == 0) &&
5256 (unsigned)script_ofs < script_size) {
5257 printf ("%s: script cmd = %08x\n", ncr_name(np),
5258 (int)READSCRIPT_OFF(script_base, script_ofs));
5259 }
5260
5261 printf ("%s: regdump:", ncr_name(np));
5262 for (i=0; i<16;i++)
5263 printf (" %02x", (unsigned)INB_OFF(i));
5264 printf (".\n");
5265 }
5266
5267 /*==========================================================
5268 **
5269 **
5270 ** ncr chip exception handler.
5271 **
5272 **
5273 **==========================================================
5274 */
5275
5276 void ncr_exception (ncb_p np)
5277 {
5278 u_char istat, dstat;
5279 u_short sist;
5280
5281 /*
5282 ** interrupt on the fly ?
5283 */
5284 while ((istat = INB (nc_istat)) & INTF) {
5285 if (DEBUG_FLAGS & DEBUG_TINY) printf ("F ");
5286 OUTB (nc_istat, INTF);
5287 np->profile.num_fly++;
5288 ncr_wakeup (np, 0);
5289 };
5290 if (!(istat & (SIP|DIP))) {
5291 return;
5292 }
5293
5294 /*
5295 ** Steinbach's Guideline for Systems Programming:
5296 ** Never test for an error condition you don't know how to handle.
5297 */
5298
5299 sist = (istat & SIP) ? INW (nc_sist) : 0;
5300 dstat = (istat & DIP) ? INB (nc_dstat) : 0;
5301 np->profile.num_int++;
5302
5303 if (DEBUG_FLAGS & DEBUG_TINY)
5304 printf ("<%d|%x:%x|%x:%x>",
5305 INB(nc_scr0),
5306 dstat,sist,
5307 (unsigned)INL(nc_dsp),
5308 (unsigned)INL(nc_dbc));
5309 if ((dstat==DFE) && (sist==PAR)) return;
5310
5311 /*==========================================================
5312 **
5313 ** First the normal cases.
5314 **
5315 **==========================================================
5316 */
5317 /*-------------------------------------------
5318 ** SCSI reset
5319 **-------------------------------------------
5320 */
5321
5322 if (sist & RST) {
5323 ncr_init (np, bootverbose ? "scsi reset" : NULL, HS_RESET);
5324 return;
5325 };
5326
5327 /*-------------------------------------------
5328 ** selection timeout
5329 **
5330 ** IID excluded from dstat mask!
5331 ** (chip bug)
5332 **-------------------------------------------
5333 */
5334
5335 if ((sist & STO) &&
5336 !(sist & (GEN|HTH|MA|SGE|UDC|RST|PAR)) &&
5337 !(dstat & (MDPE|BF|ABRT|SIR))) {
5338 ncr_int_sto (np);
5339 return;
5340 };
5341
5342 /*-------------------------------------------
5343 ** Phase mismatch.
5344 **-------------------------------------------
5345 */
5346
5347 if ((sist & MA) &&
5348 !(sist & (STO|GEN|HTH|SGE|UDC|RST|PAR)) &&
5349 !(dstat & (MDPE|BF|ABRT|SIR|IID))) {
5350 ncr_int_ma (np, dstat);
5351 return;
5352 };
5353
5354 /*----------------------------------------
5355 ** move command with length 0
5356 **----------------------------------------
5357 */
5358
5359 if ((dstat & IID) &&
5360 !(sist & (STO|GEN|HTH|MA|SGE|UDC|RST|PAR)) &&
5361 !(dstat & (MDPE|BF|ABRT|SIR)) &&
5362 ((INL(nc_dbc) & 0xf8000000) == SCR_MOVE_TBL)) {
5363 /*
5364 ** Target wants more data than available.
5365 ** The "no_data" script will do it.
5366 */
5367 OUTL (nc_dsp, NCB_SCRIPT_PHYS (np, no_data));
5368 return;
5369 };
5370
5371 /*-------------------------------------------
5372 ** Programmed interrupt
5373 **-------------------------------------------
5374 */
5375
5376 if ((dstat & SIR) &&
5377 !(sist & (STO|GEN|HTH|MA|SGE|UDC|RST|PAR)) &&
5378 !(dstat & (MDPE|BF|ABRT|IID)) &&
5379 (INB(nc_dsps) <= SIR_MAX)) {
5380 ncr_int_sir (np);
5381 return;
5382 };
5383
5384 /*========================================
5385 ** log message for real hard errors
5386 **========================================
5387 */
5388
5389 ncr_log_hard_error(np, sist, dstat);
5390
5391 /*========================================
5392 ** do the register dump
5393 **========================================
5394 */
5395
5396 if (time_second - np->regtime > 10) {
5397 int i;
5398 np->regtime = time_second;
5399 for (i=0; i<sizeof(np->regdump); i++)
5400 ((volatile char*)&np->regdump)[i] = INB_OFF(i);
5401 np->regdump.nc_dstat = dstat;
5402 np->regdump.nc_sist = sist;
5403 };
5404
5405
5406 /*----------------------------------------
5407 ** clean up the dma fifo
5408 **----------------------------------------
5409 */
5410
5411 if ( (INB(nc_sstat0) & (ILF|ORF|OLF) ) ||
5412 (INB(nc_sstat1) & (FF3210) ) ||
5413 (INB(nc_sstat2) & (ILF1|ORF1|OLF1)) || /* wide .. */
5414 !(dstat & DFE)) {
5415 printf ("%s: have to clear fifos.\n", ncr_name (np));
5416 OUTB (nc_stest3, TE|CSF); /* clear scsi fifo */
5417 OUTB (nc_ctest3, np->rv_ctest3 | CLF);
5418 /* clear dma fifo */
5419 }
5420
5421 /*----------------------------------------
5422 ** handshake timeout
5423 **----------------------------------------
5424 */
5425
5426 if (sist & HTH) {
5427 printf ("%s: handshake timeout\n", ncr_name(np));
5428 OUTB (nc_scntl1, CRST);
5429 DELAY (1000);
5430 OUTB (nc_scntl1, 0x00);
5431 OUTB (nc_scr0, HS_FAIL);
5432 OUTL (nc_dsp, NCB_SCRIPT_PHYS (np, cleanup));
5433 return;
5434 }
5435
5436 /*----------------------------------------
5437 ** unexpected disconnect
5438 **----------------------------------------
5439 */
5440
5441 if ((sist & UDC) &&
5442 !(sist & (STO|GEN|HTH|MA|SGE|RST|PAR)) &&
5443 !(dstat & (MDPE|BF|ABRT|SIR|IID))) {
5444 OUTB (nc_scr0, HS_UNEXPECTED);
5445 OUTL (nc_dsp, NCB_SCRIPT_PHYS (np, cleanup));
5446 return;
5447 };
5448
5449 /*----------------------------------------
5450 ** cannot disconnect
5451 **----------------------------------------
5452 */
5453
5454 if ((dstat & IID) &&
5455 !(sist & (STO|GEN|HTH|MA|SGE|UDC|RST|PAR)) &&
5456 !(dstat & (MDPE|BF|ABRT|SIR)) &&
5457 ((INL(nc_dbc) & 0xf8000000) == SCR_WAIT_DISC)) {
5458 /*
5459 ** Unexpected data cycle while waiting for disconnect.
5460 */
5461 if (INB(nc_sstat2) & LDSC) {
5462 /*
5463 ** It's an early reconnect.
5464 ** Let's continue ...
5465 */
5466 OUTB (nc_dcntl, np->rv_dcntl | STD);
5467 /*
5468 ** info message
5469 */
5470 printf ("%s: INFO: LDSC while IID.\n",
5471 ncr_name (np));
5472 return;
5473 };
5474 printf ("%s: target %d doesn't release the bus.\n",
5475 ncr_name (np), INB (nc_sdid)&0x0f);
5476 /*
5477 ** return without restarting the NCR.
5478 ** timeout will do the real work.
5479 */
5480 return;
5481 };
5482
5483 /*----------------------------------------
5484 ** single step
5485 **----------------------------------------
5486 */
5487
5488 if ((dstat & SSI) &&
5489 !(sist & (STO|GEN|HTH|MA|SGE|UDC|RST|PAR)) &&
5490 !(dstat & (MDPE|BF|ABRT|SIR|IID))) {
5491 OUTB (nc_dcntl, np->rv_dcntl | STD);
5492 return;
5493 };
5494
5495 /*
5496 ** @RECOVER@ HTH, SGE, ABRT.
5497 **
5498 ** We should try to recover from these interrupts.
5499 ** They may occur if there are problems with synch transfers, or
5500 ** if targets are switched on or off while the driver is running.
5501 */
5502
5503 if (sist & SGE) {
5504 /* clear scsi offsets */
5505 OUTB (nc_ctest3, np->rv_ctest3 | CLF);
5506 }
5507
5508 /*
5509 ** Freeze controller to be able to read the messages.
5510 */
5511
5512 if (DEBUG_FLAGS & DEBUG_FREEZE) {
5513 int i;
5514 unsigned char val;
5515 for (i=0; i<0x60; i++) {
5516 switch (i%16) {
5517
5518 case 0:
5519 printf ("%s: reg[%d0]: ",
5520 ncr_name(np),i/16);
5521 break;
5522 case 4:
5523 case 8:
5524 case 12:
5525 printf (" ");
5526 break;
5527 };
5528 val = bus_space_read_1(np->bst, np->bsh, i);
5529 printf (" %x%x", val/16, val%16);
5530 if (i%16==15) printf (".\n");
5531 };
5532
5533 callout_stop(&np->timeout_ch);
5534
5535 printf ("%s: halted!\n", ncr_name(np));
5536 /*
5537 ** don't restart controller ...
5538 */
5539 OUTB (nc_istat, SRST);
5540 return;
5541 };
5542
5543 #ifdef NCR_FREEZE
5544 /*
5545 ** Freeze system to be able to read the messages.
5546 */
5547 printf ("ncr: fatal error: system halted - press reset to reboot ...");
5548 crit_enter();
5549 for (;;);
5550 #endif
5551
5552 /*
5553 ** sorry, have to kill ALL jobs ...
5554 */
5555
5556 ncr_init (np, "fatal error", HS_FAIL);
5557 }
5558
5559 /*==========================================================
5560 **
5561 ** ncr chip exception handler for selection timeout
5562 **
5563 **==========================================================
5564 **
5565 ** There seems to be a bug in the 53c810.
5566 ** Although a STO-Interrupt is pending,
5567 ** it continues executing script commands.
5568 ** But it will fail and interrupt (IID) on
5569 ** the next instruction where it's looking
5570 ** for a valid phase.
5571 **
5572 **----------------------------------------------------------
5573 */
5574
5575 void ncr_int_sto (ncb_p np)
5576 {
5577 u_long dsa, scratcha, diff;
5578 nccb_p cp;
5579 if (DEBUG_FLAGS & DEBUG_TINY) printf ("T");
5580
5581 /*
5582 ** look for nccb and set the status.
5583 */
5584
5585 dsa = INL (nc_dsa);
5586 cp = np->link_nccb;
5587 while (cp && (CCB_PHYS (cp, phys) != dsa))
5588 cp = cp->link_nccb;
5589
5590 if (cp) {
5591 cp-> host_status = HS_SEL_TIMEOUT;
5592 ncr_complete (np, cp);
5593 };
5594
5595 /*
5596 ** repair start queue
5597 */
5598
5599 scratcha = INL (nc_scratcha);
5600 diff = scratcha - NCB_SCRIPTH_PHYS (np, tryloop);
5601
5602 /* assert ((diff <= MAX_START * 20) && !(diff % 20));*/
5603
5604 if ((diff <= MAX_START * 20) && !(diff % 20)) {
5605 WRITESCRIPT(startpos[0], scratcha);
5606 OUTL (nc_dsp, NCB_SCRIPT_PHYS (np, start));
5607 return;
5608 };
5609 ncr_init (np, "selection timeout", HS_FAIL);
5610 }
5611
5612 /*==========================================================
5613 **
5614 **
5615 ** ncr chip exception handler for phase errors.
5616 **
5617 **
5618 **==========================================================
5619 **
5620 ** We have to construct a new transfer descriptor,
5621 ** to transfer the rest of the current block.
5622 **
5623 **----------------------------------------------------------
5624 */
5625
5626 static void ncr_int_ma (ncb_p np, u_char dstat)
5627 {
5628 u_int32_t dbc;
5629 u_int32_t rest;
5630 u_int32_t dsa;
5631 u_int32_t dsp;
5632 u_int32_t nxtdsp;
5633 volatile void *vdsp_base;
5634 size_t vdsp_off;
5635 u_int32_t oadr, olen;
5636 u_int32_t *tblp, *newcmd;
5637 u_char cmd, sbcl, ss0, ss2, ctest5;
5638 u_short delta;
5639 nccb_p cp;
5640
5641 dsp = INL (nc_dsp);
5642 dsa = INL (nc_dsa);
5643 dbc = INL (nc_dbc);
5644 ss0 = INB (nc_sstat0);
5645 ss2 = INB (nc_sstat2);
5646 sbcl= INB (nc_sbcl);
5647
5648 cmd = dbc >> 24;
5649 rest= dbc & 0xffffff;
5650
5651 ctest5 = (np->rv_ctest5 & DFS) ? INB (nc_ctest5) : 0;
5652 if (ctest5 & DFS)
5653 delta=(((ctest5<<8) | (INB (nc_dfifo) & 0xff)) - rest) & 0x3ff;
5654 else
5655 delta=(INB (nc_dfifo) - rest) & 0x7f;
5656
5657
5658 /*
5659 ** The data in the dma fifo has not been transfered to
5660 ** the target -> add the amount to the rest
5661 ** and clear the data.
5662 ** Check the sstat2 register in case of wide transfer.
5663 */
5664
5665 if (!(dstat & DFE)) rest += delta;
5666 if (ss0 & OLF) rest++;
5667 if (ss0 & ORF) rest++;
5668 if (INB(nc_scntl3) & EWS) {
5669 if (ss2 & OLF1) rest++;
5670 if (ss2 & ORF1) rest++;
5671 };
5672 OUTB (nc_ctest3, np->rv_ctest3 | CLF); /* clear dma fifo */
5673 OUTB (nc_stest3, TE|CSF); /* clear scsi fifo */
5674
5675 /*
5676 ** locate matching cp
5677 */
5678 cp = np->link_nccb;
5679 while (cp && (CCB_PHYS (cp, phys) != dsa))
5680 cp = cp->link_nccb;
5681
5682 if (!cp) {
5683 printf ("%s: SCSI phase error fixup: CCB already dequeued (%p)\n",
5684 ncr_name (np), (void *) np->header.cp);
5685 return;
5686 }
5687 if (cp != np->header.cp) {
5688 printf ("%s: SCSI phase error fixup: CCB address mismatch "
5689 "(%p != %p) np->nccb = %p\n",
5690 ncr_name (np), (void *)cp, (void *)np->header.cp,
5691 (void *)np->link_nccb);
5692 /* return;*/
5693 }
5694
5695 /*
5696 ** find the interrupted script command,
5697 ** and the address at which to continue.
5698 */
5699
5700 if (dsp == vtophys (&cp->patch[2])) {
5701 vdsp_base = cp;
5702 vdsp_off = offsetof(struct nccb, patch[0]);
5703 nxtdsp = READSCRIPT_OFF(vdsp_base, vdsp_off + 3*4);
5704 } else if (dsp == vtophys (&cp->patch[6])) {
5705 vdsp_base = cp;
5706 vdsp_off = offsetof(struct nccb, patch[4]);
5707 nxtdsp = READSCRIPT_OFF(vdsp_base, vdsp_off + 3*4);
5708 } else if (dsp > np->p_script &&
5709 dsp <= np->p_script + sizeof(struct script)) {
5710 vdsp_base = np->script;
5711 vdsp_off = dsp - np->p_script - 8;
5712 nxtdsp = dsp;
5713 } else {
5714 vdsp_base = np->scripth;
5715 vdsp_off = dsp - np->p_scripth - 8;
5716 nxtdsp = dsp;
5717 };
5718
5719 /*
5720 ** log the information
5721 */
5722 if (DEBUG_FLAGS & (DEBUG_TINY|DEBUG_PHASE)) {
5723 printf ("P%x%x ",cmd&7, sbcl&7);
5724 printf ("RL=%d D=%d SS0=%x ",
5725 (unsigned) rest, (unsigned) delta, ss0);
5726 };
5727 if (DEBUG_FLAGS & DEBUG_PHASE) {
5728 printf ("\nCP=%p CP2=%p DSP=%x NXT=%x VDSP=%p CMD=%x ",
5729 cp, np->header.cp,
5730 dsp,
5731 nxtdsp, (volatile char*)vdsp_base+vdsp_off, cmd);
5732 };
5733
5734 /*
5735 ** get old startaddress and old length.
5736 */
5737
5738 oadr = READSCRIPT_OFF(vdsp_base, vdsp_off + 1*4);
5739
5740 if (cmd & 0x10) { /* Table indirect */
5741 tblp = (u_int32_t *) ((char*) &cp->phys + oadr);
5742 olen = tblp[0];
5743 oadr = tblp[1];
5744 } else {
5745 tblp = (u_int32_t *) 0;
5746 olen = READSCRIPT_OFF(vdsp_base, vdsp_off) & 0xffffff;
5747 };
5748
5749 if (DEBUG_FLAGS & DEBUG_PHASE) {
5750 printf ("OCMD=%x\nTBLP=%p OLEN=%lx OADR=%lx\n",
5751 (unsigned) (READSCRIPT_OFF(vdsp_base, vdsp_off) >> 24),
5752 (void *) tblp,
5753 (u_long) olen,
5754 (u_long) oadr);
5755 };
5756
5757 /*
5758 ** if old phase not dataphase, leave here.
5759 */
5760
5761 if (cmd != (READSCRIPT_OFF(vdsp_base, vdsp_off) >> 24)) {
5762 PRINT_ADDR(cp->ccb);
5763 printf ("internal error: cmd=%02x != %02x=(vdsp[0] >> 24)\n",
5764 (unsigned)cmd,
5765 (unsigned)READSCRIPT_OFF(vdsp_base, vdsp_off) >> 24);
5766
5767 return;
5768 }
5769 if (cmd & 0x06) {
5770 PRINT_ADDR(cp->ccb);
5771 printf ("phase change %x-%x %d@%08x resid=%d.\n",
5772 cmd&7, sbcl&7, (unsigned)olen,
5773 (unsigned)oadr, (unsigned)rest);
5774
5775 OUTB (nc_dcntl, np->rv_dcntl | STD);
5776 return;
5777 };
5778
5779 /*
5780 ** choose the correct patch area.
5781 ** if savep points to one, choose the other.
5782 */
5783
5784 newcmd = cp->patch;
5785 if (cp->phys.header.savep == vtophys (newcmd)) newcmd+=4;
5786
5787 /*
5788 ** fillin the commands
5789 */
5790
5791 newcmd[0] = ((cmd & 0x0f) << 24) | rest;
5792 newcmd[1] = oadr + olen - rest;
5793 newcmd[2] = SCR_JUMP;
5794 newcmd[3] = nxtdsp;
5795
5796 if (DEBUG_FLAGS & DEBUG_PHASE) {
5797 PRINT_ADDR(cp->ccb);
5798 printf ("newcmd[%d] %x %x %x %x.\n",
5799 (int)(newcmd - cp->patch),
5800 (unsigned)newcmd[0],
5801 (unsigned)newcmd[1],
5802 (unsigned)newcmd[2],
5803 (unsigned)newcmd[3]);
5804 }
5805 /*
5806 ** fake the return address (to the patch).
5807 ** and restart script processor at dispatcher.
5808 */
5809 np->profile.num_break++;
5810 OUTL (nc_temp, vtophys (newcmd));
5811 if ((cmd & 7) == 0)
5812 OUTL (nc_dsp, NCB_SCRIPT_PHYS (np, dispatch));
5813 else
5814 OUTL (nc_dsp, NCB_SCRIPT_PHYS (np, checkatn));
5815 }
5816
5817 /*==========================================================
5818 **
5819 **
5820 ** ncr chip exception handler for programmed interrupts.
5821 **
5822 **
5823 **==========================================================
5824 */
5825
5826 static int ncr_show_msg (u_char * msg)
5827 {
5828 u_char i;
5829 printf ("%x",*msg);
5830 if (*msg==MSG_EXTENDED) {
5831 for (i=1;i<8;i++) {
5832 if (i-1>msg[1]) break;
5833 printf ("-%x",msg[i]);
5834 };
5835 return (i+1);
5836 } else if ((*msg & 0xf0) == 0x20) {
5837 printf ("-%x",msg[1]);
5838 return (2);
5839 };
5840 return (1);
5841 }
5842
5843 void ncr_int_sir (ncb_p np)
5844 {
5845 u_char scntl3;
5846 u_char chg, ofs, per, fak, wide;
5847 u_char num = INB (nc_dsps);
5848 nccb_p cp=0;
5849 u_long dsa;
5850 u_int target = INB (nc_sdid) & 0x0f;
5851 tcb_p tp = &np->target[target];
5852 int i;
5853 if (DEBUG_FLAGS & DEBUG_TINY) printf ("I#%d", num);
5854
5855 switch (num) {
5856 case SIR_SENSE_RESTART:
5857 case SIR_STALL_RESTART:
5858 break;
5859
5860 default:
5861 /*
5862 ** lookup the nccb
5863 */
5864 dsa = INL (nc_dsa);
5865 cp = np->link_nccb;
5866 while (cp && (CCB_PHYS (cp, phys) != dsa))
5867 cp = cp->link_nccb;
5868
5869 assert (cp);
5870 if (!cp)
5871 goto out;
5872 assert (cp == np->header.cp);
5873 if (cp != np->header.cp)
5874 goto out;
5875 }
5876
5877 switch (num) {
5878
5879 /*--------------------------------------------------------------------
5880 **
5881 ** Processing of interrupted getcc selects
5882 **
5883 **--------------------------------------------------------------------
5884 */
5885
5886 case SIR_SENSE_RESTART:
5887 /*------------------------------------------
5888 ** Script processor is idle.
5889 ** Look for interrupted "check cond"
5890 **------------------------------------------
5891 */
5892
5893 if (DEBUG_FLAGS & DEBUG_RESTART)
5894 printf ("%s: int#%d",ncr_name (np),num);
5895 cp = (nccb_p) 0;
5896 for (i=0; i<MAX_TARGET; i++) {
5897 if (DEBUG_FLAGS & DEBUG_RESTART) printf (" t%d", i);
5898 tp = &np->target[i];
5899 if (DEBUG_FLAGS & DEBUG_RESTART) printf ("+");
5900 cp = tp->hold_cp;
5901 if (!cp) continue;
5902 if (DEBUG_FLAGS & DEBUG_RESTART) printf ("+");
5903 if ((cp->host_status==HS_BUSY) &&
5904 (cp->s_status==SCSI_STATUS_CHECK_COND))
5905 break;
5906 if (DEBUG_FLAGS & DEBUG_RESTART) printf ("- (remove)");
5907 tp->hold_cp = cp = (nccb_p) 0;
5908 };
5909
5910 if (cp) {
5911 if (DEBUG_FLAGS & DEBUG_RESTART)
5912 printf ("+ restart job ..\n");
5913 OUTL (nc_dsa, CCB_PHYS (cp, phys));
5914 OUTL (nc_dsp, NCB_SCRIPTH_PHYS (np, getcc));
5915 return;
5916 };
5917
5918 /*
5919 ** no job, resume normal processing
5920 */
5921 if (DEBUG_FLAGS & DEBUG_RESTART) printf (" -- remove trap\n");
5922 WRITESCRIPT(start0[0], SCR_INT ^ IFFALSE (0));
5923 break;
5924
5925 case SIR_SENSE_FAILED:
5926 /*-------------------------------------------
5927 ** While trying to select for
5928 ** getting the condition code,
5929 ** a target reselected us.
5930 **-------------------------------------------
5931 */
5932 if (DEBUG_FLAGS & DEBUG_RESTART) {
5933 PRINT_ADDR(cp->ccb);
5934 printf ("in getcc reselect by t%d.\n",
5935 INB(nc_ssid) & 0x0f);
5936 }
5937
5938 /*
5939 ** Mark this job
5940 */
5941 cp->host_status = HS_BUSY;
5942 cp->s_status = SCSI_STATUS_CHECK_COND;
5943 np->target[cp->ccb->ccb_h.target_id].hold_cp = cp;
5944
5945 /*
5946 ** And patch code to restart it.
5947 */
5948 WRITESCRIPT(start0[0], SCR_INT);
5949 break;
5950
5951 /*-----------------------------------------------------------------------------
5952 **
5953 ** Was Sie schon immer ueber transfermode negotiation wissen wollten ...
5954 **
5955 ** We try to negotiate sync and wide transfer only after
5956 ** a successfull inquire command. We look at byte 7 of the
5957 ** inquire data to determine the capabilities if the target.
5958 **
5959 ** When we try to negotiate, we append the negotiation message
5960 ** to the identify and (maybe) simple tag message.
5961 ** The host status field is set to HS_NEGOTIATE to mark this
5962 ** situation.
5963 **
5964 ** If the target doesn't answer this message immidiately
5965 ** (as required by the standard), the SIR_NEGO_FAIL interrupt
5966 ** will be raised eventually.
5967 ** The handler removes the HS_NEGOTIATE status, and sets the
5968 ** negotiated value to the default (async / nowide).
5969 **
5970 ** If we receive a matching answer immediately, we check it
5971 ** for validity, and set the values.
5972 **
5973 ** If we receive a Reject message immediately, we assume the
5974 ** negotiation has failed, and fall back to standard values.
5975 **
5976 ** If we receive a negotiation message while not in HS_NEGOTIATE
5977 ** state, it's a target initiated negotiation. We prepare a
5978 ** (hopefully) valid answer, set our parameters, and send back
5979 ** this answer to the target.
5980 **
5981 ** If the target doesn't fetch the answer (no message out phase),
5982 ** we assume the negotiation has failed, and fall back to default
5983 ** settings.
5984 **
5985 ** When we set the values, we adjust them in all nccbs belonging
5986 ** to this target, in the controller's register, and in the "phys"
5987 ** field of the controller's struct ncb.
5988 **
5989 ** Possible cases: hs sir msg_in value send goto
5990 ** We try try to negotiate:
5991 ** -> target doesnt't msgin NEG FAIL noop defa. - dispatch
5992 ** -> target rejected our msg NEG FAIL reject defa. - dispatch
5993 ** -> target answered (ok) NEG SYNC sdtr set - clrack
5994 ** -> target answered (!ok) NEG SYNC sdtr defa. REJ--->msg_bad
5995 ** -> target answered (ok) NEG WIDE wdtr set - clrack
5996 ** -> target answered (!ok) NEG WIDE wdtr defa. REJ--->msg_bad
5997 ** -> any other msgin NEG FAIL noop defa. - dispatch
5998 **
5999 ** Target tries to negotiate:
6000 ** -> incoming message --- SYNC sdtr set SDTR -
6001 ** -> incoming message --- WIDE wdtr set WDTR -
6002 ** We sent our answer:
6003 ** -> target doesn't msgout --- PROTO ? defa. - dispatch
6004 **
6005 **-----------------------------------------------------------------------------
6006 */
6007
6008 case SIR_NEGO_FAILED:
6009 /*-------------------------------------------------------
6010 **
6011 ** Negotiation failed.
6012 ** Target doesn't send an answer message,
6013 ** or target rejected our message.
6014 **
6015 ** Remove negotiation request.
6016 **
6017 **-------------------------------------------------------
6018 */
6019 OUTB (HS_PRT, HS_BUSY);
6020
6021 /* fall through */
6022
6023 case SIR_NEGO_PROTO:
6024 /*-------------------------------------------------------
6025 **
6026 ** Negotiation failed.
6027 ** Target doesn't fetch the answer message.
6028 **
6029 **-------------------------------------------------------
6030 */
6031
6032 if (DEBUG_FLAGS & DEBUG_NEGO) {
6033 PRINT_ADDR(cp->ccb);
6034 printf ("negotiation failed sir=%x status=%x.\n",
6035 num, cp->nego_status);
6036 };
6037
6038 /*
6039 ** any error in negotiation:
6040 ** fall back to default mode.
6041 */
6042 switch (cp->nego_status) {
6043
6044 case NS_SYNC:
6045 ncr_setsync (np, cp, 0, 0xe0, 0);
6046 break;
6047
6048 case NS_WIDE:
6049 ncr_setwide (np, cp, 0, 0);
6050 break;
6051
6052 };
6053 np->msgin [0] = MSG_NOOP;
6054 np->msgout[0] = MSG_NOOP;
6055 cp->nego_status = 0;
6056 OUTL (nc_dsp, NCB_SCRIPT_PHYS (np, dispatch));
6057 break;
6058
6059 case SIR_NEGO_SYNC:
6060 /*
6061 ** Synchronous request message received.
6062 */
6063
6064 if (DEBUG_FLAGS & DEBUG_NEGO) {
6065 PRINT_ADDR(cp->ccb);
6066 printf ("sync msgin: ");
6067 (void) ncr_show_msg (np->msgin);
6068 printf (".\n");
6069 };
6070
6071 /*
6072 ** get requested values.
6073 */
6074
6075 chg = 0;
6076 per = np->msgin[3];
6077 ofs = np->msgin[4];
6078 if (ofs==0) per=255;
6079
6080 /*
6081 ** check values against driver limits.
6082 */
6083 if (per < np->minsync)
6084 {chg = 1; per = np->minsync;}
6085 if (per < tp->tinfo.user.period)
6086 {chg = 1; per = tp->tinfo.user.period;}
6087 if (ofs > tp->tinfo.user.offset)
6088 {chg = 1; ofs = tp->tinfo.user.offset;}
6089
6090 /*
6091 ** Check against controller limits.
6092 */
6093
6094 fak = 7;
6095 scntl3 = 0;
6096 if (ofs != 0) {
6097 ncr_getsync(np, per, &fak, &scntl3);
6098 if (fak > 7) {
6099 chg = 1;
6100 ofs = 0;
6101 }
6102 }
6103 if (ofs == 0) {
6104 fak = 7;
6105 per = 0;
6106 scntl3 = 0;
6107 }
6108
6109 if (DEBUG_FLAGS & DEBUG_NEGO) {
6110 PRINT_ADDR(cp->ccb);
6111 printf ("sync: per=%d scntl3=0x%x ofs=%d fak=%d chg=%d.\n",
6112 per, scntl3, ofs, fak, chg);
6113 }
6114
6115 if (INB (HS_PRT) == HS_NEGOTIATE) {
6116 OUTB (HS_PRT, HS_BUSY);
6117 switch (cp->nego_status) {
6118
6119 case NS_SYNC:
6120 /*
6121 ** This was an answer message
6122 */
6123 if (chg) {
6124 /*
6125 ** Answer wasn't acceptable.
6126 */
6127 ncr_setsync (np, cp, 0, 0xe0, 0);
6128 OUTL (nc_dsp, NCB_SCRIPT_PHYS (np, msg_bad));
6129 } else {
6130 /*
6131 ** Answer is ok.
6132 */
6133 ncr_setsync (np,cp,scntl3,(fak<<5)|ofs, per);
6134 OUTL (nc_dsp, NCB_SCRIPT_PHYS (np, clrack));
6135 };
6136 return;
6137
6138 case NS_WIDE:
6139 ncr_setwide (np, cp, 0, 0);
6140 break;
6141 };
6142 };
6143
6144 /*
6145 ** It was a request. Set value and
6146 ** prepare an answer message
6147 */
6148
6149 ncr_setsync (np, cp, scntl3, (fak<<5)|ofs, per);
6150
6151 np->msgout[0] = MSG_EXTENDED;
6152 np->msgout[1] = 3;
6153 np->msgout[2] = MSG_EXT_SDTR;
6154 np->msgout[3] = per;
6155 np->msgout[4] = ofs;
6156
6157 cp->nego_status = NS_SYNC;
6158
6159 if (DEBUG_FLAGS & DEBUG_NEGO) {
6160 PRINT_ADDR(cp->ccb);
6161 printf ("sync msgout: ");
6162 (void) ncr_show_msg (np->msgout);
6163 printf (".\n");
6164 }
6165
6166 if (!ofs) {
6167 OUTL (nc_dsp, NCB_SCRIPT_PHYS (np, msg_bad));
6168 return;
6169 }
6170 np->msgin [0] = MSG_NOOP;
6171
6172 break;
6173
6174 case SIR_NEGO_WIDE:
6175 /*
6176 ** Wide request message received.
6177 */
6178 if (DEBUG_FLAGS & DEBUG_NEGO) {
6179 PRINT_ADDR(cp->ccb);
6180 printf ("wide msgin: ");
6181 (void) ncr_show_msg (np->msgin);
6182 printf (".\n");
6183 };
6184
6185 /*
6186 ** get requested values.
6187 */
6188
6189 chg = 0;
6190 wide = np->msgin[3];
6191
6192 /*
6193 ** check values against driver limits.
6194 */
6195
6196 if (wide > tp->tinfo.user.width)
6197 {chg = 1; wide = tp->tinfo.user.width;}
6198
6199 if (DEBUG_FLAGS & DEBUG_NEGO) {
6200 PRINT_ADDR(cp->ccb);
6201 printf ("wide: wide=%d chg=%d.\n", wide, chg);
6202 }
6203
6204 if (INB (HS_PRT) == HS_NEGOTIATE) {
6205 OUTB (HS_PRT, HS_BUSY);
6206 switch (cp->nego_status) {
6207
6208 case NS_WIDE:
6209 /*
6210 ** This was an answer message
6211 */
6212 if (chg) {
6213 /*
6214 ** Answer wasn't acceptable.
6215 */
6216 ncr_setwide (np, cp, 0, 1);
6217 OUTL (nc_dsp, NCB_SCRIPT_PHYS (np, msg_bad));
6218 } else {
6219 /*
6220 ** Answer is ok.
6221 */
6222 ncr_setwide (np, cp, wide, 1);
6223 OUTL (nc_dsp, NCB_SCRIPT_PHYS (np, clrack));
6224 };
6225 return;
6226
6227 case NS_SYNC:
6228 ncr_setsync (np, cp, 0, 0xe0, 0);
6229 break;
6230 };
6231 };
6232
6233 /*
6234 ** It was a request, set value and
6235 ** prepare an answer message
6236 */
6237
6238 ncr_setwide (np, cp, wide, 1);
6239
6240 np->msgout[0] = MSG_EXTENDED;
6241 np->msgout[1] = 2;
6242 np->msgout[2] = MSG_EXT_WDTR;
6243 np->msgout[3] = wide;
6244
6245 np->msgin [0] = MSG_NOOP;
6246
6247 cp->nego_status = NS_WIDE;
6248
6249 if (DEBUG_FLAGS & DEBUG_NEGO) {
6250 PRINT_ADDR(cp->ccb);
6251 printf ("wide msgout: ");
6252 (void) ncr_show_msg (np->msgout);
6253 printf (".\n");
6254 }
6255 break;
6256
6257 /*--------------------------------------------------------------------
6258 **
6259 ** Processing of special messages
6260 **
6261 **--------------------------------------------------------------------
6262 */
6263
6264 case SIR_REJECT_RECEIVED:
6265 /*-----------------------------------------------
6266 **
6267 ** We received a MSG_MESSAGE_REJECT message.
6268 **
6269 **-----------------------------------------------
6270 */
6271
6272 PRINT_ADDR(cp->ccb);
6273 printf ("MSG_MESSAGE_REJECT received (%x:%x).\n",
6274 (unsigned)np->lastmsg, np->msgout[0]);
6275 break;
6276
6277 case SIR_REJECT_SENT:
6278 /*-----------------------------------------------
6279 **
6280 ** We received an unknown message
6281 **
6282 **-----------------------------------------------
6283 */
6284
6285 PRINT_ADDR(cp->ccb);
6286 printf ("MSG_MESSAGE_REJECT sent for ");
6287 (void) ncr_show_msg (np->msgin);
6288 printf (".\n");
6289 break;
6290
6291 /*--------------------------------------------------------------------
6292 **
6293 ** Processing of special messages
6294 **
6295 **--------------------------------------------------------------------
6296 */
6297
6298 case SIR_IGN_RESIDUE:
6299 /*-----------------------------------------------
6300 **
6301 ** We received an IGNORE RESIDUE message,
6302 ** which couldn't be handled by the script.
6303 **
6304 **-----------------------------------------------
6305 */
6306
6307 PRINT_ADDR(cp->ccb);
6308 printf ("MSG_IGN_WIDE_RESIDUE received, but not yet implemented.\n");
6309 break;
6310
6311 case SIR_MISSING_SAVE:
6312 /*-----------------------------------------------
6313 **
6314 ** We received an DISCONNECT message,
6315 ** but the datapointer wasn't saved before.
6316 **
6317 **-----------------------------------------------
6318 */
6319
6320 PRINT_ADDR(cp->ccb);
6321 printf ("MSG_DISCONNECT received, but datapointer not saved:\n"
6322 "\tdata=%x save=%x goal=%x.\n",
6323 (unsigned) INL (nc_temp),
6324 (unsigned) np->header.savep,
6325 (unsigned) np->header.goalp);
6326 break;
6327
6328 /*--------------------------------------------------------------------
6329 **
6330 ** Processing of a "SCSI_STATUS_QUEUE_FULL" status.
6331 **
6332 ** XXX JGibbs - We should do the same thing for BUSY status.
6333 **
6334 ** The current command has been rejected,
6335 ** because there are too many in the command queue.
6336 ** We have started too many commands for that target.
6337 **
6338 **--------------------------------------------------------------------
6339 */
6340 case SIR_STALL_QUEUE:
6341 cp->xerr_status = XE_OK;
6342 cp->host_status = HS_COMPLETE;
6343 cp->s_status = SCSI_STATUS_QUEUE_FULL;
6344 ncr_freeze_devq(np, cp->ccb->ccb_h.path);
6345 ncr_complete(np, cp);
6346
6347 /* FALL THROUGH */
6348
6349 case SIR_STALL_RESTART:
6350 /*-----------------------------------------------
6351 **
6352 ** Enable selecting again,
6353 ** if NO disconnected jobs.
6354 **
6355 **-----------------------------------------------
6356 */
6357 /*
6358 ** Look for a disconnected job.
6359 */
6360 cp = np->link_nccb;
6361 while (cp && cp->host_status != HS_DISCONNECT)
6362 cp = cp->link_nccb;
6363
6364 /*
6365 ** if there is one, ...
6366 */
6367 if (cp) {
6368 /*
6369 ** wait for reselection
6370 */
6371 OUTL (nc_dsp, NCB_SCRIPT_PHYS (np, reselect));
6372 return;
6373 };
6374
6375 /*
6376 ** else remove the interrupt.
6377 */
6378
6379 printf ("%s: queue empty.\n", ncr_name (np));
6380 WRITESCRIPT(start1[0], SCR_INT ^ IFFALSE (0));
6381 break;
6382 };
6383
6384 out:
6385 OUTB (nc_dcntl, np->rv_dcntl | STD);
6386 }
6387
6388 /*==========================================================
6389 **
6390 **
6391 ** Aquire a control block
6392 **
6393 **
6394 **==========================================================
6395 */
6396
6397 static nccb_p ncr_get_nccb
6398 (ncb_p np, u_long target, u_long lun)
6399 {
6400 lcb_p lp;
6401 nccb_p cp = NULL;
6402
6403 /* Keep our timeout handler out */
6404 crit_enter();
6405
6406 /*
6407 ** Lun structure available ?
6408 */
6409
6410 lp = np->target[target].lp[lun];
6411 if (lp) {
6412 cp = lp->next_nccb;
6413
6414 /*
6415 ** Look for free CCB
6416 */
6417
6418 while (cp && cp->magic) {
6419 cp = cp->next_nccb;
6420 }
6421 }
6422
6423 /*
6424 ** if nothing available, create one.
6425 */
6426
6427 if (cp == NULL)
6428 cp = ncr_alloc_nccb(np, target, lun);
6429
6430 if (cp != NULL) {
6431 if (cp->magic) {
6432 printf("%s: Bogus free cp found\n", ncr_name(np));
6433 crit_exit();
6434 return (NULL);
6435 }
6436 cp->magic = 1;
6437 }
6438 crit_exit();
6439 return (cp);
6440 }
6441
6442 /*==========================================================
6443 **
6444 **
6445 ** Release one control block
6446 **
6447 **
6448 **==========================================================
6449 */
6450
6451 void ncr_free_nccb (ncb_p np, nccb_p cp)
6452 {
6453 /*
6454 ** sanity
6455 */
6456
6457 assert (cp != NULL);
6458
6459 cp -> host_status = HS_IDLE;
6460 cp -> magic = 0;
6461 }
6462
6463 /*==========================================================
6464 **
6465 **
6466 ** Allocation of resources for Targets/Luns/Tags.
6467 **
6468 **
6469 **==========================================================
6470 */
6471
6472 static nccb_p
6473 ncr_alloc_nccb (ncb_p np, u_long target, u_long lun)
6474 {
6475 tcb_p tp;
6476 lcb_p lp;
6477 nccb_p cp;
6478
6479 assert (np != NULL);
6480
6481 if (target>=MAX_TARGET) return(NULL);
6482 if (lun >=MAX_LUN ) return(NULL);
6483
6484 tp=&np->target[target];
6485
6486 if (!tp->jump_tcb.l_cmd) {
6487
6488 /*
6489 ** initialize it.
6490 */
6491 tp->jump_tcb.l_cmd = (SCR_JUMP^IFFALSE (DATA (0x80 + target)));
6492 tp->jump_tcb.l_paddr = np->jump_tcb.l_paddr;
6493
6494 tp->getscr[0] =
6495 (np->features & FE_PFEN)? SCR_COPY(1) : SCR_COPY_F(1);
6496 tp->getscr[1] = vtophys (&tp->tinfo.sval);
6497 tp->getscr[2] = rman_get_start(np->reg_res) + offsetof (struct ncr_reg, nc_sxfer);
6498 tp->getscr[3] =
6499 (np->features & FE_PFEN)? SCR_COPY(1) : SCR_COPY_F(1);
6500 tp->getscr[4] = vtophys (&tp->tinfo.wval);
6501 tp->getscr[5] = rman_get_start(np->reg_res) + offsetof (struct ncr_reg, nc_scntl3);
6502
6503 assert (((offsetof(struct ncr_reg, nc_sxfer) ^
6504 (offsetof(struct tcb ,tinfo)
6505 + offsetof(struct ncr_target_tinfo, sval))) & 3) == 0);
6506 assert (((offsetof(struct ncr_reg, nc_scntl3) ^
6507 (offsetof(struct tcb, tinfo)
6508 + offsetof(struct ncr_target_tinfo, wval))) &3) == 0);
6509
6510 tp->call_lun.l_cmd = (SCR_CALL);
6511 tp->call_lun.l_paddr = NCB_SCRIPT_PHYS (np, resel_lun);
6512
6513 tp->jump_lcb.l_cmd = (SCR_JUMP);
6514 tp->jump_lcb.l_paddr = NCB_SCRIPTH_PHYS (np, abort);
6515 np->jump_tcb.l_paddr = vtophys (&tp->jump_tcb);
6516 }
6517
6518 /*
6519 ** Logic unit control block
6520 */
6521 lp = tp->lp[lun];
6522 if (!lp) {
6523 /*
6524 ** Allocate a lcb
6525 */
6526 lp = kmalloc (sizeof (struct lcb), M_DEVBUF, M_WAITOK | M_ZERO);
6527
6528 /*
6529 ** Initialize it
6530 */
6531 lp->jump_lcb.l_cmd = (SCR_JUMP ^ IFFALSE (DATA (lun)));
6532 lp->jump_lcb.l_paddr = tp->jump_lcb.l_paddr;
6533
6534 lp->call_tag.l_cmd = (SCR_CALL);
6535 lp->call_tag.l_paddr = NCB_SCRIPT_PHYS (np, resel_tag);
6536
6537 lp->jump_nccb.l_cmd = (SCR_JUMP);
6538 lp->jump_nccb.l_paddr = NCB_SCRIPTH_PHYS (np, aborttag);
6539
6540 lp->actlink = 1;
6541
6542 /*
6543 ** Chain into LUN list
6544 */
6545 tp->jump_lcb.l_paddr = vtophys (&lp->jump_lcb);
6546 tp->lp[lun] = lp;
6547
6548 }
6549
6550 /*
6551 ** Allocate a nccb
6552 */
6553 cp = kmalloc (sizeof (struct nccb), M_DEVBUF, M_WAITOK | M_ZERO);
6554
6555 if (DEBUG_FLAGS & DEBUG_ALLOC) {
6556 printf ("new nccb @%p.\n", cp);
6557 }
6558
6559 /*
6560 ** Fill in physical addresses
6561 */
6562
6563 cp->p_nccb = vtophys (cp);
6564
6565 /*
6566 ** Chain into reselect list
6567 */
6568 cp->jump_nccb.l_cmd = SCR_JUMP;
6569 cp->jump_nccb.l_paddr = lp->jump_nccb.l_paddr;
6570 lp->jump_nccb.l_paddr = CCB_PHYS (cp, jump_nccb);
6571 cp->call_tmp.l_cmd = SCR_CALL;
6572 cp->call_tmp.l_paddr = NCB_SCRIPT_PHYS (np, resel_tmp);
6573
6574 /*
6575 ** Chain into wakeup list
6576 */
6577 cp->link_nccb = np->link_nccb;
6578 np->link_nccb = cp;
6579
6580 /*
6581 ** Chain into CCB list
6582 */
6583 cp->next_nccb = lp->next_nccb;
6584 lp->next_nccb = cp;
6585
6586 return (cp);
6587 }
6588
6589 /*==========================================================
6590 **
6591 **
6592 ** Build Scatter Gather Block
6593 **
6594 **
6595 **==========================================================
6596 **
6597 ** The transfer area may be scattered among
6598 ** several non adjacent physical pages.
6599 **
6600 ** We may use MAX_SCATTER blocks.
6601 **
6602 **----------------------------------------------------------
6603 */
6604
6605 static int ncr_scatter
6606 (struct dsb* phys, vm_offset_t vaddr, vm_size_t datalen)
6607 {
6608 u_long paddr, pnext;
6609
6610 u_short segment = 0;
6611 u_long segsize, segaddr;
6612 u_long size, csize = 0;
6613 u_long chunk = MAX_SIZE;
6614 int free;
6615
6616 bzero (&phys->data, sizeof (phys->data));
6617 if (!datalen) return (0);
6618
6619 paddr = vtophys (vaddr);
6620
6621 /*
6622 ** insert extra break points at a distance of chunk.
6623 ** We try to reduce the number of interrupts caused
6624 ** by unexpected phase changes due to disconnects.
6625 ** A typical harddisk may disconnect before ANY block.
6626 ** If we wanted to avoid unexpected phase changes at all
6627 ** we had to use a break point every 512 bytes.
6628 ** Of course the number of scatter/gather blocks is
6629 ** limited.
6630 */
6631
6632 free = MAX_SCATTER - 1;
6633
6634 if (vaddr & PAGE_MASK) free -= datalen / PAGE_SIZE;
6635
6636 if (free>1)
6637 while ((chunk * free >= 2 * datalen) && (chunk>=1024))
6638 chunk /= 2;
6639
6640 if(DEBUG_FLAGS & DEBUG_SCATTER)
6641 printf("ncr?:\tscattering virtual=%p size=%d chunk=%d.\n",
6642 (void *) vaddr, (unsigned) datalen, (unsigned) chunk);
6643
6644 /*
6645 ** Build data descriptors.
6646 */
6647 while (datalen && (segment < MAX_SCATTER)) {
6648
6649 /*
6650 ** this segment is empty
6651 */
6652 segsize = 0;
6653 segaddr = paddr;
6654 pnext = paddr;
6655
6656 if (!csize) csize = chunk;
6657
6658 while ((datalen) && (paddr == pnext) && (csize)) {
6659
6660 /*
6661 ** continue this segment
6662 */
6663 pnext = (paddr & (~PAGE_MASK)) + PAGE_SIZE;
6664
6665 /*
6666 ** Compute max size
6667 */
6668
6669 size = pnext - paddr; /* page size */
6670 if (size > datalen) size = datalen; /* data size */
6671 if (size > csize ) size = csize ; /* chunksize */
6672
6673 segsize += size;
6674 vaddr += size;
6675 csize -= size;
6676 datalen -= size;
6677 paddr = vtophys (vaddr);
6678 };
6679
6680 if(DEBUG_FLAGS & DEBUG_SCATTER)
6681 printf ("\tseg #%d addr=%x size=%d (rest=%d).\n",
6682 segment,
6683 (unsigned) segaddr,
6684 (unsigned) segsize,
6685 (unsigned) datalen);
6686
6687 phys->data[segment].addr = segaddr;
6688 phys->data[segment].size = segsize;
6689 segment++;
6690 }
6691
6692 if (datalen) {
6693 printf("ncr?: scatter/gather failed (residue=%d).\n",
6694 (unsigned) datalen);
6695 return (-1);
6696 };
6697
6698 return (segment);
6699 }
6700
6701 /*==========================================================
6702 **
6703 **
6704 ** Test the pci bus snoop logic :-(
6705 **
6706 ** Has to be called with interrupts disabled.
6707 **
6708 **
6709 **==========================================================
6710 */
6711
6712 #ifndef NCR_IOMAPPED
6713 static int ncr_regtest (struct ncb* np)
6714 {
6715 volatile u_int32_t data;
6716 /*
6717 ** ncr registers may NOT be cached.
6718 ** write 0xffffffff to a read only register area,
6719 ** and try to read it back.
6720 */
6721 data = 0xffffffff;
6722 OUTL_OFF(offsetof(struct ncr_reg, nc_dstat), data);
6723 data = INL_OFF(offsetof(struct ncr_reg, nc_dstat));
6724 #if 1
6725 if (data == 0xffffffff) {
6726 #else
6727 if ((data & 0xe2f0fffd) != 0x02000080) {
6728 #endif
6729 printf ("CACHE TEST FAILED: reg dstat-sstat2 readback %x.\n",
6730 (unsigned) data);
6731 return (0x10);
6732 };
6733 return (0);
6734 }
6735 #endif
6736
6737 static int ncr_snooptest (struct ncb* np)
6738 {
6739 u_int32_t ncr_rd, ncr_wr, ncr_bk, host_rd, host_wr, pc;
6740 int i, err=0;
6741 #ifndef NCR_IOMAPPED
6742 err |= ncr_regtest (np);
6743 if (err) return (err);
6744 #endif
6745 /*
6746 ** init
6747 */
6748 pc = NCB_SCRIPTH_PHYS (np, snooptest);
6749 host_wr = 1;
6750 ncr_wr = 2;
6751 /*
6752 ** Set memory and register.
6753 */
6754 ncr_cache = host_wr;
6755 OUTL (nc_temp, ncr_wr);
6756 /*
6757 ** Start script (exchange values)
6758 */
6759 OUTL (nc_dsp, pc);
6760 /*
6761 ** Wait 'til done (with timeout)
6762 */
6763 for (i=0; i<NCR_SNOOP_TIMEOUT; i++)
6764 if (INB(nc_istat) & (INTF|SIP|DIP))
6765 break;
6766 /*
6767 ** Save termination position.
6768 */
6769 pc = INL (nc_dsp);
6770 /*
6771 ** Read memory and register.
6772 */
6773 host_rd = ncr_cache;
6774 ncr_rd = INL (nc_scratcha);
6775 ncr_bk = INL (nc_temp);
6776 /*
6777 ** Reset ncr chip
6778 */
6779 OUTB (nc_istat, SRST);
6780 DELAY (1000);
6781 OUTB (nc_istat, 0 );
6782 /*
6783 ** check for timeout
6784 */
6785 if (i>=NCR_SNOOP_TIMEOUT) {
6786 printf ("CACHE TEST FAILED: timeout.\n");
6787 return (0x20);
6788 };
6789 /*
6790 ** Check termination position.
6791 */
6792 if (pc != NCB_SCRIPTH_PHYS (np, snoopend)+8) {
6793 printf ("CACHE TEST FAILED: script execution failed.\n");
6794 printf ("start=%08lx, pc=%08lx, end=%08lx\n",
6795 (u_long) NCB_SCRIPTH_PHYS (np, snooptest), (u_long) pc,
6796 (u_long) NCB_SCRIPTH_PHYS (np, snoopend) +8);
6797 return (0x40);
6798 };
6799 /*
6800 ** Show results.
6801 */
6802 if (host_wr != ncr_rd) {
6803 printf ("CACHE TEST FAILED: host wrote %d, ncr read %d.\n",
6804 (int) host_wr, (int) ncr_rd);
6805 err |= 1;
6806 };
6807 if (host_rd != ncr_wr) {
6808 printf ("CACHE TEST FAILED: ncr wrote %d, host read %d.\n",
6809 (int) ncr_wr, (int) host_rd);
6810 err |= 2;
6811 };
6812 if (ncr_bk != ncr_wr) {
6813 printf ("CACHE TEST FAILED: ncr wrote %d, read back %d.\n",
6814 (int) ncr_wr, (int) ncr_bk);
6815 err |= 4;
6816 };
6817 return (err);
6818 }
6819
6820 /*==========================================================
6821 **
6822 **
6823 ** Profiling the drivers and targets performance.
6824 **
6825 **
6826 **==========================================================
6827 */
6828
6829 /*
6830 ** Compute the difference in milliseconds.
6831 **/
6832
6833 static int ncr_delta (int *from, int *to)
6834 {
6835 if (!from) return (-1);
6836 if (!to) return (-2);
6837 return ((to - from) * 1000 / hz);
6838 }
6839
6840 #define PROFILE cp->phys.header.stamp
6841 static void ncb_profile (ncb_p np, nccb_p cp)
6842 {
6843 int co, da, st, en, di, se, post,work,disc;
6844 u_long diff;
6845
6846 PROFILE.end = ticks;
6847
6848 st = ncr_delta (&PROFILE.start,&PROFILE.status);
6849 if (st<0) return; /* status not reached */
6850
6851 da = ncr_delta (&PROFILE.start,&PROFILE.data);
6852 if (da<0) return; /* No data transfer phase */
6853
6854 co = ncr_delta (&PROFILE.start,&PROFILE.command);
6855 if (co<0) return; /* command not executed */
6856
6857 en = ncr_delta (&PROFILE.start,&PROFILE.end),
6858 di = ncr_delta (&PROFILE.start,&PROFILE.disconnect),
6859 se = ncr_delta (&PROFILE.start,&PROFILE.select);
6860 post = en - st;
6861
6862 /*
6863 ** @PROFILE@ Disconnect time invalid if multiple disconnects
6864 */
6865
6866 if (di>=0) disc = se-di; else disc = 0;
6867
6868 work = (st - co) - disc;
6869
6870 diff = (np->disc_phys - np->disc_ref) & 0xff;
6871 np->disc_ref += diff;
6872
6873 np->profile.num_trans += 1;
6874 if (cp->ccb)
6875 np->profile.num_bytes += cp->ccb->csio.dxfer_len;
6876 np->profile.num_disc += diff;
6877 np->profile.ms_setup += co;
6878 np->profile.ms_data += work;
6879 np->profile.ms_disc += disc;
6880 np->profile.ms_post += post;
6881 }
6882 #undef PROFILE
6883
6884 /*==========================================================
6885 **
6886 ** Determine the ncr's clock frequency.
6887 ** This is essential for the negotiation
6888 ** of the synchronous transfer rate.
6889 **
6890 **==========================================================
6891 **
6892 ** Note: we have to return the correct value.
6893 ** THERE IS NO SAVE DEFAULT VALUE.
6894 **
6895 ** Most NCR/SYMBIOS boards are delivered with a 40 Mhz clock.
6896 ** 53C860 and 53C875 rev. 1 support fast20 transfers but
6897 ** do not have a clock doubler and so are provided with a
6898 ** 80 MHz clock. All other fast20 boards incorporate a doubler
6899 ** and so should be delivered with a 40 MHz clock.
6900 ** The future fast40 chips (895/895) use a 40 Mhz base clock
6901 ** and provide a clock quadrupler (160 Mhz). The code below
6902 ** tries to deal as cleverly as possible with all this stuff.
6903 **
6904 **----------------------------------------------------------
6905 */
6906
6907 /*
6908 * Select NCR SCSI clock frequency
6909 */
6910 static void ncr_selectclock(ncb_p np, u_char scntl3)
6911 {
6912 if (np->multiplier < 2) {
6913 OUTB(nc_scntl3, scntl3);
6914 return;
6915 }
6916
6917 if (bootverbose >= 2)
6918 printf ("%s: enabling clock multiplier\n", ncr_name(np));
6919
6920 OUTB(nc_stest1, DBLEN); /* Enable clock multiplier */
6921 if (np->multiplier > 2) { /* Poll bit 5 of stest4 for quadrupler */
6922 int i = 20;
6923 while (!(INB(nc_stest4) & LCKFRQ) && --i > 0)
6924 DELAY(20);
6925 if (!i)
6926 printf("%s: the chip cannot lock the frequency\n", ncr_name(np));
6927 } else /* Wait 20 micro-seconds for doubler */
6928 DELAY(20);
6929 OUTB(nc_stest3, HSC); /* Halt the scsi clock */
6930 OUTB(nc_scntl3, scntl3);
6931 OUTB(nc_stest1, (DBLEN|DBLSEL));/* Select clock multiplier */
6932 OUTB(nc_stest3, 0x00); /* Restart scsi clock */
6933 }
6934
6935 /*
6936 * calculate NCR SCSI clock frequency (in KHz)
6937 */
6938 static unsigned
6939 ncrgetfreq (ncb_p np, int gen)
6940 {
6941 int ms = 0;
6942 /*
6943 * Measure GEN timer delay in order
6944 * to calculate SCSI clock frequency
6945 *
6946 * This code will never execute too
6947 * many loop iterations (if DELAY is
6948 * reasonably correct). It could get
6949 * too low a delay (too high a freq.)
6950 * if the CPU is slow executing the
6951 * loop for some reason (an NMI, for
6952 * example). For this reason we will
6953 * if multiple measurements are to be
6954 * performed trust the higher delay
6955 * (lower frequency returned).
6956 */
6957 OUTB (nc_stest1, 0); /* make sure clock doubler is OFF */
6958 OUTW (nc_sien , 0); /* mask all scsi interrupts */
6959 (void) INW (nc_sist); /* clear pending scsi interrupt */
6960 OUTB (nc_dien , 0); /* mask all dma interrupts */
6961 (void) INW (nc_sist); /* another one, just to be sure :) */
6962 OUTB (nc_scntl3, 4); /* set pre-scaler to divide by 3 */
6963 OUTB (nc_stime1, 0); /* disable general purpose timer */
6964 OUTB (nc_stime1, gen); /* set to nominal delay of (1<<gen) * 125us */
6965 while (!(INW(nc_sist) & GEN) && ms++ < 1000)
6966 DELAY(1000); /* count ms */
6967 OUTB (nc_stime1, 0); /* disable general purpose timer */
6968 OUTB (nc_scntl3, 0);
6969 /*
6970 * Set prescaler to divide by whatever "0" means.
6971 * "0" ought to choose divide by 2, but appears
6972 * to set divide by 3.5 mode in my 53c810 ...
6973 */
6974 OUTB (nc_scntl3, 0);
6975
6976 if (bootverbose >= 2)
6977 printf ("\tDelay (GEN=%d): %u msec\n", gen, ms);
6978 /*
6979 * adjust for prescaler, and convert into KHz
6980 */
6981 return ms ? ((1 << gen) * 4440) / ms : 0;
6982 }
6983
6984 static void ncr_getclock (ncb_p np, u_char multiplier)
6985 {
6986 unsigned char scntl3;
6987 unsigned char stest1;
6988 scntl3 = INB(nc_scntl3);
6989 stest1 = INB(nc_stest1);
6990
6991 np->multiplier = 1;
6992
6993 if (multiplier > 1) {
6994 np->multiplier = multiplier;
6995 np->clock_khz = 40000 * multiplier;
6996 } else {
6997 if ((scntl3 & 7) == 0) {
6998 unsigned f1, f2;
6999 /* throw away first result */
7000 (void) ncrgetfreq (np, 11);
7001 f1 = ncrgetfreq (np, 11);
7002 f2 = ncrgetfreq (np, 11);
7003
7004 if (bootverbose >= 2)
7005 printf ("\tNCR clock is %uKHz, %uKHz\n", f1, f2);
7006 if (f1 > f2) f1 = f2; /* trust lower result */
7007 if (f1 > 45000) {
7008 scntl3 = 5; /* >45Mhz: assume 80MHz */
7009 } else {
7010 scntl3 = 3; /* <45Mhz: assume 40MHz */
7011 }
7012 }
7013 else if ((scntl3 & 7) == 5)
7014 np->clock_khz = 80000; /* Probably a 875 rev. 1 ? */
7015 }
7016 }
7017
7018 /*=========================================================================*/
7019
7020 #ifdef NCR_TEKRAM_EEPROM
7021
7022 struct tekram_eeprom_dev {
7023 u_char devmode;
7024 #define TKR_PARCHK 0x01
7025 #define TKR_TRYSYNC 0x02
7026 #define TKR_ENDISC 0x04
7027 #define TKR_STARTUNIT 0x08
7028 #define TKR_USETAGS 0x10
7029 #define TKR_TRYWIDE 0x20
7030 u_char syncparam; /* max. sync transfer rate (table ?) */
7031 u_char filler1;
7032 u_char filler2;
7033 };
7034
7035
7036 struct tekram_eeprom {
7037 struct tekram_eeprom_dev
7038 dev[16];
7039 u_char adaptid;
7040 u_char adaptmode;
7041 #define TKR_ADPT_GT2DRV 0x01
7042 #define TKR_ADPT_GT1GB 0x02
7043 #define TKR_ADPT_RSTBUS 0x04
7044 #define TKR_ADPT_ACTNEG 0x08
7045 #define TKR_ADPT_NOSEEK 0x10
7046 #define TKR_ADPT_MORLUN 0x20
7047 u_char delay; /* unit ? ( table ??? ) */
7048 u_char tags; /* use 4 times as many ... */
7049 u_char filler[60];
7050 };
7051
7052 static void
7053 tekram_write_bit (ncb_p np, int bit)
7054 {
7055 u_char val = 0x10 + ((bit & 1) << 1);
7056
7057 DELAY(10);
7058 OUTB (nc_gpreg, val);
7059 DELAY(10);
7060 OUTB (nc_gpreg, val | 0x04);
7061 DELAY(10);
7062 OUTB (nc_gpreg, val);
7063 DELAY(10);
7064 }
7065
7066 static int
7067 tekram_read_bit (ncb_p np)
7068 {
7069 OUTB (nc_gpreg, 0x10);
7070 DELAY(10);
7071 OUTB (nc_gpreg, 0x14);
7072 DELAY(10);
7073 return INB (nc_gpreg) & 1;
7074 }
7075
7076 static u_short
7077 read_tekram_eeprom_reg (ncb_p np, int reg)
7078 {
7079 int bit;
7080 u_short result = 0;
7081 int cmd = 0x80 | reg;
7082
7083 OUTB (nc_gpreg, 0x10);
7084
7085 tekram_write_bit (np, 1);
7086 for (bit = 7; bit >= 0; bit--)
7087 {
7088 tekram_write_bit (np, cmd >> bit);
7089 }
7090
7091 for (bit = 0; bit < 16; bit++)
7092 {
7093 result <<= 1;
7094 result |= tekram_read_bit (np);
7095 }
7096
7097 OUTB (nc_gpreg, 0x00);
7098 return result;
7099 }
7100
7101 static int
7102 read_tekram_eeprom(ncb_p np, struct tekram_eeprom *buffer)
7103 {
7104 u_short *p = (u_short *) buffer;
7105 u_short sum = 0;
7106 int i;
7107
7108 if (INB (nc_gpcntl) != 0x09)
7109 {
7110 return 0;
7111 }
7112 for (i = 0; i < 64; i++)
7113 {
7114 u_short val;
7115 if((i&0x0f) == 0) printf ("%02x:", i*2);
7116 val = read_tekram_eeprom_reg (np, i);
7117 if (p)
7118 *p++ = val;
7119 sum += val;
7120 if((i&0x01) == 0x00) printf (" ");
7121 printf ("%02x%02x", val & 0xff, (val >> 8) & 0xff);
7122 if((i&0x0f) == 0x0f) printf ("\n");
7123 }
7124 printf ("Sum = %04x\n", sum);
7125 return sum == 0x1234;
7126 }
7127 #endif /* NCR_TEKRAM_EEPROM */
7128
7129 static device_method_t ncr_methods[] = {
7130 /* Device interface */
7131 DEVMETHOD(device_probe, ncr_probe),
7132 DEVMETHOD(device_attach, ncr_attach),
7133
7134 { 0, 0 }
7135 };
7136
7137 static driver_t ncr_driver = {
7138 "ncr",
7139 ncr_methods,
7140 sizeof(struct ncb),
7141 };
7142
7143 static devclass_t ncr_devclass;
7144
7145 DRIVER_MODULE(if_ncr, pci, ncr_driver, ncr_devclass, 0, 0);
7146
7147 /*=========================================================================*/
7148 #endif /* _KERNEL */
Port diff from OpenBSD to DragonFly