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- Set number of TX descriptors to 512.
[dfdiff.git] / sys / dev / netif / msk / if_msk.c
blob25de3a4adc01e6618f32fe9465756997469bfd43
1 /******************************************************************************
2 *
3 * Name : sky2.c
4 * Project: Gigabit Ethernet Driver for FreeBSD 5.x/6.x
5 * Version: $Revision: 1.23 $
6 * Date : $Date: 2005/12/22 09:04:11 $
7 * Purpose: Main driver source file
8 *
9 *****************************************************************************/
10
11 /******************************************************************************
12 *
13 * LICENSE:
14 * Copyright (C) Marvell International Ltd. and/or its affiliates
15 *
16 * The computer program files contained in this folder ("Files")
17 * are provided to you under the BSD-type license terms provided
18 * below, and any use of such Files and any derivative works
19 * thereof created by you shall be governed by the following terms
20 * and conditions:
21 *
22 * - Redistributions of source code must retain the above copyright
23 * notice, this list of conditions and the following disclaimer.
24 * - Redistributions in binary form must reproduce the above
25 * copyright notice, this list of conditions and the following
26 * disclaimer in the documentation and/or other materials provided
27 * with the distribution.
28 * - Neither the name of Marvell nor the names of its contributors
29 * may be used to endorse or promote products derived from this
30 * software without specific prior written permission.
31 *
32 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
33 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
34 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
35 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
36 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
37 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
38 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
39 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
40 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
41 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
42 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
43 * OF THE POSSIBILITY OF SUCH DAMAGE.
44 * /LICENSE
45 *
46 *****************************************************************************/
47
48 /*-
49 * Copyright (c) 1997, 1998, 1999, 2000
50 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
51 *
52 * Redistribution and use in source and binary forms, with or without
53 * modification, are permitted provided that the following conditions
54 * are met:
55 * 1. Redistributions of source code must retain the above copyright
56 * notice, this list of conditions and the following disclaimer.
57 * 2. Redistributions in binary form must reproduce the above copyright
58 * notice, this list of conditions and the following disclaimer in the
59 * documentation and/or other materials provided with the distribution.
60 * 3. All advertising materials mentioning features or use of this software
61 * must display the following acknowledgement:
62 * This product includes software developed by Bill Paul.
63 * 4. Neither the name of the author nor the names of any co-contributors
64 * may be used to endorse or promote products derived from this software
65 * without specific prior written permission.
66 *
67 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
68 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
69 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
70 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
71 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
72 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
73 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
74 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
75 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
76 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
77 * THE POSSIBILITY OF SUCH DAMAGE.
78 */
79 /*-
80 * Copyright (c) 2003 Nathan L. Binkert <binkertn@umich.edu>
81 *
82 * Permission to use, copy, modify, and distribute this software for any
83 * purpose with or without fee is hereby granted, provided that the above
84 * copyright notice and this permission notice appear in all copies.
85 *
86 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
87 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
88 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
89 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
90 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
91 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
92 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
93 */
94
95 /* $FreeBSD: src/sys/dev/msk/if_msk.c,v 1.26 2007/12/05 09:41:58 remko Exp $ */
96 /* $DragonFly: src/sys/dev/netif/msk/if_msk.c,v 1.2 2008/03/22 07:07:34 sephe Exp $ */
97
98 /*
99 * Device driver for the Marvell Yukon II Ethernet controller.
100 * Due to lack of documentation, this driver is based on the code from
101 * sk(4) and Marvell's myk(4) driver for FreeBSD 5.x.
102 */
103
104 #include <sys/param.h>
105 #include <sys/endian.h>
106 #include <sys/kernel.h>
107 #include <sys/bus.h>
108 #include <sys/in_cksum.h>
109 #include <sys/malloc.h>
110 #include <sys/proc.h>
111 #include <sys/rman.h>
112 #include <sys/serialize.h>
113 #include <sys/socket.h>
114 #include <sys/sockio.h>
115 #include <sys/sysctl.h>
116
117 #include <net/ethernet.h>
118 #include <net/if.h>
119 #include <net/bpf.h>
120 #include <net/if_arp.h>
121 #include <net/if_dl.h>
122 #include <net/if_media.h>
123 #include <net/ifq_var.h>
124 #include <net/vlan/if_vlan_var.h>
125
126 #include <netinet/ip.h>
127 #include <netinet/ip_var.h>
128
129 #include <dev/netif/mii_layer/miivar.h>
130
131 #include <bus/pci/pcireg.h>
132 #include <bus/pci/pcivar.h>
133
134 #include "if_mskreg.h"
135
136 /* "device miibus" required. See GENERIC if you get errors here. */
137 #include "miibus_if.h"
138
139 #define MSK_CSUM_FEATURES (CSUM_TCP | CSUM_UDP)
140
141 /*
142 * Devices supported by this driver.
143 */
144 static const struct msk_product {
145 uint16_t msk_vendorid;
146 uint16_t msk_deviceid;
147 const char *msk_name;
148 } msk_products[] = {
149 { VENDORID_SK, DEVICEID_SK_YUKON2,
150 "SK-9Sxx Gigabit Ethernet" },
151 { VENDORID_SK, DEVICEID_SK_YUKON2_EXPR,
152 "SK-9Exx Gigabit Ethernet"},
153 { VENDORID_MARVELL, DEVICEID_MRVL_8021CU,
154 "Marvell Yukon 88E8021CU Gigabit Ethernet" },
155 { VENDORID_MARVELL, DEVICEID_MRVL_8021X,
156 "Marvell Yukon 88E8021 SX/LX Gigabit Ethernet" },
157 { VENDORID_MARVELL, DEVICEID_MRVL_8022CU,
158 "Marvell Yukon 88E8022CU Gigabit Ethernet" },
159 { VENDORID_MARVELL, DEVICEID_MRVL_8022X,
160 "Marvell Yukon 88E8022 SX/LX Gigabit Ethernet" },
161 { VENDORID_MARVELL, DEVICEID_MRVL_8061CU,
162 "Marvell Yukon 88E8061CU Gigabit Ethernet" },
163 { VENDORID_MARVELL, DEVICEID_MRVL_8061X,
164 "Marvell Yukon 88E8061 SX/LX Gigabit Ethernet" },
165 { VENDORID_MARVELL, DEVICEID_MRVL_8062CU,
166 "Marvell Yukon 88E8062CU Gigabit Ethernet" },
167 { VENDORID_MARVELL, DEVICEID_MRVL_8062X,
168 "Marvell Yukon 88E8062 SX/LX Gigabit Ethernet" },
169 { VENDORID_MARVELL, DEVICEID_MRVL_8035,
170 "Marvell Yukon 88E8035 Gigabit Ethernet" },
171 { VENDORID_MARVELL, DEVICEID_MRVL_8036,
172 "Marvell Yukon 88E8036 Gigabit Ethernet" },
173 { VENDORID_MARVELL, DEVICEID_MRVL_8038,
174 "Marvell Yukon 88E8038 Gigabit Ethernet" },
175 { VENDORID_MARVELL, DEVICEID_MRVL_8039,
176 "Marvell Yukon 88E8039 Gigabit Ethernet" },
177 { VENDORID_MARVELL, DEVICEID_MRVL_4361,
178 "Marvell Yukon 88E8050 Gigabit Ethernet" },
179 { VENDORID_MARVELL, DEVICEID_MRVL_4360,
180 "Marvell Yukon 88E8052 Gigabit Ethernet" },
181 { VENDORID_MARVELL, DEVICEID_MRVL_4362,
182 "Marvell Yukon 88E8053 Gigabit Ethernet" },
183 { VENDORID_MARVELL, DEVICEID_MRVL_4363,
184 "Marvell Yukon 88E8055 Gigabit Ethernet" },
185 { VENDORID_MARVELL, DEVICEID_MRVL_4364,
186 "Marvell Yukon 88E8056 Gigabit Ethernet" },
187 { VENDORID_MARVELL, DEVICEID_MRVL_436A,
188 "Marvell Yukon 88E8058 Gigabit Ethernet" },
189 { VENDORID_DLINK, DEVICEID_DLINK_DGE550SX,
190 "D-Link 550SX Gigabit Ethernet" },
191 { VENDORID_DLINK, DEVICEID_DLINK_DGE560T,
192 "D-Link 560T Gigabit Ethernet" },
193 { 0, 0, NULL }
194 };
195
196 static const char *model_name[] = {
197 "Yukon XL",
198 "Yukon EC Ultra",
199 "Yukon Unknown",
200 "Yukon EC",
201 "Yukon FE"
202 };
203
204 static int mskc_probe(device_t);
205 static int mskc_attach(device_t);
206 static int mskc_detach(device_t);
207 static int mskc_shutdown(device_t);
208 static int mskc_suspend(device_t);
209 static int mskc_resume(device_t);
210 static void mskc_intr(void *);
211
212 static void mskc_reset(struct msk_softc *);
213 static void mskc_set_imtimer(struct msk_softc *);
214 static void mskc_intr_hwerr(struct msk_softc *);
215 static int mskc_handle_events(struct msk_softc *);
216 static void mskc_phy_power(struct msk_softc *, int);
217 static int mskc_setup_rambuffer(struct msk_softc *);
218 static int mskc_status_dma_alloc(struct msk_softc *);
219 static void mskc_status_dma_free(struct msk_softc *);
220 static int mskc_sysctl_proc_limit(SYSCTL_HANDLER_ARGS);
221 static int mskc_sysctl_intr_rate(SYSCTL_HANDLER_ARGS);
222
223 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int);
224
225 static int msk_probe(device_t);
226 static int msk_attach(device_t);
227 static int msk_detach(device_t);
228 static int msk_miibus_readreg(device_t, int, int);
229 static int msk_miibus_writereg(device_t, int, int, int);
230 static void msk_miibus_statchg(device_t);
231
232 static void msk_init(void *);
233 static int msk_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
234 static void msk_start(struct ifnet *);
235 static void msk_watchdog(struct ifnet *);
236 static int msk_mediachange(struct ifnet *);
237 static void msk_mediastatus(struct ifnet *, struct ifmediareq *);
238
239 static void msk_tick(void *);
240 static void msk_intr_phy(struct msk_if_softc *);
241 static void msk_intr_gmac(struct msk_if_softc *);
242 static __inline void
243 msk_rxput(struct msk_if_softc *);
244 static void msk_handle_hwerr(struct msk_if_softc *, uint32_t);
245 static void msk_rxeof(struct msk_if_softc *, uint32_t, int);
246 static void msk_txeof(struct msk_if_softc *, int);
247 static void msk_set_prefetch(struct msk_softc *, int, bus_addr_t, uint32_t);
248 static void msk_set_rambuffer(struct msk_if_softc *);
249 static void msk_stop(struct msk_if_softc *);
250
251 static void msk_dmamap_cb(void *, bus_dma_segment_t *, int, int);
252 static void msk_dmamap_mbuf_cb(void *, bus_dma_segment_t *, int,
253 bus_size_t, int);
254 static int msk_txrx_dma_alloc(struct msk_if_softc *);
255 static void msk_txrx_dma_free(struct msk_if_softc *);
256 static int msk_init_rx_ring(struct msk_if_softc *);
257 static void msk_init_tx_ring(struct msk_if_softc *);
258 static __inline void
259 msk_discard_rxbuf(struct msk_if_softc *, int);
260 static int msk_newbuf(struct msk_if_softc *, int);
261 static struct mbuf *
262 msk_defrag(struct mbuf *, int, int);
263 static int msk_encap(struct msk_if_softc *, struct mbuf **);
264
265 #ifdef MSK_JUMBO
266 static int msk_init_jumbo_rx_ring(struct msk_if_softc *);
267 static __inline void msk_discard_jumbo_rxbuf(struct msk_if_softc *, int);
268 static int msk_jumbo_newbuf(struct msk_if_softc *, int);
269 static void msk_jumbo_rxeof(struct msk_if_softc *, uint32_t, int);
270 static void *msk_jalloc(struct msk_if_softc *);
271 static void msk_jfree(void *, void *);
272 #endif
273
274 static int msk_phy_readreg(struct msk_if_softc *, int, int);
275 static int msk_phy_writereg(struct msk_if_softc *, int, int, int);
276
277 static void msk_setmulti(struct msk_if_softc *);
278 static void msk_setvlan(struct msk_if_softc *, struct ifnet *);
279 static void msk_setpromisc(struct msk_if_softc *);
280
281 static int msk_dmamem_create(device_t, bus_size_t, bus_dma_tag_t *,
282 void **, bus_addr_t *, bus_dmamap_t *);
283 static void msk_dmamem_destroy(bus_dma_tag_t, void *, bus_dmamap_t);
284
285 static device_method_t mskc_methods[] = {
286 /* Device interface */
287 DEVMETHOD(device_probe, mskc_probe),
288 DEVMETHOD(device_attach, mskc_attach),
289 DEVMETHOD(device_detach, mskc_detach),
290 DEVMETHOD(device_suspend, mskc_suspend),
291 DEVMETHOD(device_resume, mskc_resume),
292 DEVMETHOD(device_shutdown, mskc_shutdown),
293
294 /* bus interface */
295 DEVMETHOD(bus_print_child, bus_generic_print_child),
296 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
297
298 { NULL, NULL }
299 };
300
301 static DEFINE_CLASS_0(mskc, mskc_driver, mskc_methods, sizeof(struct msk_softc));
302 static devclass_t mskc_devclass;
303
304 static device_method_t msk_methods[] = {
305 /* Device interface */
306 DEVMETHOD(device_probe, msk_probe),
307 DEVMETHOD(device_attach, msk_attach),
308 DEVMETHOD(device_detach, msk_detach),
309 DEVMETHOD(device_shutdown, bus_generic_shutdown),
310
311 /* bus interface */
312 DEVMETHOD(bus_print_child, bus_generic_print_child),
313 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
314
315 /* MII interface */
316 DEVMETHOD(miibus_readreg, msk_miibus_readreg),
317 DEVMETHOD(miibus_writereg, msk_miibus_writereg),
318 DEVMETHOD(miibus_statchg, msk_miibus_statchg),
319
320 { NULL, NULL }
321 };
322
323 static DEFINE_CLASS_0(msk, msk_driver, msk_methods, sizeof(struct msk_if_softc));
324 static devclass_t msk_devclass;
325
326 DECLARE_DUMMY_MODULE(if_msk);
327 DRIVER_MODULE(if_msk, pci, mskc_driver, mskc_devclass, 0, 0);
328 DRIVER_MODULE(if_msk, mskc, msk_driver, msk_devclass, 0, 0);
329 DRIVER_MODULE(miibus, msk, miibus_driver, miibus_devclass, 0, 0);
330
331 static int mskc_intr_rate = 0;
332 static int mskc_process_limit = MSK_PROC_DEFAULT;
333
334 TUNABLE_INT("hw.mskc.intr_rate", &mskc_intr_rate);
335 TUNABLE_INT("hw.mskc.process_limit", &mskc_process_limit);
336
337 static int
338 msk_miibus_readreg(device_t dev, int phy, int reg)
339 {
340 struct msk_if_softc *sc_if;
341
342 if (phy != PHY_ADDR_MARV)
343 return (0);
344
345 sc_if = device_get_softc(dev);
346
347 return (msk_phy_readreg(sc_if, phy, reg));
348 }
349
350 static int
351 msk_phy_readreg(struct msk_if_softc *sc_if, int phy, int reg)
352 {
353 struct msk_softc *sc;
354 int i, val;
355
356 sc = sc_if->msk_softc;
357
358 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SMI_CTRL,
359 GM_SMI_CT_PHY_AD(phy) | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
360
361 for (i = 0; i < MSK_TIMEOUT; i++) {
362 DELAY(1);
363 val = GMAC_READ_2(sc, sc_if->msk_port, GM_SMI_CTRL);
364 if ((val & GM_SMI_CT_RD_VAL) != 0) {
365 val = GMAC_READ_2(sc, sc_if->msk_port, GM_SMI_DATA);
366 break;
367 }
368 }
369
370 if (i == MSK_TIMEOUT) {
371 if_printf(sc_if->msk_ifp, "phy failed to come ready\n");
372 val = 0;
373 }
374
375 return (val);
376 }
377
378 static int
379 msk_miibus_writereg(device_t dev, int phy, int reg, int val)
380 {
381 struct msk_if_softc *sc_if;
382
383 if (phy != PHY_ADDR_MARV)
384 return (0);
385
386 sc_if = device_get_softc(dev);
387
388 return (msk_phy_writereg(sc_if, phy, reg, val));
389 }
390
391 static int
392 msk_phy_writereg(struct msk_if_softc *sc_if, int phy, int reg, int val)
393 {
394 struct msk_softc *sc;
395 int i;
396
397 sc = sc_if->msk_softc;
398
399 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SMI_DATA, val);
400 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SMI_CTRL,
401 GM_SMI_CT_PHY_AD(phy) | GM_SMI_CT_REG_AD(reg));
402 for (i = 0; i < MSK_TIMEOUT; i++) {
403 DELAY(1);
404 if ((GMAC_READ_2(sc, sc_if->msk_port, GM_SMI_CTRL) &
405 GM_SMI_CT_BUSY) == 0)
406 break;
407 }
408 if (i == MSK_TIMEOUT)
409 if_printf(sc_if->msk_ifp, "phy write timeout\n");
410
411 return (0);
412 }
413
414 static void
415 msk_miibus_statchg(device_t dev)
416 {
417 struct msk_if_softc *sc_if;
418 struct msk_softc *sc;
419 struct mii_data *mii;
420 struct ifnet *ifp;
421 uint32_t gmac;
422
423 sc_if = device_get_softc(dev);
424 sc = sc_if->msk_softc;
425
426 mii = device_get_softc(sc_if->msk_miibus);
427 ifp = sc_if->msk_ifp;
428
429 if (mii->mii_media_status & IFM_ACTIVE) {
430 if (IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE)
431 sc_if->msk_link = 1;
432 } else
433 sc_if->msk_link = 0;
434
435 if (sc_if->msk_link != 0) {
436 /* Enable Tx FIFO Underrun. */
437 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, GMAC_IRQ_MSK),
438 GM_IS_TX_FF_UR | GM_IS_RX_FF_OR);
439 /*
440 * Because mii(4) notify msk(4) that it detected link status
441 * change, there is no need to enable automatic
442 * speed/flow-control/duplex updates.
443 */
444 gmac = GM_GPCR_AU_ALL_DIS;
445 switch (IFM_SUBTYPE(mii->mii_media_active)) {
446 case IFM_1000_SX:
447 case IFM_1000_T:
448 gmac |= GM_GPCR_SPEED_1000;
449 break;
450 case IFM_100_TX:
451 gmac |= GM_GPCR_SPEED_100;
452 break;
453 case IFM_10_T:
454 break;
455 }
456
457 if (((mii->mii_media_active & IFM_GMASK) & IFM_FDX) != 0)
458 gmac |= GM_GPCR_DUP_FULL;
459 /* Disable Rx flow control. */
460 if (((mii->mii_media_active & IFM_GMASK) & IFM_FLAG0) == 0)
461 gmac |= GM_GPCR_FC_RX_DIS;
462 /* Disable Tx flow control. */
463 if (((mii->mii_media_active & IFM_GMASK) & IFM_FLAG1) == 0)
464 gmac |= GM_GPCR_FC_TX_DIS;
465 gmac |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
466 GMAC_WRITE_2(sc, sc_if->msk_port, GM_GP_CTRL, gmac);
467 /* Read again to ensure writing. */
468 GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL);
469
470 gmac = GMC_PAUSE_ON;
471 if (((mii->mii_media_active & IFM_GMASK) &
472 (IFM_FLAG0 | IFM_FLAG1)) == 0)
473 gmac = GMC_PAUSE_OFF;
474 /* Diable pause for 10/100 Mbps in half-duplex mode. */
475 if ((((mii->mii_media_active & IFM_GMASK) & IFM_FDX) == 0) &&
476 (IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX ||
477 IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T))
478 gmac = GMC_PAUSE_OFF;
479 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), gmac);
480
481 /* Enable PHY interrupt for FIFO underrun/overflow. */
482 msk_phy_writereg(sc_if, PHY_ADDR_MARV,
483 PHY_MARV_INT_MASK, PHY_M_IS_FIFO_ERROR);
484 } else {
485 /*
486 * Link state changed to down.
487 * Disable PHY interrupts.
488 */
489 msk_phy_writereg(sc_if, PHY_ADDR_MARV, PHY_MARV_INT_MASK, 0);
490 /* Disable Rx/Tx MAC. */
491 gmac = GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL);
492 gmac &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
493 GMAC_WRITE_2(sc, sc_if->msk_port, GM_GP_CTRL, gmac);
494 /* Read again to ensure writing. */
495 GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL);
496 }
497 }
498
499 static void
500 msk_setmulti(struct msk_if_softc *sc_if)
501 {
502 struct msk_softc *sc;
503 struct ifnet *ifp;
504 struct ifmultiaddr *ifma;
505 uint32_t mchash[2];
506 uint32_t crc;
507 uint16_t mode;
508
509 sc = sc_if->msk_softc;
510 ifp = sc_if->msk_ifp;
511
512 bzero(mchash, sizeof(mchash));
513 mode = GMAC_READ_2(sc, sc_if->msk_port, GM_RX_CTRL);
514 mode |= GM_RXCR_UCF_ENA;
515 if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) {
516 if ((ifp->if_flags & IFF_PROMISC) != 0)
517 mode &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
518 else if ((ifp->if_flags & IFF_ALLMULTI) != 0) {
519 mchash[0] = 0xffff;
520 mchash[1] = 0xffff;
521 }
522 } else {
523 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
524 if (ifma->ifma_addr->sa_family != AF_LINK)
525 continue;
526 crc = ether_crc32_be(LLADDR((struct sockaddr_dl *)
527 ifma->ifma_addr), ETHER_ADDR_LEN);
528 /* Just want the 6 least significant bits. */
529 crc &= 0x3f;
530 /* Set the corresponding bit in the hash table. */
531 mchash[crc >> 5] |= 1 << (crc & 0x1f);
532 }
533 mode |= GM_RXCR_MCF_ENA;
534 }
535
536 GMAC_WRITE_2(sc, sc_if->msk_port, GM_MC_ADDR_H1,
537 mchash[0] & 0xffff);
538 GMAC_WRITE_2(sc, sc_if->msk_port, GM_MC_ADDR_H2,
539 (mchash[0] >> 16) & 0xffff);
540 GMAC_WRITE_2(sc, sc_if->msk_port, GM_MC_ADDR_H3,
541 mchash[1] & 0xffff);
542 GMAC_WRITE_2(sc, sc_if->msk_port, GM_MC_ADDR_H4,
543 (mchash[1] >> 16) & 0xffff);
544 GMAC_WRITE_2(sc, sc_if->msk_port, GM_RX_CTRL, mode);
545 }
546
547 static void
548 msk_setvlan(struct msk_if_softc *sc_if, struct ifnet *ifp)
549 {
550 struct msk_softc *sc;
551
552 sc = sc_if->msk_softc;
553 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) {
554 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T),
555 RX_VLAN_STRIP_ON);
556 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T),
557 TX_VLAN_TAG_ON);
558 } else {
559 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T),
560 RX_VLAN_STRIP_OFF);
561 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T),
562 TX_VLAN_TAG_OFF);
563 }
564 }
565
566 static void
567 msk_setpromisc(struct msk_if_softc *sc_if)
568 {
569 struct msk_softc *sc;
570 struct ifnet *ifp;
571 uint16_t mode;
572
573 sc = sc_if->msk_softc;
574 ifp = sc_if->msk_ifp;
575
576 mode = GMAC_READ_2(sc, sc_if->msk_port, GM_RX_CTRL);
577 if (ifp->if_flags & IFF_PROMISC)
578 mode &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
579 else
580 mode |= (GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
581 GMAC_WRITE_2(sc, sc_if->msk_port, GM_RX_CTRL, mode);
582 }
583
584 static int
585 msk_init_rx_ring(struct msk_if_softc *sc_if)
586 {
587 struct msk_ring_data *rd;
588 struct msk_rxdesc *rxd;
589 int i, prod;
590
591 sc_if->msk_cdata.msk_rx_cons = 0;
592 sc_if->msk_cdata.msk_rx_prod = 0;
593 sc_if->msk_cdata.msk_rx_putwm = MSK_PUT_WM;
594
595 rd = &sc_if->msk_rdata;
596 bzero(rd->msk_rx_ring, sizeof(struct msk_rx_desc) * MSK_RX_RING_CNT);
597 prod = sc_if->msk_cdata.msk_rx_prod;
598 for (i = 0; i < MSK_RX_RING_CNT; i++) {
599 rxd = &sc_if->msk_cdata.msk_rxdesc[prod];
600 rxd->rx_m = NULL;
601 rxd->rx_le = &rd->msk_rx_ring[prod];
602 if (msk_newbuf(sc_if, prod) != 0)
603 return (ENOBUFS);
604 MSK_INC(prod, MSK_RX_RING_CNT);
605 }
606
607 bus_dmamap_sync(sc_if->msk_cdata.msk_rx_ring_tag,
608 sc_if->msk_cdata.msk_rx_ring_map, BUS_DMASYNC_PREWRITE);
609
610 /* Update prefetch unit. */
611 sc_if->msk_cdata.msk_rx_prod = MSK_RX_RING_CNT - 1;
612 CSR_WRITE_2(sc_if->msk_softc,
613 Y2_PREF_Q_ADDR(sc_if->msk_rxq, PREF_UNIT_PUT_IDX_REG),
614 sc_if->msk_cdata.msk_rx_prod);
615
616 return (0);
617 }
618
619 #ifdef MSK_JUMBO
620 static int
621 msk_init_jumbo_rx_ring(struct msk_if_softc *sc_if)
622 {
623 struct msk_ring_data *rd;
624 struct msk_rxdesc *rxd;
625 int i, prod;
626
627 MSK_IF_LOCK_ASSERT(sc_if);
628
629 sc_if->msk_cdata.msk_rx_cons = 0;
630 sc_if->msk_cdata.msk_rx_prod = 0;
631 sc_if->msk_cdata.msk_rx_putwm = MSK_PUT_WM;
632
633 rd = &sc_if->msk_rdata;
634 bzero(rd->msk_jumbo_rx_ring,
635 sizeof(struct msk_rx_desc) * MSK_JUMBO_RX_RING_CNT);
636 prod = sc_if->msk_cdata.msk_rx_prod;
637 for (i = 0; i < MSK_JUMBO_RX_RING_CNT; i++) {
638 rxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[prod];
639 rxd->rx_m = NULL;
640 rxd->rx_le = &rd->msk_jumbo_rx_ring[prod];
641 if (msk_jumbo_newbuf(sc_if, prod) != 0)
642 return (ENOBUFS);
643 MSK_INC(prod, MSK_JUMBO_RX_RING_CNT);
644 }
645
646 bus_dmamap_sync(sc_if->msk_cdata.msk_jumbo_rx_ring_tag,
647 sc_if->msk_cdata.msk_jumbo_rx_ring_map,
648 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
649
650 sc_if->msk_cdata.msk_rx_prod = MSK_JUMBO_RX_RING_CNT - 1;
651 CSR_WRITE_2(sc_if->msk_softc,
652 Y2_PREF_Q_ADDR(sc_if->msk_rxq, PREF_UNIT_PUT_IDX_REG),
653 sc_if->msk_cdata.msk_rx_prod);
654
655 return (0);
656 }
657 #endif
658
659 static void
660 msk_init_tx_ring(struct msk_if_softc *sc_if)
661 {
662 struct msk_ring_data *rd;
663 struct msk_txdesc *txd;
664 int i;
665
666 sc_if->msk_cdata.msk_tx_prod = 0;
667 sc_if->msk_cdata.msk_tx_cons = 0;
668 sc_if->msk_cdata.msk_tx_cnt = 0;
669
670 rd = &sc_if->msk_rdata;
671 bzero(rd->msk_tx_ring, sizeof(struct msk_tx_desc) * MSK_TX_RING_CNT);
672 for (i = 0; i < MSK_TX_RING_CNT; i++) {
673 txd = &sc_if->msk_cdata.msk_txdesc[i];
674 txd->tx_m = NULL;
675 txd->tx_le = &rd->msk_tx_ring[i];
676 }
677
678 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_ring_tag,
679 sc_if->msk_cdata.msk_tx_ring_map, BUS_DMASYNC_PREWRITE);
680 }
681
682 static __inline void
683 msk_discard_rxbuf(struct msk_if_softc *sc_if, int idx)
684 {
685 struct msk_rx_desc *rx_le;
686 struct msk_rxdesc *rxd;
687 struct mbuf *m;
688
689 rxd = &sc_if->msk_cdata.msk_rxdesc[idx];
690 m = rxd->rx_m;
691 rx_le = rxd->rx_le;
692 rx_le->msk_control = htole32(m->m_len | OP_PACKET | HW_OWNER);
693 }
694
695 #ifdef MSK_JUMBO
696 static __inline void
697 msk_discard_jumbo_rxbuf(struct msk_if_softc *sc_if, int idx)
698 {
699 struct msk_rx_desc *rx_le;
700 struct msk_rxdesc *rxd;
701 struct mbuf *m;
702
703 rxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[idx];
704 m = rxd->rx_m;
705 rx_le = rxd->rx_le;
706 rx_le->msk_control = htole32(m->m_len | OP_PACKET | HW_OWNER);
707 }
708 #endif
709
710 static int
711 msk_newbuf(struct msk_if_softc *sc_if, int idx)
712 {
713 struct msk_rx_desc *rx_le;
714 struct msk_rxdesc *rxd;
715 struct mbuf *m;
716 struct msk_dmamap_arg ctx;
717 bus_dma_segment_t seg;
718 bus_dmamap_t map;
719
720 m = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR);
721 if (m == NULL)
722 return (ENOBUFS);
723
724 m->m_len = m->m_pkthdr.len = MCLBYTES;
725 m_adj(m, ETHER_ALIGN);
726
727 bzero(&ctx, sizeof(ctx));
728 ctx.nseg = 1;
729 ctx.segs = &seg;
730 if (bus_dmamap_load_mbuf(sc_if->msk_cdata.msk_rx_tag,
731 sc_if->msk_cdata.msk_rx_sparemap, m, msk_dmamap_mbuf_cb, &ctx,
732 BUS_DMA_NOWAIT) != 0) {
733 m_freem(m);
734 return (ENOBUFS);
735 }
736 KASSERT(ctx.nseg == 1,
737 ("%s: %d segments returned!", __func__, ctx.nseg));
738
739 rxd = &sc_if->msk_cdata.msk_rxdesc[idx];
740 if (rxd->rx_m != NULL) {
741 bus_dmamap_sync(sc_if->msk_cdata.msk_rx_tag, rxd->rx_dmamap,
742 BUS_DMASYNC_POSTREAD);
743 bus_dmamap_unload(sc_if->msk_cdata.msk_rx_tag, rxd->rx_dmamap);
744 }
745 map = rxd->rx_dmamap;
746 rxd->rx_dmamap = sc_if->msk_cdata.msk_rx_sparemap;
747 sc_if->msk_cdata.msk_rx_sparemap = map;
748 bus_dmamap_sync(sc_if->msk_cdata.msk_rx_tag, rxd->rx_dmamap,
749 BUS_DMASYNC_PREREAD);
750 rxd->rx_m = m;
751 rx_le = rxd->rx_le;
752 rx_le->msk_addr = htole32(MSK_ADDR_LO(seg.ds_addr));
753 rx_le->msk_control =
754 htole32(seg.ds_len | OP_PACKET | HW_OWNER);
755
756 return (0);
757 }
758
759 #ifdef MSK_JUMBO
760 static int
761 msk_jumbo_newbuf(struct msk_if_softc *sc_if, int idx)
762 {
763 struct msk_rx_desc *rx_le;
764 struct msk_rxdesc *rxd;
765 struct mbuf *m;
766 bus_dma_segment_t segs[1];
767 bus_dmamap_t map;
768 int nsegs;
769 void *buf;
770
771 MGETHDR(m, M_DONTWAIT, MT_DATA);
772 if (m == NULL)
773 return (ENOBUFS);
774 buf = msk_jalloc(sc_if);
775 if (buf == NULL) {
776 m_freem(m);
777 return (ENOBUFS);
778 }
779 /* Attach the buffer to the mbuf. */
780 MEXTADD(m, buf, MSK_JLEN, msk_jfree, (struct msk_if_softc *)sc_if, 0,
781 EXT_NET_DRV);
782 if ((m->m_flags & M_EXT) == 0) {
783 m_freem(m);
784 return (ENOBUFS);
785 }
786 m->m_pkthdr.len = m->m_len = MSK_JLEN;
787 m_adj(m, ETHER_ALIGN);
788
789 if (bus_dmamap_load_mbuf_sg(sc_if->msk_cdata.msk_jumbo_rx_tag,
790 sc_if->msk_cdata.msk_jumbo_rx_sparemap, m, segs, &nsegs,
791 BUS_DMA_NOWAIT) != 0) {
792 m_freem(m);
793 return (ENOBUFS);
794 }
795 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
796
797 rxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[idx];
798 if (rxd->rx_m != NULL) {
799 bus_dmamap_sync(sc_if->msk_cdata.msk_jumbo_rx_tag,
800 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD);
801 bus_dmamap_unload(sc_if->msk_cdata.msk_jumbo_rx_tag,
802 rxd->rx_dmamap);
803 }
804 map = rxd->rx_dmamap;
805 rxd->rx_dmamap = sc_if->msk_cdata.msk_jumbo_rx_sparemap;
806 sc_if->msk_cdata.msk_jumbo_rx_sparemap = map;
807 bus_dmamap_sync(sc_if->msk_cdata.msk_jumbo_rx_tag, rxd->rx_dmamap,
808 BUS_DMASYNC_PREREAD);
809 rxd->rx_m = m;
810 rx_le = rxd->rx_le;
811 rx_le->msk_addr = htole32(MSK_ADDR_LO(segs[0].ds_addr));
812 rx_le->msk_control =
813 htole32(segs[0].ds_len | OP_PACKET | HW_OWNER);
814
815 return (0);
816 }
817 #endif
818
819 /*
820 * Set media options.
821 */
822 static int
823 msk_mediachange(struct ifnet *ifp)
824 {
825 struct msk_if_softc *sc_if = ifp->if_softc;
826 struct mii_data *mii;
827
828 mii = device_get_softc(sc_if->msk_miibus);
829 mii_mediachg(mii);
830
831 return (0);
832 }
833
834 /*
835 * Report current media status.
836 */
837 static void
838 msk_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr)
839 {
840 struct msk_if_softc *sc_if = ifp->if_softc;
841 struct mii_data *mii;
842
843 mii = device_get_softc(sc_if->msk_miibus);
844 mii_pollstat(mii);
845
846 ifmr->ifm_active = mii->mii_media_active;
847 ifmr->ifm_status = mii->mii_media_status;
848 }
849
850 static int
851 msk_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
852 {
853 struct msk_if_softc *sc_if;
854 struct ifreq *ifr;
855 struct mii_data *mii;
856 int error, mask;
857
858 sc_if = ifp->if_softc;
859 ifr = (struct ifreq *)data;
860 error = 0;
861
862 switch(command) {
863 case SIOCSIFMTU:
864 #ifdef MSK_JUMBO
865 if (ifr->ifr_mtu > MSK_JUMBO_MTU || ifr->ifr_mtu < ETHERMIN) {
866 error = EINVAL;
867 break;
868 }
869 if (sc_if->msk_softc->msk_hw_id == CHIP_ID_YUKON_FE &&
870 ifr->ifr_mtu > MSK_MAX_FRAMELEN) {
871 error = EINVAL;
872 break;
873 }
874 ifp->if_mtu = ifr->ifr_mtu;
875 if ((ifp->if_flags & IFF_RUNNING) != 0)
876 msk_init(sc_if);
877 #else
878 error = EOPNOTSUPP;
879 #endif
880 break;
881
882 case SIOCSIFFLAGS:
883 if (ifp->if_flags & IFF_UP) {
884 if (ifp->if_flags & IFF_RUNNING) {
885 if (((ifp->if_flags ^ sc_if->msk_if_flags)
886 & IFF_PROMISC) != 0) {
887 msk_setpromisc(sc_if);
888 msk_setmulti(sc_if);
889 }
890 } else {
891 if (sc_if->msk_detach == 0)
892 msk_init(sc_if);
893 }
894 } else {
895 if (ifp->if_flags & IFF_RUNNING)
896 msk_stop(sc_if);
897 }
898 sc_if->msk_if_flags = ifp->if_flags;
899 break;
900
901 case SIOCADDMULTI:
902 case SIOCDELMULTI:
903 if (ifp->if_flags & IFF_RUNNING)
904 msk_setmulti(sc_if);
905 break;
906
907 case SIOCGIFMEDIA:
908 case SIOCSIFMEDIA:
909 mii = device_get_softc(sc_if->msk_miibus);
910 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
911 break;
912
913 case SIOCSIFCAP:
914 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
915 if ((mask & IFCAP_TXCSUM) != 0) {
916 ifp->if_capenable ^= IFCAP_TXCSUM;
917 if ((IFCAP_TXCSUM & ifp->if_capenable) != 0 &&
918 (IFCAP_TXCSUM & ifp->if_capabilities) != 0)
919 ifp->if_hwassist |= MSK_CSUM_FEATURES;
920 else
921 ifp->if_hwassist &= ~MSK_CSUM_FEATURES;
922 }
923 #ifdef notyet
924 if ((mask & IFCAP_VLAN_HWTAGGING) != 0) {
925 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
926 msk_setvlan(sc_if, ifp);
927 }
928 #endif
929
930 if (sc_if->msk_framesize > MSK_MAX_FRAMELEN &&
931 sc_if->msk_softc->msk_hw_id == CHIP_ID_YUKON_EC_U) {
932 /*
933 * In Yukon EC Ultra, TSO & checksum offload is not
934 * supported for jumbo frame.
935 */
936 ifp->if_hwassist &= ~MSK_CSUM_FEATURES;
937 ifp->if_capenable &= ~IFCAP_TXCSUM;
938 }
939 break;
940
941 default:
942 error = ether_ioctl(ifp, command, data);
943 break;
944 }
945
946 return (error);
947 }
948
949 static int
950 mskc_probe(device_t dev)
951 {
952 const struct msk_product *mp;
953 uint16_t vendor, devid;
954
955 vendor = pci_get_vendor(dev);
956 devid = pci_get_device(dev);
957 for (mp = msk_products; mp->msk_name != NULL; ++mp) {
958 if (vendor == mp->msk_vendorid && devid == mp->msk_deviceid) {
959 device_set_desc(dev, mp->msk_name);
960 return (0);
961 }
962 }
963 return (ENXIO);
964 }
965
966 static int
967 mskc_setup_rambuffer(struct msk_softc *sc)
968 {
969 int next;
970 int i;
971 uint8_t val;
972
973 /* Get adapter SRAM size. */
974 val = CSR_READ_1(sc, B2_E_0);
975 sc->msk_ramsize = (val == 0) ? 128 : val * 4;
976 if (bootverbose) {
977 device_printf(sc->msk_dev,
978 "RAM buffer size : %dKB\n", sc->msk_ramsize);
979 }
980 /*
981 * Give receiver 2/3 of memory and round down to the multiple
982 * of 1024. Tx/Rx RAM buffer size of Yukon II shoud be multiple
983 * of 1024.
984 */
985 sc->msk_rxqsize = rounddown((sc->msk_ramsize * 1024 * 2) / 3, 1024);
986 sc->msk_txqsize = (sc->msk_ramsize * 1024) - sc->msk_rxqsize;
987 for (i = 0, next = 0; i < sc->msk_num_port; i++) {
988 sc->msk_rxqstart[i] = next;
989 sc->msk_rxqend[i] = next + sc->msk_rxqsize - 1;
990 next = sc->msk_rxqend[i] + 1;
991 sc->msk_txqstart[i] = next;
992 sc->msk_txqend[i] = next + sc->msk_txqsize - 1;
993 next = sc->msk_txqend[i] + 1;
994 if (bootverbose) {
995 device_printf(sc->msk_dev,
996 "Port %d : Rx Queue %dKB(0x%08x:0x%08x)\n", i,
997 sc->msk_rxqsize / 1024, sc->msk_rxqstart[i],
998 sc->msk_rxqend[i]);
999 device_printf(sc->msk_dev,
1000 "Port %d : Tx Queue %dKB(0x%08x:0x%08x)\n", i,
1001 sc->msk_txqsize / 1024, sc->msk_txqstart[i],
1002 sc->msk_txqend[i]);
1003 }
1004 }
1005
1006 return (0);
1007 }
1008
1009 static void
1010 mskc_phy_power(struct msk_softc *sc, int mode)
1011 {
1012 uint32_t val;
1013 int i;
1014
1015 switch (mode) {
1016 case MSK_PHY_POWERUP:
1017 /* Switch power to VCC (WA for VAUX problem). */
1018 CSR_WRITE_1(sc, B0_POWER_CTRL,
1019 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
1020 /* Disable Core Clock Division, set Clock Select to 0. */
1021 CSR_WRITE_4(sc, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
1022
1023 val = 0;
1024 if (sc->msk_hw_id == CHIP_ID_YUKON_XL &&
1025 sc->msk_hw_rev > CHIP_REV_YU_XL_A1) {
1026 /* Enable bits are inverted. */
1027 val = Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
1028 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
1029 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS;
1030 }
1031 /*
1032 * Enable PCI & Core Clock, enable clock gating for both Links.
1033 */
1034 CSR_WRITE_1(sc, B2_Y2_CLK_GATE, val);
1035
1036 val = pci_read_config(sc->msk_dev, PCI_OUR_REG_1, 4);
1037 val &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
1038 if (sc->msk_hw_id == CHIP_ID_YUKON_XL &&
1039 sc->msk_hw_rev > CHIP_REV_YU_XL_A1) {
1040 /* Deassert Low Power for 1st PHY. */
1041 val |= PCI_Y2_PHY1_COMA;
1042 if (sc->msk_num_port > 1)
1043 val |= PCI_Y2_PHY2_COMA;
1044 } else if (sc->msk_hw_id == CHIP_ID_YUKON_EC_U) {
1045 uint32_t our;
1046
1047 CSR_WRITE_2(sc, B0_CTST, Y2_HW_WOL_ON);
1048
1049 /* Enable all clocks. */
1050 pci_write_config(sc->msk_dev, PCI_OUR_REG_3, 0, 4);
1051 our = pci_read_config(sc->msk_dev, PCI_OUR_REG_4, 4);
1052 our &= (PCI_FORCE_ASPM_REQUEST|PCI_ASPM_GPHY_LINK_DOWN|
1053 PCI_ASPM_INT_FIFO_EMPTY|PCI_ASPM_CLKRUN_REQUEST);
1054 /* Set all bits to 0 except bits 15..12. */
1055 pci_write_config(sc->msk_dev, PCI_OUR_REG_4, our, 4);
1056 /* Set to default value. */
1057 pci_write_config(sc->msk_dev, PCI_OUR_REG_5, 0, 4);
1058 }
1059 /* Release PHY from PowerDown/COMA mode. */
1060 pci_write_config(sc->msk_dev, PCI_OUR_REG_1, val, 4);
1061 for (i = 0; i < sc->msk_num_port; i++) {
1062 CSR_WRITE_2(sc, MR_ADDR(i, GMAC_LINK_CTRL),
1063 GMLC_RST_SET);
1064 CSR_WRITE_2(sc, MR_ADDR(i, GMAC_LINK_CTRL),
1065 GMLC_RST_CLR);
1066 }
1067 break;
1068 case MSK_PHY_POWERDOWN:
1069 val = pci_read_config(sc->msk_dev, PCI_OUR_REG_1, 4);
1070 val |= PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD;
1071 if (sc->msk_hw_id == CHIP_ID_YUKON_XL &&
1072 sc->msk_hw_rev > CHIP_REV_YU_XL_A1) {
1073 val &= ~PCI_Y2_PHY1_COMA;
1074 if (sc->msk_num_port > 1)
1075 val &= ~PCI_Y2_PHY2_COMA;
1076 }
1077 pci_write_config(sc->msk_dev, PCI_OUR_REG_1, val, 4);
1078
1079 val = Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
1080 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
1081 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS;
1082 if (sc->msk_hw_id == CHIP_ID_YUKON_XL &&
1083 sc->msk_hw_rev > CHIP_REV_YU_XL_A1) {
1084 /* Enable bits are inverted. */
1085 val = 0;
1086 }
1087 /*
1088 * Disable PCI & Core Clock, disable clock gating for
1089 * both Links.
1090 */
1091 CSR_WRITE_1(sc, B2_Y2_CLK_GATE, val);
1092 CSR_WRITE_1(sc, B0_POWER_CTRL,
1093 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_ON | PC_VCC_OFF);
1094 break;
1095 default:
1096 break;
1097 }
1098 }
1099
1100 static void
1101 mskc_reset(struct msk_softc *sc)
1102 {
1103 bus_addr_t addr;
1104 uint16_t status;
1105 uint32_t val;
1106 int i;
1107
1108 CSR_WRITE_2(sc, B0_CTST, CS_RST_CLR);
1109
1110 /* Disable ASF. */
1111 if (sc->msk_hw_id < CHIP_ID_YUKON_XL) {
1112 CSR_WRITE_4(sc, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
1113 CSR_WRITE_2(sc, B0_CTST, Y2_ASF_DISABLE);
1114 }
1115 /*
1116 * Since we disabled ASF, S/W reset is required for Power Management.
1117 */
1118 CSR_WRITE_2(sc, B0_CTST, CS_RST_SET);
1119 CSR_WRITE_2(sc, B0_CTST, CS_RST_CLR);
1120
1121 /* Clear all error bits in the PCI status register. */
1122 status = pci_read_config(sc->msk_dev, PCIR_STATUS, 2);
1123 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_ON);
1124
1125 pci_write_config(sc->msk_dev, PCIR_STATUS, status |
1126 PCIM_STATUS_PERR | PCIM_STATUS_SERR | PCIM_STATUS_RMABORT |
1127 PCIM_STATUS_RTABORT | PCIM_STATUS_PERRREPORT, 2);
1128 CSR_WRITE_2(sc, B0_CTST, CS_MRST_CLR);
1129
1130 switch (sc->msk_bustype) {
1131 case MSK_PEX_BUS:
1132 /* Clear all PEX errors. */
1133 CSR_PCI_WRITE_4(sc, PEX_UNC_ERR_STAT, 0xffffffff);
1134 val = CSR_PCI_READ_4(sc, PEX_UNC_ERR_STAT);
1135 if ((val & PEX_RX_OV) != 0) {
1136 sc->msk_intrmask &= ~Y2_IS_HW_ERR;
1137 sc->msk_intrhwemask &= ~Y2_IS_PCI_EXP;
1138 }
1139 break;
1140 case MSK_PCI_BUS:
1141 case MSK_PCIX_BUS:
1142 /* Set Cache Line Size to 2(8bytes) if configured to 0. */
1143 val = pci_read_config(sc->msk_dev, PCIR_CACHELNSZ, 1);
1144 if (val == 0)
1145 pci_write_config(sc->msk_dev, PCIR_CACHELNSZ, 2, 1);
1146 if (sc->msk_bustype == MSK_PCIX_BUS) {
1147 /* Set Cache Line Size opt. */
1148 val = pci_read_config(sc->msk_dev, PCI_OUR_REG_1, 4);
1149 val |= PCI_CLS_OPT;
1150 pci_write_config(sc->msk_dev, PCI_OUR_REG_1, val, 4);
1151 }
1152 break;
1153 }
1154 /* Set PHY power state. */
1155 mskc_phy_power(sc, MSK_PHY_POWERUP);
1156
1157 /* Reset GPHY/GMAC Control */
1158 for (i = 0; i < sc->msk_num_port; i++) {
1159 /* GPHY Control reset. */
1160 CSR_WRITE_4(sc, MR_ADDR(i, GPHY_CTRL), GPC_RST_SET);
1161 CSR_WRITE_4(sc, MR_ADDR(i, GPHY_CTRL), GPC_RST_CLR);
1162 /* GMAC Control reset. */
1163 CSR_WRITE_4(sc, MR_ADDR(i, GMAC_CTRL), GMC_RST_SET);
1164 CSR_WRITE_4(sc, MR_ADDR(i, GMAC_CTRL), GMC_RST_CLR);
1165 CSR_WRITE_4(sc, MR_ADDR(i, GMAC_CTRL), GMC_F_LOOPB_OFF);
1166 }
1167 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
1168
1169 /* LED On. */
1170 CSR_WRITE_2(sc, B0_CTST, Y2_LED_STAT_ON);
1171
1172 /* Clear TWSI IRQ. */
1173 CSR_WRITE_4(sc, B2_I2C_IRQ, I2C_CLR_IRQ);
1174
1175 /* Turn off hardware timer. */
1176 CSR_WRITE_1(sc, B2_TI_CTRL, TIM_STOP);
1177 CSR_WRITE_1(sc, B2_TI_CTRL, TIM_CLR_IRQ);
1178
1179 /* Turn off descriptor polling. */
1180 CSR_WRITE_1(sc, B28_DPT_CTRL, DPT_STOP);
1181
1182 /* Turn off time stamps. */
1183 CSR_WRITE_1(sc, GMAC_TI_ST_CTRL, GMT_ST_STOP);
1184 CSR_WRITE_1(sc, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
1185
1186 /* Configure timeout values. */
1187 for (i = 0; i < sc->msk_num_port; i++) {
1188 CSR_WRITE_2(sc, SELECT_RAM_BUFFER(i, B3_RI_CTRL), RI_RST_SET);
1189 CSR_WRITE_2(sc, SELECT_RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
1190 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_R1),
1191 MSK_RI_TO_53);
1192 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_XA1),
1193 MSK_RI_TO_53);
1194 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_XS1),
1195 MSK_RI_TO_53);
1196 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_R1),
1197 MSK_RI_TO_53);
1198 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_XA1),
1199 MSK_RI_TO_53);
1200 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_XS1),
1201 MSK_RI_TO_53);
1202 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_R2),
1203 MSK_RI_TO_53);
1204 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_XA2),
1205 MSK_RI_TO_53);
1206 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_XS2),
1207 MSK_RI_TO_53);
1208 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_R2),
1209 MSK_RI_TO_53);
1210 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_XA2),
1211 MSK_RI_TO_53);
1212 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_XS2),
1213 MSK_RI_TO_53);
1214 }
1215
1216 /* Disable all interrupts. */
1217 CSR_WRITE_4(sc, B0_HWE_IMSK, 0);
1218 CSR_READ_4(sc, B0_HWE_IMSK);
1219 CSR_WRITE_4(sc, B0_IMSK, 0);
1220 CSR_READ_4(sc, B0_IMSK);
1221
1222 /*
1223 * On dual port PCI-X card, there is an problem where status
1224 * can be received out of order due to split transactions.
1225 */
1226 if (sc->msk_bustype == MSK_PCIX_BUS && sc->msk_num_port > 1) {
1227 uint16_t pcix_cmd;
1228 uint8_t pcix;
1229
1230 pcix = pci_get_pcixcap_ptr(sc->msk_dev);
1231
1232 pcix_cmd = pci_read_config(sc->msk_dev, pcix + 2, 2);
1233 /* Clear Max Outstanding Split Transactions. */
1234 pcix_cmd &= ~0x70;
1235 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_ON);
1236 pci_write_config(sc->msk_dev, pcix + 2, pcix_cmd, 2);
1237 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
1238 }
1239 if (sc->msk_bustype == MSK_PEX_BUS) {
1240 uint16_t v, width;
1241
1242 v = pci_read_config(sc->msk_dev, PEX_DEV_CTRL, 2);
1243 /* Change Max. Read Request Size to 4096 bytes. */
1244 v &= ~PEX_DC_MAX_RRS_MSK;
1245 v |= PEX_DC_MAX_RD_RQ_SIZE(5);
1246 pci_write_config(sc->msk_dev, PEX_DEV_CTRL, v, 2);
1247 width = pci_read_config(sc->msk_dev, PEX_LNK_STAT, 2);
1248 width = (width & PEX_LS_LINK_WI_MSK) >> 4;
1249 v = pci_read_config(sc->msk_dev, PEX_LNK_CAP, 2);
1250 v = (v & PEX_LS_LINK_WI_MSK) >> 4;
1251 if (v != width) {
1252 device_printf(sc->msk_dev,
1253 "negotiated width of link(x%d) != "
1254 "max. width of link(x%d)\n", width, v);
1255 }
1256 }
1257
1258 /* Clear status list. */
1259 bzero(sc->msk_stat_ring,
1260 sizeof(struct msk_stat_desc) * MSK_STAT_RING_CNT);
1261 sc->msk_stat_cons = 0;
1262 bus_dmamap_sync(sc->msk_stat_tag, sc->msk_stat_map,
1263 BUS_DMASYNC_PREWRITE);
1264 CSR_WRITE_4(sc, STAT_CTRL, SC_STAT_RST_SET);
1265 CSR_WRITE_4(sc, STAT_CTRL, SC_STAT_RST_CLR);
1266 /* Set the status list base address. */
1267 addr = sc->msk_stat_ring_paddr;
1268 CSR_WRITE_4(sc, STAT_LIST_ADDR_LO, MSK_ADDR_LO(addr));
1269 CSR_WRITE_4(sc, STAT_LIST_ADDR_HI, MSK_ADDR_HI(addr));
1270 /* Set the status list last index. */
1271 CSR_WRITE_2(sc, STAT_LAST_IDX, MSK_STAT_RING_CNT - 1);
1272 if (sc->msk_hw_id == CHIP_ID_YUKON_EC &&
1273 sc->msk_hw_rev == CHIP_REV_YU_EC_A1) {
1274 /* WA for dev. #4.3 */
1275 CSR_WRITE_2(sc, STAT_TX_IDX_TH, ST_TXTH_IDX_MASK);
1276 /* WA for dev. #4.18 */
1277 CSR_WRITE_1(sc, STAT_FIFO_WM, 0x21);
1278 CSR_WRITE_1(sc, STAT_FIFO_ISR_WM, 0x07);
1279 } else {
1280 CSR_WRITE_2(sc, STAT_TX_IDX_TH, 0x0a);
1281 CSR_WRITE_1(sc, STAT_FIFO_WM, 0x10);
1282 if (sc->msk_hw_id == CHIP_ID_YUKON_XL &&
1283 sc->msk_hw_rev == CHIP_REV_YU_XL_A0)
1284 CSR_WRITE_1(sc, STAT_FIFO_ISR_WM, 0x04);
1285 else
1286 CSR_WRITE_1(sc, STAT_FIFO_ISR_WM, 0x10);
1287 CSR_WRITE_4(sc, STAT_ISR_TIMER_INI, 0x0190);
1288 }
1289 /*
1290 * Use default value for STAT_ISR_TIMER_INI, STAT_LEV_TIMER_INI.
1291 */
1292 CSR_WRITE_4(sc, STAT_TX_TIMER_INI, MSK_USECS(sc, 1000));
1293
1294 /* Enable status unit. */
1295 CSR_WRITE_4(sc, STAT_CTRL, SC_STAT_OP_ON);
1296
1297 CSR_WRITE_1(sc, STAT_TX_TIMER_CTRL, TIM_START);
1298 CSR_WRITE_1(sc, STAT_LEV_TIMER_CTRL, TIM_START);
1299 CSR_WRITE_1(sc, STAT_ISR_TIMER_CTRL, TIM_START);
1300 }
1301
1302 static int
1303 msk_probe(device_t dev)
1304 {
1305 struct msk_softc *sc = device_get_softc(device_get_parent(dev));
1306 char desc[100];
1307
1308 /*
1309 * Not much to do here. We always know there will be
1310 * at least one GMAC present, and if there are two,
1311 * mskc_attach() will create a second device instance
1312 * for us.
1313 */
1314 ksnprintf(desc, sizeof(desc),
1315 "Marvell Technology Group Ltd. %s Id 0x%02x Rev 0x%02x",
1316 model_name[sc->msk_hw_id - CHIP_ID_YUKON_XL], sc->msk_hw_id,
1317 sc->msk_hw_rev);
1318 device_set_desc_copy(dev, desc);
1319
1320 return (0);
1321 }
1322
1323 static int
1324 msk_attach(device_t dev)
1325 {
1326 struct msk_softc *sc = device_get_softc(device_get_parent(dev));
1327 struct msk_if_softc *sc_if = device_get_softc(dev);
1328 struct ifnet *ifp = &sc_if->arpcom.ac_if;
1329 int i, port, error;
1330 uint8_t eaddr[ETHER_ADDR_LEN];
1331
1332 port = *(int *)device_get_ivars(dev);
1333 KKASSERT(port == MSK_PORT_A || port == MSK_PORT_B);
1334
1335 kfree(device_get_ivars(dev), M_DEVBUF);
1336 device_set_ivars(dev, NULL);
1337
1338 callout_init(&sc_if->msk_tick_ch);
1339 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1340
1341 sc_if->msk_if_dev = dev;
1342 sc_if->msk_port = port;
1343 sc_if->msk_softc = sc;
1344 sc_if->msk_ifp = ifp;
1345 sc->msk_if[port] = sc_if;
1346
1347 /* Setup Tx/Rx queue register offsets. */
1348 if (port == MSK_PORT_A) {
1349 sc_if->msk_txq = Q_XA1;
1350 sc_if->msk_txsq = Q_XS1;
1351 sc_if->msk_rxq = Q_R1;
1352 } else {
1353 sc_if->msk_txq = Q_XA2;
1354 sc_if->msk_txsq = Q_XS2;
1355 sc_if->msk_rxq = Q_R2;
1356 }
1357
1358 error = msk_txrx_dma_alloc(sc_if);
1359 if (error)
1360 goto fail;
1361
1362 ifp->if_softc = sc_if;
1363 ifp->if_mtu = ETHERMTU;
1364 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1365 ifp->if_init = msk_init;
1366 ifp->if_ioctl = msk_ioctl;
1367 ifp->if_start = msk_start;
1368 ifp->if_watchdog = msk_watchdog;
1369 ifq_set_maxlen(&ifp->if_snd, MSK_TX_RING_CNT - 1);
1370 ifq_set_ready(&ifp->if_snd);
1371
1372 #ifdef notyet
1373 /*
1374 * IFCAP_RXCSUM capability is intentionally disabled as the hardware
1375 * has serious bug in Rx checksum offload for all Yukon II family
1376 * hardware. It seems there is a workaround to make it work somtimes.
1377 * However, the workaround also have to check OP code sequences to
1378 * verify whether the OP code is correct. Sometimes it should compute
1379 * IP/TCP/UDP checksum in driver in order to verify correctness of
1380 * checksum computed by hardware. If you have to compute checksum
1381 * with software to verify the hardware's checksum why have hardware
1382 * compute the checksum? I think there is no reason to spend time to
1383 * make Rx checksum offload work on Yukon II hardware.
1384 */
1385 ifp->if_capabilities = IFCAP_TXCSUM | IFCAP_VLAN_MTU |
1386 IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_HWCSUM;
1387 ifp->if_hwassist = MSK_CSUM_FEATURES;
1388 ifp->if_capenable = ifp->if_capabilities;
1389 #endif
1390
1391 /*
1392 * Get station address for this interface. Note that
1393 * dual port cards actually come with three station
1394 * addresses: one for each port, plus an extra. The
1395 * extra one is used by the SysKonnect driver software
1396 * as a 'virtual' station address for when both ports
1397 * are operating in failover mode. Currently we don't
1398 * use this extra address.
1399 */
1400 for (i = 0; i < ETHER_ADDR_LEN; i++)
1401 eaddr[i] = CSR_READ_1(sc, B2_MAC_1 + (port * 8) + i);
1402
1403 sc_if->msk_framesize = ifp->if_mtu + ETHER_HDR_LEN + EVL_ENCAPLEN;
1404
1405 /*
1406 * Do miibus setup.
1407 */
1408 error = mii_phy_probe(dev, &sc_if->msk_miibus,
1409 msk_mediachange, msk_mediastatus);
1410 if (error) {
1411 device_printf(sc_if->msk_if_dev, "no PHY found!\n");
1412 goto fail;
1413 }
1414
1415 /*
1416 * Call MI attach routine. Can't hold locks when calling into ether_*.
1417 */
1418 ether_ifattach(ifp, eaddr, &sc->msk_serializer);
1419 #if 0
1420 /*
1421 * Tell the upper layer(s) we support long frames.
1422 * Must appear after the call to ether_ifattach() because
1423 * ether_ifattach() sets ifi_hdrlen to the default value.
1424 */
1425 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
1426 #endif
1427
1428 return 0;
1429 fail:
1430 msk_detach(dev);
1431 sc->msk_if[port] = NULL;
1432 return (error);
1433 }
1434
1435 /*
1436 * Attach the interface. Allocate softc structures, do ifmedia
1437 * setup and ethernet/BPF attach.
1438 */
1439 static int
1440 mskc_attach(device_t dev)
1441 {
1442 struct msk_softc *sc;
1443 int error, *port;
1444
1445 sc = device_get_softc(dev);
1446 sc->msk_dev = dev;
1447 lwkt_serialize_init(&sc->msk_serializer);
1448
1449 /*
1450 * Initailize sysctl variables
1451 */
1452 sc->msk_process_limit = mskc_process_limit;
1453 sc->msk_intr_rate = mskc_intr_rate;
1454
1455 #ifndef BURN_BRIDGES
1456 /*
1457 * Handle power management nonsense.
1458 */
1459 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
1460 uint32_t irq, bar0, bar1;
1461
1462 /* Save important PCI config data. */
1463 bar0 = pci_read_config(dev, PCIR_BAR(0), 4);
1464 bar1 = pci_read_config(dev, PCIR_BAR(1), 4);
1465 irq = pci_read_config(dev, PCIR_INTLINE, 4);
1466
1467 /* Reset the power state. */
1468 device_printf(dev, "chip is in D%d power mode "
1469 "-- setting to D0\n", pci_get_powerstate(dev));
1470
1471 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
1472
1473 /* Restore PCI config data. */
1474 pci_write_config(dev, PCIR_BAR(0), bar0, 4);
1475 pci_write_config(dev, PCIR_BAR(1), bar1, 4);
1476 pci_write_config(dev, PCIR_INTLINE, irq, 4);
1477 }
1478 #endif /* BURN_BRIDGES */
1479
1480 /*
1481 * Map control/status registers.
1482 */
1483 pci_enable_busmaster(dev);
1484
1485 /*
1486 * Allocate I/O resource
1487 */
1488 #ifdef MSK_USEIOSPACE
1489 sc->msk_res_type = SYS_RES_IOPORT;
1490 sc->msk_res_rid = PCIR_BAR(1);
1491 #else
1492 sc->msk_res_type = SYS_RES_MEMORY;
1493 sc->msk_res_rid = PCIR_BAR(0);
1494 #endif
1495 sc->msk_res = bus_alloc_resource_any(dev, sc->msk_res_type,
1496 &sc->msk_res_rid, RF_ACTIVE);
1497 if (sc->msk_res == NULL) {
1498 if (sc->msk_res_type == SYS_RES_MEMORY) {
1499 sc->msk_res_type = SYS_RES_IOPORT;
1500 sc->msk_res_rid = PCIR_BAR(1);
1501 } else {
1502 sc->msk_res_type = SYS_RES_MEMORY;
1503 sc->msk_res_rid = PCIR_BAR(0);
1504 }
1505 sc->msk_res = bus_alloc_resource_any(dev, sc->msk_res_type,
1506 &sc->msk_res_rid,
1507 RF_ACTIVE);
1508 if (sc->msk_res == NULL) {
1509 device_printf(dev, "couldn't allocate %s resources\n",
1510 sc->msk_res_type == SYS_RES_MEMORY ? "memory" : "I/O");
1511 return (ENXIO);
1512 }
1513 }
1514 sc->msk_res_bt = rman_get_bustag(sc->msk_res);
1515 sc->msk_res_bh = rman_get_bushandle(sc->msk_res);
1516
1517 /*
1518 * Allocate IRQ
1519 */
1520 sc->msk_irq_rid = 0;
1521 sc->msk_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ,
1522 &sc->msk_irq_rid,
1523 RF_SHAREABLE | RF_ACTIVE);
1524 if (sc->msk_irq == NULL) {
1525 device_printf(dev, "couldn't allocate IRQ resources\n");
1526 error = ENXIO;
1527 goto fail;
1528 }
1529
1530 CSR_WRITE_2(sc, B0_CTST, CS_RST_CLR);
1531 sc->msk_hw_id = CSR_READ_1(sc, B2_CHIP_ID);
1532 sc->msk_hw_rev = (CSR_READ_1(sc, B2_MAC_CFG) >> 4) & 0x0f;
1533 /* Bail out if chip is not recognized. */
1534 if (sc->msk_hw_id < CHIP_ID_YUKON_XL ||
1535 sc->msk_hw_id > CHIP_ID_YUKON_FE) {
1536 device_printf(dev, "unknown device: id=0x%02x, rev=0x%02x\n",
1537 sc->msk_hw_id, sc->msk_hw_rev);
1538 error = ENXIO;
1539 goto fail;
1540 }
1541
1542 /*
1543 * Create sysctl tree
1544 */
1545 sysctl_ctx_init(&sc->msk_sysctl_ctx);
1546 sc->msk_sysctl_tree = SYSCTL_ADD_NODE(&sc->msk_sysctl_ctx,
1547 SYSCTL_STATIC_CHILDREN(_hw),
1548 OID_AUTO,
1549 device_get_nameunit(dev),
1550 CTLFLAG_RD, 0, "");
1551 if (sc->msk_sysctl_tree == NULL) {
1552 device_printf(dev, "can't add sysctl node\n");
1553 error = ENXIO;
1554 goto fail;
1555 }
1556
1557 SYSCTL_ADD_PROC(&sc->msk_sysctl_ctx,
1558 SYSCTL_CHILDREN(sc->msk_sysctl_tree),
1559 OID_AUTO, "process_limit", CTLTYPE_INT | CTLFLAG_RW,
1560 &sc->msk_process_limit, 0, mskc_sysctl_proc_limit,
1561 "I", "max number of Rx events to process");
1562 SYSCTL_ADD_PROC(&sc->msk_sysctl_ctx,
1563 SYSCTL_CHILDREN(sc->msk_sysctl_tree),
1564 OID_AUTO, "intr_rate", CTLTYPE_INT | CTLFLAG_RW,
1565 sc, 0, mskc_sysctl_intr_rate,
1566 "I", "max number of interrupt per second");
1567
1568 /* Soft reset. */
1569 CSR_WRITE_2(sc, B0_CTST, CS_RST_SET);
1570 CSR_WRITE_2(sc, B0_CTST, CS_RST_CLR);
1571 sc->msk_pmd = CSR_READ_1(sc, B2_PMD_TYP);
1572 if (sc->msk_pmd == 'L' || sc->msk_pmd == 'S')
1573 sc->msk_coppertype = 0;
1574 else
1575 sc->msk_coppertype = 1;
1576 /* Check number of MACs. */
1577 sc->msk_num_port = 1;
1578 if ((CSR_READ_1(sc, B2_Y2_HW_RES) & CFG_DUAL_MAC_MSK) ==
1579 CFG_DUAL_MAC_MSK) {
1580 if (!(CSR_READ_1(sc, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
1581 sc->msk_num_port++;
1582 }
1583
1584 /* Check bus type. */
1585 if (pci_is_pcie(sc->msk_dev) == 0)
1586 sc->msk_bustype = MSK_PEX_BUS;
1587 else if (pci_is_pcix(sc->msk_dev) == 0)
1588 sc->msk_bustype = MSK_PCIX_BUS;
1589 else
1590 sc->msk_bustype = MSK_PCI_BUS;
1591
1592 switch (sc->msk_hw_id) {
1593 case CHIP_ID_YUKON_EC:
1594 case CHIP_ID_YUKON_EC_U:
1595 sc->msk_clock = 125; /* 125 Mhz */
1596 break;
1597 case CHIP_ID_YUKON_FE:
1598 sc->msk_clock = 100; /* 100 Mhz */
1599 break;
1600 case CHIP_ID_YUKON_XL:
1601 sc->msk_clock = 156; /* 156 Mhz */
1602 break;
1603 default:
1604 sc->msk_clock = 156; /* 156 Mhz */
1605 break;
1606 }
1607
1608 error = mskc_status_dma_alloc(sc);
1609 if (error)
1610 goto fail;
1611
1612 /* Set base interrupt mask. */
1613 sc->msk_intrmask = Y2_IS_HW_ERR | Y2_IS_STAT_BMU;
1614 sc->msk_intrhwemask = Y2_IS_TIST_OV | Y2_IS_MST_ERR |
1615 Y2_IS_IRQ_STAT | Y2_IS_PCI_EXP | Y2_IS_PCI_NEXP;
1616
1617 /* Reset the adapter. */
1618 mskc_reset(sc);
1619
1620 error = mskc_setup_rambuffer(sc);
1621 if (error)
1622 goto fail;
1623
1624 sc->msk_devs[MSK_PORT_A] = device_add_child(dev, "msk", -1);
1625 if (sc->msk_devs[MSK_PORT_A] == NULL) {
1626 device_printf(dev, "failed to add child for PORT_A\n");
1627 error = ENXIO;
1628 goto fail;
1629 }
1630 port = kmalloc(sizeof(*port), M_DEVBUF, M_WAITOK);
1631 *port = MSK_PORT_A;
1632 device_set_ivars(sc->msk_devs[MSK_PORT_A], port);
1633
1634 if (sc->msk_num_port > 1) {
1635 sc->msk_devs[MSK_PORT_B] = device_add_child(dev, "msk", -1);
1636 if (sc->msk_devs[MSK_PORT_B] == NULL) {
1637 device_printf(dev, "failed to add child for PORT_B\n");
1638 error = ENXIO;
1639 goto fail;
1640 }
1641 port = kmalloc(sizeof(*port), M_DEVBUF, M_WAITOK);
1642 *port = MSK_PORT_B;
1643 device_set_ivars(sc->msk_devs[MSK_PORT_B], port);
1644 }
1645
1646 bus_generic_attach(dev);
1647
1648 error = bus_setup_intr(dev, sc->msk_irq, INTR_MPSAFE,
1649 mskc_intr, sc, &sc->msk_intrhand,
1650 &sc->msk_serializer);
1651 if (error) {
1652 device_printf(dev, "couldn't set up interrupt handler\n");
1653 goto fail;
1654 }
1655 return 0;
1656 fail:
1657 mskc_detach(dev);
1658 return (error);
1659 }
1660
1661 /*
1662 * Shutdown hardware and free up resources. This can be called any
1663 * time after the mutex has been initialized. It is called in both
1664 * the error case in attach and the normal detach case so it needs
1665 * to be careful about only freeing resources that have actually been
1666 * allocated.
1667 */
1668 static int
1669 msk_detach(device_t dev)
1670 {
1671 struct msk_if_softc *sc_if = device_get_softc(dev);
1672
1673 if (device_is_attached(dev)) {
1674 struct msk_softc *sc = sc_if->msk_softc;
1675 struct ifnet *ifp = &sc_if->arpcom.ac_if;
1676
1677 lwkt_serialize_enter(ifp->if_serializer);
1678
1679 if (sc->msk_intrhand != NULL) {
1680 if (sc->msk_if[MSK_PORT_A] != NULL)
1681 msk_stop(sc->msk_if[MSK_PORT_A]);
1682 if (sc->msk_if[MSK_PORT_B] != NULL)
1683 msk_stop(sc->msk_if[MSK_PORT_B]);
1684
1685 bus_teardown_intr(sc->msk_dev, sc->msk_irq,
1686 sc->msk_intrhand);
1687 sc->msk_intrhand = NULL;
1688 }
1689
1690 lwkt_serialize_exit(ifp->if_serializer);
1691
1692 ether_ifdetach(ifp);
1693 }
1694
1695 if (sc_if->msk_miibus != NULL)
1696 device_delete_child(dev, sc_if->msk_miibus);
1697
1698 msk_txrx_dma_free(sc_if);
1699 return (0);
1700 }
1701
1702 static int
1703 mskc_detach(device_t dev)
1704 {
1705 struct msk_softc *sc = device_get_softc(dev);
1706 int *port, i;
1707
1708 #ifdef INVARIANTS
1709 if (device_is_attached(dev)) {
1710 KASSERT(sc->msk_intrhand == NULL,
1711 ("intr is not torn down yet\n"));
1712 }
1713 #endif
1714
1715 for (i = 0; i < sc->msk_num_port; ++i) {
1716 if (sc->msk_devs[i] != NULL) {
1717 port = device_get_ivars(sc->msk_devs[i]);
1718 if (port != NULL) {
1719 kfree(port, M_DEVBUF);
1720 device_set_ivars(sc->msk_devs[i], NULL);
1721 }
1722 device_delete_child(dev, sc->msk_devs[i]);
1723 }
1724 }
1725
1726 /* Disable all interrupts. */
1727 CSR_WRITE_4(sc, B0_IMSK, 0);
1728 CSR_READ_4(sc, B0_IMSK);
1729 CSR_WRITE_4(sc, B0_HWE_IMSK, 0);
1730 CSR_READ_4(sc, B0_HWE_IMSK);
1731
1732 /* LED Off. */
1733 CSR_WRITE_2(sc, B0_CTST, Y2_LED_STAT_OFF);
1734
1735 /* Put hardware reset. */
1736 CSR_WRITE_2(sc, B0_CTST, CS_RST_SET);
1737
1738 mskc_status_dma_free(sc);
1739
1740 if (sc->msk_irq != NULL) {
1741 bus_release_resource(dev, SYS_RES_IRQ, sc->msk_irq_rid,
1742 sc->msk_irq);
1743 }
1744 if (sc->msk_res != NULL) {
1745 bus_release_resource(dev, sc->msk_res_type, sc->msk_res_rid,
1746 sc->msk_res);
1747 }
1748
1749 if (sc->msk_sysctl_tree != NULL)
1750 sysctl_ctx_free(&sc->msk_sysctl_ctx);
1751
1752 return (0);
1753 }
1754
1755 static void
1756 msk_dmamap_mbuf_cb(void *arg, bus_dma_segment_t *segs, int nseg,
1757 bus_size_t mapsz __unused, int error)
1758 {
1759 struct msk_dmamap_arg *ctx = arg;
1760 int i;
1761
1762 if (error)
1763 return;
1764
1765 if (ctx->nseg < nseg) {
1766 ctx->nseg = 0;
1767 return;
1768 }
1769
1770 ctx->nseg = nseg;
1771 for (i = 0; i < ctx->nseg; ++i)
1772 ctx->segs[i] = segs[i];
1773 }
1774
1775 static void
1776 msk_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
1777 {
1778 struct msk_dmamap_arg *ctx = arg;
1779 int i;
1780
1781 if (error)
1782 return;
1783
1784 KKASSERT(nseg <= ctx->nseg);
1785
1786 ctx->nseg = nseg;
1787 for (i = 0; i < ctx->nseg; ++i)
1788 ctx->segs[i] = segs[i];
1789 }
1790
1791 /* Create status DMA region. */
1792 static int
1793 mskc_status_dma_alloc(struct msk_softc *sc)
1794 {
1795 struct msk_dmamap_arg ctx;
1796 bus_dma_segment_t seg;
1797 int error;
1798
1799 error = bus_dma_tag_create(
1800 NULL, /* XXX parent */
1801 MSK_STAT_ALIGN, 0, /* alignment, boundary */
1802 BUS_SPACE_MAXADDR, /* lowaddr */
1803 BUS_SPACE_MAXADDR, /* highaddr */
1804 NULL, NULL, /* filter, filterarg */
1805 MSK_STAT_RING_SZ, /* maxsize */
1806 1, /* nsegments */
1807 MSK_STAT_RING_SZ, /* maxsegsize */
1808 0, /* flags */
1809 &sc->msk_stat_tag);
1810 if (error) {
1811 device_printf(sc->msk_dev,
1812 "failed to create status DMA tag\n");
1813 return (error);
1814 }
1815
1816 /* Allocate DMA'able memory and load the DMA map for status ring. */
1817 error = bus_dmamem_alloc(sc->msk_stat_tag,
1818 (void **)&sc->msk_stat_ring,
1819 BUS_DMA_WAITOK | BUS_DMA_ZERO,
1820 &sc->msk_stat_map);
1821 if (error) {
1822 device_printf(sc->msk_dev,
1823 "failed to allocate DMA'able memory for status ring\n");
1824 bus_dma_tag_destroy(sc->msk_stat_tag);
1825 sc->msk_stat_tag = NULL;
1826 return (error);
1827 }
1828
1829 bzero(&ctx, sizeof(ctx));
1830 ctx.nseg = 1;
1831 ctx.segs = &seg;
1832 error = bus_dmamap_load(sc->msk_stat_tag, sc->msk_stat_map,
1833 sc->msk_stat_ring, MSK_STAT_RING_SZ,
1834 msk_dmamap_cb, &ctx, 0);
1835 if (error) {
1836 device_printf(sc->msk_dev,
1837 "failed to load DMA'able memory for status ring\n");
1838 bus_dmamem_free(sc->msk_stat_tag, sc->msk_stat_ring,
1839 sc->msk_stat_map);
1840 bus_dma_tag_destroy(sc->msk_stat_tag);
1841 sc->msk_stat_tag = NULL;
1842 return (error);
1843 }
1844 sc->msk_stat_ring_paddr = seg.ds_addr;
1845
1846 return (0);
1847 }
1848
1849 static void
1850 mskc_status_dma_free(struct msk_softc *sc)
1851 {
1852 /* Destroy status block. */
1853 if (sc->msk_stat_tag) {
1854 bus_dmamap_unload(sc->msk_stat_tag, sc->msk_stat_map);
1855 bus_dmamem_free(sc->msk_stat_tag, sc->msk_stat_ring,
1856 sc->msk_stat_map);
1857 bus_dma_tag_destroy(sc->msk_stat_tag);
1858 sc->msk_stat_tag = NULL;
1859 }
1860 }
1861
1862 static int
1863 msk_txrx_dma_alloc(struct msk_if_softc *sc_if)
1864 {
1865 int error, i, j;
1866 #ifdef MSK_JUMBO
1867 struct msk_rxdesc *jrxd;
1868 struct msk_jpool_entry *entry;
1869 uint8_t *ptr;
1870 #endif
1871
1872 /* Create parent DMA tag. */
1873 /*
1874 * XXX
1875 * It seems that Yukon II supports full 64bits DMA operations. But
1876 * it needs two descriptors(list elements) for 64bits DMA operations.
1877 * Since we don't know what DMA address mappings(32bits or 64bits)
1878 * would be used in advance for each mbufs, we limits its DMA space
1879 * to be in range of 32bits address space. Otherwise, we should check
1880 * what DMA address is used and chain another descriptor for the
1881 * 64bits DMA operation. This also means descriptor ring size is
1882 * variable. Limiting DMA address to be in 32bit address space greatly
1883 * simplyfies descriptor handling and possibly would increase
1884 * performance a bit due to efficient handling of descriptors.
1885 * Apart from harassing checksum offloading mechanisms, it seems
1886 * it's really bad idea to use a seperate descriptor for 64bit
1887 * DMA operation to save small descriptor memory. Anyway, I've
1888 * never seen these exotic scheme on ethernet interface hardware.
1889 */
1890 error = bus_dma_tag_create(
1891 NULL, /* parent */
1892 1, 0, /* alignment, boundary */
1893 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
1894 BUS_SPACE_MAXADDR, /* highaddr */
1895 NULL, NULL, /* filter, filterarg */
1896 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */
1897 0, /* nsegments */
1898 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
1899 0, /* flags */
1900 &sc_if->msk_cdata.msk_parent_tag);
1901 if (error) {
1902 device_printf(sc_if->msk_if_dev,
1903 "failed to create parent DMA tag\n");
1904 return error;
1905 }
1906
1907 /* Create DMA stuffs for Tx ring. */
1908 error = msk_dmamem_create(sc_if->msk_if_dev, MSK_TX_RING_SZ,
1909 &sc_if->msk_cdata.msk_tx_ring_tag,
1910 (void **)&sc_if->msk_rdata.msk_tx_ring,
1911 &sc_if->msk_rdata.msk_tx_ring_paddr,
1912 &sc_if->msk_cdata.msk_tx_ring_map);
1913 if (error) {
1914 device_printf(sc_if->msk_if_dev,
1915 "failed to create TX ring DMA stuffs\n");
1916 return error;
1917 }
1918
1919 /* Create DMA stuffs for Rx ring. */
1920 error = msk_dmamem_create(sc_if->msk_if_dev, MSK_RX_RING_SZ,
1921 &sc_if->msk_cdata.msk_rx_ring_tag,
1922 (void **)&sc_if->msk_rdata.msk_rx_ring,
1923 &sc_if->msk_rdata.msk_rx_ring_paddr,
1924 &sc_if->msk_cdata.msk_rx_ring_map);
1925 if (error) {
1926 device_printf(sc_if->msk_if_dev,
1927 "failed to create RX ring DMA stuffs\n");
1928 return error;
1929 }
1930
1931 /* Create tag for Tx buffers. */
1932 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */
1933 1, 0, /* alignment, boundary */
1934 BUS_SPACE_MAXADDR, /* lowaddr */
1935 BUS_SPACE_MAXADDR, /* highaddr */
1936 NULL, NULL, /* filter, filterarg */
1937 MSK_TSO_MAXSIZE, /* maxsize */
1938 MSK_MAXTXSEGS, /* nsegments */
1939 MSK_TSO_MAXSGSIZE, /* maxsegsize */
1940 0, /* flags */
1941 &sc_if->msk_cdata.msk_tx_tag);
1942 if (error) {
1943 device_printf(sc_if->msk_if_dev,
1944 "failed to create Tx DMA tag\n");
1945 return error;
1946 }
1947
1948 /* Create DMA maps for Tx buffers. */
1949 for (i = 0; i < MSK_TX_RING_CNT; i++) {
1950 struct msk_txdesc *txd = &sc_if->msk_cdata.msk_txdesc[i];
1951
1952 error = bus_dmamap_create(sc_if->msk_cdata.msk_tx_tag, 0,
1953 &txd->tx_dmamap);
1954 if (error) {
1955 device_printf(sc_if->msk_if_dev,
1956 "failed to create %dth Tx dmamap\n", i);
1957
1958 for (j = 0; j < i; ++j) {
1959 txd = &sc_if->msk_cdata.msk_txdesc[j];
1960 bus_dmamap_destroy(sc_if->msk_cdata.msk_tx_tag,
1961 txd->tx_dmamap);
1962 }
1963 bus_dma_tag_destroy(sc_if->msk_cdata.msk_tx_tag);
1964 sc_if->msk_cdata.msk_tx_tag = NULL;
1965
1966 return error;
1967 }
1968 }
1969
1970 /* Create tag for Rx buffers. */
1971 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */
1972 1, 0, /* alignment, boundary */
1973 BUS_SPACE_MAXADDR, /* lowaddr */
1974 BUS_SPACE_MAXADDR, /* highaddr */
1975 NULL, NULL, /* filter, filterarg */
1976 MCLBYTES, /* maxsize */
1977 1, /* nsegments */
1978 MCLBYTES, /* maxsegsize */
1979 0, /* flags */
1980 &sc_if->msk_cdata.msk_rx_tag);
1981 if (error) {
1982 device_printf(sc_if->msk_if_dev,
1983 "failed to create Rx DMA tag\n");
1984 return error;
1985 }
1986
1987 /* Create DMA maps for Rx buffers. */
1988 error = bus_dmamap_create(sc_if->msk_cdata.msk_rx_tag, 0,
1989 &sc_if->msk_cdata.msk_rx_sparemap);
1990 if (error) {
1991 device_printf(sc_if->msk_if_dev,
1992 "failed to create spare Rx dmamap\n");
1993 bus_dma_tag_destroy(sc_if->msk_cdata.msk_rx_tag);
1994 sc_if->msk_cdata.msk_rx_tag = NULL;
1995 return error;
1996 }
1997 for (i = 0; i < MSK_RX_RING_CNT; i++) {
1998 struct msk_rxdesc *rxd = &sc_if->msk_cdata.msk_rxdesc[i];
1999
2000 error = bus_dmamap_create(sc_if->msk_cdata.msk_rx_tag, 0,
2001 &rxd->rx_dmamap);
2002 if (error) {
2003 device_printf(sc_if->msk_if_dev,
2004 "failed to create %dth Rx dmamap\n", i);
2005
2006 for (j = 0; j < i; ++j) {
2007 rxd = &sc_if->msk_cdata.msk_rxdesc[j];
2008 bus_dmamap_destroy(sc_if->msk_cdata.msk_rx_tag,
2009 rxd->rx_dmamap);
2010 }
2011 bus_dma_tag_destroy(sc_if->msk_cdata.msk_rx_tag);
2012 sc_if->msk_cdata.msk_rx_tag = NULL;
2013
2014 return error;
2015 }
2016 }
2017
2018 #ifdef MSK_JUMBO
2019 SLIST_INIT(&sc_if->msk_jfree_listhead);
2020 SLIST_INIT(&sc_if->msk_jinuse_listhead);
2021
2022 /* Create tag for jumbo Rx ring. */
2023 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */
2024 MSK_RING_ALIGN, 0, /* alignment, boundary */
2025 BUS_SPACE_MAXADDR, /* lowaddr */
2026 BUS_SPACE_MAXADDR, /* highaddr */
2027 NULL, NULL, /* filter, filterarg */
2028 MSK_JUMBO_RX_RING_SZ, /* maxsize */
2029 1, /* nsegments */
2030 MSK_JUMBO_RX_RING_SZ, /* maxsegsize */
2031 0, /* flags */
2032 NULL, NULL, /* lockfunc, lockarg */
2033 &sc_if->msk_cdata.msk_jumbo_rx_ring_tag);
2034 if (error != 0) {
2035 device_printf(sc_if->msk_if_dev,
2036 "failed to create jumbo Rx ring DMA tag\n");
2037 goto fail;
2038 }
2039
2040 /* Allocate DMA'able memory and load the DMA map for jumbo Rx ring. */
2041 error = bus_dmamem_alloc(sc_if->msk_cdata.msk_jumbo_rx_ring_tag,
2042 (void **)&sc_if->msk_rdata.msk_jumbo_rx_ring,
2043 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO,
2044 &sc_if->msk_cdata.msk_jumbo_rx_ring_map);
2045 if (error != 0) {
2046 device_printf(sc_if->msk_if_dev,
2047 "failed to allocate DMA'able memory for jumbo Rx ring\n");
2048 goto fail;
2049 }
2050
2051 ctx.msk_busaddr = 0;
2052 error = bus_dmamap_load(sc_if->msk_cdata.msk_jumbo_rx_ring_tag,
2053 sc_if->msk_cdata.msk_jumbo_rx_ring_map,
2054 sc_if->msk_rdata.msk_jumbo_rx_ring, MSK_JUMBO_RX_RING_SZ,
2055 msk_dmamap_cb, &ctx, 0);
2056 if (error != 0) {
2057 device_printf(sc_if->msk_if_dev,
2058 "failed to load DMA'able memory for jumbo Rx ring\n");
2059 goto fail;
2060 }
2061 sc_if->msk_rdata.msk_jumbo_rx_ring_paddr = ctx.msk_busaddr;
2062
2063 /* Create tag for jumbo buffer blocks. */
2064 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */
2065 PAGE_SIZE, 0, /* alignment, boundary */
2066 BUS_SPACE_MAXADDR, /* lowaddr */
2067 BUS_SPACE_MAXADDR, /* highaddr */
2068 NULL, NULL, /* filter, filterarg */
2069 MSK_JMEM, /* maxsize */
2070 1, /* nsegments */
2071 MSK_JMEM, /* maxsegsize */
2072 0, /* flags */
2073 NULL, NULL, /* lockfunc, lockarg */
2074 &sc_if->msk_cdata.msk_jumbo_tag);
2075 if (error != 0) {
2076 device_printf(sc_if->msk_if_dev,
2077 "failed to create jumbo Rx buffer block DMA tag\n");
2078 goto fail;
2079 }
2080
2081 /* Create tag for jumbo Rx buffers. */
2082 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */
2083 PAGE_SIZE, 0, /* alignment, boundary */
2084 BUS_SPACE_MAXADDR, /* lowaddr */
2085 BUS_SPACE_MAXADDR, /* highaddr */
2086 NULL, NULL, /* filter, filterarg */
2087 MCLBYTES * MSK_MAXRXSEGS, /* maxsize */
2088 MSK_MAXRXSEGS, /* nsegments */
2089 MSK_JLEN, /* maxsegsize */
2090 0, /* flags */
2091 NULL, NULL, /* lockfunc, lockarg */
2092 &sc_if->msk_cdata.msk_jumbo_rx_tag);
2093 if (error != 0) {
2094 device_printf(sc_if->msk_if_dev,
2095 "failed to create jumbo Rx DMA tag\n");
2096 goto fail;
2097 }
2098
2099 /* Create DMA maps for jumbo Rx buffers. */
2100 if ((error = bus_dmamap_create(sc_if->msk_cdata.msk_jumbo_rx_tag, 0,
2101 &sc_if->msk_cdata.msk_jumbo_rx_sparemap)) != 0) {
2102 device_printf(sc_if->msk_if_dev,
2103 "failed to create spare jumbo Rx dmamap\n");
2104 goto fail;
2105 }
2106 for (i = 0; i < MSK_JUMBO_RX_RING_CNT; i++) {
2107 jrxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[i];
2108 jrxd->rx_m = NULL;
2109 jrxd->rx_dmamap = NULL;
2110 error = bus_dmamap_create(sc_if->msk_cdata.msk_jumbo_rx_tag, 0,
2111 &jrxd->rx_dmamap);
2112 if (error != 0) {
2113 device_printf(sc_if->msk_if_dev,
2114 "failed to create jumbo Rx dmamap\n");
2115 goto fail;
2116 }
2117 }
2118
2119 /* Allocate DMA'able memory and load the DMA map for jumbo buf. */
2120 error = bus_dmamem_alloc(sc_if->msk_cdata.msk_jumbo_tag,
2121 (void **)&sc_if->msk_rdata.msk_jumbo_buf,
2122 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO,
2123 &sc_if->msk_cdata.msk_jumbo_map);
2124 if (error != 0) {
2125 device_printf(sc_if->msk_if_dev,
2126 "failed to allocate DMA'able memory for jumbo buf\n");
2127 goto fail;
2128 }
2129
2130 ctx.msk_busaddr = 0;
2131 error = bus_dmamap_load(sc_if->msk_cdata.msk_jumbo_tag,
2132 sc_if->msk_cdata.msk_jumbo_map, sc_if->msk_rdata.msk_jumbo_buf,
2133 MSK_JMEM, msk_dmamap_cb, &ctx, 0);
2134 if (error != 0) {
2135 device_printf(sc_if->msk_if_dev,
2136 "failed to load DMA'able memory for jumbobuf\n");
2137 goto fail;
2138 }
2139 sc_if->msk_rdata.msk_jumbo_buf_paddr = ctx.msk_busaddr;
2140
2141 /*
2142 * Now divide it up into 9K pieces and save the addresses
2143 * in an array.
2144 */
2145 ptr = sc_if->msk_rdata.msk_jumbo_buf;
2146 for (i = 0; i < MSK_JSLOTS; i++) {
2147 sc_if->msk_cdata.msk_jslots[i] = ptr;
2148 ptr += MSK_JLEN;
2149 entry = malloc(sizeof(struct msk_jpool_entry),
2150 M_DEVBUF, M_WAITOK);
2151 if (entry == NULL) {
2152 device_printf(sc_if->msk_if_dev,
2153 "no memory for jumbo buffers!\n");
2154 error = ENOMEM;
2155 goto fail;
2156 }
2157 entry->slot = i;
2158 SLIST_INSERT_HEAD(&sc_if->msk_jfree_listhead, entry,
2159 jpool_entries);
2160 }
2161 #endif
2162 return 0;
2163 }
2164
2165 static void
2166 msk_txrx_dma_free(struct msk_if_softc *sc_if)
2167 {
2168 struct msk_txdesc *txd;
2169 struct msk_rxdesc *rxd;
2170 #ifdef MSK_JUMBO
2171 struct msk_rxdesc *jrxd;
2172 struct msk_jpool_entry *entry;
2173 #endif
2174 int i;
2175
2176 #ifdef MSK_JUMBO
2177 MSK_JLIST_LOCK(sc_if);
2178 while ((entry = SLIST_FIRST(&sc_if->msk_jinuse_listhead))) {
2179 device_printf(sc_if->msk_if_dev,
2180 "asked to free buffer that is in use!\n");
2181 SLIST_REMOVE_HEAD(&sc_if->msk_jinuse_listhead, jpool_entries);
2182 SLIST_INSERT_HEAD(&sc_if->msk_jfree_listhead, entry,
2183 jpool_entries);
2184 }
2185
2186 while (!SLIST_EMPTY(&sc_if->msk_jfree_listhead)) {
2187 entry = SLIST_FIRST(&sc_if->msk_jfree_listhead);
2188 SLIST_REMOVE_HEAD(&sc_if->msk_jfree_listhead, jpool_entries);
2189 free(entry, M_DEVBUF);
2190 }
2191 MSK_JLIST_UNLOCK(sc_if);
2192
2193 /* Destroy jumbo buffer block. */
2194 if (sc_if->msk_cdata.msk_jumbo_map)
2195 bus_dmamap_unload(sc_if->msk_cdata.msk_jumbo_tag,
2196 sc_if->msk_cdata.msk_jumbo_map);
2197
2198 if (sc_if->msk_rdata.msk_jumbo_buf) {
2199 bus_dmamem_free(sc_if->msk_cdata.msk_jumbo_tag,
2200 sc_if->msk_rdata.msk_jumbo_buf,
2201 sc_if->msk_cdata.msk_jumbo_map);
2202 sc_if->msk_rdata.msk_jumbo_buf = NULL;
2203 sc_if->msk_cdata.msk_jumbo_map = NULL;
2204 }
2205
2206 /* Jumbo Rx ring. */
2207 if (sc_if->msk_cdata.msk_jumbo_rx_ring_tag) {
2208 if (sc_if->msk_cdata.msk_jumbo_rx_ring_map)
2209 bus_dmamap_unload(sc_if->msk_cdata.msk_jumbo_rx_ring_tag,
2210 sc_if->msk_cdata.msk_jumbo_rx_ring_map);
2211 if (sc_if->msk_cdata.msk_jumbo_rx_ring_map &&
2212 sc_if->msk_rdata.msk_jumbo_rx_ring)
2213 bus_dmamem_free(sc_if->msk_cdata.msk_jumbo_rx_ring_tag,
2214 sc_if->msk_rdata.msk_jumbo_rx_ring,
2215 sc_if->msk_cdata.msk_jumbo_rx_ring_map);
2216 sc_if->msk_rdata.msk_jumbo_rx_ring = NULL;
2217 sc_if->msk_cdata.msk_jumbo_rx_ring_map = NULL;
2218 bus_dma_tag_destroy(sc_if->msk_cdata.msk_jumbo_rx_ring_tag);
2219 sc_if->msk_cdata.msk_jumbo_rx_ring_tag = NULL;
2220 }
2221
2222 /* Jumbo Rx buffers. */
2223 if (sc_if->msk_cdata.msk_jumbo_rx_tag) {
2224 for (i = 0; i < MSK_JUMBO_RX_RING_CNT; i++) {
2225 jrxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[i];
2226 if (jrxd->rx_dmamap) {
2227 bus_dmamap_destroy(
2228 sc_if->msk_cdata.msk_jumbo_rx_tag,
2229 jrxd->rx_dmamap);
2230 jrxd->rx_dmamap = NULL;
2231 }
2232 }
2233 if (sc_if->msk_cdata.msk_jumbo_rx_sparemap) {
2234 bus_dmamap_destroy(sc_if->msk_cdata.msk_jumbo_rx_tag,
2235 sc_if->msk_cdata.msk_jumbo_rx_sparemap);
2236 sc_if->msk_cdata.msk_jumbo_rx_sparemap = 0;
2237 }
2238 bus_dma_tag_destroy(sc_if->msk_cdata.msk_jumbo_rx_tag);
2239 sc_if->msk_cdata.msk_jumbo_rx_tag = NULL;
2240 }
2241 #endif
2242
2243 /* Tx ring. */
2244 msk_dmamem_destroy(sc_if->msk_cdata.msk_tx_ring_tag,
2245 sc_if->msk_rdata.msk_tx_ring,
2246 sc_if->msk_cdata.msk_tx_ring_map);
2247
2248 /* Rx ring. */
2249 msk_dmamem_destroy(sc_if->msk_cdata.msk_rx_ring_tag,
2250 sc_if->msk_rdata.msk_rx_ring,
2251 sc_if->msk_cdata.msk_rx_ring_map);
2252
2253 /* Tx buffers. */
2254 if (sc_if->msk_cdata.msk_tx_tag) {
2255 for (i = 0; i < MSK_TX_RING_CNT; i++) {
2256 txd = &sc_if->msk_cdata.msk_txdesc[i];
2257 bus_dmamap_destroy(sc_if->msk_cdata.msk_tx_tag,
2258 txd->tx_dmamap);
2259 }
2260 bus_dma_tag_destroy(sc_if->msk_cdata.msk_tx_tag);
2261 sc_if->msk_cdata.msk_tx_tag = NULL;
2262 }
2263
2264 /* Rx buffers. */
2265 if (sc_if->msk_cdata.msk_rx_tag) {
2266 for (i = 0; i < MSK_RX_RING_CNT; i++) {
2267 rxd = &sc_if->msk_cdata.msk_rxdesc[i];
2268 bus_dmamap_destroy(sc_if->msk_cdata.msk_rx_tag,
2269 rxd->rx_dmamap);
2270 }
2271 bus_dmamap_destroy(sc_if->msk_cdata.msk_rx_tag,
2272 sc_if->msk_cdata.msk_rx_sparemap);
2273 bus_dma_tag_destroy(sc_if->msk_cdata.msk_rx_tag);
2274 sc_if->msk_cdata.msk_rx_tag = NULL;
2275 }
2276
2277 if (sc_if->msk_cdata.msk_parent_tag) {
2278 bus_dma_tag_destroy(sc_if->msk_cdata.msk_parent_tag);
2279 sc_if->msk_cdata.msk_parent_tag = NULL;
2280 }
2281 }
2282
2283 #ifdef MSK_JUMBO
2284 /*
2285 * Allocate a jumbo buffer.
2286 */
2287 static void *
2288 msk_jalloc(struct msk_if_softc *sc_if)
2289 {
2290 struct msk_jpool_entry *entry;
2291
2292 MSK_JLIST_LOCK(sc_if);
2293
2294 entry = SLIST_FIRST(&sc_if->msk_jfree_listhead);
2295
2296 if (entry == NULL) {
2297 MSK_JLIST_UNLOCK(sc_if);
2298 return (NULL);
2299 }
2300
2301 SLIST_REMOVE_HEAD(&sc_if->msk_jfree_listhead, jpool_entries);
2302 SLIST_INSERT_HEAD(&sc_if->msk_jinuse_listhead, entry, jpool_entries);
2303
2304 MSK_JLIST_UNLOCK(sc_if);
2305
2306 return (sc_if->msk_cdata.msk_jslots[entry->slot]);
2307 }
2308
2309 /*
2310 * Release a jumbo buffer.
2311 */
2312 static void
2313 msk_jfree(void *buf, void *args)
2314 {
2315 struct msk_if_softc *sc_if;
2316 struct msk_jpool_entry *entry;
2317 int i;
2318
2319 /* Extract the softc struct pointer. */
2320 sc_if = (struct msk_if_softc *)args;
2321 KASSERT(sc_if != NULL, ("%s: can't find softc pointer!", __func__));
2322
2323 MSK_JLIST_LOCK(sc_if);
2324 /* Calculate the slot this buffer belongs to. */
2325 i = ((vm_offset_t)buf
2326 - (vm_offset_t)sc_if->msk_rdata.msk_jumbo_buf) / MSK_JLEN;
2327 KASSERT(i >= 0 && i < MSK_JSLOTS,
2328 ("%s: asked to free buffer that we don't manage!", __func__));
2329
2330 entry = SLIST_FIRST(&sc_if->msk_jinuse_listhead);
2331 KASSERT(entry != NULL, ("%s: buffer not in use!", __func__));
2332 entry->slot = i;
2333 SLIST_REMOVE_HEAD(&sc_if->msk_jinuse_listhead, jpool_entries);
2334 SLIST_INSERT_HEAD(&sc_if->msk_jfree_listhead, entry, jpool_entries);
2335 if (SLIST_EMPTY(&sc_if->msk_jinuse_listhead))
2336 wakeup(sc_if);
2337
2338 MSK_JLIST_UNLOCK(sc_if);
2339 }
2340 #endif
2341
2342 /*
2343 * It's copy of ath_defrag(ath(4)).
2344 *
2345 * Defragment an mbuf chain, returning at most maxfrags separate
2346 * mbufs+clusters. If this is not possible NULL is returned and
2347 * the original mbuf chain is left in it's present (potentially
2348 * modified) state. We use two techniques: collapsing consecutive
2349 * mbufs and replacing consecutive mbufs by a cluster.
2350 */
2351 static struct mbuf *
2352 msk_defrag(struct mbuf *m0, int how, int maxfrags)
2353 {
2354 struct mbuf *m, *n, *n2, **prev;
2355 u_int curfrags;
2356
2357 /*
2358 * Calculate the current number of frags.
2359 */
2360 curfrags = 0;
2361 for (m = m0; m != NULL; m = m->m_next)
2362 curfrags++;
2363 /*
2364 * First, try to collapse mbufs. Note that we always collapse
2365 * towards the front so we don't need to deal with moving the
2366 * pkthdr. This may be suboptimal if the first mbuf has much
2367 * less data than the following.
2368 */
2369 m = m0;
2370 again:
2371 for (;;) {
2372 n = m->m_next;
2373 if (n == NULL)
2374 break;
2375 if (n->m_len < M_TRAILINGSPACE(m)) {
2376 bcopy(mtod(n, void *), mtod(m, char *) + m->m_len,
2377 n->m_len);
2378 m->m_len += n->m_len;
2379 m->m_next = n->m_next;
2380 m_free(n);
2381 if (--curfrags <= maxfrags)
2382 return (m0);
2383 } else
2384 m = n;
2385 }
2386 KASSERT(maxfrags > 1,
2387 ("maxfrags %u, but normal collapse failed", maxfrags));
2388 /*
2389 * Collapse consecutive mbufs to a cluster.
2390 */
2391 prev = &m0->m_next; /* NB: not the first mbuf */
2392 while ((n = *prev) != NULL) {
2393 if ((n2 = n->m_next) != NULL &&
2394 n->m_len + n2->m_len < MCLBYTES) {
2395 m = m_getcl(how, MT_DATA, 0);
2396 if (m == NULL)
2397 goto bad;
2398 bcopy(mtod(n, void *), mtod(m, void *), n->m_len);
2399 bcopy(mtod(n2, void *), mtod(m, char *) + n->m_len,
2400 n2->m_len);
2401 m->m_len = n->m_len + n2->m_len;
2402 m->m_next = n2->m_next;
2403 *prev = m;
2404 m_free(n);
2405 m_free(n2);
2406 if (--curfrags <= maxfrags) /* +1 cl -2 mbufs */
2407 return m0;
2408 /*
2409 * Still not there, try the normal collapse
2410 * again before we allocate another cluster.
2411 */
2412 goto again;
2413 }
2414 prev = &n->m_next;
2415 }
2416 /*
2417 * No place where we can collapse to a cluster; punt.
2418 * This can occur if, for example, you request 2 frags
2419 * but the packet requires that both be clusters (we
2420 * never reallocate the first mbuf to avoid moving the
2421 * packet header).
2422 */
2423 bad:
2424 return (NULL);
2425 }
2426
2427 static int
2428 msk_encap(struct msk_if_softc *sc_if, struct mbuf **m_head)
2429 {
2430 struct msk_txdesc *txd, *txd_last;
2431 struct msk_tx_desc *tx_le;
2432 struct mbuf *m;
2433 bus_dmamap_t map;
2434 struct msk_dmamap_arg ctx;
2435 bus_dma_segment_t txsegs[MSK_MAXTXSEGS];
2436 uint32_t control, prod, si;
2437 uint16_t offset, tcp_offset;
2438 int error, i;
2439
2440 tcp_offset = offset = 0;
2441 m = *m_head;
2442 if (m->m_pkthdr.csum_flags & MSK_CSUM_FEATURES) {
2443 /*
2444 * Since mbuf has no protocol specific structure information
2445 * in it we have to inspect protocol information here to
2446 * setup TSO and checksum offload. I don't know why Marvell
2447 * made a such decision in chip design because other GigE
2448 * hardwares normally takes care of all these chores in
2449 * hardware. However, TSO performance of Yukon II is very
2450 * good such that it's worth to implement it.
2451 */
2452 struct ether_header *eh;
2453 struct ip *ip;
2454
2455 /* TODO check for M_WRITABLE(m) */
2456
2457 offset = sizeof(struct ether_header);
2458 m = m_pullup(m, offset);
2459 if (m == NULL) {
2460 *m_head = NULL;
2461 return (ENOBUFS);
2462 }
2463 eh = mtod(m, struct ether_header *);
2464 /* Check if hardware VLAN insertion is off. */
2465 if (eh->ether_type == htons(ETHERTYPE_VLAN)) {
2466 offset = sizeof(struct ether_vlan_header);
2467 m = m_pullup(m, offset);
2468 if (m == NULL) {
2469 *m_head = NULL;
2470 return (ENOBUFS);
2471 }
2472 }
2473 m = m_pullup(m, offset + sizeof(struct ip));
2474 if (m == NULL) {
2475 *m_head = NULL;
2476 return (ENOBUFS);
2477 }
2478 ip = (struct ip *)(mtod(m, char *) + offset);
2479 offset += (ip->ip_hl << 2);
2480 tcp_offset = offset;
2481 /*
2482 * It seems that Yukon II has Tx checksum offload bug for
2483 * small TCP packets that's less than 60 bytes in size
2484 * (e.g. TCP window probe packet, pure ACK packet).
2485 * Common work around like padding with zeros to make the
2486 * frame minimum ethernet frame size didn't work at all.
2487 * Instead of disabling checksum offload completely we
2488 * resort to S/W checksum routine when we encounter short
2489 * TCP frames.
2490 * Short UDP packets appear to be handled correctly by
2491 * Yukon II.
2492 */
2493 if (m->m_pkthdr.len < MSK_MIN_FRAMELEN &&
2494 (m->m_pkthdr.csum_flags & CSUM_TCP) != 0) {
2495 uint16_t csum;
2496
2497 csum = in_cksum_skip(m, ntohs(ip->ip_len) + offset -
2498 (ip->ip_hl << 2), offset);
2499 *(uint16_t *)(m->m_data + offset +
2500 m->m_pkthdr.csum_data) = csum;
2501 m->m_pkthdr.csum_flags &= ~CSUM_TCP;
2502 }
2503 *m_head = m;
2504 }
2505
2506 prod = sc_if->msk_cdata.msk_tx_prod;
2507 txd = &sc_if->msk_cdata.msk_txdesc[prod];
2508 txd_last = txd;
2509 map = txd->tx_dmamap;
2510 bzero(&ctx, sizeof(ctx));
2511 ctx.nseg = MSK_MAXTXSEGS;
2512 ctx.segs = txsegs;
2513 error = bus_dmamap_load_mbuf(sc_if->msk_cdata.msk_tx_tag, map,
2514 *m_head, msk_dmamap_mbuf_cb, &ctx, BUS_DMA_NOWAIT);
2515 if (error == 0 && ctx.nseg == 0) {
2516 bus_dmamap_unload(sc_if->msk_cdata.msk_tx_tag, map);
2517 error = EFBIG;
2518 }
2519 if (error == EFBIG) {
2520 m = msk_defrag(*m_head, MB_DONTWAIT, MSK_MAXTXSEGS);
2521 if (m == NULL) {
2522 m_freem(*m_head);
2523 *m_head = NULL;
2524 return (ENOBUFS);
2525 }
2526 *m_head = m;
2527
2528 bzero(&ctx, sizeof(ctx));
2529 ctx.nseg = MSK_MAXTXSEGS;
2530 ctx.segs = txsegs;
2531 error = bus_dmamap_load_mbuf(sc_if->msk_cdata.msk_tx_tag,
2532 map, *m_head, msk_dmamap_mbuf_cb, &ctx, BUS_DMA_NOWAIT);
2533 if (error == 0 && ctx.nseg == 0) {
2534 bus_dmamap_unload(sc_if->msk_cdata.msk_tx_tag, map);
2535 error = EFBIG;
2536 }
2537 if (error != 0) {
2538 m_freem(*m_head);
2539 *m_head = NULL;
2540 return (error);
2541 }
2542 } else if (error != 0) {
2543 return (error);
2544 }
2545
2546 /* Check number of available descriptors. */
2547 if (sc_if->msk_cdata.msk_tx_cnt + ctx.nseg >=
2548 (MSK_TX_RING_CNT - MSK_RESERVED_TX_DESC_CNT)) {
2549 bus_dmamap_unload(sc_if->msk_cdata.msk_tx_tag, map);
2550 return (ENOBUFS);
2551 }
2552
2553 control = 0;
2554 tx_le = NULL;
2555
2556 #ifdef notyet
2557 /* Check if we have a VLAN tag to insert. */
2558 if ((m->m_flags & M_VLANTAG) != 0) {
2559 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod];
2560 tx_le->msk_addr = htole32(0);
2561 tx_le->msk_control = htole32(OP_VLAN | HW_OWNER |
2562 htons(m->m_pkthdr.ether_vtag));
2563 sc_if->msk_cdata.msk_tx_cnt++;
2564 MSK_INC(prod, MSK_TX_RING_CNT);
2565 control |= INS_VLAN;
2566 }
2567 #endif
2568 /* Check if we have to handle checksum offload. */
2569 if (m->m_pkthdr.csum_flags & MSK_CSUM_FEATURES) {
2570 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod];
2571 tx_le->msk_addr = htole32(((tcp_offset + m->m_pkthdr.csum_data)
2572 & 0xffff) | ((uint32_t)tcp_offset << 16));
2573 tx_le->msk_control = htole32(1 << 16 | (OP_TCPLISW | HW_OWNER));
2574 control = CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
2575 if ((m->m_pkthdr.csum_flags & CSUM_UDP) != 0)
2576 control |= UDPTCP;
2577 sc_if->msk_cdata.msk_tx_cnt++;
2578 MSK_INC(prod, MSK_TX_RING_CNT);
2579 }
2580
2581 si = prod;
2582 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod];
2583 tx_le->msk_addr = htole32(MSK_ADDR_LO(txsegs[0].ds_addr));
2584 tx_le->msk_control = htole32(txsegs[0].ds_len | control |
2585 OP_PACKET);
2586 sc_if->msk_cdata.msk_tx_cnt++;
2587 MSK_INC(prod, MSK_TX_RING_CNT);
2588
2589 for (i = 1; i < ctx.nseg; i++) {
2590 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod];
2591 tx_le->msk_addr = htole32(MSK_ADDR_LO(txsegs[i].ds_addr));
2592 tx_le->msk_control = htole32(txsegs[i].ds_len | control |
2593 OP_BUFFER | HW_OWNER);
2594 sc_if->msk_cdata.msk_tx_cnt++;
2595 MSK_INC(prod, MSK_TX_RING_CNT);
2596 }
2597 /* Update producer index. */
2598 sc_if->msk_cdata.msk_tx_prod = prod;
2599
2600 /* Set EOP on the last desciptor. */
2601 prod = (prod + MSK_TX_RING_CNT - 1) % MSK_TX_RING_CNT;
2602 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod];
2603 tx_le->msk_control |= htole32(EOP);
2604
2605 /* Turn the first descriptor ownership to hardware. */
2606 tx_le = &sc_if->msk_rdata.msk_tx_ring[si];
2607 tx_le->msk_control |= htole32(HW_OWNER);
2608
2609 txd = &sc_if->msk_cdata.msk_txdesc[prod];
2610 map = txd_last->tx_dmamap;
2611 txd_last->tx_dmamap = txd->tx_dmamap;
2612 txd->tx_dmamap = map;
2613 txd->tx_m = m;
2614
2615 /* Sync descriptors. */
2616 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_tag, map, BUS_DMASYNC_PREWRITE);
2617 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_ring_tag,
2618 sc_if->msk_cdata.msk_tx_ring_map, BUS_DMASYNC_PREWRITE);
2619
2620 return (0);
2621 }
2622
2623 static void
2624 msk_start(struct ifnet *ifp)
2625 {
2626 struct msk_if_softc *sc_if;
2627 struct mbuf *m_head;
2628 int enq;
2629
2630 sc_if = ifp->if_softc;
2631
2632 ASSERT_SERIALIZED(ifp->if_serializer);
2633
2634 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) !=
2635 IFF_RUNNING || sc_if->msk_link == 0)
2636 return;
2637
2638 for (enq = 0; !ifq_is_empty(&ifp->if_snd) &&
2639 sc_if->msk_cdata.msk_tx_cnt <
2640 (MSK_TX_RING_CNT - MSK_RESERVED_TX_DESC_CNT); ) {
2641 m_head = ifq_dequeue(&ifp->if_snd, NULL);
2642 if (m_head == NULL)
2643 break;
2644
2645 /*
2646 * Pack the data into the transmit ring. If we
2647 * don't have room, set the OACTIVE flag and wait
2648 * for the NIC to drain the ring.
2649 */
2650 if (msk_encap(sc_if, &m_head) != 0) {
2651 if (m_head == NULL)
2652 break;
2653 m_freem(m_head);
2654 ifp->if_flags |= IFF_OACTIVE;
2655 break;
2656 }
2657
2658 enq++;
2659 /*
2660 * If there's a BPF listener, bounce a copy of this frame
2661 * to him.
2662 */
2663 BPF_MTAP(ifp, m_head);
2664 }
2665
2666 if (enq > 0) {
2667 /* Transmit */
2668 CSR_WRITE_2(sc_if->msk_softc,
2669 Y2_PREF_Q_ADDR(sc_if->msk_txq, PREF_UNIT_PUT_IDX_REG),
2670 sc_if->msk_cdata.msk_tx_prod);
2671
2672 /* Set a timeout in case the chip goes out to lunch. */
2673 ifp->if_timer = MSK_TX_TIMEOUT;
2674 }
2675 }
2676
2677 static void
2678 msk_watchdog(struct ifnet *ifp)
2679 {
2680 struct msk_if_softc *sc_if = ifp->if_softc;
2681 uint32_t ridx;
2682 int idx;
2683
2684 ASSERT_SERIALIZED(ifp->if_serializer);
2685
2686 if (sc_if->msk_link == 0) {
2687 if (bootverbose)
2688 if_printf(sc_if->msk_ifp, "watchdog timeout "
2689 "(missed link)\n");
2690 ifp->if_oerrors++;
2691 msk_init(sc_if);
2692 return;
2693 }
2694
2695 /*
2696 * Reclaim first as there is a possibility of losing Tx completion
2697 * interrupts.
2698 */
2699 ridx = sc_if->msk_port == MSK_PORT_A ? STAT_TXA1_RIDX : STAT_TXA2_RIDX;
2700 idx = CSR_READ_2(sc_if->msk_softc, ridx);
2701 if (sc_if->msk_cdata.msk_tx_cons != idx) {
2702 msk_txeof(sc_if, idx);
2703 if (sc_if->msk_cdata.msk_tx_cnt == 0) {
2704 if_printf(ifp, "watchdog timeout (missed Tx interrupts) "
2705 "-- recovering\n");
2706 if (!ifq_is_empty(&ifp->if_snd))
2707 ifp->if_start(ifp);
2708 return;
2709 }
2710 }
2711
2712 if_printf(ifp, "watchdog timeout\n");
2713 ifp->if_oerrors++;
2714 msk_init(sc_if);
2715 if (!ifq_is_empty(&ifp->if_snd))
2716 ifp->if_start(ifp);
2717 }
2718
2719 static int
2720 mskc_shutdown(device_t dev)
2721 {
2722 struct msk_softc *sc = device_get_softc(dev);
2723 int i;
2724
2725 lwkt_serialize_enter(&sc->msk_serializer);
2726
2727 for (i = 0; i < sc->msk_num_port; i++) {
2728 if (sc->msk_if[i] != NULL)
2729 msk_stop(sc->msk_if[i]);
2730 }
2731
2732 /* Disable all interrupts. */
2733 CSR_WRITE_4(sc, B0_IMSK, 0);
2734 CSR_READ_4(sc, B0_IMSK);
2735 CSR_WRITE_4(sc, B0_HWE_IMSK, 0);
2736 CSR_READ_4(sc, B0_HWE_IMSK);
2737
2738 /* Put hardware reset. */
2739 CSR_WRITE_2(sc, B0_CTST, CS_RST_SET);
2740
2741 lwkt_serialize_exit(&sc->msk_serializer);
2742 return (0);
2743 }
2744
2745 static int
2746 mskc_suspend(device_t dev)
2747 {
2748 struct msk_softc *sc = device_get_softc(dev);
2749 int i;
2750
2751 lwkt_serialize_enter(&sc->msk_serializer);
2752
2753 for (i = 0; i < sc->msk_num_port; i++) {
2754 if (sc->msk_if[i] != NULL && sc->msk_if[i]->msk_ifp != NULL &&
2755 ((sc->msk_if[i]->msk_ifp->if_flags & IFF_RUNNING) != 0))
2756 msk_stop(sc->msk_if[i]);
2757 }
2758
2759 /* Disable all interrupts. */
2760 CSR_WRITE_4(sc, B0_IMSK, 0);
2761 CSR_READ_4(sc, B0_IMSK);
2762 CSR_WRITE_4(sc, B0_HWE_IMSK, 0);
2763 CSR_READ_4(sc, B0_HWE_IMSK);
2764
2765 mskc_phy_power(sc, MSK_PHY_POWERDOWN);
2766
2767 /* Put hardware reset. */
2768 CSR_WRITE_2(sc, B0_CTST, CS_RST_SET);
2769 sc->msk_suspended = 1;
2770
2771 lwkt_serialize_exit(&sc->msk_serializer);
2772
2773 return (0);
2774 }
2775
2776 static int
2777 mskc_resume(device_t dev)
2778 {
2779 struct msk_softc *sc = device_get_softc(dev);
2780 int i;
2781
2782 lwkt_serialize_enter(&sc->msk_serializer);
2783
2784 mskc_reset(sc);
2785 for (i = 0; i < sc->msk_num_port; i++) {
2786 if (sc->msk_if[i] != NULL && sc->msk_if[i]->msk_ifp != NULL &&
2787 ((sc->msk_if[i]->msk_ifp->if_flags & IFF_UP) != 0))
2788 msk_init(sc->msk_if[i]);
2789 }
2790 sc->msk_suspended = 0;
2791
2792 lwkt_serialize_exit(&sc->msk_serializer);
2793
2794 return (0);
2795 }
2796
2797 static void
2798 msk_rxeof(struct msk_if_softc *sc_if, uint32_t status, int len)
2799 {
2800 struct mbuf *m;
2801 struct ifnet *ifp;
2802 struct msk_rxdesc *rxd;
2803 int cons, rxlen;
2804
2805 ifp = sc_if->msk_ifp;
2806
2807 cons = sc_if->msk_cdata.msk_rx_cons;
2808 do {
2809 rxlen = status >> 16;
2810 if ((status & GMR_FS_VLAN) != 0 &&
2811 (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0)
2812 rxlen -= EVL_ENCAPLEN;
2813 if (len > sc_if->msk_framesize ||
2814 ((status & GMR_FS_ANY_ERR) != 0) ||
2815 ((status & GMR_FS_RX_OK) == 0) || (rxlen != len)) {
2816 /* Don't count flow-control packet as errors. */
2817 if ((status & GMR_FS_GOOD_FC) == 0)
2818 ifp->if_ierrors++;
2819 msk_discard_rxbuf(sc_if, cons);
2820 break;
2821 }
2822 rxd = &sc_if->msk_cdata.msk_rxdesc[cons];
2823 m = rxd->rx_m;
2824 if (msk_newbuf(sc_if, cons) != 0) {
2825 ifp->if_iqdrops++;
2826 /* Reuse old buffer. */
2827 msk_discard_rxbuf(sc_if, cons);
2828 break;
2829 }
2830 m->m_pkthdr.rcvif = ifp;
2831 m->m_pkthdr.len = m->m_len = len;
2832 ifp->if_ipackets++;
2833 #ifdef notyet
2834 /* Check for VLAN tagged packets. */
2835 if ((status & GMR_FS_VLAN) != 0 &&
2836 (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) {
2837 m->m_pkthdr.ether_vtag = sc_if->msk_vtag;
2838 m->m_flags |= M_VLANTAG;
2839 }
2840 #endif
2841 ifp->if_input(ifp, m);
2842 } while (0);
2843
2844 MSK_INC(sc_if->msk_cdata.msk_rx_cons, MSK_RX_RING_CNT);
2845 MSK_INC(sc_if->msk_cdata.msk_rx_prod, MSK_RX_RING_CNT);
2846 }
2847
2848 #ifdef MSK_JUMBO
2849 static void
2850 msk_jumbo_rxeof(struct msk_if_softc *sc_if, uint32_t status, int len)
2851 {
2852 struct mbuf *m;
2853 struct ifnet *ifp;
2854 struct msk_rxdesc *jrxd;
2855 int cons, rxlen;
2856
2857 ifp = sc_if->msk_ifp;
2858
2859 MSK_IF_LOCK_ASSERT(sc_if);
2860
2861 cons = sc_if->msk_cdata.msk_rx_cons;
2862 do {
2863 rxlen = status >> 16;
2864 if ((status & GMR_FS_VLAN) != 0 &&
2865 (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0)
2866 rxlen -= ETHER_VLAN_ENCAP_LEN;
2867 if (len > sc_if->msk_framesize ||
2868 ((status & GMR_FS_ANY_ERR) != 0) ||
2869 ((status & GMR_FS_RX_OK) == 0) || (rxlen != len)) {
2870 /* Don't count flow-control packet as errors. */
2871 if ((status & GMR_FS_GOOD_FC) == 0)
2872 ifp->if_ierrors++;
2873 msk_discard_jumbo_rxbuf(sc_if, cons);
2874 break;
2875 }
2876 jrxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[cons];
2877 m = jrxd->rx_m;
2878 if (msk_jumbo_newbuf(sc_if, cons) != 0) {
2879 ifp->if_iqdrops++;
2880 /* Reuse old buffer. */
2881 msk_discard_jumbo_rxbuf(sc_if, cons);
2882 break;
2883 }
2884 m->m_pkthdr.rcvif = ifp;
2885 m->m_pkthdr.len = m->m_len = len;
2886 ifp->if_ipackets++;
2887 /* Check for VLAN tagged packets. */
2888 if ((status & GMR_FS_VLAN) != 0 &&
2889 (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) {
2890 m->m_pkthdr.ether_vtag = sc_if->msk_vtag;
2891 m->m_flags |= M_VLANTAG;
2892 }
2893 MSK_IF_UNLOCK(sc_if);
2894 (*ifp->if_input)(ifp, m);
2895 MSK_IF_LOCK(sc_if);
2896 } while (0);
2897
2898 MSK_INC(sc_if->msk_cdata.msk_rx_cons, MSK_JUMBO_RX_RING_CNT);
2899 MSK_INC(sc_if->msk_cdata.msk_rx_prod, MSK_JUMBO_RX_RING_CNT);
2900 }
2901 #endif
2902
2903 static void
2904 msk_txeof(struct msk_if_softc *sc_if, int idx)
2905 {
2906 struct msk_txdesc *txd;
2907 struct msk_tx_desc *cur_tx;
2908 struct ifnet *ifp;
2909 uint32_t control;
2910 int cons, prog;
2911
2912 ifp = sc_if->msk_ifp;
2913
2914 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_ring_tag,
2915 sc_if->msk_cdata.msk_tx_ring_map, BUS_DMASYNC_POSTREAD);
2916
2917 /*
2918 * Go through our tx ring and free mbufs for those
2919 * frames that have been sent.
2920 */
2921 cons = sc_if->msk_cdata.msk_tx_cons;
2922 prog = 0;
2923 for (; cons != idx; MSK_INC(cons, MSK_TX_RING_CNT)) {
2924 if (sc_if->msk_cdata.msk_tx_cnt <= 0)
2925 break;
2926 prog++;
2927 cur_tx = &sc_if->msk_rdata.msk_tx_ring[cons];
2928 control = le32toh(cur_tx->msk_control);
2929 sc_if->msk_cdata.msk_tx_cnt--;
2930 ifp->if_flags &= ~IFF_OACTIVE;
2931 if ((control & EOP) == 0)
2932 continue;
2933 txd = &sc_if->msk_cdata.msk_txdesc[cons];
2934 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_tag, txd->tx_dmamap,
2935 BUS_DMASYNC_POSTWRITE);
2936 bus_dmamap_unload(sc_if->msk_cdata.msk_tx_tag, txd->tx_dmamap);
2937
2938 ifp->if_opackets++;
2939 KASSERT(txd->tx_m != NULL, ("%s: freeing NULL mbuf!",
2940 __func__));
2941 m_freem(txd->tx_m);
2942 txd->tx_m = NULL;
2943 }
2944
2945 if (prog > 0) {
2946 sc_if->msk_cdata.msk_tx_cons = cons;
2947 if (sc_if->msk_cdata.msk_tx_cnt == 0)
2948 ifp->if_timer = 0;
2949 /* No need to sync LEs as we didn't update LEs. */
2950 }
2951 }
2952
2953 static void
2954 msk_tick(void *xsc_if)
2955 {
2956 struct msk_if_softc *sc_if = xsc_if;
2957 struct ifnet *ifp = &sc_if->arpcom.ac_if;
2958 struct mii_data *mii;
2959
2960 lwkt_serialize_enter(ifp->if_serializer);
2961
2962 mii = device_get_softc(sc_if->msk_miibus);
2963
2964 mii_tick(mii);
2965 callout_reset(&sc_if->msk_tick_ch, hz, msk_tick, sc_if);
2966
2967 lwkt_serialize_exit(ifp->if_serializer);
2968 }
2969
2970 static void
2971 msk_intr_phy(struct msk_if_softc *sc_if)
2972 {
2973 uint16_t status;
2974
2975 msk_phy_readreg(sc_if, PHY_ADDR_MARV, PHY_MARV_INT_STAT);
2976 status = msk_phy_readreg(sc_if, PHY_ADDR_MARV, PHY_MARV_INT_STAT);
2977 /* Handle FIFO Underrun/Overflow? */
2978 if (status & PHY_M_IS_FIFO_ERROR) {
2979 device_printf(sc_if->msk_if_dev,
2980 "PHY FIFO underrun/overflow.\n");
2981 }
2982 }
2983
2984 static void
2985 msk_intr_gmac(struct msk_if_softc *sc_if)
2986 {
2987 struct msk_softc *sc;
2988 uint8_t status;
2989
2990 sc = sc_if->msk_softc;
2991 status = CSR_READ_1(sc, MR_ADDR(sc_if->msk_port, GMAC_IRQ_SRC));
2992
2993 /* GMAC Rx FIFO overrun. */
2994 if ((status & GM_IS_RX_FF_OR) != 0) {
2995 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T),
2996 GMF_CLI_RX_FO);
2997 device_printf(sc_if->msk_if_dev, "Rx FIFO overrun!\n");
2998 }
2999 /* GMAC Tx FIFO underrun. */
3000 if ((status & GM_IS_TX_FF_UR) != 0) {
3001 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T),
3002 GMF_CLI_TX_FU);
3003 device_printf(sc_if->msk_if_dev, "Tx FIFO underrun!\n");
3004 /*
3005 * XXX
3006 * In case of Tx underrun, we may need to flush/reset
3007 * Tx MAC but that would also require resynchronization
3008 * with status LEs. Reintializing status LEs would
3009 * affect other port in dual MAC configuration so it
3010 * should be avoided as possible as we can.
3011 * Due to lack of documentation it's all vague guess but
3012 * it needs more investigation.
3013 */
3014 }
3015 }
3016
3017 static void
3018 msk_handle_hwerr(struct msk_if_softc *sc_if, uint32_t status)
3019 {
3020 struct msk_softc *sc;
3021
3022 sc = sc_if->msk_softc;
3023 if ((status & Y2_IS_PAR_RD1) != 0) {
3024 device_printf(sc_if->msk_if_dev,
3025 "RAM buffer read parity error\n");
3026 /* Clear IRQ. */
3027 CSR_WRITE_2(sc, SELECT_RAM_BUFFER(sc_if->msk_port, B3_RI_CTRL),
3028 RI_CLR_RD_PERR);
3029 }
3030 if ((status & Y2_IS_PAR_WR1) != 0) {
3031 device_printf(sc_if->msk_if_dev,
3032 "RAM buffer write parity error\n");
3033 /* Clear IRQ. */
3034 CSR_WRITE_2(sc, SELECT_RAM_BUFFER(sc_if->msk_port, B3_RI_CTRL),
3035 RI_CLR_WR_PERR);
3036 }
3037 if ((status & Y2_IS_PAR_MAC1) != 0) {
3038 device_printf(sc_if->msk_if_dev, "Tx MAC parity error\n");
3039 /* Clear IRQ. */
3040 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T),
3041 GMF_CLI_TX_PE);
3042 }
3043 if ((status & Y2_IS_PAR_RX1) != 0) {
3044 device_printf(sc_if->msk_if_dev, "Rx parity error\n");
3045 /* Clear IRQ. */
3046 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), BMU_CLR_IRQ_PAR);
3047 }
3048 if ((status & (Y2_IS_TCP_TXS1 | Y2_IS_TCP_TXA1)) != 0) {
3049 device_printf(sc_if->msk_if_dev, "TCP segmentation error\n");
3050 /* Clear IRQ. */
3051 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_CLR_IRQ_TCP);
3052 }
3053 }
3054
3055 static void
3056 mskc_intr_hwerr(struct msk_softc *sc)
3057 {
3058 uint32_t status;
3059 uint32_t tlphead[4];
3060
3061 status = CSR_READ_4(sc, B0_HWE_ISRC);
3062 /* Time Stamp timer overflow. */
3063 if ((status & Y2_IS_TIST_OV) != 0)
3064 CSR_WRITE_1(sc, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
3065 if ((status & Y2_IS_PCI_NEXP) != 0) {
3066 /*
3067 * PCI Express Error occured which is not described in PEX
3068 * spec.
3069 * This error is also mapped either to Master Abort(
3070 * Y2_IS_MST_ERR) or Target Abort (Y2_IS_IRQ_STAT) bit and
3071 * can only be cleared there.
3072 */
3073 device_printf(sc->msk_dev,
3074 "PCI Express protocol violation error\n");
3075 }
3076
3077 if ((status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) != 0) {
3078 uint16_t v16;
3079
3080 if ((status & Y2_IS_MST_ERR) != 0)
3081 device_printf(sc->msk_dev,
3082 "unexpected IRQ Status error\n");
3083 else
3084 device_printf(sc->msk_dev,
3085 "unexpected IRQ Master error\n");
3086 /* Reset all bits in the PCI status register. */
3087 v16 = pci_read_config(sc->msk_dev, PCIR_STATUS, 2);
3088 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3089 pci_write_config(sc->msk_dev, PCIR_STATUS, v16 |
3090 PCIM_STATUS_PERR | PCIM_STATUS_SERR | PCIM_STATUS_RMABORT |
3091 PCIM_STATUS_RTABORT | PCIM_STATUS_PERRREPORT, 2);
3092 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3093 }
3094
3095 /* Check for PCI Express Uncorrectable Error. */
3096 if ((status & Y2_IS_PCI_EXP) != 0) {
3097 uint32_t v32;
3098
3099 /*
3100 * On PCI Express bus bridges are called root complexes (RC).
3101 * PCI Express errors are recognized by the root complex too,
3102 * which requests the system to handle the problem. After
3103 * error occurence it may be that no access to the adapter
3104 * may be performed any longer.
3105 */
3106
3107 v32 = CSR_PCI_READ_4(sc, PEX_UNC_ERR_STAT);
3108 if ((v32 & PEX_UNSUP_REQ) != 0) {
3109 /* Ignore unsupported request error. */
3110 if (bootverbose) {
3111 device_printf(sc->msk_dev,
3112 "Uncorrectable PCI Express error\n");
3113 }
3114 }
3115 if ((v32 & (PEX_FATAL_ERRORS | PEX_POIS_TLP)) != 0) {
3116 int i;
3117
3118 /* Get TLP header form Log Registers. */
3119 for (i = 0; i < 4; i++)
3120 tlphead[i] = CSR_PCI_READ_4(sc,
3121 PEX_HEADER_LOG + i * 4);
3122 /* Check for vendor defined broadcast message. */
3123 if (!(tlphead[0] == 0x73004001 && tlphead[1] == 0x7f)) {
3124 sc->msk_intrhwemask &= ~Y2_IS_PCI_EXP;
3125 CSR_WRITE_4(sc, B0_HWE_IMSK,
3126 sc->msk_intrhwemask);
3127 CSR_READ_4(sc, B0_HWE_IMSK);
3128 }
3129 }
3130 /* Clear the interrupt. */
3131 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3132 CSR_PCI_WRITE_4(sc, PEX_UNC_ERR_STAT, 0xffffffff);
3133 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3134 }
3135
3136 if ((status & Y2_HWE_L1_MASK) != 0 && sc->msk_if[MSK_PORT_A] != NULL)
3137 msk_handle_hwerr(sc->msk_if[MSK_PORT_A], status);
3138 if ((status & Y2_HWE_L2_MASK) != 0 && sc->msk_if[MSK_PORT_B] != NULL)
3139 msk_handle_hwerr(sc->msk_if[MSK_PORT_B], status >> 8);
3140 }
3141
3142 static __inline void
3143 msk_rxput(struct msk_if_softc *sc_if)
3144 {
3145 struct msk_softc *sc;
3146
3147 sc = sc_if->msk_softc;
3148 #ifdef MSK_JUMBO
3149 if (sc_if->msk_framesize > (MCLBYTES - ETHER_HDR_LEN)) {
3150 bus_dmamap_sync(
3151 sc_if->msk_cdata.msk_jumbo_rx_ring_tag,
3152 sc_if->msk_cdata.msk_jumbo_rx_ring_map,
3153 BUS_DMASYNC_PREWRITE);
3154 } else
3155 #endif
3156 {
3157 bus_dmamap_sync(
3158 sc_if->msk_cdata.msk_rx_ring_tag,
3159 sc_if->msk_cdata.msk_rx_ring_map,
3160 BUS_DMASYNC_PREWRITE);
3161 }
3162 CSR_WRITE_2(sc, Y2_PREF_Q_ADDR(sc_if->msk_rxq,
3163 PREF_UNIT_PUT_IDX_REG), sc_if->msk_cdata.msk_rx_prod);
3164 }
3165
3166 static int
3167 mskc_handle_events(struct msk_softc *sc)
3168 {
3169 struct msk_if_softc *sc_if;
3170 int rxput[2];
3171 struct msk_stat_desc *sd;
3172 uint32_t control, status;
3173 int cons, idx, len, port, rxprog;
3174
3175 idx = CSR_READ_2(sc, STAT_PUT_IDX);
3176 if (idx == sc->msk_stat_cons)
3177 return (0);
3178
3179 /* Sync status LEs. */
3180 bus_dmamap_sync(sc->msk_stat_tag, sc->msk_stat_map,
3181 BUS_DMASYNC_POSTREAD);
3182 /* XXX Sync Rx LEs here. */
3183
3184 rxput[MSK_PORT_A] = rxput[MSK_PORT_B] = 0;
3185
3186 rxprog = 0;
3187 for (cons = sc->msk_stat_cons; cons != idx;) {
3188 sd = &sc->msk_stat_ring[cons];
3189 control = le32toh(sd->msk_control);
3190 if ((control & HW_OWNER) == 0)
3191 break;
3192 /*
3193 * Marvell's FreeBSD driver updates status LE after clearing
3194 * HW_OWNER. However we don't have a way to sync single LE
3195 * with bus_dma(9) API. bus_dma(9) provides a way to sync
3196 * an entire DMA map. So don't sync LE until we have a better
3197 * way to sync LEs.
3198 */
3199 control &= ~HW_OWNER;
3200 sd->msk_control = htole32(control);
3201 status = le32toh(sd->msk_status);
3202 len = control & STLE_LEN_MASK;
3203 port = (control >> 16) & 0x01;
3204 sc_if = sc->msk_if[port];
3205 if (sc_if == NULL) {
3206 device_printf(sc->msk_dev, "invalid port opcode "
3207 "0x%08x\n", control & STLE_OP_MASK);
3208 continue;
3209 }
3210
3211 switch (control & STLE_OP_MASK) {
3212 case OP_RXVLAN:
3213 sc_if->msk_vtag = ntohs(len);
3214 break;
3215 case OP_RXCHKSVLAN:
3216 sc_if->msk_vtag = ntohs(len);
3217 break;
3218 case OP_RXSTAT:
3219 #ifdef MSK_JUMBO
3220 if (sc_if->msk_framesize > (MCLBYTES - ETHER_HDR_LEN))
3221 msk_jumbo_rxeof(sc_if, status, len);
3222 else
3223 #endif
3224 msk_rxeof(sc_if, status, len);
3225 rxprog++;
3226 /*
3227 * Because there is no way to sync single Rx LE
3228 * put the DMA sync operation off until the end of
3229 * event processing.
3230 */
3231 rxput[port]++;
3232 /* Update prefetch unit if we've passed water mark. */
3233 if (rxput[port] >= sc_if->msk_cdata.msk_rx_putwm) {
3234 msk_rxput(sc_if);
3235 rxput[port] = 0;
3236 }
3237 break;
3238 case OP_TXINDEXLE:
3239 if (sc->msk_if[MSK_PORT_A] != NULL) {
3240 msk_txeof(sc->msk_if[MSK_PORT_A],
3241 status & STLE_TXA1_MSKL);
3242 }
3243 if (sc->msk_if[MSK_PORT_B] != NULL) {
3244 msk_txeof(sc->msk_if[MSK_PORT_B],
3245 ((status & STLE_TXA2_MSKL) >>
3246 STLE_TXA2_SHIFTL) |
3247 ((len & STLE_TXA2_MSKH) <<
3248 STLE_TXA2_SHIFTH));
3249 }
3250 break;
3251 default:
3252 device_printf(sc->msk_dev, "unhandled opcode 0x%08x\n",
3253 control & STLE_OP_MASK);
3254 break;
3255 }
3256 MSK_INC(cons, MSK_STAT_RING_CNT);
3257 if (rxprog > sc->msk_process_limit)
3258 break;
3259 }
3260
3261 sc->msk_stat_cons = cons;
3262 /* XXX We should sync status LEs here. See above notes. */
3263
3264 if (rxput[MSK_PORT_A] > 0)
3265 msk_rxput(sc->msk_if[MSK_PORT_A]);
3266 if (rxput[MSK_PORT_B] > 0)
3267 msk_rxput(sc->msk_if[MSK_PORT_B]);
3268
3269 return (sc->msk_stat_cons != CSR_READ_2(sc, STAT_PUT_IDX));
3270 }
3271
3272 /* Legacy interrupt handler for shared interrupt. */
3273 static void
3274 mskc_intr(void *xsc)
3275 {
3276 struct msk_softc *sc;
3277 struct msk_if_softc *sc_if0, *sc_if1;
3278 struct ifnet *ifp0, *ifp1;
3279 uint32_t status;
3280
3281 sc = xsc;
3282 ASSERT_SERIALIZED(&sc->msk_serializer);
3283
3284 /* Reading B0_Y2_SP_ISRC2 masks further interrupts. */
3285 status = CSR_READ_4(sc, B0_Y2_SP_ISRC2);
3286 if (status == 0 || status == 0xffffffff || sc->msk_suspended != 0 ||
3287 (status & sc->msk_intrmask) == 0) {
3288 CSR_WRITE_4(sc, B0_Y2_SP_ICR, 2);
3289 return;
3290 }
3291
3292 sc_if0 = sc->msk_if[MSK_PORT_A];
3293 sc_if1 = sc->msk_if[MSK_PORT_B];
3294 ifp0 = ifp1 = NULL;
3295 if (sc_if0 != NULL)
3296 ifp0 = sc_if0->msk_ifp;
3297 if (sc_if1 != NULL)
3298 ifp1 = sc_if1->msk_ifp;
3299
3300 if ((status & Y2_IS_IRQ_PHY1) != 0 && sc_if0 != NULL)
3301 msk_intr_phy(sc_if0);
3302 if ((status & Y2_IS_IRQ_PHY2) != 0 && sc_if1 != NULL)
3303 msk_intr_phy(sc_if1);
3304 if ((status & Y2_IS_IRQ_MAC1) != 0 && sc_if0 != NULL)
3305 msk_intr_gmac(sc_if0);
3306 if ((status & Y2_IS_IRQ_MAC2) != 0 && sc_if1 != NULL)
3307 msk_intr_gmac(sc_if1);
3308 if ((status & (Y2_IS_CHK_RX1 | Y2_IS_CHK_RX2)) != 0) {
3309 device_printf(sc->msk_dev, "Rx descriptor error\n");
3310 sc->msk_intrmask &= ~(Y2_IS_CHK_RX1 | Y2_IS_CHK_RX2);
3311 CSR_WRITE_4(sc, B0_IMSK, sc->msk_intrmask);
3312 CSR_READ_4(sc, B0_IMSK);
3313 }
3314 if ((status & (Y2_IS_CHK_TXA1 | Y2_IS_CHK_TXA2)) != 0) {
3315 device_printf(sc->msk_dev, "Tx descriptor error\n");
3316 sc->msk_intrmask &= ~(Y2_IS_CHK_TXA1 | Y2_IS_CHK_TXA2);
3317 CSR_WRITE_4(sc, B0_IMSK, sc->msk_intrmask);
3318 CSR_READ_4(sc, B0_IMSK);
3319 }
3320 if ((status & Y2_IS_HW_ERR) != 0)
3321 mskc_intr_hwerr(sc);
3322
3323 while (mskc_handle_events(sc) != 0)
3324 ;
3325 if ((status & Y2_IS_STAT_BMU) != 0)
3326 CSR_WRITE_4(sc, STAT_CTRL, SC_STAT_CLR_IRQ);
3327
3328 /* Reenable interrupts. */
3329 CSR_WRITE_4(sc, B0_Y2_SP_ICR, 2);
3330
3331 if (ifp0 != NULL && (ifp0->if_flags & IFF_RUNNING) != 0 &&
3332 !ifq_is_empty(&ifp0->if_snd))
3333 ifp0->if_start(ifp0);
3334 if (ifp1 != NULL && (ifp1->if_flags & IFF_RUNNING) != 0 &&
3335 !ifq_is_empty(&ifp1->if_snd))
3336 ifp1->if_start(ifp1);
3337 }
3338
3339 static void
3340 msk_init(void *xsc)
3341 {
3342 struct msk_if_softc *sc_if = xsc;
3343 struct msk_softc *sc = sc_if->msk_softc;
3344 struct ifnet *ifp = sc_if->msk_ifp;
3345 struct mii_data *mii;
3346 uint16_t eaddr[ETHER_ADDR_LEN / 2];
3347 uint16_t gmac;
3348 int error, i;
3349
3350 ASSERT_SERIALIZED(ifp->if_serializer);
3351
3352 mii = device_get_softc(sc_if->msk_miibus);
3353
3354 error = 0;
3355 /* Cancel pending I/O and free all Rx/Tx buffers. */
3356 msk_stop(sc_if);
3357
3358 sc_if->msk_framesize = ifp->if_mtu + ETHER_HDR_LEN + EVL_ENCAPLEN;
3359 if (sc_if->msk_framesize > MSK_MAX_FRAMELEN &&
3360 sc_if->msk_softc->msk_hw_id == CHIP_ID_YUKON_EC_U) {
3361 /*
3362 * In Yukon EC Ultra, TSO & checksum offload is not
3363 * supported for jumbo frame.
3364 */
3365 ifp->if_hwassist &= ~MSK_CSUM_FEATURES;
3366 ifp->if_capenable &= ~IFCAP_TXCSUM;
3367 }
3368
3369 /*
3370 * Initialize GMAC first.
3371 * Without this initialization, Rx MAC did not work as expected
3372 * and Rx MAC garbled status LEs and it resulted in out-of-order
3373 * or duplicated frame delivery which in turn showed very poor
3374 * Rx performance.(I had to write a packet analysis code that
3375 * could be embeded in driver to diagnose this issue.)
3376 * I've spent almost 2 months to fix this issue. If I have had
3377 * datasheet for Yukon II I wouldn't have encountered this. :-(
3378 */
3379 gmac = GM_GPCR_SPEED_100 | GM_GPCR_SPEED_1000 | GM_GPCR_DUP_FULL;
3380 GMAC_WRITE_2(sc, sc_if->msk_port, GM_GP_CTRL, gmac);
3381
3382 /* Dummy read the Interrupt Source Register. */
3383 CSR_READ_1(sc, MR_ADDR(sc_if->msk_port, GMAC_IRQ_SRC));
3384
3385 /* Set MIB Clear Counter Mode. */
3386 gmac = GMAC_READ_2(sc, sc_if->msk_port, GM_PHY_ADDR);
3387 GMAC_WRITE_2(sc, sc_if->msk_port, GM_PHY_ADDR, gmac | GM_PAR_MIB_CLR);
3388 /* Read all MIB Counters with Clear Mode set. */
3389 for (i = 0; i < GM_MIB_CNT_SIZE; i++)
3390 GMAC_READ_2(sc, sc_if->msk_port, GM_MIB_CNT_BASE + 8 * i);
3391 /* Clear MIB Clear Counter Mode. */
3392 gmac &= ~GM_PAR_MIB_CLR;
3393 GMAC_WRITE_2(sc, sc_if->msk_port, GM_PHY_ADDR, gmac);
3394
3395 /* Disable FCS. */
3396 GMAC_WRITE_2(sc, sc_if->msk_port, GM_RX_CTRL, GM_RXCR_CRC_DIS);
3397
3398 /* Setup Transmit Control Register. */
3399 GMAC_WRITE_2(sc, sc_if->msk_port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
3400
3401 /* Setup Transmit Flow Control Register. */
3402 GMAC_WRITE_2(sc, sc_if->msk_port, GM_TX_FLOW_CTRL, 0xffff);
3403
3404 /* Setup Transmit Parameter Register. */
3405 GMAC_WRITE_2(sc, sc_if->msk_port, GM_TX_PARAM,
3406 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) | TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
3407 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) | TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
3408
3409 gmac = DATA_BLIND_VAL(DATA_BLIND_DEF) |
3410 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
3411
3412 if (sc_if->msk_framesize > MSK_MAX_FRAMELEN)
3413 gmac |= GM_SMOD_JUMBO_ENA;
3414 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SERIAL_MODE, gmac);
3415
3416 /* Set station address. */
3417 bcopy(IF_LLADDR(ifp), eaddr, ETHER_ADDR_LEN);
3418 for (i = 0; i < ETHER_ADDR_LEN /2; i++)
3419 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SRC_ADDR_1L + i * 4,
3420 eaddr[i]);
3421 for (i = 0; i < ETHER_ADDR_LEN /2; i++)
3422 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SRC_ADDR_2L + i * 4,
3423 eaddr[i]);
3424
3425 /* Disable interrupts for counter overflows. */
3426 GMAC_WRITE_2(sc, sc_if->msk_port, GM_TX_IRQ_MSK, 0);
3427 GMAC_WRITE_2(sc, sc_if->msk_port, GM_RX_IRQ_MSK, 0);
3428 GMAC_WRITE_2(sc, sc_if->msk_port, GM_TR_IRQ_MSK, 0);
3429
3430 /* Configure Rx MAC FIFO. */
3431 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), GMF_RST_SET);
3432 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), GMF_RST_CLR);
3433 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T),
3434 GMF_OPER_ON | GMF_RX_F_FL_ON);
3435
3436 /* Set promiscuous mode. */
3437 msk_setpromisc(sc_if);
3438
3439 /* Set multicast filter. */
3440 msk_setmulti(sc_if);
3441
3442 /* Flush Rx MAC FIFO on any flow control or error. */
3443 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_FL_MSK),
3444 GMR_FS_ANY_ERR);
3445
3446 /* Set Rx FIFO flush threshold to 64 bytes. */
3447 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_FL_THR),
3448 RX_GMF_FL_THR_DEF);
3449
3450 /* Configure Tx MAC FIFO. */
3451 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), GMF_RST_SET);
3452 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), GMF_RST_CLR);
3453 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), GMF_OPER_ON);
3454
3455 /* Configure hardware VLAN tag insertion/stripping. */
3456 msk_setvlan(sc_if, ifp);
3457
3458 if (sc->msk_hw_id == CHIP_ID_YUKON_EC_U) {
3459 /* Set Rx Pause threshould. */
3460 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, RX_GMF_LP_THR),
3461 MSK_ECU_LLPP);
3462 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, RX_GMF_UP_THR),
3463 MSK_ECU_ULPP);
3464 if (sc_if->msk_framesize > MSK_MAX_FRAMELEN) {
3465 /*
3466 * Set Tx GMAC FIFO Almost Empty Threshold.
3467 */
3468 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_AE_THR),
3469 MSK_ECU_JUMBO_WM << 16 | MSK_ECU_AE_THR);
3470 /* Disable Store & Forward mode for Tx. */
3471 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T),
3472 TX_JUMBO_ENA | TX_STFW_DIS);
3473 } else {
3474 /* Enable Store & Forward mode for Tx. */
3475 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T),
3476 TX_JUMBO_DIS | TX_STFW_ENA);
3477 }
3478 }
3479
3480 /*
3481 * Disable Force Sync bit and Alloc bit in Tx RAM interface
3482 * arbiter as we don't use Sync Tx queue.
3483 */
3484 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, TXA_CTRL),
3485 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
3486 /* Enable the RAM Interface Arbiter. */
3487 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, TXA_CTRL), TXA_ENA_ARB);
3488
3489 /* Setup RAM buffer. */
3490 msk_set_rambuffer(sc_if);
3491
3492 /* Disable Tx sync Queue. */
3493 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txsq, RB_CTRL), RB_RST_SET);
3494
3495 /* Setup Tx Queue Bus Memory Interface. */
3496 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_CLR_RESET);
3497 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_OPER_INIT);
3498 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_FIFO_OP_ON);
3499 CSR_WRITE_2(sc, Q_ADDR(sc_if->msk_txq, Q_WM), MSK_BMU_TX_WM);
3500 if (sc->msk_hw_id == CHIP_ID_YUKON_EC_U &&
3501 sc->msk_hw_rev == CHIP_REV_YU_EC_U_A0) {
3502 /* Fix for Yukon-EC Ultra: set BMU FIFO level */
3503 CSR_WRITE_2(sc, Q_ADDR(sc_if->msk_txq, Q_AL), MSK_ECU_TXFF_LEV);
3504 }
3505
3506 /* Setup Rx Queue Bus Memory Interface. */
3507 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), BMU_CLR_RESET);
3508 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), BMU_OPER_INIT);
3509 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), BMU_FIFO_OP_ON);
3510 CSR_WRITE_2(sc, Q_ADDR(sc_if->msk_rxq, Q_WM), MSK_BMU_RX_WM);
3511 if (sc->msk_hw_id == CHIP_ID_YUKON_EC_U &&
3512 sc->msk_hw_rev >= CHIP_REV_YU_EC_U_A1) {
3513 /* MAC Rx RAM Read is controlled by hardware. */
3514 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_F), F_M_RX_RAM_DIS);
3515 }
3516
3517 msk_set_prefetch(sc, sc_if->msk_txq,
3518 sc_if->msk_rdata.msk_tx_ring_paddr, MSK_TX_RING_CNT - 1);
3519 msk_init_tx_ring(sc_if);
3520
3521 /* Disable Rx checksum offload and RSS hash. */
3522 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR),
3523 BMU_DIS_RX_CHKSUM | BMU_DIS_RX_RSS_HASH);
3524 #ifdef MSK_JUMBO
3525 if (sc_if->msk_framesize > (MCLBYTES - ETHER_HDR_LEN)) {
3526 msk_set_prefetch(sc, sc_if->msk_rxq,
3527 sc_if->msk_rdata.msk_jumbo_rx_ring_paddr,
3528 MSK_JUMBO_RX_RING_CNT - 1);
3529 error = msk_init_jumbo_rx_ring(sc_if);
3530 } else
3531 #endif
3532 {
3533 msk_set_prefetch(sc, sc_if->msk_rxq,
3534 sc_if->msk_rdata.msk_rx_ring_paddr,
3535 MSK_RX_RING_CNT - 1);
3536 error = msk_init_rx_ring(sc_if);
3537 }
3538 if (error != 0) {
3539 device_printf(sc_if->msk_if_dev,
3540 "initialization failed: no memory for Rx buffers\n");
3541 msk_stop(sc_if);
3542 return;
3543 }
3544
3545 /* Configure interrupt handling. */
3546 if (sc_if->msk_port == MSK_PORT_A) {
3547 sc->msk_intrmask |= Y2_IS_PORT_A;
3548 sc->msk_intrhwemask |= Y2_HWE_L1_MASK;
3549 } else {
3550 sc->msk_intrmask |= Y2_IS_PORT_B;
3551 sc->msk_intrhwemask |= Y2_HWE_L2_MASK;
3552 }
3553 CSR_WRITE_4(sc, B0_HWE_IMSK, sc->msk_intrhwemask);
3554 CSR_READ_4(sc, B0_HWE_IMSK);
3555 CSR_WRITE_4(sc, B0_IMSK, sc->msk_intrmask);
3556 CSR_READ_4(sc, B0_IMSK);
3557
3558 sc_if->msk_link = 0;
3559 mii_mediachg(mii);
3560
3561 mskc_set_imtimer(sc);
3562
3563 ifp->if_flags |= IFF_RUNNING;
3564 ifp->if_flags &= ~IFF_OACTIVE;
3565
3566 callout_reset(&sc_if->msk_tick_ch, hz, msk_tick, sc_if);
3567 }
3568
3569 static void
3570 msk_set_rambuffer(struct msk_if_softc *sc_if)
3571 {
3572 struct msk_softc *sc;
3573 int ltpp, utpp;
3574
3575 sc = sc_if->msk_softc;
3576
3577 /* Setup Rx Queue. */
3578 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL), RB_RST_CLR);
3579 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_START),
3580 sc->msk_rxqstart[sc_if->msk_port] / 8);
3581 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_END),
3582 sc->msk_rxqend[sc_if->msk_port] / 8);
3583 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_WP),
3584 sc->msk_rxqstart[sc_if->msk_port] / 8);
3585 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_RP),
3586 sc->msk_rxqstart[sc_if->msk_port] / 8);
3587
3588 utpp = (sc->msk_rxqend[sc_if->msk_port] + 1 -
3589 sc->msk_rxqstart[sc_if->msk_port] - MSK_RB_ULPP) / 8;
3590 ltpp = (sc->msk_rxqend[sc_if->msk_port] + 1 -
3591 sc->msk_rxqstart[sc_if->msk_port] - MSK_RB_LLPP_B) / 8;
3592 if (sc->msk_rxqsize < MSK_MIN_RXQ_SIZE)
3593 ltpp += (MSK_RB_LLPP_B - MSK_RB_LLPP_S) / 8;
3594 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_RX_UTPP), utpp);
3595 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_RX_LTPP), ltpp);
3596 /* Set Rx priority(RB_RX_UTHP/RB_RX_LTHP) thresholds? */
3597
3598 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL), RB_ENA_OP_MD);
3599 CSR_READ_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL));
3600
3601 /* Setup Tx Queue. */
3602 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), RB_RST_CLR);
3603 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_txq, RB_START),
3604 sc->msk_txqstart[sc_if->msk_port] / 8);
3605 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_txq, RB_END),
3606 sc->msk_txqend[sc_if->msk_port] / 8);
3607 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_txq, RB_WP),
3608 sc->msk_txqstart[sc_if->msk_port] / 8);
3609 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_txq, RB_RP),
3610 sc->msk_txqstart[sc_if->msk_port] / 8);
3611 /* Enable Store & Forward for Tx side. */
3612 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), RB_ENA_STFWD);
3613 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), RB_ENA_OP_MD);
3614 CSR_READ_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL));
3615 }
3616
3617 static void
3618 msk_set_prefetch(struct msk_softc *sc, int qaddr, bus_addr_t addr,
3619 uint32_t count)
3620 {
3621
3622 /* Reset the prefetch unit. */
3623 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_CTRL_REG),
3624 PREF_UNIT_RST_SET);
3625 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_CTRL_REG),
3626 PREF_UNIT_RST_CLR);
3627 /* Set LE base address. */
3628 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_ADDR_LOW_REG),
3629 MSK_ADDR_LO(addr));
3630 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_ADDR_HI_REG),
3631 MSK_ADDR_HI(addr));
3632 /* Set the list last index. */
3633 CSR_WRITE_2(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_LAST_IDX_REG),
3634 count);
3635 /* Turn on prefetch unit. */
3636 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_CTRL_REG),
3637 PREF_UNIT_OP_ON);
3638 /* Dummy read to ensure write. */
3639 CSR_READ_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_CTRL_REG));
3640 }
3641
3642 static void
3643 msk_stop(struct msk_if_softc *sc_if)
3644 {
3645 struct msk_softc *sc = sc_if->msk_softc;
3646 struct ifnet *ifp = sc_if->msk_ifp;
3647 struct msk_txdesc *txd;
3648 struct msk_rxdesc *rxd;
3649 #ifdef MSK_JUMBO
3650 struct msk_rxdesc *jrxd;
3651 #endif
3652 uint32_t val;
3653 int i;
3654
3655 ASSERT_SERIALIZED(ifp->if_serializer);
3656
3657 callout_stop(&sc_if->msk_tick_ch);
3658 ifp->if_timer = 0;
3659
3660 /* Disable interrupts. */
3661 if (sc_if->msk_port == MSK_PORT_A) {
3662 sc->msk_intrmask &= ~Y2_IS_PORT_A;
3663 sc->msk_intrhwemask &= ~Y2_HWE_L1_MASK;
3664 } else {
3665 sc->msk_intrmask &= ~Y2_IS_PORT_B;
3666 sc->msk_intrhwemask &= ~Y2_HWE_L2_MASK;
3667 }
3668 CSR_WRITE_4(sc, B0_HWE_IMSK, sc->msk_intrhwemask);
3669 CSR_READ_4(sc, B0_HWE_IMSK);
3670 CSR_WRITE_4(sc, B0_IMSK, sc->msk_intrmask);
3671 CSR_READ_4(sc, B0_IMSK);
3672
3673 /* Disable Tx/Rx MAC. */
3674 val = GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL);
3675 val &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
3676 GMAC_WRITE_2(sc, sc_if->msk_port, GM_GP_CTRL, val);
3677 /* Read again to ensure writing. */
3678 GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL);
3679
3680 /* Stop Tx BMU. */
3681 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_STOP);
3682 val = CSR_READ_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR));
3683 for (i = 0; i < MSK_TIMEOUT; i++) {
3684 if ((val & (BMU_STOP | BMU_IDLE)) == 0) {
3685 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR),
3686 BMU_STOP);
3687 CSR_READ_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR));
3688 } else
3689 break;
3690 DELAY(1);
3691 }
3692 if (i == MSK_TIMEOUT)
3693 device_printf(sc_if->msk_if_dev, "Tx BMU stop failed\n");
3694 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL),
3695 RB_RST_SET | RB_DIS_OP_MD);
3696
3697 /* Disable all GMAC interrupt. */
3698 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, GMAC_IRQ_MSK), 0);
3699 /* Disable PHY interrupt. */
3700 msk_phy_writereg(sc_if, PHY_ADDR_MARV, PHY_MARV_INT_MASK, 0);
3701
3702 /* Disable the RAM Interface Arbiter. */
3703 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, TXA_CTRL), TXA_DIS_ARB);
3704
3705 /* Reset the PCI FIFO of the async Tx queue */
3706 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR),
3707 BMU_RST_SET | BMU_FIFO_RST);
3708
3709 /* Reset the Tx prefetch units. */
3710 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(sc_if->msk_txq, PREF_UNIT_CTRL_REG),
3711 PREF_UNIT_RST_SET);
3712
3713 /* Reset the RAM Buffer async Tx queue. */
3714 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), RB_RST_SET);
3715
3716 /* Reset Tx MAC FIFO. */
3717 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), GMF_RST_SET);
3718 /* Set Pause Off. */
3719 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), GMC_PAUSE_OFF);
3720
3721 /*
3722 * The Rx Stop command will not work for Yukon-2 if the BMU does not
3723 * reach the end of packet and since we can't make sure that we have
3724 * incoming data, we must reset the BMU while it is not during a DMA
3725 * transfer. Since it is possible that the Rx path is still active,
3726 * the Rx RAM buffer will be stopped first, so any possible incoming
3727 * data will not trigger a DMA. After the RAM buffer is stopped, the
3728 * BMU is polled until any DMA in progress is ended and only then it
3729 * will be reset.
3730 */
3731
3732 /* Disable the RAM Buffer receive queue. */
3733 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL), RB_DIS_OP_MD);
3734 for (i = 0; i < MSK_TIMEOUT; i++) {
3735 if (CSR_READ_1(sc, RB_ADDR(sc_if->msk_rxq, Q_RSL)) ==
3736 CSR_READ_1(sc, RB_ADDR(sc_if->msk_rxq, Q_RL)))
3737 break;
3738 DELAY(1);
3739 }
3740 if (i == MSK_TIMEOUT)
3741 device_printf(sc_if->msk_if_dev, "Rx BMU stop failed\n");
3742 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR),
3743 BMU_RST_SET | BMU_FIFO_RST);
3744 /* Reset the Rx prefetch unit. */
3745 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(sc_if->msk_rxq, PREF_UNIT_CTRL_REG),
3746 PREF_UNIT_RST_SET);
3747 /* Reset the RAM Buffer receive queue. */
3748 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL), RB_RST_SET);
3749 /* Reset Rx MAC FIFO. */
3750 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), GMF_RST_SET);
3751
3752 /* Free Rx and Tx mbufs still in the queues. */
3753 for (i = 0; i < MSK_RX_RING_CNT; i++) {
3754 rxd = &sc_if->msk_cdata.msk_rxdesc[i];
3755 if (rxd->rx_m != NULL) {
3756 bus_dmamap_sync(sc_if->msk_cdata.msk_rx_tag,
3757 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD);
3758 bus_dmamap_unload(sc_if->msk_cdata.msk_rx_tag,
3759 rxd->rx_dmamap);
3760 m_freem(rxd->rx_m);
3761 rxd->rx_m = NULL;
3762 }
3763 }
3764 #ifdef MSK_JUMBO
3765 for (i = 0; i < MSK_JUMBO_RX_RING_CNT; i++) {
3766 jrxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[i];
3767 if (jrxd->rx_m != NULL) {
3768 bus_dmamap_sync(sc_if->msk_cdata.msk_jumbo_rx_tag,
3769 jrxd->rx_dmamap, BUS_DMASYNC_POSTREAD);
3770 bus_dmamap_unload(sc_if->msk_cdata.msk_jumbo_rx_tag,
3771 jrxd->rx_dmamap);
3772 m_freem(jrxd->rx_m);
3773 jrxd->rx_m = NULL;
3774 }
3775 }
3776 #endif
3777 for (i = 0; i < MSK_TX_RING_CNT; i++) {
3778 txd = &sc_if->msk_cdata.msk_txdesc[i];
3779 if (txd->tx_m != NULL) {
3780 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_tag,
3781 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE);
3782 bus_dmamap_unload(sc_if->msk_cdata.msk_tx_tag,
3783 txd->tx_dmamap);
3784 m_freem(txd->tx_m);
3785 txd->tx_m = NULL;
3786 }
3787 }
3788
3789 /*
3790 * Mark the interface down.
3791 */
3792 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
3793 sc_if->msk_link = 0;
3794 }
3795
3796 static int
3797 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high)
3798 {
3799 int error, value;
3800
3801 if (!arg1)
3802 return (EINVAL);
3803 value = *(int *)arg1;
3804 error = sysctl_handle_int(oidp, &value, 0, req);
3805 if (error || !req->newptr)
3806 return (error);
3807 if (value < low || value > high)
3808 return (EINVAL);
3809 *(int *)arg1 = value;
3810
3811 return (0);
3812 }
3813
3814 static int
3815 mskc_sysctl_proc_limit(SYSCTL_HANDLER_ARGS)
3816 {
3817 return sysctl_int_range(oidp, arg1, arg2, req,
3818 MSK_PROC_MIN, MSK_PROC_MAX);
3819 }
3820
3821 static int
3822 mskc_sysctl_intr_rate(SYSCTL_HANDLER_ARGS)
3823 {
3824 struct msk_softc *sc = arg1;
3825 struct lwkt_serialize *serializer = &sc->msk_serializer;
3826 int error = 0, v;
3827
3828 lwkt_serialize_enter(serializer);
3829
3830 v = sc->msk_intr_rate;
3831 error = sysctl_handle_int(oidp, &v, 0, req);
3832 if (error || req->newptr == NULL)
3833 goto back;
3834 if (v < 0) {
3835 error = EINVAL;
3836 goto back;
3837 }
3838
3839 if (sc->msk_intr_rate != v) {
3840 int flag = 0, i;
3841
3842 sc->msk_intr_rate = v;
3843 for (i = 0; i < 2; ++i) {
3844 if (sc->msk_if[i] != NULL) {
3845 flag |= sc->msk_if[i]->
3846 arpcom.ac_if.if_flags & IFF_RUNNING;
3847 }
3848 }
3849 if (flag)
3850 mskc_set_imtimer(sc);
3851 }
3852 back:
3853 lwkt_serialize_exit(serializer);
3854 return error;
3855 }
3856
3857 static int
3858 msk_dmamem_create(device_t dev, bus_size_t size, bus_dma_tag_t *dtag,
3859 void **addr, bus_addr_t *paddr, bus_dmamap_t *dmap)
3860 {
3861 struct msk_if_softc *sc_if = device_get_softc(dev);
3862 struct msk_dmamap_arg ctx;
3863 bus_dma_segment_t seg;
3864 int error;
3865
3866 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,
3867 MSK_RING_ALIGN, 0,
3868 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3869 NULL, NULL,
3870 size, 1, BUS_SPACE_MAXSIZE_32BIT,
3871 0, dtag);
3872 if (error) {
3873 device_printf(dev, "can't create DMA tag\n");
3874 return error;
3875 }
3876
3877 error = bus_dmamem_alloc(*dtag, addr, BUS_DMA_WAITOK | BUS_DMA_ZERO,
3878 dmap);
3879 if (error) {
3880 device_printf(dev, "can't allocate DMA mem\n");
3881 bus_dma_tag_destroy(*dtag);
3882 *dtag = NULL;
3883 return error;
3884 }
3885
3886 bzero(&ctx, sizeof(ctx));
3887 ctx.nseg = 1;
3888 ctx.segs = &seg;
3889 error = bus_dmamap_load(*dtag, *dmap, *addr, size,
3890 msk_dmamap_cb, &ctx, BUS_DMA_WAITOK);
3891 if (error) {
3892 device_printf(dev, "can't load DMA mem\n");
3893 bus_dmamem_free(*dtag, *addr, *dmap);
3894 bus_dma_tag_destroy(*dtag);
3895 *dtag = NULL;
3896 return error;
3897 }
3898 *paddr = seg.ds_addr;
3899 return 0;
3900 }
3901
3902 static void
3903 msk_dmamem_destroy(bus_dma_tag_t dtag, void *addr, bus_dmamap_t dmap)
3904 {
3905 if (dtag != NULL) {
3906 bus_dmamap_unload(dtag, dmap);
3907 bus_dmamem_free(dtag, addr, dmap);
3908 bus_dma_tag_destroy(dtag);
3909 }
3910 }
3911
3912 static void
3913 mskc_set_imtimer(struct msk_softc *sc)
3914 {
3915 if (sc->msk_intr_rate > 0) {
3916 /*
3917 * XXX myk(4) seems to use 125MHz for EC/FE/XL
3918 * and 78.125MHz for rest of chip types
3919 */
3920 CSR_WRITE_4(sc, B2_IRQM_INI,
3921 MSK_USECS(sc, 1000000 / sc->msk_intr_rate));
3922 CSR_WRITE_4(sc, B2_IRQM_MSK, sc->msk_intrmask);
3923 CSR_WRITE_4(sc, B2_IRQM_CTRL, TIM_START);
3924 kprintf("%s start imtimer\n", __func__);
3925 } else {
3926 CSR_WRITE_4(sc, B2_IRQM_CTRL, TIM_STOP);
3927 kprintf("%s stop imtimer\n", __func__);
3928 }
3929 }
Port diff from OpenBSD to DragonFly