sys/dev/netif/re/if_rereg.h

   1 /*
   2  * Copyright (c) 2004
   3  *      Joerg Sonnenberger <joerg@bec.de>.  All rights reserved.
   4  *
   5  * Copyright (c) 1997, 1998-2003
   6  *      Bill Paul <wpaul@ctr.columbia.edu>.  All rights reserved.
   7  *
   8  * Redistribution and use in source and binary forms, with or without
   9  * modification, are permitted provided that the following conditions
  10  * are met:
  11  * 1. Redistributions of source code must retain the above copyright
  12  *    notice, this list of conditions and the following disclaimer.
  13  * 2. Redistributions in binary form must reproduce the above copyright
  14  *    notice, this list of conditions and the following disclaimer in the
  15  *    documentation and/or other materials provided with the distribution.
  16  * 3. All advertising materials mentioning features or use of this software
  17  *    must display the following acknowledgement:
  18  *      This product includes software developed by Bill Paul.
  19  * 4. Neither the name of the author nor the names of any co-contributors
  20  *    may be used to endorse or promote products derived from this software
  21  *    without specific prior written permission.
  22  *
  23  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
  24  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  25  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  26  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
  27  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  28  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  29  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  30  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  31  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  32  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  33  * THE POSSIBILITY OF SUCH DAMAGE.
  34  *
  35  * $FreeBSD: src/sys/pci/if_rlreg.h,v 1.42 2004/05/24 19:39:23 jhb Exp $
  36  * $DragonFly: src/sys/dev/netif/re/if_rereg.h,v 1.9 2008/04/27 15:10:37 sephe Exp $
  37  */
  38
  39 /*
  40  * RealTek 8129/8139 register offsets
  41  */
  42 #define RE_IDR0         0x0000          /* ID register 0 (station addr) */
  43 #define RE_IDR1         0x0001          /* Must use 32-bit accesses (?) */
  44 #define RE_IDR2         0x0002
  45 #define RE_IDR3         0x0003
  46 #define RE_IDR4         0x0004
  47 #define RE_IDR5         0x0005
  48                                         /* 0006-0007 reserved */
  49 #define RE_MAR0         0x0008          /* Multicast hash table */
  50 #define RE_MAR1         0x0009
  51 #define RE_MAR2         0x000A
  52 #define RE_MAR3         0x000B
  53 #define RE_MAR4         0x000C
  54 #define RE_MAR5         0x000D
  55 #define RE_MAR6         0x000E
  56 #define RE_MAR7         0x000F
  57
  58 #define RE_RXADDR               0x0030  /* RX ring start address */
  59 #define RE_RX_EARLY_BYTES       0x0034  /* RX early byte count */
  60 #define RE_RX_EARLY_STAT        0x0036  /* RX early status */
  61 #define RE_COMMAND      0x0037          /* command register */
  62 #define RE_CURRXADDR    0x0038          /* current address of packet read */
  63 #define RE_CURRXBUF     0x003A          /* current RX buffer address */
  64 #define RE_IMR          0x003C          /* interrupt mask register */
  65 #define RE_ISR          0x003E          /* interrupt status register */
  66 #define RE_TXCFG        0x0040          /* transmit config */
  67 #define RE_RXCFG        0x0044          /* receive config */
  68 #define RE_TIMERCNT     0x0048          /* timer count register */
  69 #define RE_MISSEDPKT    0x004C          /* missed packet counter */
  70 #define RE_EECMD        0x0050          /* EEPROM command register */
  71 #define RE_CFG0         0x0051          /* config register #0 */
  72 #define RE_CFG1         0x0052          /* config register #1 */
  73                                         /* 0053-0057 reserved */
  74 #define RE_MEDIASTAT    0x0058          /* media status register (8139) */
  75                                         /* 0059-005A reserved */
  76 #define RE_MII          0x005A          /* 8129 chip only */
  77 #define RE_HALTCLK      0x005B
  78 #define RE_MULTIINTR    0x005C          /* multiple interrupt */
  79 #define RE_PCIREV       0x005E          /* PCI revision value */
  80                                         /* 005F reserved */
  81 #define RE_TXSTAT_ALL   0x0060          /* TX status of all descriptors */
  82
  83 /* Direct PHY access registers only available on 8139 */
  84 #define RE_BMCR         0x0062          /* PHY basic mode control */
  85 #define RE_BMSR         0x0064          /* PHY basic mode status */
  86 #define RE_ANAR         0x0066          /* PHY autoneg advert */
  87 #define RE_LPAR         0x0068          /* PHY link partner ability */
  88 #define RE_ANER         0x006A          /* PHY autoneg expansion */
  89
  90 #define RE_DISCCNT      0x006C          /* disconnect counter */
  91 #define RE_FALSECAR     0x006E          /* false carrier counter */
  92 #define RE_NWAYTST      0x0070          /* NWAY test register */
  93 #define RE_RX_ER        0x0072          /* RX_ER counter */
  94 #define RE_CSCFG        0x0074          /* CS configuration register */
  95
  96 /*
  97  * When operating in special C+ mode, some of the registers in an
  98  * 8139C+ chip have different definitions. These are also used for
  99  * the 8169 gigE chip.
 100  */
 101 #define RE_DUMPSTATS_LO         0x0010  /* counter dump command register */
 102 #define RE_DUMPSTATS_HI         0x0014  /* counter dump command register */
 103 #define RE_TXLIST_ADDR_LO       0x0020  /* 64 bits, 256 byte alignment */
 104 #define RE_TXLIST_ADDR_HI       0x0024  /* 64 bits, 256 byte alignment */
 105 #define RE_TXLIST_ADDR_HPRIO_LO 0x0028  /* 64 bits, 256 byte alignment */
 106 #define RE_TXLIST_ADDR_HPRIO_HI 0x002C  /* 64 bits, 256 byte alignment */
 107 #define RE_CFG2                 0x0053
 108 #define RE_TIMERINT             0x0054  /* interrupt on timer expire */
 109 #define RE_TXSTART              0x00D9  /* 8 bits */
 110 #define RE_CPLUS_CMD            0x00E0  /* 16 bits */
 111 #define RE_RXLIST_ADDR_LO       0x00E4  /* 64 bits, 256 byte alignment */
 112 #define RE_RXLIST_ADDR_HI       0x00E8  /* 64 bits, 256 byte alignment */
 113 #define RE_EARLY_TX_THRESH      0x00EC  /* 8 bits */
 114
 115 /*
 116  * Registers specific to the 8169 gigE chip
 117  */
 118 #define RE_TIMERINT_8169        0x0058  /* different offset than 8139 */
 119 #define RE_PHYAR                0x0060
 120 #define RE_TBICSR               0x0064
 121 #define RE_TBI_ANAR             0x0068
 122 #define RE_TBI_LPAR             0x006A
 123 #define RE_GMEDIASTAT           0x006C  /* 8 bits */
 124 #define RE_MAXRXPKTLEN          0x00DA  /* 16 bits, chip multiplies by 8 */
 125 #define RE_GTXSTART             0x0038  /* 16 bits */
 126
 127 /*
 128  * TX config register bits
 129  */
 130 #define RE_TXCFG_CLRABRT        0x00000001      /* retransmit aborted pkt */
 131 #define RE_TXCFG_MAXDMA         0x00000700      /* max DMA burst size */
 132 #define RE_TXCFG_CRCAPPEND      0x00010000      /* CRC append (0 = yes) */
 133 #define RE_TXCFG_LOOPBKTST      0x00060000      /* loopback test */
 134 #define RE_TXCFG_IFG2           0x00080000      /* 8169 only */
 135 #define RE_TXCFG_IFG            0x03000000      /* interframe gap */
 136 #define RE_TXCFG_HWREV          0x7CC00000
 137
 138 #define RE_LOOPTEST_OFF         0x00000000
 139 #define RE_LOOPTEST_ON          0x00020000
 140 #define RE_LOOPTEST_ON_CPLUS    0x00060000
 141
 142 #define RE_HWREV_8169           0x00000000
 143 #define RE_HWREV_8110S          0x00800000
 144 #define RE_HWREV_8169S          0x04000000
 145 #define RE_HWREV_8169_8110SB    0x10000000
 146 #define RE_HWREV_8169_8110SC    0x18000000
 147 #define RE_HWREV_8168_SPIN1     0x30000000
 148 #define RE_HWREV_8100E          0x30800000
 149 #define RE_HWREV_8101E          0x34000000
 150 #define RE_HWREV_8168_SPIN2     0x38000000
 151 #define RE_HWREV_8168_SPIN3     0x38400000
 152 #define RE_HWREV_8168C          0x3c000000
 153 #define RE_HWREV_8139CPLUS      0x74800000
 154
 155 #define RE_TXDMA_16BYTES        0x00000000
 156 #define RE_TXDMA_32BYTES        0x00000100
 157 #define RE_TXDMA_64BYTES        0x00000200
 158 #define RE_TXDMA_128BYTES       0x00000300
 159 #define RE_TXDMA_256BYTES       0x00000400
 160 #define RE_TXDMA_512BYTES       0x00000500
 161 #define RE_TXDMA_1024BYTES      0x00000600
 162 #define RE_TXDMA_2048BYTES      0x00000700
 163
 164 /*
 165  * Transmit descriptor status register bits.
 166  */
 167 #define RE_TXSTAT_LENMASK       0x00001FFF
 168 #define RE_TXSTAT_OWN           0x00002000
 169 #define RE_TXSTAT_TX_UNDERRUN   0x00004000
 170 #define RE_TXSTAT_TX_OK         0x00008000
 171 #define RE_TXSTAT_EARLY_THRESH  0x003F0000
 172 #define RE_TXSTAT_COLLCNT       0x0F000000
 173 #define RE_TXSTAT_CARR_HBEAT    0x10000000
 174 #define RE_TXSTAT_OUTOFWIN      0x20000000
 175 #define RE_TXSTAT_TXABRT        0x40000000
 176 #define RE_TXSTAT_CARRLOSS      0x80000000
 177
 178 /*
 179  * Interrupt status register bits.
 180  */
 181 #define RE_ISR_RX_OK            0x0001
 182 #define RE_ISR_RX_ERR           0x0002
 183 #define RE_ISR_TX_OK            0x0004
 184 #define RE_ISR_TX_ERR           0x0008
 185 #define RE_ISR_RX_OVERRUN       0x0010
 186 #define RE_ISR_PKT_UNDERRUN     0x0020
 187 #define RE_ISR_LINKCHG          0x0020  /* 8169 only */
 188 #define RE_ISR_FIFO_OFLOW       0x0040  /* 8139 only */
 189 #define RE_ISR_TX_DESC_UNAVAIL  0x0080  /* C+ only */
 190 #define RE_ISR_SWI              0x0100  /* C+ only */
 191 #define RE_ISR_CABLE_LEN_CHGD   0x2000
 192 #define RE_ISR_PCS_TIMEOUT      0x4000  /* 8129 only */
 193 #define RE_ISR_TIMEOUT_EXPIRED  0x4000
 194 #define RE_ISR_SYSTEM_ERR       0x8000
 195
 196 #define RE_INTRS        \
 197         (RE_ISR_RX_OK|RE_ISR_RX_ERR|RE_ISR_TX_ERR|                      \
 198         RE_ISR_RX_OVERRUN|RE_ISR_PKT_UNDERRUN|RE_ISR_FIFO_OFLOW|        \
 199         RE_ISR_PCS_TIMEOUT|RE_ISR_SYSTEM_ERR|RE_ISR_TIMEOUT_EXPIRED)
 200
 201 #ifdef RE_DIAG
 202 #define RE_INTRS_DIAG   \
 203         (RE_ISR_TX_OK|RE_ISR_RX_OK|RE_ISR_RX_ERR|RE_ISR_TX_ERR|         \
 204         RE_ISR_RX_OVERRUN|RE_ISR_PKT_UNDERRUN|RE_ISR_FIFO_OFLOW|        \
 205         RE_ISR_PCS_TIMEOUT|RE_ISR_SYSTEM_ERR)
 206 #endif
 207
 208 /*
 209  * Media status register. (8139 only)
 210  */
 211 #define RE_MEDIASTAT_RXPAUSE    0x01
 212 #define RE_MEDIASTAT_TXPAUSE    0x02
 213 #define RE_MEDIASTAT_LINK       0x04
 214 #define RE_MEDIASTAT_SPEED10    0x08
 215 #define RE_MEDIASTAT_RXFLOWCTL  0x40    /* duplex mode */
 216 #define RE_MEDIASTAT_TXFLOWCTL  0x80    /* duplex mode */
 217
 218 /*
 219  * Receive config register.
 220  */
 221 #define RE_RXCFG_RX_ALLPHYS     0x00000001      /* accept all nodes */
 222 #define RE_RXCFG_RX_INDIV       0x00000002      /* match filter */
 223 #define RE_RXCFG_RX_MULTI       0x00000004      /* accept all multicast */
 224 #define RE_RXCFG_RX_BROAD       0x00000008      /* accept all broadcast */
 225 #define RE_RXCFG_RX_RUNT        0x00000010
 226 #define RE_RXCFG_RX_ERRPKT      0x00000020
 227 #define RE_RXCFG_WRAP           0x00000080
 228 #define RE_RXCFG_MAXDMA         0x00000700
 229 #define RE_RXCFG_BUFSZ          0x00001800
 230 #define RE_RXCFG_FIFOTHRESH     0x0000E000
 231 #define RE_RXCFG_EARLYTHRESH    0x07000000
 232
 233 #define RE_RXDMA_16BYTES        0x00000000
 234 #define RE_RXDMA_32BYTES        0x00000100
 235 #define RE_RXDMA_64BYTES        0x00000200
 236 #define RE_RXDMA_128BYTES       0x00000300
 237 #define RE_RXDMA_256BYTES       0x00000400
 238 #define RE_RXDMA_512BYTES       0x00000500
 239 #define RE_RXDMA_1024BYTES      0x00000600
 240 #define RE_RXDMA_UNLIMITED      0x00000700
 241
 242 #define RE_RXBUF_8              0x00000000
 243 #define RE_RXBUF_16             0x00000800
 244 #define RE_RXBUF_32             0x00001000
 245 #define RE_RXBUF_64             0x00001800
 246
 247 #define RE_RXFIFO_16BYTES       0x00000000
 248 #define RE_RXFIFO_32BYTES       0x00002000
 249 #define RE_RXFIFO_64BYTES       0x00004000
 250 #define RE_RXFIFO_128BYTES      0x00006000
 251 #define RE_RXFIFO_256BYTES      0x00008000
 252 #define RE_RXFIFO_512BYTES      0x0000A000
 253 #define RE_RXFIFO_1024BYTES     0x0000C000
 254 #define RE_RXFIFO_NOTHRESH      0x0000E000
 255
 256 /*
 257  * Bits in RX status header (included with RX'ed packet
 258  * in ring buffer).
 259  */
 260 #define RE_RXSTAT_RXOK          0x00000001
 261 #define RE_RXSTAT_ALIGNERR      0x00000002
 262 #define RE_RXSTAT_CRCERR        0x00000004
 263 #define RE_RXSTAT_GIANT         0x00000008
 264 #define RE_RXSTAT_RUNT          0x00000010
 265 #define RE_RXSTAT_BADSYM        0x00000020
 266 #define RE_RXSTAT_BROAD         0x00002000
 267 #define RE_RXSTAT_INDIV         0x00004000
 268 #define RE_RXSTAT_MULTI         0x00008000
 269 #define RE_RXSTAT_LENMASK       0xFFFF0000
 270
 271 #define RE_RXSTAT_UNFINISHED    0xFFF0          /* DMA still in progress */
 272 /*
 273  * Command register.
 274  */
 275 #define RE_CMD_EMPTY_RXBUF      0x0001
 276 #define RE_CMD_TX_ENB           0x0004
 277 #define RE_CMD_RX_ENB           0x0008
 278 #define RE_CMD_RESET            0x0010
 279
 280 /*
 281  * EEPROM control register
 282  */
 283 #define RE_EE_DATAOUT           0x01    /* Data out */
 284 #define RE_EE_DATAIN            0x02    /* Data in */
 285 #define RE_EE_CLK               0x04    /* clock */
 286 #define RE_EE_SEL               0x08    /* chip select */
 287 #define RE_EE_MODE              (0x40|0x80)
 288
 289 #define RE_EEMODE_OFF           0x00
 290 #define RE_EEMODE_AUTOLOAD      0x40
 291 #define RE_EEMODE_PROGRAM       0x80
 292 #define RE_EEMODE_WRITECFG      (0x80|0x40)
 293
 294 /* 9346 EEPROM commands */
 295 #define RE_9346_READ            0x6
 296 #define RE_EECMD_WRITE          0x140
 297 #define RE_EECMD_READ_6BIT      0x180
 298 #define RE_EECMD_READ_8BIT      0x600
 299 #define RE_EECMD_ERASE          0x1c0
 300
 301 #define RE_EE_ID                0x00
 302 #define RE_EE_PCI_VID           0x01
 303 #define RE_EE_PCI_DID           0x02
 304 /* Location of station address inside EEPROM */
 305 #define RE_EE_EADDR             0x07
 306
 307 /*
 308  * Config 0 register
 309  */
 310 #define RE_CFG0_ROM0            0x01
 311 #define RE_CFG0_ROM1            0x02
 312 #define RE_CFG0_ROM2            0x04
 313 #define RE_CFG0_PL0             0x08
 314 #define RE_CFG0_PL1             0x10
 315 #define RE_CFG0_10MBPS          0x20    /* 10 Mbps internal mode */
 316 #define RE_CFG0_PCS             0x40
 317 #define RE_CFG0_SCR             0x80
 318
 319 /*
 320  * Config 1 register
 321  */
 322 #define RE_CFG1_PWRDWN          0x01
 323 #define RE_CFG1_SLEEP           0x02
 324 #define RE_CFG1_IOMAP           0x04
 325 #define RE_CFG1_MEMMAP          0x08
 326 #define RE_CFG1_RSVD            0x10
 327 #define RE_CFG1_DRVLOAD         0x20
 328 #define RE_CFG1_LED0            0x40
 329 #define RE_CFG1_FULLDUPLEX      0x40    /* 8129 only */
 330 #define RE_CFG1_LED1            0x80
 331
 332 /*
 333  * 8139C+ register definitions
 334  */
 335
 336 /* RE_DUMPSTATS_LO register */
 337
 338 #define RE_DUMPSTATS_START      0x00000008
 339
 340 /* Transmit start register */
 341
 342 #define RE_TXSTART_SWI          0x01    /* generate TX interrupt */
 343 #define RE_TXSTART_START        0x40    /* start normal queue transmit */
 344 #define RE_TXSTART_HPRIO_START  0x80    /* start hi prio queue transmit */
 345
 346 /*
 347  * Config 2 register, 8139C+/8169/8169S/8110S only
 348  */
 349 #define RE_CFG2_BUSFREQ         0x07
 350 #define RE_CFG2_BUSWIDTH        0x08
 351 #define RE_CFG2_AUXPWRSTS       0x10
 352
 353 #define RE_BUSFREQ_33MHZ        0x00
 354 #define RE_BUSFREQ_66MHZ        0x01
 355
 356 #define RE_BUSWIDTH_32BITS      0x00
 357 #define RE_BUSWIDTH_64BITS      0x08
 358
 359 /* C+ mode command register */
 360
 361 #define RE_CPLUSCMD_TXENB       0x0001  /* enable C+ transmit mode */
 362 #define RE_CPLUSCMD_RXENB       0x0002  /* enable C+ receive mode */
 363 #define RE_CPLUSCMD_PCI_MRW     0x0008  /* enable PCI multi-read/write */
 364 #define RE_CPLUSCMD_PCI_DAC     0x0010  /* PCI dual-address cycle only */
 365 #define RE_CPLUSCMD_RXCSUM_ENB  0x0020  /* enable RX checksum offload */
 366 #define RE_CPLUSCMD_VLANSTRIP   0x0040  /* enable VLAN tag stripping */
 367
 368 /* C+ early transmit threshold */
 369
 370 #define RE_EARLYTXTHRESH_CNT    0x003F  /* byte count times 8 */
 371
 372 /*
 373  * Gigabit PHY access register (8169 only)
 374  */
 375
 376 #define RE_PHYAR_PHYDATA        0x0000FFFF
 377 #define RE_PHYAR_PHYREG         0x001F0000
 378 #define RE_PHYAR_BUSY           0x80000000
 379
 380 /*
 381  * Gigabit media status (8169 only)
 382  */
 383 #define RE_GMEDIASTAT_FDX       0x01    /* full duplex */
 384 #define RE_GMEDIASTAT_LINK      0x02    /* link up */
 385 #define RE_GMEDIASTAT_10MBPS    0x04    /* 10mps link */
 386 #define RE_GMEDIASTAT_100MBPS   0x08    /* 100mbps link */
 387 #define RE_GMEDIASTAT_1000MBPS  0x10    /* gigE link */
 388 #define RE_GMEDIASTAT_RXFLOW    0x20    /* RX flow control on */
 389 #define RE_GMEDIASTAT_TXFLOW    0x40    /* TX flow control on */
 390 #define RE_GMEDIASTAT_TBI       0x80    /* TBI enabled */
 391
 392 /*
 393  * The RealTek doesn't use a fragment-based descriptor mechanism.
 394  * Instead, there are only four register sets, each or which represents
 395  * one 'descriptor.' Basically, each TX descriptor is just a contiguous
 396  * packet buffer (32-bit aligned!) and we place the buffer addresses in
 397  * the registers so the chip knows where they are.
 398  *
 399  * We can sort of kludge together the same kind of buffer management
 400  * used in previous drivers, but we have to do buffer copies almost all
 401  * the time, so it doesn't really buy us much.
 402  *
 403  * For reception, there's just one large buffer where the chip stores
 404  * all received packets.
 405  */
 406
 407 #define RE_RX_BUF_SZ            RE_RXBUF_64
 408 #define RE_RXBUFLEN             (1 << ((RE_RX_BUF_SZ >> 11) + 13))
 409 #define RE_TX_LIST_CNT          4
 410 #define RE_MIN_FRAMELEN         60
 411 #define RE_TXTHRESH(x)          ((x) << 11)
 412 #define RE_TX_THRESH_INIT       96
 413 #define RE_RX_FIFOTHRESH        RE_RXFIFO_NOTHRESH
 414 #define RE_RX_MAXDMA            RE_RXDMA_UNLIMITED
 415 #define RE_TX_MAXDMA            RE_TXDMA_2048BYTES
 416
 417 #define RE_RXCFG_CONFIG (RE_RX_FIFOTHRESH|RE_RX_MAXDMA|RE_RX_BUF_SZ)
 418 #define RE_TXCFG_CONFIG (RE_TXCFG_IFG|RE_TX_MAXDMA)
 419
 420 #if 0
 421 struct re_mii_frame {
 422         uint8_t                 mii_stdelim;
 423         uint8_t                 mii_opcode;
 424         uint8_t                 mii_phyaddr;
 425         uint8_t                 mii_regaddr;
 426         uint8_t                 mii_turnaround;
 427         uint16_t                mii_data;
 428 };
 429 #endif
 430
 431 /*
 432  * MII constants
 433  */
 434 #define RE_MII_STARTDELIM       0x01
 435 #define RE_MII_READOP           0x02
 436 #define RE_MII_WRITEOP          0x01
 437 #define RE_MII_TURNAROUND       0x02
 438
 439 /*
 440  * The 8139C+ and 8160 gigE chips support descriptor-based TX
 441  * and RX. In fact, they even support TCP large send. Descriptors
 442  * must be allocated in contiguous blocks that are aligned on a
 443  * 256-byte boundary. The rings can hold a maximum of 64 descriptors.
 444  */
 445
 446 /*
 447  * RX/TX descriptor definition. When large send mode is enabled, the
 448  * lower 11 bits of the TX re_cmd word are used to hold the MSS, and
 449  * the checksum offload bits are disabled. The structure layout is
 450  * the same for RX and TX descriptors
 451  */
 452
 453 struct re_desc {
 454         uint32_t                re_cmdstat;
 455         uint32_t                re_vlanctl;
 456         uint32_t                re_bufaddr_lo;
 457         uint32_t                re_bufaddr_hi;
 458 };
 459
 460 #define RE_TDESC_CMD_FRAGLEN    0x0000FFFF
 461 #define RE_TDESC_CMD_TCPCSUM    0x00010000      /* TCP checksum enable */
 462 #define RE_TDESC_CMD_UDPCSUM    0x00020000      /* UDP checksum enable */
 463 #define RE_TDESC_CMD_IPCSUM     0x00040000      /* IP header checksum enable */
 464 #define RE_TDESC_CMD_MSSVAL     0x07FF0000      /* Large send MSS value */
 465 #define RE_TDESC_CMD_LGSEND     0x08000000      /* TCP large send enb */
 466 #define RE_TDESC_CMD_EOF        0x10000000      /* end of frame marker */
 467 #define RE_TDESC_CMD_SOF        0x20000000      /* start of frame marker */
 468 #define RE_TDESC_CMD_EOR        0x40000000      /* end of ring marker */
 469 #define RE_TDESC_CMD_OWN        0x80000000      /* chip owns descriptor */
 470
 471 #define RE_TDESC_VLANCTL_TAG    0x00020000      /* Insert VLAN tag */
 472 #define RE_TDESC_VLANCTL_DATA   0x0000FFFF      /* TAG data */
 473
 474 /*
 475  * Error bits are valid only on the last descriptor of a frame
 476  * (i.e. RE_TDESC_CMD_EOF == 1)
 477  */
 478
 479 #define RE_TDESC_STAT_COLCNT    0x000F0000      /* collision count */
 480 #define RE_TDESC_STAT_EXCESSCOL 0x00100000      /* excessive collisions */
 481 #define RE_TDESC_STAT_LINKFAIL  0x00200000      /* link faulure */
 482 #define RE_TDESC_STAT_OWINCOL   0x00400000      /* out-of-window collision */
 483 #define RE_TDESC_STAT_TXERRSUM  0x00800000      /* transmit error summary */
 484 #define RE_TDESC_STAT_UNDERRUN  0x02000000      /* TX underrun occured */
 485 #define RE_TDESC_STAT_OWN       0x80000000
 486
 487 /*
 488  * RX descriptor cmd/vlan definitions
 489  */
 490
 491 #define RE_RDESC_CMD_EOR        0x40000000
 492 #define RE_RDESC_CMD_OWN        0x80000000
 493 #define RE_RDESC_CMD_BUFLEN     0x00001FFF
 494
 495 #define RE_RDESC_STAT_OWN       0x80000000
 496 #define RE_RDESC_STAT_EOR       0x40000000
 497 #define RE_RDESC_STAT_SOF       0x20000000
 498 #define RE_RDESC_STAT_EOF       0x10000000
 499 #define RE_RDESC_STAT_FRALIGN   0x08000000      /* frame alignment error */
 500 #define RE_RDESC_STAT_MCAST     0x04000000      /* multicast pkt received */
 501 #define RE_RDESC_STAT_UCAST     0x02000000      /* unicast pkt received */
 502 #define RE_RDESC_STAT_BCAST     0x01000000      /* broadcast pkt received */
 503 #define RE_RDESC_STAT_BUFOFLOW  0x00800000      /* out of buffer space */
 504 #define RE_RDESC_STAT_FIFOOFLOW 0x00400000      /* FIFO overrun */
 505 #define RE_RDESC_STAT_GIANT     0x00200000      /* pkt > 4096 bytes */
 506 #define RE_RDESC_STAT_RXERRSUM  0x00100000      /* RX error summary */
 507 #define RE_RDESC_STAT_RUNT      0x00080000      /* runt packet received */
 508 #define RE_RDESC_STAT_CRCERR    0x00040000      /* CRC error */
 509 #define RE_RDESC_STAT_PROTOID   0x00030000      /* Protocol type */
 510 #define RE_RDESC_STAT_IPSUMBAD  0x00008000      /* IP header checksum bad */
 511 #define RE_RDESC_STAT_UDPSUMBAD 0x00004000      /* UDP checksum bad */
 512 #define RE_RDESC_STAT_TCPSUMBAD 0x00002000      /* TCP checksum bad */
 513 #define RE_RDESC_STAT_FRAGLEN   0x00001FFF      /* RX'ed frame/frag len */
 514 #define RE_RDESC_STAT_GFRAGLEN  0x00003FFF      /* RX'ed frame/frag len */
 515
 516 #define RE_RDESC_VLANCTL_TAG    0x00010000      /* VLAN tag available
 517                                                    (re_vlandata valid)*/
 518 #define RE_RDESC_VLANCTL_DATA   0x0000FFFF      /* TAG data */
 519
 520 #define RE_PROTOID_NONIP        0x00000000
 521 #define RE_PROTOID_TCPIP        0x00010000
 522 #define RE_PROTOID_UDPIP        0x00020000
 523 #define RE_PROTOID_IP           0x00030000
 524 #define RE_TCPPKT(x)            (((x) & RE_RDESC_STAT_PROTOID) == \
 525                                  RE_PROTOID_TCPIP)
 526 #define RE_UDPPKT(x)            (((x) & RE_RDESC_STAT_PROTOID) == \
 527                                  RE_PROTOID_UDPIP)
 528
 529 /*
 530  * Statistics counter structure (8139C+ and 8169 only)
 531  */
 532 struct re_stats {
 533         uint32_t                re_tx_pkts_lo;
 534         uint32_t                re_tx_pkts_hi;
 535         uint32_t                re_tx_errs_lo;
 536         uint32_t                re_tx_errs_hi;
 537         uint32_t                re_tx_errs;
 538         uint16_t                re_missed_pkts;
 539         uint16_t                re_rx_framealign_errs;
 540         uint32_t                re_tx_onecoll;
 541         uint32_t                re_tx_multicolls;
 542         uint32_t                re_rx_ucasts_hi;
 543         uint32_t                re_rx_ucasts_lo;
 544         uint32_t                re_rx_bcasts_lo;
 545         uint32_t                re_rx_bcasts_hi;
 546         uint32_t                re_rx_mcasts;
 547         uint16_t                re_tx_aborts;
 548         uint16_t                re_rx_underruns;
 549 };
 550
 551 #define RE_RX_DESC_CNT          64
 552 #define RE_TX_DESC_CNT          64
 553 #define RE_RX_LIST_SZ           (RE_RX_DESC_CNT * sizeof(struct re_desc))
 554 #define RE_TX_LIST_SZ           (RE_TX_DESC_CNT * sizeof(struct re_desc))
 555 #define RE_RING_ALIGN           256
 556 #define RE_IFQ_MAXLEN           512
 557 #define RE_DESC_INC(x)          (x = (x + 1) % RE_TX_DESC_CNT)
 558 #define RE_OWN(x)               (le32toh((x)->re_cmdstat) & RE_RDESC_STAT_OWN)
 559 #define RE_RXBYTES(x)           (le32toh((x)->re_cmdstat) & sc->re_rxlenmask)
 560 #define RE_PKTSZ(x)             ((x)/* >> 3*/)
 561
 562 #define RE_ADDR_LO(y)           ((uint64_t) (y) & 0xFFFFFFFF)
 563 #define RE_ADDR_HI(y)           ((uint64_t) (y) >> 32)
 564
 565 #define RE_JUMBO_FRAMELEN       9018
 566 #define RE_JUMBO_MTU            (RE_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN)
 567
 568 #define RE_TIMEOUT              1000
 569
 570 /*
 571  * General constants that are fun to know.
 572  *
 573  * PCI low memory base and low I/O base register, and
 574  * other PCI registers.
 575  */
 576
 577 #define RE_PCI_LOMEM            0x14
 578 #define RE_PCI_LOIO             0x10
 579
 580 #define PCI_SUBDEVICE_LINKSYS_EG1032_REV3       0x0024