drivers/net/sk_mca.h

   1 #ifndef _SK_MCA_INCLUDE_
   2 #define _SK_MCA_INCLUDE_
   3
   4 #ifdef _SK_MCA_DRIVER_
   5
   6 /* version-dependent functions/structures */
   7
   8 #if LINUX_VERSION_CODE >= 0x020318
   9 #define SKMCA_READB(addr) isa_readb(addr)
  10 #define SKMCA_READW(addr) isa_readw(addr)
  11 #define SKMCA_WRITEB(data, addr) isa_writeb(data, addr)
  12 #define SKMCA_WRITEW(data, addr) isa_writew(data, addr)
  13 #define SKMCA_TOIO(dest, src, len) isa_memcpy_toio(dest, src, len)
  14 #define SKMCA_FROMIO(dest, src, len) isa_memcpy_fromio(dest, src, len)
  15 #define SKMCA_SETIO(dest, val, len) isa_memset_io(dest, val, len)
  16 #define SKMCA_NETDEV net_device
  17 #else
  18 #define SKMCA_READB(addr) readb(addr)
  19 #define SKMCA_READW(addr) readw(addr)
  20 #define SKMCA_WRITEB(data, addr) writeb(data, addr)
  21 #define SKMCA_WRITEW(data, addr) writew(data, addr)
  22 #define SKMCA_TOIO(dest, src, len) memcpy_toio(dest, src, len)
  23 #define SKMCA_FROMIO(dest, src, len) memcpy_fromio(dest, src, len)
  24 #define SKMCA_SETIO(dest, val, len) memset_io(dest, val, len)
  25 #define SKMCA_NETDEV device
  26 #endif
  27
  28 /* Adapter ID's */
  29 #define SKNET_MCA_ID 0x6afd
  30 #define SKNET_JUNIOR_MCA_ID 0x6be9
  31
  32 /* media enumeration - defined in a way that it fits onto the MC2+'s
  33    POS registers... */
  34
  35 typedef enum { Media_10Base2, Media_10BaseT,
  36         Media_10Base5, Media_Unknown, Media_Count
  37 } skmca_medium;
  38
  39 /* private structure */
  40 typedef struct {
  41         unsigned int slot;      /* MCA-Slot-#                       */
  42         unsigned int macbase;   /* base address of MAC address PROM */
  43         unsigned int ioregaddr; /* address of I/O-register (Lo)     */
  44         unsigned int ctrladdr;  /* address of control/stat register */
  45         unsigned int cmdaddr;   /* address of I/O-command register  */
  46         int nextrx;             /* index of next RX descriptor to
  47                                    be read                          */
  48         int nexttxput;          /* index of next free TX descriptor */
  49         int nexttxdone;         /* index of next TX descriptor to
  50                                    be finished                      */
  51         int txbusy;             /* # of busy TX descriptors         */
  52         struct net_device_stats stat;   /* packet statistics            */
  53         int realirq;            /* memorizes actual IRQ, even when
  54                                    currently not allocated          */
  55         skmca_medium medium;    /* physical cannector               */
  56 } skmca_priv;
  57
  58 /* card registers: control/status register bits */
  59
  60 #define CTRL_ADR_DATA      0    /* Bit 0 = 0 ->access data register  */
  61 #define CTRL_ADR_RAP       1    /* Bit 0 = 1 ->access RAP register   */
  62 #define CTRL_RW_WRITE      0    /* Bit 1 = 0 ->write register        */
  63 #define CTRL_RW_READ       2    /* Bit 1 = 1 ->read register         */
  64 #define CTRL_RESET_ON      0    /* Bit 3 = 0 ->reset board           */
  65 #define CTRL_RESET_OFF     8    /* Bit 3 = 1 ->no reset of board     */
  66
  67 #define STAT_ADR_DATA      0    /* Bit 0 of ctrl register read back  */
  68 #define STAT_ADR_RAP       1
  69 #define STAT_RW_WRITE      0    /* Bit 1 of ctrl register read back  */
  70 #define STAT_RW_READ       2
  71 #define STAT_RESET_ON      0    /* Bit 3 of ctrl register read back  */
  72 #define STAT_RESET_OFF     8
  73 #define STAT_IRQ_ACT       0    /* interrupt pending                 */
  74 #define STAT_IRQ_NOACT     16   /* no interrupt pending              */
  75 #define STAT_IO_NOBUSY     0    /* no transfer busy                  */
  76 #define STAT_IO_BUSY       32   /* transfer busy                     */
  77
  78 /* I/O command register bits */
  79
  80 #define IOCMD_GO           128  /* Bit 7 = 1 -> start register xfer  */
  81
  82 /* LANCE registers */
  83
  84 #define LANCE_CSR0         0    /* Status/Control                    */
  85
  86 #define CSR0_ERR           0x8000       /* general error flag                */
  87 #define CSR0_BABL          0x4000       /* transmitter timeout               */
  88 #define CSR0_CERR          0x2000       /* collision error                   */
  89 #define CSR0_MISS          0x1000       /* lost Rx block                     */
  90 #define CSR0_MERR          0x0800       /* memory access error               */
  91 #define CSR0_RINT          0x0400       /* receiver interrupt                */
  92 #define CSR0_TINT          0x0200       /* transmitter interrupt             */
  93 #define CSR0_IDON          0x0100       /* initialization done               */
  94 #define CSR0_INTR          0x0080       /* general interrupt flag            */
  95 #define CSR0_INEA          0x0040       /* interrupt enable                  */
  96 #define CSR0_RXON          0x0020       /* receiver enabled                  */
  97 #define CSR0_TXON          0x0010       /* transmitter enabled               */
  98 #define CSR0_TDMD          0x0008       /* force transmission now            */
  99 #define CSR0_STOP          0x0004       /* stop LANCE                        */
 100 #define CSR0_STRT          0x0002       /* start LANCE                       */
 101 #define CSR0_INIT          0x0001       /* read initialization block         */
 102
 103 #define LANCE_CSR1         1    /* addr bit 0..15 of initialization  */
 104 #define LANCE_CSR2         2    /*          16..23 block             */
 105
 106 #define LANCE_CSR3         3    /* Bus control                       */
 107 #define CSR3_BCON_HOLD     0    /* Bit 0 = 0 -> BM1,BM0,HOLD         */
 108 #define CSR3_BCON_BUSRQ    1    /* Bit 0 = 1 -> BUSAK0,BYTE,BUSRQ    */
 109 #define CSR3_ALE_HIGH      0    /* Bit 1 = 0 -> ALE asserted high    */
 110 #define CSR3_ALE_LOW       2    /* Bit 1 = 1 -> ALE asserted low     */
 111 #define CSR3_BSWAP_OFF     0    /* Bit 2 = 0 -> no byte swap         */
 112 #define CSR3_BSWAP_ON      0    /* Bit 2 = 1 -> byte swap            */
 113
 114 /* LANCE structures */
 115
 116 typedef struct {                /* LANCE initialization block        */
 117         u16 Mode;               /* mode flags                        */
 118         u8 PAdr[6];             /* MAC address                       */
 119         u8 LAdrF[8];            /* Multicast filter                  */
 120         u32 RdrP;               /* Receive descriptor                */
 121         u32 TdrP;               /* Transmit descriptor               */
 122 } LANCE_InitBlock;
 123
 124 /* Mode flags init block */
 125
 126 #define LANCE_INIT_PROM    0x8000       /* enable promiscous mode            */
 127 #define LANCE_INIT_INTL    0x0040       /* internal loopback                 */
 128 #define LANCE_INIT_DRTY    0x0020       /* disable retry                     */
 129 #define LANCE_INIT_COLL    0x0010       /* force collision                   */
 130 #define LANCE_INIT_DTCR    0x0008       /* disable transmit CRC              */
 131 #define LANCE_INIT_LOOP    0x0004       /* loopback                          */
 132 #define LANCE_INIT_DTX     0x0002       /* disable transmitter               */
 133 #define LANCE_INIT_DRX     0x0001       /* disable receiver                  */
 134
 135 typedef struct {                /* LANCE Tx descriptor               */
 136         u16 LowAddr;            /* bit 0..15 of address              */
 137         u16 Flags;              /* bit 16..23 of address + Flags     */
 138         u16 Len;                /* 2s complement of packet length    */
 139         u16 Status;             /* Result of transmission            */
 140 } LANCE_TxDescr;
 141
 142 #define TXDSCR_FLAGS_OWN   0x8000       /* LANCE owns descriptor             */
 143 #define TXDSCR_FLAGS_ERR   0x4000       /* summary error flag                */
 144 #define TXDSCR_FLAGS_MORE  0x1000       /* more than one retry needed?       */
 145 #define TXDSCR_FLAGS_ONE   0x0800       /* one retry?                        */
 146 #define TXDSCR_FLAGS_DEF   0x0400       /* transmission deferred?            */
 147 #define TXDSCR_FLAGS_STP   0x0200       /* first packet in chain?            */
 148 #define TXDSCR_FLAGS_ENP   0x0100       /* last packet in chain?             */
 149
 150 #define TXDSCR_STATUS_BUFF 0x8000       /* buffer error?                     */
 151 #define TXDSCR_STATUS_UFLO 0x4000       /* silo underflow during transmit?   */
 152 #define TXDSCR_STATUS_LCOL 0x1000       /* late collision?                   */
 153 #define TXDSCR_STATUS_LCAR 0x0800       /* loss of carrier?                  */
 154 #define TXDSCR_STATUS_RTRY 0x0400       /* retry error?                      */
 155
 156 typedef struct {                /* LANCE Rx descriptor               */
 157         u16 LowAddr;            /* bit 0..15 of address              */
 158         u16 Flags;              /* bit 16..23 of address + Flags     */
 159         u16 MaxLen;             /* 2s complement of buffer length    */
 160         u16 Len;                /* packet length                     */
 161 } LANCE_RxDescr;
 162
 163 #define RXDSCR_FLAGS_OWN   0x8000       /* LANCE owns descriptor             */
 164 #define RXDSCR_FLAGS_ERR   0x4000       /* summary error flag                */
 165 #define RXDSCR_FLAGS_FRAM  0x2000       /* framing error flag                */
 166 #define RXDSCR_FLAGS_OFLO  0x1000       /* FIFO overflow?                    */
 167 #define RXDSCR_FLAGS_CRC   0x0800       /* CRC error?                        */
 168 #define RXDSCR_FLAGS_BUFF  0x0400       /* buffer error?                     */
 169 #define RXDSCR_FLAGS_STP   0x0200       /* first packet in chain?            */
 170 #define RXDCSR_FLAGS_ENP   0x0100       /* last packet in chain?             */
 171
 172 /* RAM layout */
 173
 174 #define TXCOUNT            4    /* length of TX descriptor queue     */
 175 #define LTXCOUNT           2    /* log2 of it                        */
 176 #define RXCOUNT            4    /* length of RX descriptor queue     */
 177 #define LRXCOUNT           2    /* log2 of it                        */
 178
 179 #define RAM_INITBASE       0    /* LANCE init block                  */
 180 #define RAM_TXBASE         24   /* Start of TX descriptor queue      */
 181 #define RAM_RXBASE         \
 182 (RAM_TXBASE + (TXCOUNT * 8))    /* Start of RX descriptor queue      */
 183 #define RAM_DATABASE       \
 184 (RAM_RXBASE + (RXCOUNT * 8))    /* Start of data area for frames     */
 185 #define RAM_BUFSIZE        1580 /* max. frame size - should never be
 186                                    reached                           */
 187
 188 #endif                          /* _SK_MCA_DRIVER_ */
 189
 190 extern int skmca_probe(struct SKMCA_NETDEV *);
 191
 192
 193 #endif  /* _SK_MCA_INCLUDE_ */