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Import 2.4.0-test5pre6
[davej-history.git] / drivers / video / aty128fb.c
blobef0871369c81d94eda3e08e3b9c0a82c83e02145
1 /* $Id: aty128fb.c,v 1.1.1.1.36.1 1999/12/11 09:03:05 Exp $
2 * linux/drivers/video/aty128fb.c -- Frame buffer device for ATI Rage128
3 *
4 * Copyright (C) 1999-2000, Brad Douglas <brad@neruo.com>
5 * Copyright (C) 1999, Anthony Tong <atong@uiuc.edu>
6 *
7 * Ani Joshi / Jeff Garzik
8 * - Code cleanup
9 *
10 * Based off of Geert's atyfb.c and vfb.c.
11 *
12 * TODO:
13 * - panning
14 * - monitor sensing (DDC)
15 * - virtual display
16 * - other platform support (only ppc/x86 supported)
17 * - hardware cursor support
18 * - ioctl()'s
19 *
20 * Please cc: your patches to brad@neruo.com.
21 */
22
23 /*
24 * A special note of gratitude to ATI's devrel for providing documentation,
25 * example code and hardware. Thanks Nitya. -atong and brad
26 */
27
28
29 #include <linux/config.h>
30 #include <linux/module.h>
31 #include <linux/kernel.h>
32 #include <linux/errno.h>
33 #include <linux/string.h>
34 #include <linux/mm.h>
35 #include <linux/tty.h>
36 #include <linux/malloc.h>
37 #include <linux/vmalloc.h>
38 #include <linux/delay.h>
39 #include <linux/interrupt.h>
40 #include <asm/uaccess.h>
41 #include <linux/fb.h>
42 #include <linux/init.h>
43 #include <linux/selection.h>
44 #include <linux/console.h>
45 #include <linux/pci.h>
46 #include <linux/ioport.h>
47 #include <asm/io.h>
48
49 #ifdef CONFIG_PPC
50 #include <asm/prom.h>
51 #include <asm/pci-bridge.h>
52 #include <video/macmodes.h>
53 #ifdef CONFIG_NVRAM
54 #include <linux/nvram.h>
55 #endif
56 #endif
57
58 #ifdef CONFIG_FB_COMPAT_XPMAC
59 #include <asm/vc_ioctl.h>
60 #endif
61
62 #include <video/fbcon.h>
63 #include <video/fbcon-cfb8.h>
64 #include <video/fbcon-cfb16.h>
65 #include <video/fbcon-cfb24.h>
66 #include <video/fbcon-cfb32.h>
67
68 #ifdef CONFIG_MTRR
69 #include <asm/mtrr.h>
70 #endif
71
72 #include "aty128.h"
73
74 /* Debug flag */
75 #undef DEBUG
76
77 #ifdef DEBUG
78 #define DBG(fmt, args...) printk(KERN_DEBUG "aty128fb: %s " fmt, __FUNCTION__, ##args);
79 #else
80 #define DBG(fmt, args...)
81 #endif
82
83 #ifndef CONFIG_PPC
84 /* default mode */
85 static struct fb_var_screeninfo default_var __initdata = {
86 /* 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock) */
87 640, 480, 640, 480, 0, 0, 8, 0,
88 {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0},
89 0, 0, -1, -1, 0, 39722, 48, 16, 33, 10, 96, 2,
90 0, FB_VMODE_NONINTERLACED
91 };
92
93 #else /* CONFIG_PPC */
94 /* default to 1024x768 at 75Hz on PPC - this will work
95 * on the iMac, the usual 640x480 @ 60Hz doesn't. */
96 static struct fb_var_screeninfo default_var = {
97 /* 1024x768, 75 Hz, Non-Interlaced (78.75 MHz dotclock) */
98 1024, 768, 1024, 768, 0, 0, 8, 0,
99 {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0},
100 0, 0, -1, -1, 0, 12699, 160, 32, 28, 1, 96, 3,
101 FB_SYNC_HOR_HIGH_ACT|FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED
102 };
103 #endif /* CONFIG_PPC */
104
105 #ifndef MODULE
106 /* default modedb mode */
107 /* 640x480, 60 Hz, Non-Interlaced (25.172 MHz dotclock) */
108 static struct fb_videomode defaultmode __initdata = {
109 refresh: 60,
110 xres: 640,
111 yres: 480,
112 pixclock: 39722,
113 left_margin: 48,
114 right_margin: 16,
115 upper_margin: 33,
116 lower_margin: 10,
117 hsync_len: 96,
118 vsync_len: 2,
119 sync: 0,
120 vmode: FB_VMODE_NONINTERLACED
121 };
122 #endif /* MODULE */
123
124 /* struct to hold chip description information */
125 struct aty128_chip_info {
126 const char *name;
127 unsigned short device;
128 int chip_gen;
129 };
130
131 /* Chip generations */
132 enum {
133 rage_128,
134 rage_128_pro,
135 rage_M3
136 };
137
138 /* supported Rage128 chipsets */
139 static const struct aty128_chip_info aty128_pci_probe_list[] __initdata =
140 {
141 {"Rage128 RE (PCI)", PCI_DEVICE_ID_ATI_RAGE128_RE, rage_128},
142 {"Rage128 RF (AGP)", PCI_DEVICE_ID_ATI_RAGE128_RF, rage_128},
143 {"Rage128 RK (PCI)", PCI_DEVICE_ID_ATI_RAGE128_RK, rage_128},
144 {"Rage128 RL (AGP)", PCI_DEVICE_ID_ATI_RAGE128_RL, rage_128},
145 {"Rage128 Pro PF (AGP)", PCI_DEVICE_ID_ATI_RAGE128_PF, rage_128_pro},
146 {"Rage128 Pro PR (PCI)", PCI_DEVICE_ID_ATI_RAGE128_PR, rage_128_pro},
147 {"Rage Mobility M3 (PCI)", PCI_DEVICE_ID_ATI_RAGE128_LE, rage_M3},
148 {"Rage Mobility M3 (AGP)", PCI_DEVICE_ID_ATI_RAGE128_LF, rage_M3},
149 {NULL, 0, rage_128}
150 };
151
152 /* packed BIOS settings */
153 #ifndef CONFIG_PPC
154 typedef struct {
155 u8 clock_chip_type;
156 u8 struct_size;
157 u8 accelerator_entry;
158 u8 VGA_entry;
159 u16 VGA_table_offset;
160 u16 POST_table_offset;
161 u16 XCLK;
162 u16 MCLK;
163 u8 num_PLL_blocks;
164 u8 size_PLL_blocks;
165 u16 PCLK_ref_freq;
166 u16 PCLK_ref_divider;
167 u32 PCLK_min_freq;
168 u32 PCLK_max_freq;
169 u16 MCLK_ref_freq;
170 u16 MCLK_ref_divider;
171 u32 MCLK_min_freq;
172 u32 MCLK_max_freq;
173 u16 XCLK_ref_freq;
174 u16 XCLK_ref_divider;
175 u32 XCLK_min_freq;
176 u32 XCLK_max_freq;
177 } __attribute__ ((packed)) PLL_BLOCK;
178 #endif /* !CONFIG_PPC */
179
180 /* onboard memory information */
181 struct aty128_meminfo {
182 u8 ML;
183 u8 MB;
184 u8 Trcd;
185 u8 Trp;
186 u8 Twr;
187 u8 CL;
188 u8 Tr2w;
189 u8 LoopLatency;
190 u8 DspOn;
191 u8 Rloop;
192 const char *name;
193 };
194
195 /* various memory configurations */
196 static const struct aty128_meminfo sdr_128 =
197 { 4, 4, 3, 3, 1, 3, 1, 16, 30, 16, "128-bit SDR SGRAM (1:1)" };
198 static const struct aty128_meminfo sdr_64 =
199 { 4, 8, 3, 3, 1, 3, 1, 17, 46, 17, "64-bit SDR SGRAM (1:1)" };
200 static const struct aty128_meminfo sdr_sgram =
201 { 4, 4, 1, 2, 1, 2, 1, 16, 24, 16, "64-bit SDR SGRAM (2:1)" };
202 static const struct aty128_meminfo ddr_sgram =
203 { 4, 4, 3, 3, 2, 3, 1, 16, 31, 16, "64-bit DDR SGRAM" };
204
205 static const char *aty128fb_name = "ATY Rage128";
206 static char fontname[40] __initdata = { 0 };
207 static int noaccel __initdata = 0;
208
209 #ifndef MODULE
210 static const char *mode_option __initdata = NULL;
211 #endif
212
213 #ifdef CONFIG_PPC
214 #ifdef CONFIG_NVRAM_NOT_DEFINED
215 static int default_vmode __initdata = VMODE_640_480_60;
216 static int default_cmode __initdata = CMODE_8;
217 #else
218 static int default_vmode __initdata = VMODE_NVRAM;
219 static int default_cmode __initdata = CMODE_NVRAM;
220 #endif
221 #endif
222
223 #ifdef CONFIG_MTRR
224 static int mtrr = 1;
225 #endif
226
227 /* PLL constants */
228 struct aty128_constants {
229 u32 dotclock;
230 u32 ppll_min;
231 u32 ppll_max;
232 u32 ref_divider;
233 u32 xclk;
234 u32 fifo_width;
235 u32 fifo_depth;
236 };
237
238 struct aty128_crtc {
239 u32 gen_cntl;
240 u32 ext_cntl;
241 u32 h_total, h_sync_strt_wid;
242 u32 v_total, v_sync_strt_wid;
243 u32 pitch;
244 u32 offset, offset_cntl;
245 u32 xoffset, yoffset;
246 u32 vxres, vyres;
247 u32 bpp;
248 };
249
250 struct aty128_pll {
251 u32 post_divider;
252 u32 feedback_divider;
253 u32 vclk;
254 };
255
256 struct aty128_ddafifo {
257 u32 dda_config;
258 u32 dda_on_off;
259 };
260
261 /* register values for a specific mode */
262 struct aty128fb_par {
263 struct aty128_crtc crtc;
264 struct aty128_pll pll;
265 struct aty128_ddafifo fifo_reg;
266 u32 accel_flags;
267 };
268
269 struct fb_info_aty128 {
270 struct fb_info fb_info;
271 struct fb_info_aty128 *next;
272 struct aty128_constants constants; /* PLL and others */
273 u32 regbase_phys; /* physical mmio */
274 void *regbase; /* remapped mmio */
275 u32 frame_buffer_phys; /* physical fb memory */
276 u32 frame_buffer; /* remaped framebuffer */
277 u32 vram_size; /* onboard video ram */
278 int chip_gen;
279 const struct aty128_meminfo *mem; /* onboard mem info */
280 struct aty128fb_par default_par, current_par;
281 struct display disp;
282 struct display_switch dispsw; /* for cursor and font */
283 struct { u8 red, green, blue, pad; } palette[256];
284 union {
285 #ifdef FBCON_HAS_CFB16
286 u16 cfb16[16];
287 #endif
288 #ifdef FBCON_HAS_CFB24
289 u32 cfb24[16];
290 #endif
291 #ifdef FBCON_HAS_CFB32
292 u32 cfb32[16];
293 #endif
294 } fbcon_cmap;
295 #ifdef CONFIG_PCI
296 struct pci_dev *pdev;
297 #endif
298 #ifdef CONFIG_MTRR
299 struct { int vram; int vram_valid; } mtrr;
300 #endif
301 int currcon;
302 int blitter_may_be_busy;
303 int fifo_slots; /* free slots in FIFO (64 max) */
304 };
305
306 static struct fb_info_aty128 *board_list = NULL;
307
308 #define round_div(n, d) ((n+(d/2))/d)
309
310 /*
311 * Interface used by the world
312 */
313
314 int aty128fb_setup(char *options);
315
316 static int aty128fb_get_fix(struct fb_fix_screeninfo *fix, int con,
317 struct fb_info *info);
318 static int aty128fb_get_var(struct fb_var_screeninfo *var, int con,
319 struct fb_info *info);
320 static int aty128fb_set_var(struct fb_var_screeninfo *var, int con,
321 struct fb_info *info);
322 static int aty128fb_get_cmap(struct fb_cmap *cmap, int kspc, int con,
323 struct fb_info *info);
324 static int aty128fb_set_cmap(struct fb_cmap *cmap, int kspc, int con,
325 struct fb_info *info);
326 static int aty128fb_pan_display(struct fb_var_screeninfo *var, int con,
327 struct fb_info *fb);
328 static int aty128fb_rasterimg(struct fb_info *info, int start);
329
330
331 /*
332 * Interface to the low level console driver
333 */
334
335 int aty128fb_init(void);
336 static int aty128fbcon_switch(int con, struct fb_info *fb);
337 static void aty128fbcon_blank(int blank, struct fb_info *fb);
338
339 /*
340 * Internal routines
341 */
342
343 static void aty128_encode_fix(struct fb_fix_screeninfo *fix,
344 struct aty128fb_par *par,
345 const struct fb_info_aty128 *info);
346 static void aty128_set_disp(struct display *disp,
347 struct fb_info_aty128 *info, int bpp, int accel);
348 static int aty128_getcolreg(u_int regno, u_int *red, u_int *green, u_int *blue,
349 u_int *transp, struct fb_info *info);
350 static int aty128_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
351 u_int transp, struct fb_info *info);
352 static void do_install_cmap(int con, struct fb_info *info);
353 static int aty128_encode_var(struct fb_var_screeninfo *var,
354 const struct aty128fb_par *par,
355 const struct fb_info_aty128 *info);
356 static int aty128_decode_var(struct fb_var_screeninfo *var,
357 struct aty128fb_par *par,
358 const struct fb_info_aty128 *info);
359 static int aty128_pci_register(struct pci_dev *pdev,
360 const struct aty128_chip_info *aci);
361 static struct fb_info_aty128 *aty128_board_list_add(struct fb_info_aty128
362 *board_list, struct fb_info_aty128 *new_node);
363 #if !defined(CONFIG_PPC) && !defined(__sparc__)
364 static void __init aty128_get_pllinfo(struct fb_info_aty128 *info,
365 char *bios_seg);
366 static char __init *aty128find_ROM(struct fb_info_aty128 *info);
367 #endif
368 static void aty128_timings(struct fb_info_aty128 *info);
369 static void aty128_init_engine(const struct aty128fb_par *par,
370 struct fb_info_aty128 *info);
371 static void aty128_reset_engine(const struct fb_info_aty128 *info);
372 static void aty128_flush_pixel_cache(const struct fb_info_aty128 *info);
373 static void do_wait_for_fifo(u16 entries, struct fb_info_aty128 *info);
374 static void wait_for_fifo(u16 entries, struct fb_info_aty128 *info);
375 static void wait_for_idle(struct fb_info_aty128 *info);
376 static u32 bpp_to_depth(u32 bpp);
377
378 #ifdef FBCON_HAS_CFB8
379 static struct display_switch fbcon_aty128_8;
380 static void fbcon_aty8_putc(struct vc_data *conp, struct display *p,
381 int c, int yy, int xx);
382 static void fbcon_aty8_putcs(struct vc_data *conp, struct display *p,
383 const unsigned short *s, int count,
384 int yy, int xx);
385 #endif
386 #ifdef FBCON_HAS_CFB16
387 static struct display_switch fbcon_aty128_16;
388 static void fbcon_aty16_putc(struct vc_data *conp, struct display *p,
389 int c, int yy, int xx);
390 static void fbcon_aty16_putcs(struct vc_data *conp, struct display *p,
391 const unsigned short *s, int count,
392 int yy, int xx);
393 #endif
394 #ifdef FBCON_HAS_CFB24
395 static struct display_switch fbcon_aty128_24;
396 static void fbcon_aty24_putc(struct vc_data *conp, struct display *p,
397 int c, int yy, int xx);
398 static void fbcon_aty24_putcs(struct vc_data *conp, struct display *p,
399 const unsigned short *s, int count,
400 int yy, int xx);
401 #endif
402 #ifdef FBCON_HAS_CFB32
403 static struct display_switch fbcon_aty128_32;
404 static void fbcon_aty32_putc(struct vc_data *conp, struct display *p,
405 int c, int yy, int xx);
406 static void fbcon_aty32_putcs(struct vc_data *conp, struct display *p,
407 const unsigned short *s, int count,
408 int yy, int xx);
409 #endif
410
411 static struct fb_ops aty128fb_ops = {
412 owner: THIS_MODULE,
413 fb_get_fix: aty128fb_get_fix,
414 fb_get_var: aty128fb_get_var,
415 fb_set_var: aty128fb_set_var,
416 fb_get_cmap: aty128fb_get_cmap,
417 fb_set_cmap: aty128fb_set_cmap,
418 fb_pan_display: aty128fb_pan_display,
419 fb_rasterimg: aty128fb_rasterimg,
420 };
421
422
423 /*
424 * Functions to read from/write to the mmio registers
425 * - endian conversions may possibly be avoided by
426 * using the other register aperture. TODO.
427 */
428 static inline u32
429 _aty_ld_le32(volatile unsigned int regindex,
430 const struct fb_info_aty128 *info)
431 {
432 u32 val;
433
434 #if defined(__powerpc__)
435 asm("lwbrx %0,%1,%2;eieio" : "=r"(val) : "b"(regindex), "r"(info->regbase));
436 #else
437 val = readl (info->regbase + regindex);
438 #endif
439
440 return val;
441 }
442
443 static inline void
444 _aty_st_le32(volatile unsigned int regindex, u32 val,
445 const struct fb_info_aty128 *info)
446 {
447 #if defined(__powerpc__)
448 asm("stwbrx %0,%1,%2;eieio" : : "r"(val), "b"(regindex),
449 "r"(info->regbase) : "memory");
450 #else
451 writel (val, info->regbase + regindex);
452 #endif
453 }
454
455 static inline u8
456 _aty_ld_8(unsigned int regindex, const struct fb_info_aty128 *info)
457 {
458 return readb (info->regbase + regindex);
459 }
460
461 static inline void
462 _aty_st_8(unsigned int regindex, u8 val, const struct fb_info_aty128 *info)
463 {
464 writeb (val, info->regbase + regindex);
465 }
466
467 #define aty_ld_le32(regindex) _aty_ld_le32(regindex, info)
468 #define aty_st_le32(regindex, val) _aty_st_le32(regindex, val, info)
469 #define aty_ld_8(regindex) _aty_ld_8(regindex, info)
470 #define aty_st_8(regindex, val) _aty_st_8(regindex, val, info)
471
472 /*
473 * Functions to read from/write to the pll registers
474 */
475
476 #define aty_ld_pll(pll_index) _aty_ld_pll(pll_index, info)
477 #define aty_st_pll(pll_index, val) _aty_st_pll(pll_index, val, info)
478
479
480 static u32
481 _aty_ld_pll(unsigned int pll_index,
482 const struct fb_info_aty128 *info)
483 {
484 aty_st_8(CLOCK_CNTL_INDEX, pll_index & 0x1F);
485 return aty_ld_le32(CLOCK_CNTL_DATA);
486 }
487
488
489 static void
490 _aty_st_pll(unsigned int pll_index, u32 val,
491 const struct fb_info_aty128 *info)
492 {
493 aty_st_8(CLOCK_CNTL_INDEX, (pll_index & 0x1F) | PLL_WR_EN);
494 aty_st_le32(CLOCK_CNTL_DATA, val);
495 }
496
497
498 /* return true when the PLL has completed an atomic update */
499 static int
500 aty_pll_readupdate(const struct fb_info_aty128 *info)
501 {
502 return !(aty_ld_pll(PPLL_REF_DIV) & PPLL_ATOMIC_UPDATE_R);
503 }
504
505
506 static void
507 aty_pll_wait_readupdate(const struct fb_info_aty128 *info)
508 {
509 unsigned long timeout = jiffies + HZ/100; // should be more than enough
510 int reset = 1;
511
512 while (time_before(jiffies, timeout))
513 if (aty_pll_readupdate(info)) {
514 reset = 0;
515 break;
516 }
517
518 if (reset) /* reset engine?? */
519 printk(KERN_DEBUG "aty128fb: PLL write timeout!");
520 }
521
522
523 /* tell PLL to update */
524 static void
525 aty_pll_writeupdate(const struct fb_info_aty128 *info)
526 {
527 aty_pll_wait_readupdate(info);
528
529 aty_st_pll(PPLL_REF_DIV,
530 aty_ld_pll(PPLL_REF_DIV) | PPLL_ATOMIC_UPDATE_W);
531 }
532
533
534 /* write to the scratch register to test r/w functionality */
535 static int __init
536 register_test(const struct fb_info_aty128 *info)
537 {
538 u32 val;
539 int flag = 0;
540
541 val = aty_ld_le32(BIOS_0_SCRATCH);
542
543 aty_st_le32(BIOS_0_SCRATCH, 0x55555555);
544 if (aty_ld_le32(BIOS_0_SCRATCH) == 0x55555555) {
545 aty_st_le32(BIOS_0_SCRATCH, 0xAAAAAAAA);
546
547 if (aty_ld_le32(BIOS_0_SCRATCH) == 0xAAAAAAAA)
548 flag = 1;
549 }
550
551 aty_st_le32(BIOS_0_SCRATCH, val); // restore value
552 return flag;
553 }
554
555
556 /*
557 * Accelerator engine functions
558 */
559 static void
560 do_wait_for_fifo(u16 entries, struct fb_info_aty128 *info)
561 {
562 int i;
563
564 for (;;) {
565 for (i = 0; i < 2000000; i++) {
566 info->fifo_slots = aty_ld_le32(GUI_STAT) & 0x0fff;
567 if (info->fifo_slots >= entries)
568 return;
569 }
570 aty128_reset_engine(info);
571 }
572 }
573
574
575 static void
576 wait_for_idle(struct fb_info_aty128 *info)
577 {
578 int i;
579
580 do_wait_for_fifo(64, info);
581
582 for (;;) {
583 for (i = 0; i < 2000000; i++) {
584 if (!(aty_ld_le32(GUI_STAT) & (1 << 31))) {
585 aty128_flush_pixel_cache(info);
586 info->blitter_may_be_busy = 0;
587 return;
588 }
589 }
590 aty128_reset_engine(info);
591 }
592 }
593
594
595 static void
596 wait_for_fifo(u16 entries, struct fb_info_aty128 *info)
597 {
598 if (info->fifo_slots < entries)
599 do_wait_for_fifo(64, info);
600 info->fifo_slots -= entries;
601 }
602
603
604 static void
605 aty128_flush_pixel_cache(const struct fb_info_aty128 *info)
606 {
607 int i;
608 u32 tmp;
609
610 tmp = aty_ld_le32(PC_NGUI_CTLSTAT);
611 tmp &= ~(0x00ff);
612 tmp |= 0x00ff;
613 aty_st_le32(PC_NGUI_CTLSTAT, tmp);
614
615 for (i = 0; i < 2000000; i++)
616 if (!(aty_ld_le32(PC_NGUI_CTLSTAT) & PC_BUSY))
617 break;
618 }
619
620
621 static void
622 aty128_reset_engine(const struct fb_info_aty128 *info)
623 {
624 u32 gen_reset_cntl, clock_cntl_index, mclk_cntl;
625
626 aty128_flush_pixel_cache(info);
627
628 clock_cntl_index = aty_ld_le32(CLOCK_CNTL_INDEX);
629 mclk_cntl = aty_ld_pll(MCLK_CNTL);
630
631 aty_st_pll(MCLK_CNTL, mclk_cntl | 0x00030000);
632
633 gen_reset_cntl = aty_ld_le32(GEN_RESET_CNTL);
634 aty_st_le32(GEN_RESET_CNTL, gen_reset_cntl | SOFT_RESET_GUI);
635 aty_ld_le32(GEN_RESET_CNTL);
636 aty_st_le32(GEN_RESET_CNTL, gen_reset_cntl & ~(SOFT_RESET_GUI));
637 aty_ld_le32(GEN_RESET_CNTL);
638
639 aty_st_pll(MCLK_CNTL, mclk_cntl);
640 aty_st_le32(CLOCK_CNTL_INDEX, clock_cntl_index);
641 aty_st_le32(GEN_RESET_CNTL, gen_reset_cntl);
642
643 /* use old pio mode */
644 aty_st_le32(PM4_BUFFER_CNTL, PM4_BUFFER_CNTL_NONPM4);
645
646 DBG("engine reset");
647 }
648
649
650 static void
651 aty128_init_engine(const struct aty128fb_par *par,
652 struct fb_info_aty128 *info)
653 {
654 u32 pitch_value;
655
656 wait_for_idle(info);
657
658 /* 3D scaler not spoken here */
659 wait_for_fifo(1, info);
660 aty_st_le32(SCALE_3D_CNTL, 0x00000000);
661
662 aty128_reset_engine(info);
663
664 pitch_value = par->crtc.pitch;
665 if (par->crtc.bpp == 24) {
666 pitch_value = pitch_value * 3;
667 }
668
669 wait_for_fifo(4, info);
670 /* setup engine offset registers */
671 aty_st_le32(DEFAULT_OFFSET, 0x00000000);
672
673 /* setup engine pitch registers */
674 aty_st_le32(DEFAULT_PITCH, pitch_value);
675
676 /* set the default scissor register to max dimensions */
677 aty_st_le32(DEFAULT_SC_BOTTOM_RIGHT, (0x1FFF << 16) | 0x1FFF);
678
679 /* set the drawing controls registers */
680 aty_st_le32(DP_GUI_MASTER_CNTL,
681 GMC_SRC_PITCH_OFFSET_DEFAULT |
682 GMC_DST_PITCH_OFFSET_DEFAULT |
683 GMC_SRC_CLIP_DEFAULT |
684 GMC_DST_CLIP_DEFAULT |
685 GMC_BRUSH_SOLIDCOLOR |
686 (bpp_to_depth(par->crtc.bpp) << 8) |
687 GMC_SRC_DSTCOLOR |
688 GMC_BYTE_ORDER_MSB_TO_LSB |
689 GMC_DP_CONVERSION_TEMP_6500 |
690 ROP3_PATCOPY |
691 GMC_DP_SRC_RECT |
692 GMC_3D_FCN_EN_CLR |
693 GMC_DST_CLR_CMP_FCN_CLEAR |
694 GMC_AUX_CLIP_CLEAR |
695 GMC_WRITE_MASK_SET);
696
697 wait_for_fifo(8, info);
698 /* clear the line drawing registers */
699 aty_st_le32(DST_BRES_ERR, 0);
700 aty_st_le32(DST_BRES_INC, 0);
701 aty_st_le32(DST_BRES_DEC, 0);
702
703 /* set brush color registers */
704 aty_st_le32(DP_BRUSH_FRGD_CLR, 0xFFFFFFFF); /* white */
705 aty_st_le32(DP_BRUSH_BKGD_CLR, 0x00000000); /* black */
706
707 /* set source color registers */
708 aty_st_le32(DP_SRC_FRGD_CLR, 0xFFFFFFFF); /* white */
709 aty_st_le32(DP_SRC_BKGD_CLR, 0x00000000); /* black */
710
711 /* default write mask */
712 aty_st_le32(DP_WRITE_MASK, 0xFFFFFFFF);
713
714 /* Wait for all the writes to be completed before returning */
715 wait_for_idle(info);
716 }
717
718
719 /* convert bpp values to their register representation */
720 static u32
721 bpp_to_depth(u32 bpp)
722 {
723 if (bpp <= 8)
724 return DST_8BPP;
725 else if (bpp <= 16)
726 return DST_15BPP;
727 else if (bpp <= 24)
728 return DST_24BPP;
729 else if (bpp <= 32)
730 return DST_32BPP;
731
732 return -EINVAL;
733 }
734
735
736 /*
737 * CRTC programming
738 */
739
740 /* Program the CRTC registers */
741 static void
742 aty128_set_crtc(const struct aty128_crtc *crtc,
743 const struct fb_info_aty128 *info)
744 {
745 aty_st_le32(CRTC_GEN_CNTL, crtc->gen_cntl);
746 aty_st_le32(CRTC_H_TOTAL_DISP, crtc->h_total);
747 aty_st_le32(CRTC_H_SYNC_STRT_WID, crtc->h_sync_strt_wid);
748 aty_st_le32(CRTC_V_TOTAL_DISP, crtc->v_total);
749 aty_st_le32(CRTC_V_SYNC_STRT_WID, crtc->v_sync_strt_wid);
750 aty_st_le32(CRTC_PITCH, crtc->pitch);
751 aty_st_le32(CRTC_OFFSET, crtc->offset);
752 aty_st_le32(CRTC_OFFSET_CNTL, crtc->offset_cntl);
753 /* Disable ATOMIC updating. Is this the right place?
754 * -- BenH: Breaks on my G4
755 */
756 #if 0
757 aty_st_le32(PPLL_CNTL, aty_ld_le32(PPLL_CNTL) & ~(0x00030000));
758 #endif
759 }
760
761
762 static int
763 aty128_var_to_crtc(const struct fb_var_screeninfo *var,
764 struct aty128_crtc *crtc,
765 const struct fb_info_aty128 *info)
766 {
767 u32 xres, yres, vxres, vyres, xoffset, yoffset, bpp;
768 u32 left, right, upper, lower, hslen, vslen, sync, vmode;
769 u32 h_total, h_disp, h_sync_strt, h_sync_wid, h_sync_pol;
770 u32 v_total, v_disp, v_sync_strt, v_sync_wid, v_sync_pol, c_sync;
771 u32 depth, bytpp;
772 u8 hsync_strt_pix[5] = { 0, 0x12, 9, 6, 5 };
773 u8 mode_bytpp[7] = { 0, 0, 1, 2, 2, 3, 4 };
774
775 /* input */
776 xres = var->xres;
777 yres = var->yres;
778 vxres = var->xres_virtual;
779 vyres = var->yres_virtual;
780 xoffset = var->xoffset;
781 yoffset = var->yoffset;
782 bpp = var->bits_per_pixel;
783 left = var->left_margin;
784 right = var->right_margin;
785 upper = var->upper_margin;
786 lower = var->lower_margin;
787 hslen = var->hsync_len;
788 vslen = var->vsync_len;
789 sync = var->sync;
790 vmode = var->vmode;
791
792 /* check for mode eligibility
793 * accept only non interlaced modes */
794 if ((vmode & FB_VMODE_MASK) != FB_VMODE_NONINTERLACED)
795 return -EINVAL;
796
797 /* convert (and round up) and validate */
798 xres = (xres + 7) & ~7;
799 xoffset = (xoffset + 7) & ~7;
800
801 if (vxres < xres + xoffset)
802 vxres = xres + xoffset;
803
804 if (vyres < yres + yoffset)
805 vyres = yres + yoffset;
806
807 /* convert bpp into ATI register depth */
808 depth = bpp_to_depth(bpp);
809
810 /* make sure we didn't get an invalid depth */
811 if (depth == -EINVAL) {
812 printk(KERN_ERR "aty128fb: Invalid depth\n");
813 return -EINVAL;
814 }
815
816 /* convert depth to bpp */
817 bytpp = mode_bytpp[depth];
818
819 /* make sure there is enough video ram for the mode */
820 if ((u32)(vxres * vyres * bytpp) > info->vram_size) {
821 printk(KERN_ERR "aty128fb: Not enough memory for mode\n");
822 return -EINVAL;
823 }
824
825 h_disp = (xres >> 3) - 1;
826 h_total = (((xres + right + hslen + left) >> 3) - 1) & 0xFFFFL;
827
828 v_disp = yres - 1;
829 v_total = (yres + upper + vslen + lower - 1) & 0xFFFFL;
830
831 /* check to make sure h_total and v_total are in range */
832 if (((h_total >> 3) - 1) > 0x1ff || (v_total - 1) > 0x7FF) {
833 printk(KERN_ERR "aty128fb: invalid width ranges\n");
834 return -EINVAL;
835 }
836
837 h_sync_wid = (hslen + 7) >> 3;
838 if (h_sync_wid == 0)
839 h_sync_wid = 1;
840 else if (h_sync_wid > 0x3f) /* 0x3f = max hwidth */
841 h_sync_wid = 0x3f;
842
843 h_sync_strt = h_disp + (right >> 3);
844
845 v_sync_wid = vslen;
846 if (v_sync_wid == 0)
847 v_sync_wid = 1;
848 else if (v_sync_wid > 0x1f) /* 0x1f = max vwidth */
849 v_sync_wid = 0x1f;
850
851 v_sync_strt = v_disp + lower;
852
853 h_sync_pol = sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1;
854 v_sync_pol = sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1;
855
856 c_sync = sync & FB_SYNC_COMP_HIGH_ACT ? (1 << 4) : 0;
857
858 crtc->gen_cntl = 0x3000000L | c_sync | (depth << 8);
859
860 crtc->h_total = h_total | (h_disp << 16);
861 crtc->v_total = v_total | (v_disp << 16);
862
863 crtc->h_sync_strt_wid = hsync_strt_pix[bytpp] | (h_sync_strt << 3) |
864 (h_sync_wid << 16) | (h_sync_pol << 23);
865 crtc->v_sync_strt_wid = v_sync_strt | (v_sync_wid << 16) |
866 (v_sync_pol << 23);
867
868 crtc->pitch = vxres >> 3;
869
870 crtc->offset = 0;
871 crtc->offset_cntl = 0;
872
873 crtc->vxres = vxres;
874 crtc->vyres = vyres;
875 crtc->xoffset = xoffset;
876 crtc->yoffset = yoffset;
877 crtc->bpp = bpp;
878
879 return 0;
880 }
881
882
883 static int
884 aty128_bpp_to_var(int pix_width, struct fb_var_screeninfo *var)
885 {
886
887 /* fill in pixel info */
888 switch (pix_width) {
889 case CRTC_PIX_WIDTH_8BPP:
890 var->bits_per_pixel = 8;
891 var->red.offset = 0;
892 var->red.length = 8;
893 var->green.offset = 0;
894 var->green.length = 8;
895 var->blue.offset = 0;
896 var->blue.length = 8;
897 var->transp.offset = 0;
898 var->transp.length = 0;
899 break;
900 case CRTC_PIX_WIDTH_15BPP:
901 case CRTC_PIX_WIDTH_16BPP:
902 var->bits_per_pixel = 16;
903 var->red.offset = 10;
904 var->red.length = 5;
905 var->green.offset = 5;
906 var->green.length = 5;
907 var->blue.offset = 0;
908 var->blue.length = 5;
909 var->transp.offset = 0;
910 var->transp.length = 0;
911 break;
912 case CRTC_PIX_WIDTH_24BPP:
913 var->bits_per_pixel = 24;
914 var->red.offset = 16;
915 var->red.length = 8;
916 var->green.offset = 8;
917 var->green.length = 8;
918 var->blue.offset = 0;
919 var->blue.length = 8;
920 var->transp.offset = 0;
921 var->transp.length = 0;
922 break;
923 case CRTC_PIX_WIDTH_32BPP:
924 var->bits_per_pixel = 32;
925 var->red.offset = 16;
926 var->red.length = 8;
927 var->green.offset = 8;
928 var->green.length = 8;
929 var->blue.offset = 0;
930 var->blue.length = 8;
931 var->transp.offset = 24;
932 var->transp.length = 8;
933 break;
934 default:
935 printk(KERN_ERR "aty128fb: Invalid pixel width\n");
936 return -EINVAL;
937 }
938
939 return 0;
940 }
941
942
943 static int
944 aty128_crtc_to_var(const struct aty128_crtc *crtc,
945 struct fb_var_screeninfo *var)
946 {
947 u32 xres, yres, left, right, upper, lower, hslen, vslen, sync;
948 u32 h_total, h_disp, h_sync_strt, h_sync_dly, h_sync_wid, h_sync_pol;
949 u32 v_total, v_disp, v_sync_strt, v_sync_wid, v_sync_pol, c_sync;
950 u32 pix_width;
951
952 /* fun with masking */
953 h_total = crtc->h_total & 0x1ff;
954 h_disp = (crtc->h_total >> 16) & 0xff;
955 h_sync_strt = (crtc->h_sync_strt_wid >> 3) & 0x1ff;
956 h_sync_dly = crtc->h_sync_strt_wid & 0x7;
957 h_sync_wid = (crtc->h_sync_strt_wid >> 16) & 0x3f;
958 h_sync_pol = (crtc->h_sync_strt_wid >> 23) & 0x1;
959 v_total = crtc->v_total & 0x7ff;
960 v_disp = (crtc->v_total >> 16) & 0x7ff;
961 v_sync_strt = crtc->v_sync_strt_wid & 0x7ff;
962 v_sync_wid = (crtc->v_sync_strt_wid >> 16) & 0x1f;
963 v_sync_pol = (crtc->v_sync_strt_wid >> 23) & 0x1;
964 c_sync = crtc->gen_cntl & CRTC_CSYNC_EN ? 1 : 0;
965 pix_width = crtc->gen_cntl & CRTC_PIX_WIDTH_MASK;
966
967 /* do conversions */
968 xres = (h_disp + 1) << 3;
969 yres = v_disp + 1;
970 left = ((h_total - h_sync_strt - h_sync_wid) << 3) - h_sync_dly;
971 right = ((h_sync_strt - h_disp) << 3) + h_sync_dly;
972 hslen = h_sync_wid << 3;
973 upper = v_total - v_sync_strt - v_sync_wid;
974 lower = v_sync_strt - v_disp;
975 vslen = v_sync_wid;
976 sync = (h_sync_pol ? 0 : FB_SYNC_HOR_HIGH_ACT) |
977 (v_sync_pol ? 0 : FB_SYNC_VERT_HIGH_ACT) |
978 (c_sync ? FB_SYNC_COMP_HIGH_ACT : 0);
979
980 aty128_bpp_to_var(pix_width, var);
981
982 var->xres = xres;
983 var->yres = yres;
984 var->xres_virtual = crtc->vxres;
985 var->yres_virtual = crtc->vyres;
986 var->xoffset = crtc->xoffset;
987 var->yoffset = crtc->yoffset;
988 var->left_margin = left;
989 var->right_margin = right;
990 var->upper_margin = upper;
991 var->lower_margin = lower;
992 var->hsync_len = hslen;
993 var->vsync_len = vslen;
994 var->sync = sync;
995 var->vmode = FB_VMODE_NONINTERLACED;
996
997 return 0;
998 }
999
1000 static void
1001 aty128_set_pll(struct aty128_pll *pll, const struct fb_info_aty128 *info)
1002 {
1003 u32 div3;
1004
1005 unsigned char post_conv[] = /* register values for post dividers */
1006 { 2, 0, 1, 4, 2, 2, 6, 2, 3, 2, 2, 2, 7 };
1007
1008 /* select PPLL_DIV_3 */
1009 aty_st_le32(CLOCK_CNTL_INDEX, aty_ld_le32(CLOCK_CNTL_INDEX) | (3 << 8));
1010
1011 /* reset PLL */
1012 aty_st_pll(PPLL_CNTL,
1013 aty_ld_pll(PPLL_CNTL) | PPLL_RESET | PPLL_ATOMIC_UPDATE_EN);
1014
1015 /* write the reference divider */
1016 aty_pll_wait_readupdate(info);
1017 aty_st_pll(PPLL_REF_DIV, info->constants.ref_divider & 0x3ff);
1018 aty_pll_writeupdate(info);
1019
1020 div3 = aty_ld_pll(PPLL_DIV_3);
1021 div3 &= ~PPLL_FB3_DIV_MASK;
1022 div3 |= pll->feedback_divider;
1023 div3 &= ~PPLL_POST3_DIV_MASK;
1024 div3 |= post_conv[pll->post_divider] << 16;
1025
1026 /* write feedback and post dividers */
1027 aty_pll_wait_readupdate(info);
1028 aty_st_pll(PPLL_DIV_3, div3);
1029 aty_pll_writeupdate(info);
1030
1031 aty_pll_wait_readupdate(info);
1032 aty_st_pll(HTOTAL_CNTL, 0); /* no horiz crtc adjustment */
1033 aty_pll_writeupdate(info);
1034
1035 /* clear the reset, just in case */
1036 aty_st_pll(PPLL_CNTL, aty_ld_pll(PPLL_CNTL) & ~PPLL_RESET);
1037 }
1038
1039
1040 static int
1041 aty128_var_to_pll(u32 period_in_ps, struct aty128_pll *pll,
1042 const struct fb_info_aty128 *info)
1043 {
1044 const struct aty128_constants c = info->constants;
1045 unsigned char post_dividers[] = {1,2,4,8,3,6,12};
1046 u32 output_freq;
1047 u32 vclk; /* in .01 MHz */
1048 int i;
1049 u32 n, d;
1050
1051 vclk = 100000000 / period_in_ps; /* convert units to 10 kHz */
1052
1053 /* adjust pixel clock if necessary */
1054 if (vclk > c.ppll_max)
1055 vclk = c.ppll_max;
1056 if (vclk * 12 < c.ppll_min)
1057 vclk = c.ppll_min/12;
1058
1059 /* now, find an acceptable divider */
1060 for (i = 0; i < sizeof(post_dividers); i++) {
1061 output_freq = post_dividers[i] * vclk;
1062 if (output_freq >= c.ppll_min && output_freq <= c.ppll_max)
1063 break;
1064 }
1065
1066 /* calculate feedback divider */
1067 n = c.ref_divider * output_freq;
1068 d = c.dotclock;
1069
1070 pll->post_divider = post_dividers[i];
1071 pll->feedback_divider = round_div(n, d);
1072 pll->vclk = vclk;
1073
1074 DBG("post %d feedback %d vlck %d output %d ref_divider %d "
1075 "vclk_per: %d\n", pll->post_divider,
1076 pll->feedback_divider, vclk, output_freq,
1077 c.ref_divider, period_in_ps);
1078
1079 return 0;
1080 }
1081
1082
1083 static int
1084 aty128_pll_to_var(const struct aty128_pll *pll, struct fb_var_screeninfo *var,
1085 const struct fb_info_aty128 *info)
1086 {
1087 var->pixclock = 100000000 / pll->vclk;
1088
1089 return 0;
1090 }
1091
1092
1093 static void
1094 aty128_set_fifo(const struct aty128_ddafifo *dsp,
1095 const struct fb_info_aty128 *info)
1096 {
1097 aty_st_le32(DDA_CONFIG, dsp->dda_config);
1098 aty_st_le32(DDA_ON_OFF, dsp->dda_on_off);
1099 }
1100
1101
1102 static int
1103 aty128_ddafifo(struct aty128_ddafifo *dsp,
1104 const struct aty128_pll *pll,
1105 u32 bpp,
1106 const struct fb_info_aty128 *info)
1107 {
1108 const struct aty128_meminfo *m = info->mem;
1109 u32 xclk = info->constants.xclk;
1110 u32 fifo_width = info->constants.fifo_width;
1111 u32 fifo_depth = info->constants.fifo_depth;
1112 s32 x, b, p, ron, roff;
1113 u32 n, d;
1114
1115 /* 15bpp is really 16bpp */
1116 if (bpp == 15)
1117 bpp = 16;
1118
1119 n = xclk * fifo_width;
1120 d = pll->vclk * bpp;
1121 x = round_div(n, d);
1122
1123 ron = 4 * m->MB +
1124 3 * ((m->Trcd - 2 > 0) ? m->Trcd - 2 : 0) +
1125 2 * m->Trp +
1126 m->Twr +
1127 m->CL +
1128 m->Tr2w +
1129 x;
1130
1131 DBG("x %x\n", x);
1132
1133 b = 0;
1134 while (x) {
1135 x >>= 1;
1136 b++;
1137 }
1138 p = b + 1;
1139
1140 ron <<= (11 - p);
1141
1142 n <<= (11 - p);
1143 x = round_div(n, d);
1144 roff = x * (fifo_depth - 4);
1145
1146 if ((ron + m->Rloop) >= roff) {
1147 printk(KERN_ERR "aty128fb: Mode out of range!\n");
1148 return -EINVAL;
1149 }
1150
1151 DBG("p: %x rloop: %x x: %x ron: %x roff: %x\n",
1152 p, m->Rloop, x, ron, roff);
1153
1154 dsp->dda_config = p << 16 | m->Rloop << 20 | x;
1155 dsp->dda_on_off = ron << 16 | roff;
1156
1157 return 0;
1158 }
1159
1160
1161 /*
1162 * This actually sets the video mode.
1163 */
1164 static void
1165 aty128_set_par(struct aty128fb_par *par,
1166 struct fb_info_aty128 *info)
1167 {
1168 u32 config;
1169
1170 info->current_par = *par;
1171
1172 if (info->blitter_may_be_busy)
1173 wait_for_idle(info);
1174
1175 /* clear all registers that may interfere with mode setting */
1176 aty_st_le32(OVR_CLR, 0);
1177 aty_st_le32(OVR_WID_LEFT_RIGHT, 0);
1178 aty_st_le32(OVR_WID_TOP_BOTTOM, 0);
1179 aty_st_le32(OV0_SCALE_CNTL, 0);
1180 aty_st_le32(MPP_TB_CONFIG, 0);
1181 aty_st_le32(MPP_GP_CONFIG, 0);
1182 aty_st_le32(SUBPIC_CNTL, 0);
1183 aty_st_le32(VIPH_CONTROL, 0);
1184 aty_st_le32(I2C_CNTL_1, 0); /* turn off i2c */
1185 aty_st_le32(GEN_INT_CNTL, 0); /* turn off interrupts */
1186 aty_st_le32(CAP0_TRIG_CNTL, 0);
1187 aty_st_le32(CAP1_TRIG_CNTL, 0);
1188
1189 aty_st_8(CRTC_EXT_CNTL + 1, 4); /* turn video off */
1190
1191 aty128_set_crtc(&par->crtc, info);
1192 aty128_set_pll(&par->pll, info);
1193 aty128_set_fifo(&par->fifo_reg, info);
1194
1195 config = aty_ld_le32(CONFIG_CNTL) & ~3;
1196
1197 #if defined(__BIG_ENDIAN)
1198 if (par->crtc.bpp >= 24)
1199 config |= 2; /* make aperture do 32 byte swapping */
1200 else if (par->crtc.bpp > 8)
1201 config |= 1; /* make aperture do 16 byte swapping */
1202 #endif
1203
1204 aty_st_le32(CONFIG_CNTL, config);
1205 aty_st_8(CRTC_EXT_CNTL + 1, 0); /* turn the video back on */
1206
1207 if (par->accel_flags & FB_ACCELF_TEXT)
1208 aty128_init_engine(par, info);
1209
1210 #ifdef CONFIG_FB_COMPAT_XPMAC
1211 if (!console_fb_info || console_fb_info == &info->fb_info) {
1212 struct fb_var_screeninfo var;
1213 int cmode, vmode;
1214
1215 display_info.height = ((par->crtc.v_total >> 16) & 0x7ff) + 1;
1216 display_info.width = (((par->crtc.h_total >> 16) & 0xff) + 1) << 3;
1217 display_info.depth = par->crtc.bpp;
1218 display_info.pitch = (par->crtc.vxres * par->crtc.bpp) >> 3;
1219 aty128_encode_var(&var, par, info);
1220 if (mac_var_to_vmode(&var, &vmode, &cmode))
1221 display_info.mode = 0;
1222 else
1223 display_info.mode = vmode;
1224 strcpy(display_info.name, aty128fb_name);
1225 display_info.fb_address = info->frame_buffer_phys;
1226 display_info.cmap_adr_address = 0;
1227 display_info.cmap_data_address = 0;
1228 display_info.disp_reg_address = info->regbase_phys;
1229 }
1230 #endif /* CONFIG_FB_COMPAT_XPMAC */
1231 }
1232
1233 /*
1234 * encode/decode the User Defined Part of the Display
1235 */
1236
1237 static int
1238 aty128_decode_var(struct fb_var_screeninfo *var, struct aty128fb_par *par,
1239 const struct fb_info_aty128 *info)
1240 {
1241 int err;
1242
1243 if ((err = aty128_var_to_crtc(var, &par->crtc, info)))
1244 return err;
1245
1246 if ((err = aty128_var_to_pll(var->pixclock, &par->pll, info)))
1247 return err;
1248
1249 if ((err = aty128_ddafifo(&par->fifo_reg, &par->pll, par->crtc.bpp, info)))
1250 return err;
1251
1252 if (var->accel_flags & FB_ACCELF_TEXT)
1253 par->accel_flags = FB_ACCELF_TEXT;
1254 else
1255 par->accel_flags = 0;
1256
1257 return 0;
1258 }
1259
1260
1261 static int
1262 aty128_encode_var(struct fb_var_screeninfo *var,
1263 const struct aty128fb_par *par,
1264 const struct fb_info_aty128 *info)
1265 {
1266 int err;
1267
1268 if ((err = aty128_crtc_to_var(&par->crtc, var)))
1269 return err;
1270
1271 if ((err = aty128_pll_to_var(&par->pll, var, info)))
1272 return err;
1273
1274 var->red.msb_right = 0;
1275 var->green.msb_right = 0;
1276 var->blue.msb_right = 0;
1277 var->transp.msb_right = 0;
1278
1279 var->nonstd = 0;
1280 var->activate = 0;
1281
1282 var->height = -1;
1283 var->width = -1;
1284 var->accel_flags = par->accel_flags;
1285
1286 return 0;
1287 }
1288
1289
1290 /*
1291 * Get the User Defined Part of the Display
1292 */
1293
1294 static int
1295 aty128fb_get_var(struct fb_var_screeninfo *var, int con, struct fb_info *fb)
1296 {
1297 const struct fb_info_aty128 *info = (struct fb_info_aty128 *)fb;
1298
1299 if (con == -1)
1300 aty128_encode_var(var, &info->default_par, info);
1301 else
1302 *var = fb_display[con].var;
1303 return 0;
1304 }
1305
1306
1307 /*
1308 * Set the User Defined Part of the Display
1309 */
1310
1311 static int
1312 aty128fb_set_var(struct fb_var_screeninfo *var, int con, struct fb_info *fb)
1313 {
1314 struct fb_info_aty128 *info = (struct fb_info_aty128 *)fb;
1315 struct aty128fb_par par;
1316 struct display *display;
1317 int oldxres, oldyres, oldvxres, oldvyres, oldbpp, oldaccel;
1318 int accel, err;
1319
1320 display = (con >= 0) ? &fb_display[con] : fb->disp;
1321
1322 /* basic (in)sanity checks */
1323 if (!var->xres)
1324 var->xres = 1;
1325 if (!var->yres)
1326 var->yres = 1;
1327 if (var->xres > var->xres_virtual)
1328 var->xres_virtual = var->xres;
1329 if (var->yres > var->yres_virtual)
1330 var->yres_virtual = var->yres;
1331
1332 switch (var->bits_per_pixel) {
1333 case 0 ... 8:
1334 var->bits_per_pixel = 8;
1335 break;
1336 case 9 ... 16:
1337 var->bits_per_pixel = 16;
1338 break;
1339 case 17 ... 24:
1340 var->bits_per_pixel = 24;
1341 break;
1342 case 25 ... 32:
1343 var->bits_per_pixel = 32;
1344 break;
1345 default:
1346 return -EINVAL;
1347 }
1348
1349 if ((err = aty128_decode_var(var, &par, info)))
1350 return err;
1351
1352 aty128_encode_var(var, &par, info);
1353
1354 if ((var->activate & FB_ACTIVATE_MASK) != FB_ACTIVATE_NOW)
1355 return 0;
1356
1357 oldxres = display->var.xres;
1358 oldyres = display->var.yres;
1359 oldvxres = display->var.xres_virtual;
1360 oldvyres = display->var.yres_virtual;
1361 oldbpp = display->var.bits_per_pixel;
1362 oldaccel = display->var.accel_flags;
1363 display->var = *var;
1364 if (oldxres != var->xres || oldyres != var->yres ||
1365 oldvxres != var->xres_virtual || oldvyres != var->yres_virtual ||
1366 oldbpp != var->bits_per_pixel || oldaccel != var->accel_flags) {
1367
1368 struct fb_fix_screeninfo fix;
1369
1370 aty128_encode_fix(&fix, &par, info);
1371 display->screen_base = (char *)info->frame_buffer;
1372 display->visual = fix.visual;
1373 display->type = fix.type;
1374 display->type_aux = fix.type_aux;
1375 display->ypanstep = fix.ypanstep;
1376 display->ywrapstep = fix.ywrapstep;
1377 display->line_length = fix.line_length;
1378 display->can_soft_blank = 1;
1379 display->inverse = 0;
1380
1381 accel = var->accel_flags & FB_ACCELF_TEXT;
1382 aty128_set_disp(display, info, par.crtc.bpp, accel);
1383
1384 if (accel)
1385 display->scrollmode = SCROLL_YNOMOVE;
1386 else
1387 display->scrollmode = SCROLL_YREDRAW;
1388
1389 if (info->fb_info.changevar)
1390 (*info->fb_info.changevar)(con);
1391 }
1392
1393 if (!info->fb_info.display_fg || info->fb_info.display_fg->vc_num == con)
1394 aty128_set_par(&par, info);
1395
1396 if (oldbpp != var->bits_per_pixel) {
1397 if ((err = fb_alloc_cmap(&display->cmap, 0, 0)))
1398 return err;
1399 do_install_cmap(con, &info->fb_info);
1400 }
1401
1402 return 0;
1403 }
1404
1405
1406 static void
1407 aty128_set_disp(struct display *disp,
1408 struct fb_info_aty128 *info, int bpp, int accel)
1409 {
1410 switch (bpp) {
1411 #ifdef FBCON_HAS_CFB8
1412 case 8:
1413 info->dispsw = accel ? fbcon_aty128_8 : fbcon_cfb8;
1414 disp->dispsw = &info->dispsw;
1415 break;
1416 #endif
1417 #ifdef FBCON_HAS_CFB16
1418 case 15:
1419 case 16:
1420 info->dispsw = accel ? fbcon_aty128_16 : fbcon_cfb16;
1421 disp->dispsw = &info->dispsw;
1422 disp->dispsw_data = info->fbcon_cmap.cfb16;
1423 break;
1424 #endif
1425 #ifdef FBCON_HAS_CFB24
1426 case 24:
1427 info->dispsw = accel ? fbcon_aty128_24 : fbcon_cfb24;
1428 disp->dispsw = &info->dispsw;
1429 disp->dispsw_data = info->fbcon_cmap.cfb24;
1430 break;
1431 #endif
1432 #ifdef FBCON_HAS_CFB32
1433 case 32:
1434 info->dispsw = accel ? fbcon_aty128_32 : fbcon_cfb32;
1435 disp->dispsw = &info->dispsw;
1436 disp->dispsw_data = info->fbcon_cmap.cfb32;
1437 break;
1438 #endif
1439 default:
1440 disp->dispsw = &fbcon_dummy;
1441 }
1442 }
1443
1444
1445 static void
1446 aty128_encode_fix(struct fb_fix_screeninfo *fix,
1447 struct aty128fb_par *par,
1448 const struct fb_info_aty128 *info)
1449 {
1450 memset(fix, 0, sizeof(struct fb_fix_screeninfo));
1451
1452 strcpy(fix->id, aty128fb_name);
1453
1454 fix->smem_start = (unsigned long)info->frame_buffer_phys;
1455 fix->mmio_start = (unsigned long)info->regbase_phys;
1456
1457 fix->smem_len = info->vram_size;
1458 fix->mmio_len = 0x1fff;
1459
1460 fix->type = FB_TYPE_PACKED_PIXELS;
1461 fix->type_aux = 0;
1462 fix->line_length = (par->crtc.vxres * par->crtc.bpp) >> 3;
1463 fix->visual = par->crtc.bpp <= 8 ? FB_VISUAL_PSEUDOCOLOR
1464 : FB_VISUAL_DIRECTCOLOR;
1465 fix->ywrapstep = 0;
1466 fix->xpanstep = 8;
1467 fix->ypanstep = 1;
1468
1469 fix->accel = FB_ACCEL_ATI_RAGE128;
1470
1471 return;
1472 }
1473
1474
1475 /*
1476 * Get the Fixed Part of the Display
1477 */
1478 static int
1479 aty128fb_get_fix(struct fb_fix_screeninfo *fix, int con, struct fb_info *fb)
1480 {
1481 const struct fb_info_aty128 *info = (struct fb_info_aty128 *)fb;
1482 struct aty128fb_par par;
1483
1484 if (con == -1)
1485 par = info->default_par;
1486 else
1487 aty128_decode_var(&fb_display[con].var, &par, info);
1488
1489 aty128_encode_fix(fix, &par, info);
1490
1491 return 0;
1492 }
1493
1494
1495 /*
1496 * Pan or Wrap the Display
1497 *
1498 * Not supported (yet!)
1499 */
1500 static int
1501 aty128fb_pan_display(struct fb_var_screeninfo *var, int con,
1502 struct fb_info *fb)
1503 {
1504 struct fb_info_aty128 *info = (struct fb_info_aty128 *)fb;
1505 struct aty128fb_par *par = &info->current_par;
1506 u32 xoffset, yoffset;
1507 u32 offset;
1508 u32 xres, yres;
1509
1510 xres = (((par->crtc.h_total >> 16) & 0xff) + 1) << 3;
1511 yres = ((par->crtc.v_total >> 16) & 0x7ff) + 1;
1512
1513 xoffset = (var->xoffset +7) & ~7;
1514 yoffset = var->yoffset;
1515
1516 if (xoffset+xres > par->crtc.vxres || yoffset+yres > par->crtc.vyres)
1517 return -EINVAL;
1518
1519 par->crtc.xoffset = xoffset;
1520 par->crtc.yoffset = yoffset;
1521
1522 offset = ((yoffset * par->crtc.vxres + xoffset) * par->crtc.bpp) >> 6;
1523
1524 aty_st_le32(CRTC_OFFSET, offset);
1525
1526 return 0;
1527 }
1528
1529
1530 /*
1531 * Get the Colormap
1532 */
1533
1534 static int
1535 aty128fb_get_cmap(struct fb_cmap *cmap, int kspc, int con,
1536 struct fb_info *info)
1537 {
1538 #if 1
1539 fb_copy_cmap(&info->cmap, cmap, kspc ? 0 : 2);
1540 #else
1541 struct fb_info_aty128 fb = (struct fb_info_aty128 *)info;
1542
1543 if (con == fb->currcon) /* current console? */
1544 return fb_get_cmap(cmap, kspc, aty128_getcolreg, info);
1545 else if (fb_display[con].cmap.len) /* non default colormap? */
1546 fb_copy_cmap(&fb_display[con].cmap, cmap, kspc ? 0 : 2);
1547 else {
1548 int size = (fb_display[con].var.bits_per_pixel <= 8) ? 256 : 32;
1549 fb_copy_cmap(fb_default_cmap(size), cmap, kspc ? 0 : 2);
1550 }
1551 #endif
1552
1553 return 0;
1554 }
1555
1556 /*
1557 * Set the Colormap
1558 */
1559
1560 static int
1561 aty128fb_set_cmap(struct fb_cmap *cmap, int kspc, int con,
1562 struct fb_info *info)
1563 {
1564 int err;
1565 struct fb_info_aty128 *fb = (struct fb_info_aty128 *)info;
1566 struct display *disp;
1567
1568 if (con >= 0)
1569 disp = &fb_display[con];
1570 else
1571 disp = info->disp;
1572
1573 if (!disp->cmap.len) { /* no colormap allocated? */
1574 int size = (disp->var.bits_per_pixel <= 8) ? 256 : 32;
1575 if ((err = fb_alloc_cmap(&disp->cmap, size, 0)))
1576 return err;
1577 }
1578
1579 if (con == fb->currcon) /* current console? */
1580 return fb_set_cmap(cmap, kspc, aty128_setcolreg, info);
1581 else
1582 fb_copy_cmap(cmap, &disp->cmap, kspc ? 0 : 1);
1583
1584 return 0;
1585 }
1586
1587
1588 static int
1589 aty128fb_rasterimg(struct fb_info *info, int start)
1590 {
1591 struct fb_info_aty128 *fb = (struct fb_info_aty128 *)info;
1592
1593 if (fb->blitter_may_be_busy)
1594 wait_for_idle(fb);
1595
1596 return 0;
1597 }
1598
1599
1600 #ifndef MODULE
1601 int __init
1602 aty128fb_setup(char *options)
1603 {
1604 char *this_opt;
1605
1606 if (!options || !*options)
1607 return 0;
1608
1609 for (this_opt = strtok(options, ","); this_opt;
1610 this_opt = strtok(NULL, ",")) {
1611 if (!strncmp(this_opt, "font:", 5)) {
1612 char *p;
1613 int i;
1614
1615 p = this_opt +5;
1616 for (i = 0; i < sizeof(fontname) - 1; i++)
1617 if (!*p || *p == ' ' || *p == ',')
1618 break;
1619 memcpy(fontname, this_opt + 5, i);
1620 fontname[i] = 0;
1621 } else if (!strncmp(this_opt, "noaccel", 7)) {
1622 noaccel = 1;
1623 }
1624 #ifdef CONFIG_MTRR
1625 else if(!strncmp(this_opt, "nomtrr", 6)) {
1626 mtrr = 0;
1627 }
1628 #endif
1629 #ifdef CONFIG_PPC
1630 /* vmode and cmode depreciated */
1631 else if (!strncmp(this_opt, "vmode:", 6)) {
1632 unsigned int vmode = simple_strtoul(this_opt+6, NULL, 0);
1633 if (vmode > 0 && vmode <= VMODE_MAX)
1634 default_vmode = vmode;
1635 } else if (!strncmp(this_opt, "cmode:", 6)) {
1636 unsigned int cmode = simple_strtoul(this_opt+6, NULL, 0);
1637 switch (cmode) {
1638 case 0:
1639 case 8:
1640 default_cmode = CMODE_8;
1641 break;
1642 case 15:
1643 case 16:
1644 default_cmode = CMODE_16;
1645 break;
1646 case 24:
1647 case 32:
1648 default_cmode = CMODE_32;
1649 break;
1650 }
1651 }
1652 #endif /* CONFIG_PPC */
1653 else
1654 mode_option = this_opt;
1655 }
1656 return 0;
1657 }
1658 #endif /* !MODULE */
1659
1660
1661 /*
1662 * Initialisation
1663 */
1664
1665 static int __init
1666 aty128_init(struct fb_info_aty128 *info, const char *name)
1667 {
1668 struct fb_var_screeninfo var;
1669 u32 dac;
1670 int j, k;
1671 u8 chip_rev;
1672 const struct aty128_chip_info *aci = &aty128_pci_probe_list[0];
1673 char *video_card = "Rage128";
1674
1675 if (!info->vram_size) /* may have already been probed */
1676 info->vram_size = aty_ld_le32(CONFIG_MEMSIZE) & 0x03FFFFFF;
1677
1678 /* Get the chip revision */
1679 chip_rev = (aty_ld_le32(CONFIG_CNTL) >> 16) & 0x1F;
1680
1681 /* put a name with the face */
1682 while (aci->name && info->pdev->device != aci->device) { aci++; }
1683 video_card = (char *)aci->name;
1684 info->chip_gen = aci->chip_gen;
1685
1686 printk(KERN_INFO "aty128fb: %s [chip rev 0x%x] ", video_card, chip_rev);
1687
1688 if (info->vram_size % (1024 * 1024) == 0)
1689 printk("%dM %s\n", info->vram_size / (1024*1024), info->mem->name);
1690 else
1691 printk("%dk %s\n", info->vram_size / 1024, info->mem->name);
1692
1693 /* fill in info */
1694 strcpy(info->fb_info.modename, aty128fb_name);
1695 info->fb_info.node = -1;
1696 info->fb_info.fbops = &aty128fb_ops;
1697 info->fb_info.disp = &info->disp;
1698 strcpy(info->fb_info.fontname, fontname);
1699 info->fb_info.changevar = NULL;
1700 info->fb_info.switch_con = &aty128fbcon_switch;
1701 info->fb_info.updatevar = NULL;
1702 info->fb_info.blank = &aty128fbcon_blank;
1703 info->fb_info.flags = FBINFO_FLAG_DEFAULT;
1704
1705 #ifdef MODULE
1706 var = default_var;
1707 #else
1708 memset(&var, 0, sizeof(var));
1709 #ifdef CONFIG_PPC
1710 if (_machine == _MACH_Pmac) {
1711 if (mode_option) {
1712 if (!mac_find_mode(&var, &info->fb_info, mode_option, 8))
1713 var = default_var;
1714 } else {
1715 #ifdef CONFIG_NVRAM
1716 if (default_vmode == VMODE_NVRAM)
1717 default_vmode = nvram_read_byte(NV_VMODE);
1718
1719 if (default_cmode == CMODE_NVRAM)
1720 default_cmode = nvram_read_byte(NV_CMODE);
1721 #endif
1722 if (default_vmode <= 0 || default_vmode > VMODE_MAX)
1723 default_vmode = VMODE_640_480_60;
1724
1725 if (default_cmode < CMODE_8 || default_cmode > CMODE_32)
1726 default_cmode = CMODE_8;
1727
1728 if (mac_vmode_to_var(default_vmode, default_cmode, &var))
1729 var = default_var;
1730 }
1731 } else
1732 #endif /* CONFIG_PPC */
1733 {
1734 if (fb_find_mode(&var, &info->fb_info, mode_option, NULL, 0,
1735 &defaultmode, 8) == 0)
1736 var = default_var;
1737 }
1738 #endif /* MODULE */
1739
1740 if (noaccel)
1741 var.accel_flags &= ~FB_ACCELF_TEXT;
1742 else
1743 var.accel_flags |= FB_ACCELF_TEXT;
1744
1745 if (aty128_decode_var(&var, &info->default_par, info)) {
1746 printk(KERN_ERR "aty128fb: Cannot set default mode.\n");
1747 return 0;
1748 }
1749
1750 /* load up the palette with default colors */
1751 for (j = 0; j < 16; j++) {
1752 k = color_table[j];
1753 info->palette[j].red = default_red[k];
1754 info->palette[j].green = default_grn[k];
1755 info->palette[j].blue = default_blu[k];
1756 }
1757
1758 /* setup the DAC the way we like it */
1759 dac = aty_ld_le32(DAC_CNTL);
1760 dac |= (DAC_8BIT_EN | DAC_RANGE_CNTL);
1761 dac |= DAC_MASK;
1762 aty_st_le32(DAC_CNTL, dac);
1763
1764 /* turn off bus mastering, just in case */
1765 aty_st_le32(BUS_CNTL, aty_ld_le32(BUS_CNTL) | BUS_MASTER_DIS);
1766
1767 aty128fb_set_var(&var, -1, &info->fb_info);
1768 aty128_init_engine(&info->default_par, info);
1769
1770 board_list = aty128_board_list_add(board_list, info);
1771
1772 if (register_framebuffer(&info->fb_info) < 0)
1773 return 0;
1774
1775 printk(KERN_INFO "fb%d: %s frame buffer device on %s\n",
1776 GET_FB_IDX(info->fb_info.node), aty128fb_name, name);
1777
1778 return 1; /* success! */
1779 }
1780
1781
1782 /* add a new card to the list ++ajoshi */
1783 static struct
1784 fb_info_aty128 *aty128_board_list_add(struct fb_info_aty128 *board_list,
1785 struct fb_info_aty128 *new_node)
1786 {
1787 struct fb_info_aty128 *i_p = board_list;
1788
1789 new_node->next = NULL;
1790 if(board_list == NULL)
1791 return new_node;
1792 while(i_p->next != NULL)
1793 i_p = i_p->next;
1794 i_p->next = new_node;
1795
1796 return board_list;
1797 }
1798
1799
1800 int __init
1801 aty128fb_init(void)
1802 {
1803 #ifdef CONFIG_PCI
1804 struct pci_dev *pdev = NULL;
1805 const struct aty128_chip_info *aci = &aty128_pci_probe_list[0];
1806
1807 while (aci->name != NULL) {
1808 pdev = pci_find_device(PCI_VENDOR_ID_ATI, aci->device, pdev);
1809 while (pdev != NULL) {
1810 if (aty128_pci_register(pdev, aci) == 0)
1811 return 0;
1812 pdev = pci_find_device(PCI_VENDOR_ID_ATI, aci->device, pdev);
1813 }
1814 aci++;
1815 }
1816 #endif
1817
1818 return 0;
1819 }
1820
1821
1822 #ifdef CONFIG_PCI
1823 /* register a card ++ajoshi */
1824 static int __init
1825 aty128_pci_register(struct pci_dev *pdev,
1826 const struct aty128_chip_info *aci)
1827 {
1828 struct fb_info_aty128 *info = NULL;
1829 u32 fb_addr, reg_addr;
1830 int err;
1831 #if !defined(CONFIG_PPC) && !defined(__sparc__)
1832 char *bios_seg = NULL;
1833 #endif
1834
1835 /* Enable device in PCI config */
1836 if ((err = pci_enable_device(pdev))) {
1837 printk(KERN_ERR "aty128fb: Cannot enable PCI device: %d\n",
1838 err);
1839 goto err_out;
1840 }
1841
1842 fb_addr = pci_resource_start(pdev, 0);
1843 if (!request_mem_region(fb_addr, pci_resource_len(pdev, 0),
1844 "aty128fb FB")) {
1845 printk(KERN_ERR "aty128fb: cannot reserve frame "
1846 "buffer memory\n");
1847 goto err_free_fb;
1848 }
1849
1850 reg_addr = pci_resource_start(pdev, 2);
1851 if (!request_mem_region(reg_addr, pci_resource_len(pdev, 2),
1852 "aty128fb MMIO")) {
1853 printk(KERN_ERR "aty128fb: cannot reserve MMIO region\n");
1854 goto err_free_mmio;
1855 }
1856
1857 /* We have the resources. Now virtualize them */
1858 if (!(info = kmalloc(sizeof(struct fb_info_aty128), GFP_ATOMIC))) {
1859 printk(KERN_ERR "aty128fb: can't alloc fb_info_aty128\n");
1860 goto err_unmap_out;
1861 }
1862 memset(info, 0, sizeof(struct fb_info_aty128));
1863
1864 /* Copy PCI device info into info->pdev */
1865 info->pdev = pdev;
1866
1867 info->currcon = -1;
1868
1869 /* Virtualize mmio region */
1870 info->regbase_phys = reg_addr;
1871 info->regbase = ioremap(reg_addr, 0x1FFF);
1872
1873 if (!info->regbase)
1874 goto err_free_info;
1875
1876 /* Grab memory size from the card */
1877 info->vram_size = aty_ld_le32(CONFIG_MEMSIZE) & 0x03FFFFFF;
1878
1879 /* Virtualize the framebuffer */
1880 info->frame_buffer_phys = fb_addr;
1881 info->frame_buffer = (u32)ioremap(fb_addr, info->vram_size);
1882
1883 if (!info->frame_buffer) {
1884 iounmap((void *)info->regbase);
1885 goto err_free_info;
1886 }
1887
1888 /* If we can't test scratch registers, something is seriously wrong */
1889 if (!register_test(info)) {
1890 printk(KERN_ERR "aty128fb: Can't write to video register!\n");
1891 goto err_out;
1892 }
1893
1894 #if !defined(CONFIG_PPC) && !defined(__sparc__)
1895 if (!(bios_seg = aty128find_ROM(info)))
1896 printk(KERN_INFO "aty128fb: Rage128 BIOS not located. "
1897 "Guessing...\n");
1898 else {
1899 printk(KERN_INFO "aty128fb: Rage128 BIOS located at "
1900 "segment %4.4X\n", (unsigned int)bios_seg);
1901 aty128_get_pllinfo(info, bios_seg);
1902 }
1903 #endif
1904 aty128_timings(info);
1905
1906 if (!aty128_init(info, "PCI"))
1907 goto err_out;
1908
1909 #ifdef CONFIG_MTRR
1910 if (mtrr) {
1911 info->mtrr.vram = mtrr_add(info->frame_buffer_phys,
1912 info->vram_size, MTRR_TYPE_WRCOMB, 1);
1913 info->mtrr.vram_valid = 1;
1914 /* let there be speed */
1915 printk(KERN_INFO "aty128fb: Rage128 MTRR set to ON\n");
1916 }
1917 #endif /* CONFIG_MTRR */
1918
1919 return 0;
1920
1921 err_out:
1922 iounmap((void *)info->frame_buffer);
1923 iounmap((void *)info->regbase);
1924 err_free_info:
1925 kfree(info);
1926 err_unmap_out:
1927 release_mem_region(pci_resource_start(pdev, 2),
1928 pci_resource_len(pdev, 2));
1929 err_free_mmio:
1930 release_mem_region(pci_resource_start(pdev, 0),
1931 pci_resource_len(pdev, 0));
1932 err_free_fb:
1933 release_mem_region(pci_resource_start(pdev, 1),
1934 pci_resource_len(pdev, 1));
1935 return -ENODEV;
1936 }
1937 #endif /* CONFIG_PCI */
1938
1939
1940 /* PPC and Sparc cannot read video ROM */
1941 #if !defined(CONFIG_PPC) && !defined(__sparc__)
1942 static char __init
1943 *aty128find_ROM(struct fb_info_aty128 *info)
1944 {
1945 u32 segstart;
1946 char *rom_base;
1947 char *rom;
1948 int stage;
1949 int i;
1950 char aty_rom_sig[] = "761295520"; /* ATI ROM Signature */
1951 char R128_sig[] = "R128"; /* Rage128 ROM identifier */
1952
1953 for (segstart=0x000c0000; segstart<0x000f0000; segstart+=0x00001000) {
1954 stage = 1;
1955
1956 rom_base = (char *)ioremap(segstart, 0x1000);
1957
1958 if ((*rom_base == 0x55) && (((*(rom_base + 1)) & 0xff) == 0xaa))
1959 stage = 2;
1960
1961 if (stage != 2) {
1962 iounmap(rom_base);
1963 continue;
1964 }
1965 rom = rom_base;
1966
1967 for (i = 0; (i < 128 - strlen(aty_rom_sig)) && (stage != 3); i++) {
1968 if (aty_rom_sig[0] == *rom)
1969 if (strncmp(aty_rom_sig, rom,
1970 strlen(aty_rom_sig)) == 0)
1971 stage = 3;
1972 rom++;
1973 }
1974 if (stage != 3) {
1975 iounmap(rom_base);
1976 continue;
1977 }
1978 rom = rom_base;
1979
1980 /* ATI signature found. Let's see if it's a Rage128 */
1981 for (i = 0; (i < 512) && (stage != 4); i++) {
1982 if (R128_sig[0] == *rom)
1983 if (strncmp(R128_sig, rom,
1984 strlen(R128_sig)) == 0)
1985 stage = 4;
1986 rom++;
1987 }
1988 if (stage != 4) {
1989 iounmap(rom_base);
1990 continue;
1991 }
1992
1993 return rom_base;
1994 }
1995
1996 return NULL;
1997 }
1998
1999
2000 static void __init
2001 aty128_get_pllinfo(struct fb_info_aty128 *info, char *bios_seg)
2002 {
2003 void *bios_header;
2004 void *header_ptr;
2005 u16 bios_header_offset, pll_info_offset;
2006 PLL_BLOCK pll;
2007
2008 bios_header = bios_seg + 0x48L;
2009 header_ptr = bios_header;
2010
2011 bios_header_offset = readw(header_ptr);
2012 bios_header = bios_seg + bios_header_offset;
2013 bios_header += 0x30;
2014
2015 header_ptr = bios_header;
2016 pll_info_offset = readw(header_ptr);
2017 header_ptr = bios_seg + pll_info_offset;
2018
2019 memcpy_fromio(&pll, header_ptr, 50);
2020
2021 info->constants.ppll_max = pll.PCLK_max_freq;
2022 info->constants.ppll_min = pll.PCLK_min_freq;
2023 info->constants.xclk = (u32)pll.XCLK;
2024 info->constants.ref_divider = (u32)pll.PCLK_ref_divider;
2025 info->constants.dotclock = (u32)pll.PCLK_ref_freq;
2026
2027 DBG("ppll_max %d ppll_min %d xclk %d ref_divider %d dotclock %d\n",
2028 info->constants.ppll_max, info->constants.ppll_min,
2029 info->constants.xclk, info->constants.ref_divider,
2030 info->constants.dotclock);
2031
2032 }
2033 #endif /* !CONFIG_PPC */
2034
2035
2036 /* fill in known card constants if pll_block is not available */
2037 static void __init
2038 aty128_timings(struct fb_info_aty128 *info)
2039 {
2040 #ifdef CONFIG_PPC
2041 /* instead of a table lookup, assume OF has properly
2042 * setup the PLL registers and use their values
2043 * to set the XCLK values and reference divider values */
2044
2045 u32 x_mpll_ref_fb_div;
2046 u32 xclk_cntl;
2047 u32 Nx, M;
2048 unsigned PostDivSet[] =
2049 { 0, 1, 2, 4, 8, 3, 6, 12 };
2050 #endif
2051
2052 if (!info->constants.dotclock)
2053 info->constants.dotclock = 2950;
2054
2055 #ifdef CONFIG_PPC
2056 x_mpll_ref_fb_div = aty_ld_pll(X_MPLL_REF_FB_DIV);
2057 xclk_cntl = aty_ld_pll(XCLK_CNTL) & 0x7;
2058 Nx = (x_mpll_ref_fb_div & 0x00ff00) >> 8;
2059 M = x_mpll_ref_fb_div & 0x0000ff;
2060
2061 info->constants.xclk = round_div((2 * Nx *
2062 info->constants.dotclock), (M * PostDivSet[xclk_cntl]));
2063
2064 info->constants.ref_divider =
2065 aty_ld_pll(PPLL_REF_DIV) & PPLL_REF_DIV_MASK;
2066 #endif
2067
2068 if (!info->constants.ref_divider) {
2069 info->constants.ref_divider = 0x3b;
2070
2071 aty_st_pll(X_MPLL_REF_FB_DIV, 0x004c4c1e);
2072 aty_pll_writeupdate(info);
2073 }
2074 aty_st_pll(PPLL_REF_DIV, info->constants.ref_divider);
2075 aty_pll_writeupdate(info);
2076
2077 /* from documentation */
2078 if (!info->constants.ppll_min)
2079 info->constants.ppll_min = 12500;
2080 if (!info->constants.ppll_max)
2081 info->constants.ppll_max = 25000; /* 23000 on some cards? */
2082 if (!info->constants.xclk)
2083 info->constants.xclk = 0x1d4d; /* same as mclk */
2084
2085 info->constants.fifo_width = 128;
2086 info->constants.fifo_depth = 32;
2087
2088 switch (aty_ld_le32(MEM_CNTL) & 0x3) {
2089 case 0:
2090 info->mem = &sdr_128;
2091 break;
2092 case 1:
2093 info->mem = &sdr_sgram;
2094 break;
2095 case 2:
2096 info->mem = &ddr_sgram;
2097 break;
2098 default:
2099 info->mem = &sdr_sgram;
2100 }
2101 }
2102
2103
2104 static int
2105 aty128fbcon_switch(int con, struct fb_info *fb)
2106 {
2107 struct fb_info_aty128 *info = (struct fb_info_aty128 *)fb;
2108 struct aty128fb_par par;
2109
2110 /* Do we have to save the colormap? */
2111 if (fb_display[info->currcon].cmap.len)
2112 fb_get_cmap(&fb_display[info->currcon].cmap, 1,
2113 aty128_getcolreg, fb);
2114
2115 /* set the current console */
2116 info->currcon = con;
2117
2118 aty128_decode_var(&fb_display[con].var, &par, info);
2119 aty128_set_par(&par, info);
2120
2121 aty128_set_disp(&fb_display[con], info, par.crtc.bpp,
2122 par.accel_flags & FB_ACCELF_TEXT);
2123
2124 do_install_cmap(con, fb);
2125
2126 return 1;
2127 }
2128
2129
2130 /*
2131 * Blank the display.
2132 */
2133 static void
2134 aty128fbcon_blank(int blank, struct fb_info *fb)
2135 {
2136 struct fb_info_aty128 *info = (struct fb_info_aty128 *)fb;
2137 u8 state = 0;
2138
2139 if (blank & VESA_VSYNC_SUSPEND)
2140 state |= 2;
2141 if (blank & VESA_HSYNC_SUSPEND)
2142 state |= 1;
2143 if (blank & VESA_POWERDOWN)
2144 state |= 4;
2145
2146 aty_st_8(CRTC_EXT_CNTL+1, state);
2147 }
2148
2149
2150 /*
2151 * Read a single color register and split it into
2152 * colors/transparent. Return != 0 for invalid regno.
2153 */
2154 static int
2155 aty128_getcolreg(u_int regno, u_int *red, u_int *green, u_int *blue,
2156 u_int *transp, struct fb_info *fb)
2157 {
2158 struct fb_info_aty128 *info = (struct fb_info_aty128 *) fb;
2159
2160 if (regno > 255)
2161 return 1;
2162
2163 *red = (info->palette[regno].red<<8) | info->palette[regno].red;
2164 *green = (info->palette[regno].green<<8) | info->palette[regno].green;
2165 *blue = (info->palette[regno].blue<<8) | info->palette[regno].blue;
2166 *transp = 0;
2167
2168 return 0;
2169 }
2170
2171 /*
2172 * Set a single color register. The values supplied are already
2173 * rounded down to the hardware's capabilities (according to the
2174 * entries in the var structure). Return != 0 for invalid regno.
2175 */
2176 static int
2177 aty128_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
2178 u_int transp, struct fb_info *fb)
2179 {
2180 struct fb_info_aty128 *info = (struct fb_info_aty128 *)fb;
2181 u32 col;
2182
2183 if (regno > 255)
2184 return 1;
2185
2186 red >>= 8;
2187 green >>= 8;
2188 blue >>= 8;
2189 info->palette[regno].red = red;
2190 info->palette[regno].green = green;
2191 info->palette[regno].blue = blue;
2192
2193 /* Note: For now, on M3, we set palette on both heads, which may
2194 * be useless. Can someone with a M3 check this ? */
2195
2196 /* initialize gamma ramp for hi-color+ */
2197
2198 if ((info->current_par.crtc.bpp > 8) && (regno == 0)) {
2199 int i;
2200
2201 if (info->chip_gen == rage_M3)
2202 aty_st_le32(DAC_CNTL, aty_ld_le32(DAC_CNTL) & ~PALETTE_ACCESS_CNTL);
2203
2204 for (i=16; i<256; i++) {
2205 aty_st_8(PALETTE_INDEX, i);
2206 col = (i << 16) | (i << 8) | i;
2207 aty_st_le32(PALETTE_DATA, col);
2208 }
2209
2210 if (info->chip_gen == rage_M3) {
2211 aty_st_le32(DAC_CNTL, aty_ld_le32(DAC_CNTL) | PALETTE_ACCESS_CNTL);
2212
2213 for (i=16; i<256; i++) {
2214 aty_st_8(PALETTE_INDEX, i);
2215 col = (i << 16) | (i << 8) | i;
2216 aty_st_le32(PALETTE_DATA, col);
2217 }
2218 }
2219 }
2220
2221 /* initialize palette */
2222
2223 if (info->chip_gen == rage_M3)
2224 aty_st_le32(DAC_CNTL, aty_ld_le32(DAC_CNTL) & ~PALETTE_ACCESS_CNTL);
2225
2226 if (info->current_par.crtc.bpp == 16)
2227 aty_st_8(PALETTE_INDEX, (regno << 3));
2228 else
2229 aty_st_8(PALETTE_INDEX, regno);
2230 col = (red << 16) | (green << 8) | blue;
2231 aty_st_le32(PALETTE_DATA, col);
2232 if (info->chip_gen == rage_M3) {
2233 aty_st_le32(DAC_CNTL, aty_ld_le32(DAC_CNTL) | PALETTE_ACCESS_CNTL);
2234 if (info->current_par.crtc.bpp == 16)
2235 aty_st_8(PALETTE_INDEX, (regno << 3));
2236 else
2237 aty_st_8(PALETTE_INDEX, regno);
2238 aty_st_le32(PALETTE_DATA, col);
2239 }
2240
2241 if (regno < 16)
2242 switch (info->current_par.crtc.bpp) {
2243 #ifdef FBCON_HAS_CFB16
2244 case 9 ... 16:
2245 info->fbcon_cmap.cfb16[regno] = (regno << 10) | (regno << 5) |
2246 regno;
2247 break;
2248 #endif
2249 #ifdef FBCON_HAS_CFB24
2250 case 17 ... 24:
2251 info->fbcon_cmap.cfb24[regno] = (regno << 16) | (regno << 8) |
2252 regno;
2253 break;
2254 #endif
2255 #ifdef FBCON_HAS_CFB32
2256 case 25 ... 32: {
2257 u32 i;
2258
2259 i = (regno << 8) | regno;
2260 info->fbcon_cmap.cfb32[regno] = (i << 16) | i;
2261 break;
2262 }
2263 #endif
2264 }
2265 return 0;
2266 }
2267
2268
2269 static void
2270 do_install_cmap(int con, struct fb_info *info)
2271 {
2272 struct fb_info_aty128 *fb = (struct fb_info_aty128 *)info;
2273
2274 if (con != fb->currcon)
2275 return;
2276
2277 if (fb_display[con].cmap.len)
2278 fb_set_cmap(&fb_display[con].cmap, 1, aty128_setcolreg, info);
2279 else {
2280 int size = (fb_display[con].var.bits_per_pixel <= 8) ? 256 : 16;
2281 fb_set_cmap(fb_default_cmap(size), 1, aty128_setcolreg, info);
2282 }
2283 }
2284
2285
2286 /*
2287 * Accelerated functions
2288 */
2289
2290 static inline void
2291 aty128_rectcopy(int srcx, int srcy, int dstx, int dsty,
2292 u_int width, u_int height,
2293 struct fb_info_aty128 *info)
2294 {
2295 u32 save_dp_datatype, save_dp_cntl, bppval;
2296
2297 if (!width || !height)
2298 return;
2299
2300 bppval = bpp_to_depth(info->current_par.crtc.bpp);
2301 if (bppval == DST_24BPP) {
2302 srcx *= 3;
2303 dstx *= 3;
2304 width *= 3;
2305 } else if (bppval == -EINVAL) {
2306 printk("aty128fb: invalid depth\n");
2307 return;
2308 }
2309
2310 wait_for_fifo(2, info);
2311 save_dp_datatype = aty_ld_le32(DP_DATATYPE);
2312 save_dp_cntl = aty_ld_le32(DP_CNTL);
2313
2314 wait_for_fifo(6, info);
2315 aty_st_le32(SRC_Y_X, (srcy << 16) | srcx);
2316 aty_st_le32(DP_MIX, ROP3_SRCCOPY | DP_SRC_RECT);
2317 aty_st_le32(DP_CNTL, DST_X_LEFT_TO_RIGHT | DST_Y_TOP_TO_BOTTOM);
2318 aty_st_le32(DP_DATATYPE, save_dp_datatype | bppval | SRC_DSTCOLOR);
2319
2320 aty_st_le32(DST_Y_X, (dsty << 16) | dstx);
2321 aty_st_le32(DST_HEIGHT_WIDTH, (height << 16) | width);
2322
2323 info->blitter_may_be_busy = 1;
2324
2325 wait_for_fifo(2, info);
2326 aty_st_le32(DP_DATATYPE, save_dp_datatype);
2327 aty_st_le32(DP_CNTL, save_dp_cntl);
2328 }
2329
2330
2331 /*
2332 * Text mode accelerated functions
2333 */
2334
2335 static void
2336 fbcon_aty128_bmove(struct display *p, int sy, int sx, int dy, int dx,
2337 int height, int width)
2338 {
2339 sx *= fontwidth(p);
2340 sy *= fontheight(p);
2341 dx *= fontwidth(p);
2342 dy *= fontheight(p);
2343 width *= fontwidth(p);
2344 height *= fontheight(p);
2345
2346 aty128_rectcopy(sx, sy, dx, dy, width, height,
2347 (struct fb_info_aty128 *)p->fb_info);
2348 }
2349
2350
2351 #ifdef FBCON_HAS_CFB8
2352 static void fbcon_aty8_putc(struct vc_data *conp, struct display *p,
2353 int c, int yy, int xx)
2354 {
2355 struct fb_info_aty128 *fb = (struct fb_info_aty128 *)(p->fb_info);
2356
2357 if (fb->blitter_may_be_busy)
2358 wait_for_idle(fb);
2359
2360 fbcon_cfb8_putc(conp, p, c, yy, xx);
2361 }
2362
2363
2364 static void fbcon_aty8_putcs(struct vc_data *conp, struct display *p,
2365 const unsigned short *s, int count,
2366 int yy, int xx)
2367 {
2368 struct fb_info_aty128 *fb = (struct fb_info_aty128 *)(p->fb_info);
2369
2370 if (fb->blitter_may_be_busy)
2371 wait_for_idle(fb);
2372
2373 fbcon_cfb8_putcs(conp, p, s, count, yy, xx);
2374 }
2375
2376
2377 static void fbcon_aty8_clear_margins(struct vc_data *conp,
2378 struct display *p, int bottom_only)
2379 {
2380 struct fb_info_aty128 *fb = (struct fb_info_aty128 *)(p->fb_info);
2381
2382 if (fb->blitter_may_be_busy)
2383 wait_for_idle(fb);
2384
2385 fbcon_cfb8_clear_margins(conp, p, bottom_only);
2386 }
2387
2388 static struct display_switch fbcon_aty128_8 = {
2389 setup: fbcon_cfb8_setup,
2390 bmove: fbcon_aty128_bmove,
2391 clear: fbcon_cfb8_clear,
2392 putc: fbcon_aty8_putc,
2393 putcs: fbcon_aty8_putcs,
2394 revc: fbcon_cfb8_revc,
2395 clear_margins: fbcon_aty8_clear_margins,
2396 fontwidthmask: FONTWIDTH(4)|FONTWIDTH(8)|FONTWIDTH(12)|FONTWIDTH(16)
2397 };
2398 #endif
2399 #ifdef FBCON_HAS_CFB16
2400 static void fbcon_aty16_putc(struct vc_data *conp, struct display *p,
2401 int c, int yy, int xx)
2402 {
2403 struct fb_info_aty128 *fb = (struct fb_info_aty128 *)(p->fb_info);
2404
2405 if (fb->blitter_may_be_busy)
2406 wait_for_idle(fb);
2407
2408 fbcon_cfb16_putc(conp, p, c, yy, xx);
2409 }
2410
2411
2412 static void fbcon_aty16_putcs(struct vc_data *conp, struct display *p,
2413 const unsigned short *s, int count,
2414 int yy, int xx)
2415 {
2416 struct fb_info_aty128 *fb = (struct fb_info_aty128 *)(p->fb_info);
2417
2418 if (fb->blitter_may_be_busy)
2419 wait_for_idle(fb);
2420
2421 fbcon_cfb16_putcs(conp, p, s, count, yy, xx);
2422 }
2423
2424
2425 static void fbcon_aty16_clear_margins(struct vc_data *conp,
2426 struct display *p, int bottom_only)
2427 {
2428 struct fb_info_aty128 *fb = (struct fb_info_aty128 *)(p->fb_info);
2429
2430 if (fb->blitter_may_be_busy)
2431 wait_for_idle(fb);
2432
2433 fbcon_cfb16_clear_margins(conp, p, bottom_only);
2434 }
2435
2436 static struct display_switch fbcon_aty128_16 = {
2437 setup: fbcon_cfb16_setup,
2438 bmove: fbcon_aty128_bmove,
2439 clear: fbcon_cfb16_clear,
2440 putc: fbcon_aty16_putc,
2441 putcs: fbcon_aty16_putcs,
2442 revc: fbcon_cfb16_revc,
2443 clear_margins: fbcon_aty16_clear_margins,
2444 fontwidthmask: FONTWIDTH(4)|FONTWIDTH(8)|FONTWIDTH(12)|FONTWIDTH(16)
2445 };
2446 #endif
2447 #ifdef FBCON_HAS_CFB24
2448 static void fbcon_aty24_putc(struct vc_data *conp, struct display *p,
2449 int c, int yy, int xx)
2450 {
2451 struct fb_info_aty128 *fb = (struct fb_info_aty128 *)(p->fb_info);
2452
2453 if (fb->blitter_may_be_busy)
2454 wait_for_idle(fb);
2455
2456 fbcon_cfb24_putc(conp, p, c, yy, xx);
2457 }
2458
2459
2460 static void fbcon_aty24_putcs(struct vc_data *conp, struct display *p,
2461 const unsigned short *s, int count,
2462 int yy, int xx)
2463 {
2464 struct fb_info_aty128 *fb = (struct fb_info_aty128 *)(p->fb_info);
2465
2466 if (fb->blitter_may_be_busy)
2467 wait_for_idle(fb);
2468
2469 fbcon_cfb24_putcs(conp, p, s, count, yy, xx);
2470 }
2471
2472
2473 static void fbcon_aty24_clear_margins(struct vc_data *conp,
2474 struct display *p, int bottom_only)
2475 {
2476 struct fb_info_aty128 *fb = (struct fb_info_aty128 *)(p->fb_info);
2477
2478 if (fb->blitter_may_be_busy)
2479 wait_for_idle(fb);
2480
2481 fbcon_cfb24_clear_margins(conp, p, bottom_only);
2482 }
2483
2484 static struct display_switch fbcon_aty128_24 = {
2485 setup: fbcon_cfb24_setup,
2486 bmove: fbcon_aty128_bmove,
2487 clear: fbcon_cfb24_clear,
2488 putc: fbcon_aty24_putc,
2489 putcs: fbcon_aty24_putcs,
2490 revc: fbcon_cfb24_revc,
2491 clear_margins: fbcon_aty24_clear_margins,
2492 fontwidthmask: FONTWIDTH(4)|FONTWIDTH(8)|FONTWIDTH(12)|FONTWIDTH(16)
2493 };
2494 #endif
2495 #ifdef FBCON_HAS_CFB32
2496 static void fbcon_aty32_putc(struct vc_data *conp, struct display *p,
2497 int c, int yy, int xx)
2498 {
2499 struct fb_info_aty128 *fb = (struct fb_info_aty128 *)(p->fb_info);
2500
2501 if (fb->blitter_may_be_busy)
2502 wait_for_idle(fb);
2503
2504 fbcon_cfb32_putc(conp, p, c, yy, xx);
2505 }
2506
2507
2508 static void fbcon_aty32_putcs(struct vc_data *conp, struct display *p,
2509 const unsigned short *s, int count,
2510 int yy, int xx)
2511 {
2512 struct fb_info_aty128 *fb = (struct fb_info_aty128 *)(p->fb_info);
2513
2514 if (fb->blitter_may_be_busy)
2515 wait_for_idle(fb);
2516
2517 fbcon_cfb32_putcs(conp, p, s, count, yy, xx);
2518 }
2519
2520
2521 static void fbcon_aty32_clear_margins(struct vc_data *conp,
2522 struct display *p, int bottom_only)
2523 {
2524 struct fb_info_aty128 *fb = (struct fb_info_aty128 *)(p->fb_info);
2525
2526 if (fb->blitter_may_be_busy)
2527 wait_for_idle(fb);
2528
2529 fbcon_cfb32_clear_margins(conp, p, bottom_only);
2530 }
2531
2532 static struct display_switch fbcon_aty128_32 = {
2533 setup: fbcon_cfb32_setup,
2534 bmove: fbcon_aty128_bmove,
2535 clear: fbcon_cfb32_clear,
2536 putc: fbcon_aty32_putc,
2537 putcs: fbcon_aty32_putcs,
2538 revc: fbcon_cfb32_revc,
2539 clear_margins: fbcon_aty32_clear_margins,
2540 fontwidthmask: FONTWIDTH(4)|FONTWIDTH(8)|FONTWIDTH(12)|FONTWIDTH(16)
2541 };
2542 #endif
2543
2544 #ifdef MODULE
2545 MODULE_AUTHOR("(c)1999-2000 Brad Douglas <brad@neruo.com>");
2546 MODULE_DESCRIPTION("FBDev driver for ATI Rage128 / Pro cards");
2547
2548 int __init
2549 init_module(void)
2550 {
2551 aty128fb_init();
2552 return 0;
2553 }
2554
2555 void __exit
2556 cleanup_module(void)
2557 {
2558 struct fb_info_aty128 *info = board_list;
2559
2560 while (board_list) {
2561 info = board_list;
2562 board_list = board_list->next;
2563
2564 unregister_framebuffer(&info->fb_info);
2565 #ifdef CONFIG_MTRR
2566 if (info->mtrr.vram_valid)
2567 mtrr_del(info->mtrr.vram, info->frame_buffer_phys,
2568 info->vram_size);
2569 #endif /* CONFIG_MTRR */
2570 iounmap(info->regbase);
2571 iounmap(&info->frame_buffer);
2572
2573 release_mem_region(pci_resource_start(info->pdev, 0),
2574 pci_resource_len(info->pdev, 0));
2575 release_mem_region(pci_resource_start(info->pdev, 1),
2576 pci_resource_len(info->pdev, 1));
2577 release_mem_region(pci_resource_start(info->pdev, 2),
2578 pci_resource_len(info->pdev, 2));
2579
2580 kfree(info);
2581 }
2582 }
2583 #endif /* MODULE */
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