drivers/net/gmac.h

   1 /*
   2  * Definitions for the GMAC ethernet chip, used in the
   3  * Apple G4 powermac.
   4  */
   5
   6
   7 /*
   8  * GMAC register definitions
   9  *
  10  * Note: We encode the register size the same way Apple does. I didn't copy
  11  *       Apple's source as-is to avoid licence issues however. That's really
  12  *       painful to re-define all those registers ...
  13  *       The constants themselves were partially found in OF code, in Sun
  14  *       GEM driver and in Apple's Darwin GMAC driver
  15  */
  16
  17 #define REG_SZ_8                        0x00000000
  18 #define REG_SZ_16                       0x40000000
  19 #define REG_SZ_32                       0x80000000
  20 #define REG_MASK                        0x0FFFFFFF
  21
  22         /*
  23          * Global registers
  24          */
  25
  26 /* -- 0x0004    RW      Global configuration
  27  * d: 0x00000042
  28  */
  29 #define GM_GCONF                        (0x0004 | REG_SZ_16)
  30 #define GM_GCONF_BURST_SZ               0x0001          /* 1: 64 bytes/burst, 0: infinite */
  31 #define GM_GCONF_TXDMA_LIMIT_MASK       0x003e          /* 5-1: No of 64 bytes transfers */
  32 #define GM_GCONF_TXDMA_LIMIT_SHIFT      1
  33 #define GM_GCONF_RXDMA_LIMIT_MASK       0x07c0          /* 10-6: No of 64 bytes transfers */
  34 #define GM_GCONF_RXDMA_LIMIT_SHIFT      6
  35
  36 /* -- 0x000C    R-C     Global Interrupt status.
  37  * d: 0x00000000        bits 0-6 cleared on read (C)
  38  */
  39 #define GM_IRQ_STATUS                   (0x000c | REG_SZ_32)
  40 #define GM_IRQ_TX_INT_ME                0x00000001      /* C Frame with INT_ME bit set in fifo */
  41 #define GM_IRQ_TX_ALL                   0x00000002      /* C TX descriptor ring empty */
  42 #define GM_IRQ_TX_DONE                  0x00000004      /* C moved from host to TX fifo */
  43 #define GM_IRQ_RX_DONE                  0x00000010      /* C moved from RX fifo to host */
  44 #define GM_IRQ_RX_NO_BUF                0x00000020      /* C No RX buffer available */
  45 #define GM_IRQ_RX_TAG_ERR               0x00000040      /* C RX tag error */
  46 #define GM_IRQ_PCS                      0x00002000      /* PCS interrupt ? */
  47 #define GM_IRQ_MAC_TX                   0x00004000      /* MAC tx register set */
  48 #define GM_IRQ_MAC_RX                   0x00008000      /* MAC rx register set  */
  49 #define GM_IRQ_MAC_CTRL                 0x00010000      /* MAC control register set  */
  50 #define GM_IRQ_MIF                      0x00020000      /* MIF status register set */
  51 #define GM_IRQ_BUS_ERROR                0x00040000      /* Bus error status register set */
  52 #define GM_IRQ_TX_COMP                  0xfff80000      /* TX completion mask */
  53
  54 /* -- 0x0010    RW      Interrupt mask.
  55  * d: 0xFFFFFFFF
  56  */
  57 #define GM_IRQ_MASK                     (0x0010 | REG_SZ_32)
  58
  59 /* -- 0x0014    WO      Interrupt ack.
  60  *                      Ack. "high" interrupts
  61  */
  62 #define GM_IRQ_ACK                      (0x0014 | REG_SZ_32)
  63
  64 /* -- 0x001C    WO      Alias of status register (no auto-clear of "low" interrupts)
  65  */
  66 #define GM_IRQ_ALT_STAT                 (0x001C | REG_SZ_32)
  67
  68 /* -- 0x1000    R-C     PCI Error status register
  69  */
  70 #define GM_PCI_ERR_STAT                 (0x1000 | REG_SZ_8)
  71 #define GM_PCI_ERR_BAD_ACK              0x01            /* Bad Ack64 */
  72 #define GM_PCI_ERR_TIMEOUT              0x02            /* Transaction timeout */
  73 #define GM_PCI_ERR_OTHER                0x04            /* Any other PCI error */
  74
  75 /* -- 0x1004    RW      PCI Error mask register
  76  * d: 0xFFFFFFFF
  77  */
  78 #define GM_PCI_ERR_MASK                 (0x1004 | REG_SZ_8)
  79
  80 /* -- 0x1008    RW      BIF Configuration
  81  * d: 0x00000000
  82  */
  83 #define GM_BIF_CFG                      (0x1008 | REG_SZ_8)
  84 #define GM_BIF_CFG_SLOWCLK              0x01            /* for parity error timing */
  85 #define GM_BIF_CFG_HOST_64              0x02            /* 64-bit host */
  86 #define GM_BIF_CFG_B64D_DIS             0x04            /* no 64-bit wide data cycle */
  87 #define GM_BIF_CFG_M66EN                0x08            /* Read-only: sense if configured for 66MHz */
  88
  89 /* -- 0x100C    RW      BIF Diagnostic ???
  90  */
  91 #define GM_BIF_DIAG                     (0x100C | REG_SZ_32)
  92 #define GM_BIF_DIAG_BURST_STATE         0x007F0000
  93 #define GM_BIF_DIAG_STATE_MACH          0xFF000000
  94
  95 /* -- 0x1010    RW      Software reset
  96  *                      Lower two bits reset TX and RX, both reset whole gmac. They come back
  97  *                      to 0 when reset is complete.
  98  *                      bit 2 force RSTOUT# pin when set (PHY reset)
  99  */
 100 #define GM_RESET                        (0x1010 | REG_SZ_8)
 101 #define GM_RESET_TX                     0x01
 102 #define GM_RESET_RX                     0x02
 103 #define GM_RESET_RSTOUT                 0x04            /* PHY reset */
 104
 105
 106         /*
 107          * Tx DMA Registers
 108          */
 109
 110 /* -- 0x2000    RW      Tx Kick
 111  * d: 0x00000000        Written by the host with the last tx descriptor number +1 to send
 112  */
 113 #define GM_TX_KICK                      (0x2000 | REG_SZ_16)
 114
 115 /* -- 0x2004    RW      Tx configuration
 116  * d: 0x118010          Controls operation of Tx DMA channel
 117  */
 118
 119 #define GM_TX_CONF                      (0x2004 | REG_SZ_32)
 120 #define GM_TX_CONF_DMA_EN               0x00000001      /* Tx DMA enable */
 121 #define GM_TX_CONF_RING_SZ_MASK         0x0000001e      /* Tx desc ring size */
 122 #define GM_TX_CONF_RING_SZ_SHIFT        1               /* Tx desc ring size shift */
 123 #define GM_TX_CONF_FIFO_PIO             0x00000020      /* Tx fifo PIO select ??? */
 124 #define GM_TX_CONF_FIFO_THR_MASK        0x001ffc00      /* Tx fifo threshold */
 125 #define GM_TX_CONF_FIFO_THR_SHIFT       10              /* Tx fifo threshold shift */
 126 #define GM_TX_CONF_FIFO_THR_DEFAULT     0x7ff           /* Tx fifo threshold default */
 127 #define GM_TX_CONF_PACED_MODE           0x00100000      /* 1: tx_all irq after last descriptor */
 128                                                         /* 0: tx_all irq when tx fifo empty */
 129 #define GM_TX_RING_SZ_32                (0 << 1)
 130 #define GM_TX_RING_SZ_64                (1 << 1)
 131 #define GM_TX_RING_SZ_128               (2 << 1)
 132 #define GM_TX_RING_SZ_256               (3 << 1)
 133 #define GM_TX_RING_SZ_512               (4 << 1)
 134 #define GM_TX_RING_SZ_1024              (5 << 1)
 135 #define GM_TX_RING_SZ_2048              (6 << 1)
 136 #define GM_TX_RING_SZ_4086              (7 << 1)
 137 #define GM_TX_RING_SZ_8192              (8 << 1)
 138
 139 /* -- 0x2008    RW      Tx descriptor ring base low
 140  * -- 0x200C    RW      Tx descriptor ring base high
 141  *
 142  * Base of tx ring, must be 2k aligned
 143  */
 144 #define GM_TX_DESC_LO                   (0x2008 | REG_SZ_32)
 145 #define GM_TX_DESC_HI                   (0x200C | REG_SZ_32)
 146
 147 /* -- 0x2100    RW      Tx Completion
 148  * d: 0x00000000        Written by the gmac with the last tx descriptor number +1 sent
 149  */
 150 #define GM_TX_COMP                      (0x2100 | REG_SZ_16)
 151
 152
 153         /*
 154          * Rx DMA registers
 155          */
 156
 157
 158 /* -- 0x4000    RW      Rx configuration
 159  * d: 0x1000010         Controls operation of Rx DMA channel
 160  */
 161
 162 #define GM_RX_CONF                      (0x4000 | REG_SZ_32)
 163 #define GM_RX_CONF_DMA_EN               0x00000001      /* Rx DMA enable */
 164 #define GM_RX_CONF_RING_SZ_MASK         0x0000001e      /* Rx desc ring size */
 165 #define GM_RX_CONF_RING_SZ_SHIFT        1
 166 #define GM_RX_CONF_BATCH_DIS            0x00000020      /* Rx batch disable */
 167 #define GM_RX_CONF_FBYTE_OFF_MASK       0x00001c00      /* First byte offset (10-12) */
 168 #define GM_RX_CONF_FBYTE_OFF_SHIFT      10
 169 #define GM_RX_CONF_CHK_START_MASK       0x000FE000      /* Checksum start offset */
 170 #define GM_RX_CONF_CHK_START_SHIFT      13
 171 #define GM_RX_CONF_DMA_THR_MASK         0x07000000      /* Rx DMA threshold */
 172 #define GM_RX_CONF_DMA_THR_SHIFT        24              /* Rx DMA threshold shift */
 173 #define GM_RX_CONF_DMA_THR_DEFAULT      1               /* Rx DMA threshold default */
 174
 175 #define GM_RX_RING_SZ_32                (0 << 1)
 176 #define GM_RX_RING_SZ_64                (1 << 1)
 177 #define GM_RX_RING_SZ_128               (2 << 1)
 178 #define GM_RX_RING_SZ_256               (3 << 1)
 179 #define GM_RX_RING_SZ_512               (4 << 1)
 180 #define GM_RX_RING_SZ_1024              (5 << 1)
 181 #define GM_RX_RING_SZ_2048              (6 << 1)
 182 #define GM_RX_RING_SZ_4086              (7 << 1)
 183 #define GM_RX_RING_SZ_8192              (8 << 1)
 184
 185 /* -- 0x4004    RW      Rx descriptor ring base low
 186  * -- 0x4008    RW      Rx descriptor ring base high
 187  *
 188  * Base of rx ring
 189  */
 190 #define GM_RX_DESC_LO                   (0x4004 | REG_SZ_32)
 191 #define GM_RX_DESC_HI                   (0x4008 | REG_SZ_32)
 192
 193 /* -- 0x4020    RW      Rx pause threshold
 194  * d: 0x000000f8
 195  *
 196  * Two PAUSE thresholds are used to define when PAUSE flow control frames are
 197  * emitted by GEM. The granularity of these thresholds is in 64 byte increments.
 198  * XOFF PAUSE frames use the pause_time value pre-programmed in the
 199  * Send PAUSE MAC Register.
 200  * XON PAUSE frames use a pause_time of 0.
 201  */
 202 #define GM_RX_PTH                       (0x4020 | REG_SZ_32)
 203                         /*
 204                          * 0-8: XOFF PAUSE emitted when RX FIFO
 205                          * occupancy rises above this value (times 64 bytes)
 206                          */
 207 #define GM_RX_PTH_OFF_MASK              0x000001ff
 208 #define GM_RX_PTH_OFF_SHIFT             0
 209                         /*
 210                          * 12-20: XON PAUSE emitted when RX FIFO
 211                          * occupancy falls below this value (times 64 bytes)
 212                          */
 213 #define GM_RX_PTH_ON_MASK               0x001ff000
 214 #define GM_RX_PTH_ON_SHIFT              12
 215
 216 #define GM_RX_PTH_UNITS                 64
 217
 218 /* -- 0x4100    RW      Rx Kick
 219  * d: 0x00000000        The last valid RX descriptor is the one right before the value of the
 220  *                      register. Initially set to 0 on reset. RX descriptors must be posted
 221  *                      in multiples of 4. The first descriptor should be cache-line aligned
 222  *                      for best performance.
 223  */
 224 #define GM_RX_KICK                      (0x4100 | REG_SZ_16)
 225
 226 /* -- 0x4104    RW      Rx Completion
 227  * d: 0x00000000        All descriptors upto but excluding the register value are ready to be
 228  *                      processed by the host.
 229  */
 230 #define GM_RX_COMP                      (0x4104 | REG_SZ_16)
 231
 232 /* -- 0x4108    RW      Rx Blanking
 233  * d: 0x00000000        Written by the gmac with the last tx descriptor number +1 sent
 234  *
 235  * Defines the values used for receive interrupt blanking.
 236  * For INTR_TIME field, every count is 2048 PCI clock time. For 66 Mhz, each
 237  * count is about 15 ns.
 238  */
 239 #define GM_RX_BLANK                     (0x4108 | REG_SZ_32)
 240                         /*
 241                          * 0-8:no.of pkts to be recvd since the last RX_DONE
 242                          * interrupt, before a new interrupt
 243                          */
 244 #define GM_RX_BLANK_INTR_PACKETS_MASK   0x000001ff
 245 #define GM_RX_BLANK_INTR_PACKETS_SHIFT  0
 246                         /*
 247                          * 12-19 : no. of clocks to be counted since the last
 248                          * RX_DONE interrupt, before a new interrupt
 249                          */
 250 #define GM_RX_BLANK_INTR_TIME_MASK      0x000ff000
 251 #define GM_RX_BLANK_INTR_TIME_SHIFT     12
 252
 253 #define GM_RX_BLANK_UNITS               2048
 254
 255 /* -- 0x4120    RO      Rx fifo size
 256  *
 257  * This 11-bit RO register indicates the size, in 64-byte multiples, of the
 258  * RX FIFO. Software should use it to properly configure the PAUSE thresholds.
 259  * The value read is 0x140, indicating a 20kbyte RX FIFO.
 260  * -------------------------------------------------------------------------
 261  */
 262 #define GM_RX_FIFO_SIZE                 (0x4120 | REG_SZ_16)
 263 #define GM_RZ_FIFO_SIZE_UNITS           64
 264
 265
 266         /*
 267          * MAC regisers
 268          */
 269
 270 /* -- 0x6000            MAC Tx reset control
 271  */
 272 #define GM_MAC_TX_RESET                 (0x6000 | REG_SZ_8)
 273 #define GM_MAC_TX_RESET_NOW             0x01
 274
 275 /* -- 0x6004            MAC Rx reset control
 276  */
 277 #define GM_MAC_RX_RESET                 (0x6004 | REG_SZ_8)
 278 #define GM_MAC_RX_RESET_NOW             0x01
 279
 280 /* -- 0x6008            Send Pause command register
 281  */
 282 #define GM_MAC_SND_PAUSE                (0x6008 | REG_SZ_32)
 283 #define GM_MAC_SND_PAUSE_TIME_MASK      0x0000ffff
 284 #define GM_MAC_SND_PAUSE_TIME_SHIFT     0
 285 #define GM_MAC_SND_PAUSE_NOW            0x00010000
 286 #define GM_MAC_SND_PAUSE_DEFAULT        0x00001bf0
 287
 288 /* -- 0x6010            MAC transmit status
 289  */
 290 #define GM_MAC_TX_STATUS                (0x6010 | REG_SZ_16)
 291 #define GM_MAC_TX_STAT_SENT             0x0001
 292 #define GM_MAC_TX_STAT_UNDERRUN         0x0002
 293 #define GM_MAC_TX_STAT_MAX_PKT_ERR      0x0004
 294 #define GM_MAC_TX_STAT_NORM_COLL_OVF    0x0008
 295 #define GM_MAC_TX_STAT_EXCS_COLL_OVF    0x0010
 296 #define GM_MAC_TX_STAT_LATE_COLL_OVF    0x0020
 297 #define GM_MAC_TX_STAT_FIRS_COLL_OVF    0x0040
 298 #define GM_MAC_TX_STAT_DEFER_TIMER_OVF  0x0080
 299 #define GM_MAC_TX_STAT_PEAK_ATTMP_OVF   0x0100
 300
 301 /* -- 0x6014            MAC receive status
 302  */
 303 #define GM_MAC_RX_STATUS                (0x6014 | REG_SZ_16)
 304 #define GM_MAC_RX_STAT_RECEIVED         0x0001
 305 #define GM_MAC_RX_STAT_FIFO_OVF         0x0002
 306 #define GM_MAC_RX_STAT_FRAME_CTR_OVF    0x0004
 307 #define GM_MAC_RX_STAT_ALIGN_ERR_OVF    0x0008
 308 #define GM_MAC_RX_STAT_CRC_ERR_OVF      0x0010
 309 #define GM_MAC_RX_STAT_LEN_ERR_OVF      0x0020
 310 #define GM_MAC_RX_STAT_CODE_ERR_OVF     0x0040
 311
 312 /* -- 0x6018            MAC control & status
 313  */
 314 #define GM_MAC_CTRLSTAT                 (0x6018 | REG_SZ_32)
 315 #define GM_MAC_CTRLSTAT_PAUSE_RCVD      0x00000001
 316 #define GM_MAC_CTRLSTAT_PAUSE_STATE     0x00000002
 317 #define GM_MAC_CTRLSTAT_PAUSE_NOT       0x00000004
 318 #define GM_MAC_CTRLSTAT_PAUSE_TIM_MASK  0xffff0000
 319 #define GM_MAC_CTRLSTAT_PAUSE_TIM_SHIFT 16
 320
 321 /* -- 0x6020            MAC Tx mask
 322  *                      Same bits as MAC Tx status
 323  */
 324 #define GM_MAC_TX_MASK                  (0x6020 | REG_SZ_16)
 325
 326 /* -- 0x6024            MAC Rx mask
 327  *                      Same bits as MAC Rx status
 328  */
 329 #define GM_MAC_RX_MASK                  (0x6024 | REG_SZ_16)
 330
 331 /* -- 0x6028            MAC Control/Status mask
 332  *                      Same bits as MAC control/status low order byte
 333  */
 334 #define GM_MAC_CTRLSTAT_MASK            (0x6024 | REG_SZ_8)
 335
 336 /* -- 0x6030            MAC Tx configuration
 337  */
 338 #define GM_MAC_TX_CONFIG                (0x6030 | REG_SZ_16)
 339 #define GM_MAC_TX_CONF_ENABLE           0x0001
 340 #define GM_MAC_TX_CONF_IGNORE_CARRIER   0x0002
 341 #define GM_MAC_TX_CONF_IGNORE_COLL      0x0004
 342 #define GM_MAC_TX_CONF_ENABLE_IPG0      0x0008
 343 #define GM_MAC_TX_CONF_DONT_GIVEUP      0x0010
 344 #define GM_MAC_TX_CONF_DONT_GIVEUP_NLMT 0x0020
 345 #define GM_MAC_TX_CONF_NO_BACKOFF       0x0040
 346 #define GM_MAC_TX_CONF_SLOWDOWN         0x0080
 347 #define GM_MAC_TX_CONF_NO_FCS           0x0100
 348 #define GM_MAC_TX_CONF_CARRIER_EXT      0x0200
 349
 350 /* -- 0x6034            MAC Rx configuration
 351  */
 352 #define GM_MAC_RX_CONFIG                (0x6034 | REG_SZ_16)
 353 #define GM_MAC_RX_CONF_ENABLE           0x0001
 354 #define GM_MAC_RX_CONF_STRIP_PAD        0x0002
 355 #define GM_MAC_RX_CONF_STIP_FCS         0x0004
 356 #define GM_MAC_RX_CONF_RX_ALL           0x0008
 357 #define GM_MAC_RX_CONF_RX_ALL_MULTI     0x0010
 358 #define GM_MAC_RX_CONF_HASH_ENABLE      0x0020
 359 #define GM_MAC_RX_CONF_ADDR_FLTR_ENABLE 0x0040
 360 #define GM_MAC_RX_CONF_PASS_ERROR_FRAM  0x0080
 361 #define GM_MAC_RX_CONF_CARRIER_EXT      0x0100
 362
 363 /* -- 0x6038            MAC control configuration
 364  */
 365 #define GM_MAC_CTRL_CONFIG              (0x6038 | REG_SZ_8)
 366 #define GM_MAC_CTRL_CONF_SND_PAUSE_EN   0x01
 367 #define GM_MAC_CTRL_CONF_RCV_PAUSE_EN   0x02
 368 #define GM_MAC_CTRL_CONF_PASS_CTRL_FRAM 0x04
 369
 370 /* -- 0x603c            MAC XIF configuration */
 371 #define GM_MAC_XIF_CONFIG               (0x603c | REG_SZ_8)
 372 #define GM_MAC_XIF_CONF_TX_MII_OUT_EN   0x01
 373 #define GM_MAC_XIF_CONF_MII_INT_LOOP    0x02
 374 #define GM_MAC_XIF_CONF_DISABLE_ECHO    0x04
 375 #define GM_MAC_XIF_CONF_GMII_MODE       0x08
 376 #define GM_MAC_XIF_CONF_MII_BUFFER_EN   0x10
 377 #define GM_MAC_XIF_CONF_LINK_LED        0x20
 378 #define GM_MAC_XIF_CONF_FULL_DPLX_LED   0x40
 379
 380 /* -- 0x6040            MAC inter-packet GAP 0
 381  */
 382 #define GM_MAC_INTR_PKT_GAP0            (0x6040 | REG_SZ_8)
 383 #define GM_MAC_INTR_PKT_GAP0_DEFAULT    0x00
 384
 385 /* -- 0x6044            MAC inter-packet GAP 1
 386  */
 387 #define GM_MAC_INTR_PKT_GAP1            (0x6044 | REG_SZ_8)
 388 #define GM_MAC_INTR_PKT_GAP1_DEFAULT    0x08
 389
 390 /* -- 0x6048            MAC inter-packet GAP 2
 391  */
 392 #define GM_MAC_INTR_PKT_GAP2            (0x6048 | REG_SZ_8)
 393 #define GM_MAC_INTR_PKT_GAP2_DEFAULT    0x04
 394
 395 /* -- 604c              MAC slot time
 396  */
 397 #define GM_MAC_SLOT_TIME                (0x604C | REG_SZ_16)
 398 #define GM_MAC_SLOT_TIME_DEFAULT        0x0040
 399
 400 /* -- 6050              MAC minimum frame size
 401  */
 402 #define GM_MAC_MIN_FRAME_SIZE           (0x6050 | REG_SZ_16)
 403 #define GM_MAC_MIN_FRAME_SIZE_DEFAULT   0x0040
 404
 405 /* -- 6054              MAC maximum frame size
 406  */
 407 #define GM_MAC_MAX_FRAME_SIZE           (0x6054 | REG_SZ_16)
 408 #define GM_MAC_MAX_FRAME_SIZE_DEFAULT   0x05ee
 409 #define GM_MAC_MAX_FRAME_SIZE_ALIGN     0x5f0
 410
 411 /* -- 6058              MAC preamble length
 412  */
 413 #define GM_MAC_PREAMBLE_LEN             (0x6058 | REG_SZ_16)
 414 #define GM_MAC_PREAMBLE_LEN_DEFAULT     0x0007
 415
 416 /* -- 605c              MAC jam size
 417  */
 418 #define GM_MAC_JAM_SIZE                 (0x605c | REG_SZ_8)
 419 #define GM_MAC_JAM_SIZE_DEFAULT         0x04
 420
 421 /* -- 6060              MAC attempt limit
 422  */
 423 #define GM_MAC_ATTEMPT_LIMIT            (0x6060 | REG_SZ_8)
 424 #define GM_MAC_ATTEMPT_LIMIT_DEFAULT    0x10
 425
 426 /* -- 6064              MAC control type
 427  */
 428 #define GM_MAC_CONTROL_TYPE             (0x6064 | REG_SZ_16)
 429 #define GM_MAC_CONTROL_TYPE_DEFAULT     0x8808
 430
 431 /* -- 6080              MAC address 15..0
 432  * -- 6084              MAC address 16..31
 433  * -- 6088              MAC address 32..47
 434  */
 435 #define GM_MAC_ADDR_NORMAL0             (0x6080 | REG_SZ_16)
 436 #define GM_MAC_ADDR_NORMAL1             (0x6084 | REG_SZ_16)
 437 #define GM_MAC_ADDR_NORMAL2             (0x6088 | REG_SZ_16)
 438
 439 /* -- 608c              MAC alternate address 15..0
 440  * -- 6090              MAC alternate address 16..31
 441  * -- 6094              MAC alternate address 32..47
 442  */
 443 #define GM_MAC_ADDR_ALT0                (0x608c | REG_SZ_16)
 444 #define GM_MAC_ADDR_ALT1                (0x6090 | REG_SZ_16)
 445 #define GM_MAC_ADDR_ALT2                (0x6094 | REG_SZ_16)
 446
 447 /* -- 6098              MAC control address 15..0
 448  * -- 609c              MAC control address 16..31
 449  * -- 60a0              MAC control address 32..47
 450  */
 451 #define GM_MAC_ADDR_CTRL0               (0x6098 | REG_SZ_16)
 452 #define GM_MAC_ADDR_CTRL1               (0x609c | REG_SZ_16)
 453 #define GM_MAC_ADDR_CTRL2               (0x60a0 | REG_SZ_16)
 454
 455 /* -- 60a4              MAC address filter (0_0)
 456  * -- 60a8              MAC address filter (0_1)
 457  * -- 60ac              MAC address filter (0_2)
 458  */
 459 #define GM_MAC_ADDR_FILTER0             (0x60a4 | REG_SZ_16)
 460 #define GM_MAC_ADDR_FILTER1             (0x60a8 | REG_SZ_16)
 461 #define GM_MAC_ADDR_FILTER2             (0x60ac | REG_SZ_16)
 462
 463 /* -- 60b0              MAC address filter mask 1,2
 464  */
 465 #define GM_MAC_ADDR_FILTER_MASK1_2      (0x60b0 | REG_SZ_8)
 466
 467 /* -- 60b4              MAC address filter mask 0
 468  */
 469 #define GM_MAC_ADDR_FILTER_MASK0        (0x60b4 | REG_SZ_16)
 470
 471 /* -- [60c0 .. 60fc]    MAC hash table
 472  */
 473 #define GM_MAC_ADDR_FILTER_HASH0        (0x60c0 | REG_SZ_16)
 474
 475 /* -- 6100              MAC normal collision counter
 476  */
 477 #define GM_MAC_COLLISION_CTR            (0x6100 | REG_SZ_16)
 478
 479 /* -- 6104              MAC 1st successful collision counter
 480  */
 481 #define GM_MAC_FIRST_COLLISION_CTR      (0x6104 | REG_SZ_16)
 482
 483 /* -- 6108              MAC excess collision counter
 484  */
 485 #define GM_MAC_EXCS_COLLISION_CTR       (0x6108 | REG_SZ_16)
 486
 487 /* -- 610c              MAC late collision counter
 488  */
 489 #define GM_MAC_LATE_COLLISION_CTR       (0x610c | REG_SZ_16)
 490
 491 /* -- 6110              MAC defer timer counter
 492  */
 493 #define GM_MAC_DEFER_TIMER_COUNTER      (0x6110 | REG_SZ_16)
 494
 495 /* -- 6114              MAC peak attempts
 496  */
 497 #define GM_MAC_PEAK_ATTEMPTS            (0x6114 | REG_SZ_16)
 498
 499 /* -- 6118              MAC Rx frame counter
 500  */
 501 #define GM_MAC_RX_FRAME_CTR             (0x6118 | REG_SZ_16)
 502
 503 /* -- 611c              MAC Rx length error counter
 504  */
 505 #define GM_MAC_RX_LEN_ERR_CTR           (0x611c | REG_SZ_16)
 506
 507 /* -- 6120              MAC Rx alignment error counter
 508  */
 509 #define GM_MAC_RX_ALIGN_ERR_CTR         (0x6120 | REG_SZ_16)
 510
 511 /* -- 6124              MAC Rx CRC error counter
 512  */
 513 #define GM_MAC_RX_CRC_ERR_CTR           (0x6124 | REG_SZ_16)
 514
 515 /* -- 6128              MAC Rx code violation error counter
 516  */
 517 #define GM_MAC_RX_CODE_VIOLATION_CTR    (0x6128 | REG_SZ_16)
 518
 519 /* -- 6130              MAC random number seed
 520  */
 521 #define GM_MAC_RANDOM_SEED              (0x6130 | REG_SZ_16)
 522
 523 /* -- 6134              MAC state machine
 524  */
 525 #define GM_MAC_STATE_MACHINE            (0x6134 | REG_SZ_8)
 526
 527
 528         /*
 529          * MIF registers
 530          */
 531
 532
 533 /* -- 0x6200    RW      MIF bit bang clock
 534  */
 535 #define GM_MIF_BB_CLOCK                 (0x6200 | REG_SZ_8)
 536
 537 /* -- 0x6204    RW      MIF bit bang data
 538  */
 539 #define GM_MIF_BB_DATA                  (0x6204 | REG_SZ_8)
 540
 541 /* -- 0x6208    RW      MIF bit bang output enable
 542  */
 543 #define GM_MIF_BB_OUT_ENABLE            (0x6208 | REG_SZ_8)
 544
 545 /* -- 0x620c    RW      MIF frame control & data
 546  */
 547 #define GM_MIF_FRAME_CTL_DATA           (0x620c | REG_SZ_32)
 548 #define GM_MIF_FRAME_START_MASK         0xc0000000
 549 #define GM_MIF_FRAME_START_SHIFT        30
 550 #define GM_MIF_FRAME_OPCODE_MASK        0x30000000
 551 #define GM_MIF_FRAME_OPCODE_SHIFT       28
 552 #define GM_MIF_FRAME_PHY_ADDR_MASK      0x0f800000
 553 #define GM_MIF_FRAME_PHY_ADDR_SHIFT     23
 554 #define GM_MIF_FRAME_REG_ADDR_MASK      0x007c0000
 555 #define GM_MIF_FRAME_REG_ADDR_SHIFT     18
 556 #define GM_MIF_FRAME_TURNAROUND_HI      0x00020000
 557 #define GM_MIF_FRAME_TURNAROUND_LO      0x00010000
 558 #define GM_MIF_FRAME_DATA_MASK          0x0000ffff
 559 #define GM_MIF_FRAME_DATA_SHIFT         0
 560
 561 /* -- 0x6210    RW      MIF config reg
 562  */
 563 #define GM_MIF_CFG                      (0x6210 | REG_SZ_16)
 564 #define GM_MIF_CFGPS                    0x00000001      /* PHY Select */
 565 #define GM_MIF_CFGPE                    0x00000002      /* Poll Enable */
 566 #define GM_MIF_CFGBB                    0x00000004      /* Bit Bang Enable */
 567 #define GM_MIF_CFGPR_MASK               0x000000f8      /* Poll Register address */
 568 #define GM_MIF_CFGPR_SHIFT              3
 569 #define GM_MIF_CFGM0                    0x00000100      /* MDIO_0 Data / MDIO_0 attached */
 570 #define GM_MIF_CFGM1                    0x00000200      /* MDIO_1 Data / MDIO_1 attached */
 571 #define GM_MIF_CFGPD_MASK               0x00007c00      /* Poll Device PHY address */
 572 #define GM_MIF_CFGPD_SHIFT              10
 573
 574 #define GM_MIF_POLL_DELAY               200
 575
 576 #define GM_INTERNAL_PHYAD               1               /* PHY address for int. transceiver */
 577 #define GM_EXTERNAL_PHYAD               0               /* PHY address for ext. transceiver */
 578
 579 /* -- 0x6214    RW      MIF interrupt mask reg
 580  *                      same as basic/status Register
 581  */
 582 #define GM_MIF_IRQ_MASK                 (0x6214 | REG_SZ_16)
 583
 584 /* -- 0x6218    RW      MIF basic/status reg
 585  *                      The Basic portion of this register indicates the last
 586  *                      value of the register read indicated in the POLL REG field
 587  *                      of the Configuration Register.
 588  *                      The Status portion indicates bit(s) that have changed.
 589  *                      The MIF Mask register is corresponding to this register in
 590  *                      terms of the bit(s) that need to be masked for generating
 591  *                      interrupt on the MIF Interrupt Bit of the Global Status Rgister.
 592  */
 593 #define GM_MIF_STATUS                   (0x6218 | REG_SZ_32)
 594
 595 #define GM_MIF_STATUS_MASK              0x0000ffff      /* 0-15 : Status */
 596 #define GM_MIF_BASIC_MASK               0xffff0000      /* 16-31 : Basic register */
 597
 598         /*
 599          * PCS link registers
 600          */
 601
 602 /* -- 0x9000    RW      PCS mii control reg
 603  */
 604 #define GM_PCS_CONTROL                  (0x9000 | REG_SZ_16)
 605
 606 /* -- 0x9004    RW      PCS mii status reg
 607  */
 608 #define GM_PCS_STATUS                   (0x9004 | REG_SZ_16)
 609
 610 /* -- 0x9008    RW      PCS mii advertisement
 611  */
 612 #define GM_PCS_ADVERTISEMENT            (0x9008 | REG_SZ_16)
 613
 614 /* -- 0x900c    RW      PCS mii LP ability
 615  */
 616 #define GM_PCS_ABILITY                  (0x900c | REG_SZ_16)
 617
 618 /* -- 0x9010    RW      PCS config
 619  */
 620 #define GM_PCS_CONFIG                   (0x9010 | REG_SZ_8)
 621
 622 /* -- 0x9014    RW      PCS state machine
 623  */
 624 #define GM_PCS_STATE_MACHINE            (0x9014 | REG_SZ_32)
 625
 626 /* -- 0x9018    RW      PCS interrupt status
 627  */
 628 #define GM_PCS_IRQ_STATUS               (0x9018 | REG_SZ_8)
 629
 630 /* -- 0x9050    RW      PCS datapath mode
 631  */
 632 #define GM_PCS_DATAPATH_MODE            (0x9050 | REG_SZ_8)
 633 #define GM_PCS_DATAPATH_INTERNAL        0x01    /* Internal serial link */
 634 #define GM_PCS_DATAPATH_SERDES          0x02    /* 10-bit Serdes interface */
 635 #define GM_PCS_DATAPATH_MII             0x04    /* Select mii/gmii mode */
 636 #define GM_PCS_DATAPATH_GMII_OUT        0x08    /* serial mode only, copy data to gmii */
 637
 638 /* -- 0x9054    RW      PCS serdes control
 639  */
 640 #define GM_PCS_SERDES_CTRL              (0x9054 | REG_SZ_8)
 641
 642 /* -- 0x9058    RW      PCS serdes output select
 643  */
 644 #define GM_PCS_SERDES_SELECT            (0x9058 | REG_SZ_8)
 645
 646 /* -- 0x905c    RW      PCS serdes state
 647  */
 648 #define GM_PCS_SERDES_STATE             (0x905c | REG_SZ_8)
 649
 650
 651         /*
 652          * PHY registers
 653          */
 654
 655 /*
 656  * Standard PHY registers (from de4x5.h)
 657  */
 658 #define MII_CR       0x00          /* MII Management Control Register */
 659 #define MII_SR       0x01          /* MII Management Status Register */
 660 #define MII_ID0      0x02          /* PHY Identifier Register 0 */
 661 #define MII_ID1      0x03          /* PHY Identifier Register 1 */
 662 #define MII_ANA      0x04          /* Auto Negotiation Advertisement */
 663 #define MII_ANLPA    0x05          /* Auto Negotiation Link Partner Ability */
 664 #define MII_ANE      0x06          /* Auto Negotiation Expansion */
 665 #define MII_ANP      0x07          /* Auto Negotiation Next Page TX */
 666
 667 /*
 668 ** MII Management Control Register
 669 */
 670 #define MII_CR_RST  0x8000         /* RESET the PHY chip */
 671 #define MII_CR_LPBK 0x4000         /* Loopback enable */
 672 #define MII_CR_SPD  0x2000         /* 0: 10Mb/s; 1: 100Mb/s */
 673 #define MII_CR_10   0x0000         /* Set 10Mb/s */
 674 #define MII_CR_100  0x2000         /* Set 100Mb/s */
 675 #define MII_CR_ASSE 0x1000         /* Auto Speed Select Enable */
 676 #define MII_CR_PD   0x0800         /* Power Down */
 677 #define MII_CR_ISOL 0x0400         /* Isolate Mode */
 678 #define MII_CR_RAN  0x0200         /* Restart Auto Negotiation */
 679 #define MII_CR_FDM  0x0100         /* Full Duplex Mode */
 680 #define MII_CR_CTE  0x0080         /* Collision Test Enable */
 681
 682 /*
 683 ** MII Management Status Register
 684 */
 685 #define MII_SR_T4C  0x8000         /* 100BASE-T4 capable */
 686 #define MII_SR_TXFD 0x4000         /* 100BASE-TX Full Duplex capable */
 687 #define MII_SR_TXHD 0x2000         /* 100BASE-TX Half Duplex capable */
 688 #define MII_SR_TFD  0x1000         /* 10BASE-T Full Duplex capable */
 689 #define MII_SR_THD  0x0800         /* 10BASE-T Half Duplex capable */
 690 #define MII_SR_ASSC 0x0020         /* Auto Speed Selection Complete*/
 691 #define MII_SR_RFD  0x0010         /* Remote Fault Detected */
 692 #define MII_SR_ANC  0x0008         /* Auto Negotiation capable */
 693 #define MII_SR_LKS  0x0004         /* Link Status */
 694 #define MII_SR_JABD 0x0002         /* Jabber Detect */
 695 #define MII_SR_XC   0x0001         /* Extended Capabilities */
 696
 697 /*
 698 ** MII Management Auto Negotiation Advertisement Register
 699 */
 700 #define MII_ANA_TAF  0x03e0        /* Technology Ability Field */
 701 #define MII_ANA_T4AM 0x0200        /* T4 Technology Ability Mask */
 702 #define MII_ANA_TXAM 0x0180        /* TX Technology Ability Mask */
 703 #define MII_ANA_FDAM 0x0140        /* Full Duplex Technology Ability Mask */
 704 #define MII_ANA_HDAM 0x02a0        /* Half Duplex Technology Ability Mask */
 705 #define MII_ANA_100M 0x0380        /* 100Mb Technology Ability Mask */
 706 #define MII_ANA_10M  0x0060        /* 10Mb Technology Ability Mask */
 707 #define MII_ANA_CSMA 0x0001        /* CSMA-CD Capable */
 708
 709 /*
 710 ** MII Management Auto Negotiation Remote End Register
 711 */
 712 #define MII_ANLPA_NP   0x8000      /* Next Page (Enable) */
 713 #define MII_ANLPA_ACK  0x4000      /* Remote Acknowledge */
 714 #define MII_ANLPA_RF   0x2000      /* Remote Fault */
 715 #define MII_ANLPA_TAF  0x03e0      /* Technology Ability Field */
 716 #define MII_ANLPA_T4AM 0x0200      /* T4 Technology Ability Mask */
 717 #define MII_ANLPA_TXAM 0x0180      /* TX Technology Ability Mask */
 718 #define MII_ANLPA_FDAM 0x0140      /* Full Duplex Technology Ability Mask */
 719 #define MII_ANLPA_HDAM 0x02a0      /* Half Duplex Technology Ability Mask */
 720 #define MII_ANLPA_100M 0x0380      /* 100Mb Technology Ability Mask */
 721 #define MII_ANLPA_10M  0x0060      /* 10Mb Technology Ability Mask */
 722 #define MII_ANLPA_CSMA 0x0001      /* CSMA-CD Capable */
 723 #define MII_ANLPA_PAUS 0x0400
 724
 725 /*
 726  * Model-specific PHY registers
 727  *
 728  * Note: Only the BCM5201 is described here for now. I'll add the 5400 once
 729  *       I see a machine using it in real world.
 730  */
 731
 732 /* Supported PHYs (phy_type field ) */
 733 #define PHY_B5400       5400
 734 #define PHY_B5201       5201
 735 #define PHY_UNKNOWN     0
 736
 737 /* Identification (for multi-PHY) */
 738 #define MII_BCM5201_OUI                         0x001018
 739 #define MII_BCM5201_MODEL                       0x21
 740 #define MII_BCM5201_REV                         0x01
 741 #define MII_BCM5201_ID                          ((MII_BCM5201_OUI << 10) | (MII_BCM5201_MODEL << 4))
 742 #define MII_BCM5201_MASK                        0xfffffff0
 743 #define MII_BCM5400_OUI                         0x000818
 744 #define MII_BCM5400_MODEL                       0x04
 745 #define MII_BCM5400_REV                         0x01
 746 #define MII_BCM5400_ID                          ((MII_BCM5400_OUI << 10) | (MII_BCM5400_MODEL << 4))
 747 #define MII_BCM5400_MASK                        0xfffffff0
 748
 749 /* BCM5201 AUX STATUS register */
 750 #define MII_BCM5201_AUXCTLSTATUS                0x18
 751 #define MII_BCM5201_AUXCTLSTATUS_DUPLEX         0x0001
 752 #define MII_BCM5201_AUXCTLSTATUS_SPEED          0x0002
 753
 754 /* MII BCM5201 MULTIPHY interrupt register */
 755 #define MII_BCM5201_INTERRUPT                   0x1A
 756 #define MII_BCM5201_INTERRUPT_INTENABLE         0x4000
 757
 758 #define MII_BCM5201_AUXMODE2                    0x1B
 759 #define MII_BCM5201_AUXMODE2_LOWPOWER           0x0008
 760
 761 #define MII_BCM5201_MULTIPHY                    0x1E
 762
 763 /* MII BCM5201 MULTIPHY register bits */
 764 #define MII_BCM5201_MULTIPHY_SERIALMODE         0x0002
 765 #define MII_BCM5201_MULTIPHY_SUPERISOLATE       0x0008
 766
 767
 768
 769         /*
 770          * DMA descriptors
 771          */
 772
 773
 774 /*
 775  * Descriptor counts and buffer sizes
 776  */
 777 #define NTX                     64              /* must be power of 2 */
 778 #define NTX_CONF                GM_TX_RING_SZ_64
 779 #define NRX                     64              /* must be power of 2 */
 780 #define NRX_CONF                GM_RX_RING_SZ_64
 781 #define RX_COPY_THRESHOLD       256
 782 #define GMAC_BUFFER_ALIGN       32              /* Align on a cache line */
 783 #define RX_BUF_ALLOC_SIZE       (ETH_FRAME_LEN + GMAC_BUFFER_ALIGN + 2)
 784 #define RX_OFFSET               2
 785
 786 /*
 787  * Definitions of Rx and Tx descriptors
 788  */
 789
 790 struct gmac_dma_desc {
 791         unsigned int    size;           /* data size and OWN bit */
 792         unsigned int    flags;          /* flags */
 793         unsigned int    lo_addr;        /* phys addr, low 32 bits */
 794         unsigned int    hi_addr;
 795 };
 796
 797 /*
 798  * Rx bits
 799  */
 800
 801 /* Bits in size */
 802 #define RX_SZ_OWN               0x80000000      /* 1 = owned by chip */
 803 #define RX_SZ_MASK              0x7FFF0000
 804 #define RX_SZ_SHIFT             16
 805 #define RX_SZ_CKSUM_MASK        0x0000FFFF
 806
 807 /* Bits in flags */
 808 #define RX_FL_CRC_ERROR         0x40000000
 809 #define RX_FL_ALT_ADDR          0x20000000      /* Packet rcv. from alt MAC address */
 810
 811 /*
 812  * Tx bits
 813  */
 814
 815 /* Bits in size */
 816 #define TX_SZ_MASK              0x00007FFF
 817 #define TX_SZ_CRC_MASK          0x00FF8000
 818 #define TX_SZ_CRC_STUFF         0x1F000000
 819 #define TX_SZ_CRC_ENABLE        0x20000000
 820 #define TX_SZ_EOP               0x40000000
 821 #define TX_SZ_SOP               0x80000000
 822 /* Bits in flags */
 823 #define TX_FL_INTERRUPT         0x00000001
 824 #define TX_FL_NO_CRC            0x00000002
 825
 826         /*
 827          * Other stuffs
 828          */
 829
 830 struct gmac {
 831         volatile unsigned int           *regs;  /* hardware registers, virtual addr */
 832         struct net_device               *dev;
 833         struct device_node              *of_node;
 834         unsigned long                   tx_desc_page;   /* page for DMA descriptors */
 835         unsigned long                   rx_desc_page;   /* page for DMA descriptors */
 836         volatile struct                 gmac_dma_desc *rxring;
 837         struct sk_buff                  *rx_buff[NRX];
 838         int                             next_rx;
 839         volatile struct gmac_dma_desc   *txring;
 840         struct sk_buff                  *tx_buff[NTX];
 841         int                             next_tx;
 842         int                             tx_gone;
 843         int                             phy_addr;
 844         unsigned int                    phy_id;
 845         int                             phy_type;
 846         int                             phy_status;     /* Cached PHY status */
 847         int                             full_duplex;    /* Current set to full duplex */
 848         struct net_device_stats         stats;
 849         u8                              pci_bus;
 850         u8                              pci_devfn;
 851         spinlock_t                      lock;
 852         int                             opened;
 853         struct net_device               *next_gmac;
 854 };
 855
 856
 857 /* Register access macros. We hope the preprocessor will be smart enough
 858  * to optimize them into one single access instruction
 859  */
 860 #define GM_OUT(reg, v)          (((reg) & REG_SZ_32) ? out_le32(gm->regs + \
 861                                         (((reg) & REG_MASK)>>2), (v))  \
 862                                 : (((reg) & REG_SZ_16) ? out_le16((volatile u16 *) \
 863                                         (gm->regs + (((reg) & REG_MASK)>>2)), (v))  \
 864                                 : out_8((volatile u8 *)(gm->regs + \
 865                                         (((reg) & REG_MASK)>>2)), (v))))
 866 #define GM_IN(reg)              (((reg) & REG_SZ_32) ? in_le32(gm->regs + \
 867                                         (((reg) & REG_MASK)>>2))  \
 868                                 : (((reg) & REG_SZ_16) ? in_le16((volatile u16 *) \
 869                                         (gm->regs + (((reg) & REG_MASK)>>2)))  \
 870                                 : in_8((volatile u8 *)(gm->regs + \
 871                                         (((reg) & REG_MASK)>>2)))))
 872 #define GM_BIS(r, v)            GM_OUT((r), GM_IN(r) | (v))
 873 #define GM_BIC(r, v)            GM_OUT((r), GM_IN(r) & ~(v))
 874
 875 /* Wrapper to alloc_skb to test various alignements */
 876 #define GMAC_ALIGNED_RX_SKB_ADDR(addr) \
 877         ((((unsigned long)(addr) + GMAC_BUFFER_ALIGN - 1) & \
 878         ~(GMAC_BUFFER_ALIGN - 1)) - (unsigned long)(addr))
 879
 880 static inline struct sk_buff *
 881 gmac_alloc_skb(unsigned int length, int gfp_flags)
 882 {
 883         struct sk_buff *skb;
 884
 885         skb = alloc_skb(length + GMAC_BUFFER_ALIGN, gfp_flags);
 886         if(skb) {
 887                 int offset = GMAC_ALIGNED_RX_SKB_ADDR(skb->data);
 888
 889                 if(offset)
 890                         skb_reserve(skb, offset);
 891         }
 892         return skb;
 893 }
 894