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Import 2.4.0-test2pre3
[davej-history.git] / drivers / ide / piix.c
blob0dbb8d88382bf5d1d5f745de6de6db2ccfe25361
1 /*
2 * linux/drivers/ide/piix.c Version 0.32 June 9, 2000
3 *
4 * Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer
5 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
6 * May be copied or modified under the terms of the GNU General Public License
7 *
8 * PIO mode setting function for Intel chipsets.
9 * For use instead of BIOS settings.
10 *
11 * 40-41
12 * 42-43
13 *
14 * 41
15 * 43
16 *
17 * | PIO 0 | c0 | 80 | 0 | piix_tune_drive(drive, 0);
18 * | PIO 2 | SW2 | d0 | 90 | 4 | piix_tune_drive(drive, 2);
19 * | PIO 3 | MW1 | e1 | a1 | 9 | piix_tune_drive(drive, 3);
20 * | PIO 4 | MW2 | e3 | a3 | b | piix_tune_drive(drive, 4);
21 *
22 * sitre = word40 & 0x4000; primary
23 * sitre = word42 & 0x4000; secondary
24 *
25 * 44 8421|8421 hdd|hdb
26 *
27 * 48 8421 hdd|hdc|hdb|hda udma enabled
28 *
29 * 0001 hda
30 * 0010 hdb
31 * 0100 hdc
32 * 1000 hdd
33 *
34 * 4a 84|21 hdb|hda
35 * 4b 84|21 hdd|hdc
36 *
37 * ata-33/82371AB
38 * ata-33/82371EB
39 * ata-33/82801AB ata-66/82801AA
40 * 00|00 udma 0 00|00 reserved
41 * 01|01 udma 1 01|01 udma 3
42 * 10|10 udma 2 10|10 udma 4
43 * 11|11 reserved 11|11 reserved
44 *
45 * 54 8421|8421 ata66 drive|ata66 enable
46 *
47 * pci_read_config_word(HWIF(drive)->pci_dev, 0x40, &reg40);
48 * pci_read_config_word(HWIF(drive)->pci_dev, 0x42, &reg42);
49 * pci_read_config_word(HWIF(drive)->pci_dev, 0x44, &reg44);
50 * pci_read_config_word(HWIF(drive)->pci_dev, 0x48, &reg48);
51 * pci_read_config_word(HWIF(drive)->pci_dev, 0x4a, &reg4a);
52 * pci_read_config_word(HWIF(drive)->pci_dev, 0x54, &reg54);
53 *
54 */
55
56 #include <linux/config.h>
57 #include <linux/types.h>
58 #include <linux/kernel.h>
59 #include <linux/ioport.h>
60 #include <linux/pci.h>
61 #include <linux/hdreg.h>
62 #include <linux/ide.h>
63 #include <linux/delay.h>
64 #include <linux/init.h>
65
66 #include <asm/io.h>
67
68 #include "ide_modes.h"
69
70 #define PIIX_DEBUG_DRIVE_INFO 0
71
72 #define DISPLAY_PIIX_TIMINGS
73
74 #if defined(DISPLAY_PIIX_TIMINGS) && defined(CONFIG_PROC_FS)
75 #include <linux/stat.h>
76 #include <linux/proc_fs.h>
77
78 static int piix_get_info(char *, char **, off_t, int);
79 extern int (*piix_display_info)(char *, char **, off_t, int); /* ide-proc.c */
80 extern char *ide_media_verbose(ide_drive_t *);
81 static struct pci_dev *bmide_dev;
82
83 static int piix_get_info (char *buffer, char **addr, off_t offset, int count)
84 {
85 char *p = buffer;
86 u32 bibma = pci_resource_start(bmide_dev, 4);
87 u16 reg40 = 0, psitre = 0, reg42 = 0, ssitre = 0;
88 u8 c0 = 0, c1 = 0;
89 u8 reg44 = 0, reg48 = 0, reg4a = 0, reg4b = 0, reg54 = 0, reg55 = 0;
90
91 pci_read_config_word(bmide_dev, 0x40, &reg40);
92 pci_read_config_word(bmide_dev, 0x42, &reg42);
93 pci_read_config_byte(bmide_dev, 0x44, &reg44);
94 pci_read_config_byte(bmide_dev, 0x48, &reg48);
95 pci_read_config_byte(bmide_dev, 0x4a, &reg4a);
96 pci_read_config_byte(bmide_dev, 0x4b, &reg4b);
97 pci_read_config_byte(bmide_dev, 0x54, &reg54);
98 pci_read_config_byte(bmide_dev, 0x55, &reg55);
99
100 psitre = (reg40 & 0x4000) ? 1 : 0;
101 ssitre = (reg42 & 0x4000) ? 1 : 0;
102
103 /*
104 * at that point bibma+0x2 et bibma+0xa are byte registers
105 * to investigate:
106 */
107 c0 = inb_p((unsigned short)bibma + 0x02);
108 c1 = inb_p((unsigned short)bibma + 0x0a);
109
110 switch(bmide_dev->device) {
111 case PCI_DEVICE_ID_INTEL_82820FW_5:
112 p += sprintf(p, "\n Intel PIIX4 Ultra 100 Chipset.\n");
113 break;
114 case PCI_DEVICE_ID_INTEL_82372FB_1:
115 case PCI_DEVICE_ID_INTEL_82801AA_1:
116 p += sprintf(p, "\n Intel PIIX4 Ultra 66 Chipset.\n");
117 break;
118 case PCI_DEVICE_ID_INTEL_82451NX:
119 case PCI_DEVICE_ID_INTEL_82801AB_1:
120 case PCI_DEVICE_ID_INTEL_82443MX_1:
121 case PCI_DEVICE_ID_INTEL_82371AB:
122 p += sprintf(p, "\n Intel PIIX4 Ultra 33 Chipset.\n");
123 break;
124 case PCI_DEVICE_ID_INTEL_82371SB_1:
125 p += sprintf(p, "\n Intel PIIX3 Chipset.\n");
126 break;
127 case PCI_DEVICE_ID_INTEL_82371FB_1:
128 case PCI_DEVICE_ID_INTEL_82371FB_0:
129 default:
130 p += sprintf(p, "\n Intel PIIX Chipset.\n");
131 break;
132 }
133 p += sprintf(p, "--------------- Primary Channel ---------------- Secondary Channel -------------\n");
134 p += sprintf(p, " %sabled %sabled\n",
135 (c0&0x80) ? "dis" : " en",
136 (c1&0x80) ? "dis" : " en");
137 p += sprintf(p, "--------------- drive0 --------- drive1 -------- drive0 ---------- drive1 ------\n");
138 p += sprintf(p, "DMA enabled: %s %s %s %s\n",
139 (c0&0x20) ? "yes" : "no ",
140 (c0&0x40) ? "yes" : "no ",
141 (c1&0x20) ? "yes" : "no ",
142 (c1&0x40) ? "yes" : "no " );
143 p += sprintf(p, "UDMA enabled: %s %s %s %s\n",
144 (reg48&0x01) ? "yes" : "no ",
145 (reg48&0x02) ? "yes" : "no ",
146 (reg48&0x04) ? "yes" : "no ",
147 (reg48&0x08) ? "yes" : "no " );
148 p += sprintf(p, "UDMA enabled: %s %s %s %s\n",
149 ((reg54&0x11) && (reg55&0x10) && (reg4a&0x01)) ? "5" :
150 ((reg54&0x11) && (reg4a&0x02)) ? "4" :
151 ((reg54&0x11) && (reg4a&0x01)) ? "3" :
152 (reg4a&0x02) ? "2" :
153 (reg4a&0x01) ? "1" :
154 (reg4a&0x00) ? "0" : "X",
155 ((reg54&0x22) && (reg55&0x20) && (reg4a&0x10)) ? "5" :
156 ((reg54&0x22) && (reg4a&0x20)) ? "4" :
157 ((reg54&0x22) && (reg4a&0x10)) ? "3" :
158 (reg4a&0x20) ? "2" :
159 (reg4a&0x10) ? "1" :
160 (reg4a&0x00) ? "0" : "X",
161 ((reg54&0x44) && (reg55&0x40) && (reg4b&0x03)) ? "5" :
162 ((reg54&0x44) && (reg4b&0x02)) ? "4" :
163 ((reg54&0x44) && (reg4b&0x01)) ? "3" :
164 (reg4b&0x02) ? "2" :
165 (reg4b&0x01) ? "1" :
166 (reg4b&0x00) ? "0" : "X",
167 ((reg54&0x88) && (reg55&0x80) && (reg4b&0x30)) ? "5" :
168 ((reg54&0x88) && (reg4b&0x20)) ? "4" :
169 ((reg54&0x88) && (reg4b&0x10)) ? "3" :
170 (reg4b&0x20) ? "2" :
171 (reg4b&0x10) ? "1" :
172 (reg4b&0x00) ? "0" : "X");
173
174 p += sprintf(p, "UDMA\n");
175 p += sprintf(p, "DMA\n");
176 p += sprintf(p, "PIO\n");
177
178 /*
179 * FIXME.... Add configuration junk data....blah blah......
180 */
181
182 return p-buffer; /* => must be less than 4k! */
183 }
184 #endif /* defined(DISPLAY_PIIX_TIMINGS) && defined(CONFIG_PROC_FS) */
185
186 /*
187 * Used to set Fifo configuration via kernel command line:
188 */
189
190 byte piix_proc = 0;
191
192 extern char *ide_xfer_verbose (byte xfer_rate);
193
194 /*
195 *
196 */
197 static byte piix_dma_2_pio (byte xfer_rate) {
198 switch(xfer_rate) {
199 case XFER_UDMA_5:
200 case XFER_UDMA_4:
201 case XFER_UDMA_3:
202 case XFER_UDMA_2:
203 case XFER_UDMA_1:
204 case XFER_UDMA_0:
205 case XFER_MW_DMA_2:
206 case XFER_PIO_4:
207 return 4;
208 case XFER_MW_DMA_1:
209 case XFER_PIO_3:
210 return 3;
211 case XFER_SW_DMA_2:
212 case XFER_PIO_2:
213 return 2;
214 case XFER_MW_DMA_0:
215 case XFER_SW_DMA_1:
216 case XFER_SW_DMA_0:
217 case XFER_PIO_1:
218 case XFER_PIO_0:
219 case XFER_PIO_SLOW:
220 default:
221 return 0;
222 }
223 }
224
225 /*
226 * Based on settings done by AMI BIOS
227 * (might be usefull if drive is not registered in CMOS for any reason).
228 */
229 static void piix_tune_drive (ide_drive_t *drive, byte pio)
230 {
231 unsigned long flags;
232 u16 master_data;
233 byte slave_data;
234 int is_slave = (&HWIF(drive)->drives[1] == drive);
235 int master_port = HWIF(drive)->index ? 0x42 : 0x40;
236 int slave_port = 0x44;
237 /* ISP RTC */
238 byte timings[][2] = { { 0, 0 },
239 { 0, 0 },
240 { 1, 0 },
241 { 2, 1 },
242 { 2, 3 }, };
243
244 pio = ide_get_best_pio_mode(drive, pio, 5, NULL);
245 pci_read_config_word(HWIF(drive)->pci_dev, master_port, &master_data);
246 if (is_slave) {
247 master_data = master_data | 0x4000;
248 if (pio > 1)
249 /* enable PPE, IE and TIME */
250 master_data = master_data | 0x0070;
251 pci_read_config_byte(HWIF(drive)->pci_dev, slave_port, &slave_data);
252 slave_data = slave_data & (HWIF(drive)->index ? 0x0f : 0xf0);
253 slave_data = slave_data | ((timings[pio][0] << 2) | (timings[pio][1]
254 << (HWIF(drive)->index ? 4 : 0)));
255 } else {
256 master_data = master_data & 0xccf8;
257 if (pio > 1)
258 /* enable PPE, IE and TIME */
259 master_data = master_data | 0x0007;
260 master_data = master_data | (timings[pio][0] << 12) |
261 (timings[pio][1] << 8);
262 }
263 save_flags(flags);
264 cli();
265 pci_write_config_word(HWIF(drive)->pci_dev, master_port, master_data);
266 if (is_slave)
267 pci_write_config_byte(HWIF(drive)->pci_dev, slave_port, slave_data);
268 restore_flags(flags);
269 }
270
271 #if defined(CONFIG_BLK_DEV_IDEDMA) && defined(CONFIG_PIIX_TUNING)
272 static int piix_tune_chipset (ide_drive_t *drive, byte speed)
273 {
274 ide_hwif_t *hwif = HWIF(drive);
275 struct pci_dev *dev = hwif->pci_dev;
276 byte maslave = hwif->channel ? 0x42 : 0x40;
277 int a_speed = 3 << (drive->dn * 4);
278 int u_flag = 1 << drive->dn;
279 int v_flag = 0x01 << drive->dn;
280 int w_flag = 0x10 << drive->dn;
281 int u_speed = 0;
282 int err = 0;
283 int sitre;
284 short reg4042, reg44, reg48, reg4a, reg54;
285 byte reg55;
286
287 pci_read_config_word(dev, maslave, &reg4042);
288 sitre = (reg4042 & 0x4000) ? 1 : 0;
289 pci_read_config_word(dev, 0x44, &reg44);
290 pci_read_config_word(dev, 0x48, &reg48);
291 pci_read_config_word(dev, 0x4a, &reg4a);
292 pci_read_config_word(dev, 0x54, &reg54);
293 pci_read_config_byte(dev, 0x55, &reg55);
294
295 switch(speed) {
296 case XFER_UDMA_4:
297 case XFER_UDMA_2: u_speed = 2 << (drive->dn * 4); break;
298 case XFER_UDMA_5:
299 case XFER_UDMA_3:
300 case XFER_UDMA_1: u_speed = 1 << (drive->dn * 4); break;
301 case XFER_UDMA_0: u_speed = 0 << (drive->dn * 4); break;
302 case XFER_MW_DMA_2:
303 case XFER_MW_DMA_1:
304 case XFER_SW_DMA_2: break;
305 default: return -1;
306 }
307
308 if (speed >= XFER_UDMA_0) {
309 if (!(reg48 & u_flag))
310 pci_write_config_word(dev, 0x48, reg48|u_flag);
311 if (speed == XFER_UDMA_5) {
312 pci_write_config_byte(dev, 0x55, (byte) reg55|w_flag);
313 } else {
314 pci_write_config_byte(dev, 0x55, (byte) reg55 & ~w_flag);
315 }
316 if (!(reg4a & u_speed)) {
317 pci_write_config_word(dev, 0x4a, reg4a & ~a_speed);
318 pci_write_config_word(dev, 0x4a, reg4a|u_speed);
319 }
320 if (speed > XFER_UDMA_2) {
321 if (!(reg54 & v_flag)) {
322 pci_write_config_word(dev, 0x54, reg54|v_flag);
323 }
324 } else {
325 pci_write_config_word(dev, 0x54, reg54 & ~v_flag);
326 }
327 }
328 if (speed < XFER_UDMA_0) {
329 if (reg48 & u_flag)
330 pci_write_config_word(dev, 0x48, reg48 & ~u_flag);
331 if (reg4a & a_speed)
332 pci_write_config_word(dev, 0x4a, reg4a & ~a_speed);
333 if (reg54 & v_flag)
334 pci_write_config_word(dev, 0x54, reg54 & ~v_flag);
335 if (reg55 & w_flag)
336 pci_write_config_byte(dev, 0x55, (byte) reg55 & ~w_flag);
337 }
338
339 piix_tune_drive(drive, piix_dma_2_pio(speed));
340
341 #if PIIX_DEBUG_DRIVE_INFO
342 printk("%s: %s drive%d\n", drive->name, ide_xfer_verbose(speed), drive->dn);
343 #endif /* PIIX_DEBUG_DRIVE_INFO */
344 if (!drive->init_speed)
345 drive->init_speed = speed;
346 err = ide_config_drive_speed(drive, speed);
347 drive->current_speed = speed;
348 return err;
349 }
350
351 static int piix_config_drive_for_dma (ide_drive_t *drive)
352 {
353 struct hd_driveid *id = drive->id;
354 ide_hwif_t *hwif = HWIF(drive);
355 struct pci_dev *dev = hwif->pci_dev;
356 byte speed;
357
358 byte udma_66 = eighty_ninty_three(drive);
359 int ultra100 = ((dev->device == PCI_DEVICE_ID_INTEL_82820FW_5)) ? 1 : 0;
360 int ultra66 = ((ultra100) ||
361 (dev->device == PCI_DEVICE_ID_INTEL_82801AA_1) ||
362 (dev->device == PCI_DEVICE_ID_INTEL_82372FB_1)) ? 1 : 0;
363 int ultra = ((ultra66) ||
364 (dev->device == PCI_DEVICE_ID_INTEL_82371AB) ||
365 (dev->device == PCI_DEVICE_ID_INTEL_82443MX_1) ||
366 (dev->device == PCI_DEVICE_ID_INTEL_82451NX) ||
367 (dev->device == PCI_DEVICE_ID_INTEL_82801AB_1)) ? 1 : 0;
368
369 if ((id->dma_ultra & 0x0020) && (udma_66) && (ultra100)) {
370 speed = XFER_UDMA_5;
371 } else if ((id->dma_ultra & 0x0010) && (ultra)) {
372 speed = ((udma_66) && (ultra66)) ? XFER_UDMA_4 : XFER_UDMA_2;
373 } else if ((id->dma_ultra & 0x0008) && (ultra)) {
374 speed = ((udma_66) && (ultra66)) ? XFER_UDMA_3 : XFER_UDMA_1;
375 } else if ((id->dma_ultra & 0x0004) && (ultra)) {
376 speed = XFER_UDMA_2;
377 } else if ((id->dma_ultra & 0x0002) && (ultra)) {
378 speed = XFER_UDMA_1;
379 } else if ((id->dma_ultra & 0x0001) && (ultra)) {
380 speed = XFER_UDMA_0;
381 } else if (id->dma_mword & 0x0004) {
382 speed = XFER_MW_DMA_2;
383 } else if (id->dma_mword & 0x0002) {
384 speed = XFER_MW_DMA_1;
385 } else if (id->dma_1word & 0x0004) {
386 speed = XFER_SW_DMA_2;
387 } else {
388 speed = XFER_PIO_0 + ide_get_best_pio_mode(drive, 255, 5, NULL);
389 }
390
391 (void) piix_tune_chipset(drive, speed);
392
393 return ((int) ((id->dma_ultra >> 11) & 7) ? ide_dma_on :
394 ((id->dma_ultra >> 8) & 7) ? ide_dma_on :
395 ((id->dma_mword >> 8) & 7) ? ide_dma_on :
396 ((id->dma_1word >> 8) & 7) ? ide_dma_on :
397 ide_dma_off_quietly);
398 }
399
400 static int piix_dmaproc(ide_dma_action_t func, ide_drive_t *drive)
401 {
402 switch (func) {
403 case ide_dma_check:
404 return ide_dmaproc((ide_dma_action_t) piix_config_drive_for_dma(drive), drive);
405 default :
406 break;
407 }
408 /* Other cases are done by generic IDE-DMA code. */
409 return ide_dmaproc(func, drive);
410 }
411 #endif /* defined(CONFIG_BLK_DEV_IDEDMA) && (CONFIG_PIIX_TUNING) */
412
413 unsigned int __init pci_init_piix (struct pci_dev *dev, const char *name)
414 {
415 #if defined(DISPLAY_PIIX_TIMINGS) && defined(CONFIG_PROC_FS)
416 if (!piix_proc) {
417 piix_proc = 1;
418 bmide_dev = dev;
419 piix_display_info = &piix_get_info;
420 }
421 #endif /* DISPLAY_PIIX_TIMINGS && CONFIG_PROC_FS */
422 return 0;
423 }
424
425 /*
426 * Sheesh, someone at Intel needs to go read the ATA-4/5 T13 standards.
427 * It does not specify device detection, but channel!!!
428 * You determine later if bit 13 of word93 is set...
429 */
430 unsigned int __init ata66_piix (ide_hwif_t *hwif)
431 {
432 byte reg54h = 0, reg55h = 0, ata66 = 0;
433 byte mask = hwif->channel ? 0xc0 : 0x30;
434
435 pci_read_config_byte(hwif->pci_dev, 0x54, &reg54h);
436 pci_read_config_byte(hwif->pci_dev, 0x55, &reg55h);
437
438 ata66 = (reg54h & mask) ? 1 : 0;
439
440 return ata66;
441 }
442
443 void __init ide_init_piix (ide_hwif_t *hwif)
444 {
445 #ifndef CONFIG_IA64
446 if (!hwif->irq)
447 hwif->irq = hwif->channel ? 15 : 14;
448 #endif /* CONFIG_IA64 */
449
450 hwif->tuneproc = &piix_tune_drive;
451 hwif->drives[0].autotune = 1;
452 hwif->drives[1].autotune = 1;
453
454 if (!hwif->dma_base)
455 return;
456
457 #ifndef CONFIG_BLK_DEV_IDEDMA
458 hwif->autodma = 0;
459 #else /* CONFIG_BLK_DEV_IDEDMA */
460 #ifdef CONFIG_PIIX_TUNING
461 hwif->autodma = 1;
462 hwif->dmaproc = &piix_dmaproc;
463 hwif->speedproc = &piix_tune_chipset;
464 #endif /* CONFIG_PIIX_TUNING */
465 #endif /* !CONFIG_BLK_DEV_IDEDMA */
466 }
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