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Linux 2.4.0-test7-pre6
[davej-history.git] / drivers / isdn / hisax / avm_pci.c
blob4302585dcec1fa6ac2d9656b163b8f254fe4389c
1 /* $Id: avm_pci.c,v 1.18 2000/08/20 07:34:04 keil Exp $
2 *
3 * avm_pci.c low level stuff for AVM Fritz!PCI and ISA PnP isdn cards
4 * Thanks to AVM, Berlin for informations
5 *
6 * Author Karsten Keil (keil@isdn4linux.de)
7 *
8 * This file is (c) under GNU PUBLIC LICENSE
9 *
10 */
11 #define __NO_VERSION__
12 #include <linux/config.h>
13 #include "hisax.h"
14 #include "isac.h"
15 #include "isdnl1.h"
16 #include <linux/pci.h>
17 #include <linux/interrupt.h>
18
19 extern const char *CardType[];
20 static const char *avm_pci_rev = "$Revision: 1.18 $";
21
22 #define AVM_FRITZ_PCI 1
23 #define AVM_FRITZ_PNP 2
24
25 #ifndef PCI_VENDOR_ID_AVM
26 #define PCI_VENDOR_ID_AVM 0x1244
27 #endif
28 #ifndef PCI_DEVICE_ID_AVM_FRITZ
29 #define PCI_DEVICE_ID_AVM_FRITZ 0xa00
30 #endif
31
32 #define HDLC_FIFO 0x0
33 #define HDLC_STATUS 0x4
34
35 #define AVM_HDLC_1 0x00
36 #define AVM_HDLC_2 0x01
37 #define AVM_ISAC_FIFO 0x02
38 #define AVM_ISAC_REG_LOW 0x04
39 #define AVM_ISAC_REG_HIGH 0x06
40
41 #define AVM_STATUS0_IRQ_ISAC 0x01
42 #define AVM_STATUS0_IRQ_HDLC 0x02
43 #define AVM_STATUS0_IRQ_TIMER 0x04
44 #define AVM_STATUS0_IRQ_MASK 0x07
45
46 #define AVM_STATUS0_RESET 0x01
47 #define AVM_STATUS0_DIS_TIMER 0x02
48 #define AVM_STATUS0_RES_TIMER 0x04
49 #define AVM_STATUS0_ENA_IRQ 0x08
50 #define AVM_STATUS0_TESTBIT 0x10
51
52 #define AVM_STATUS1_INT_SEL 0x0f
53 #define AVM_STATUS1_ENA_IOM 0x80
54
55 #define HDLC_MODE_ITF_FLG 0x01
56 #define HDLC_MODE_TRANS 0x02
57 #define HDLC_MODE_CCR_7 0x04
58 #define HDLC_MODE_CCR_16 0x08
59 #define HDLC_MODE_TESTLOOP 0x80
60
61 #define HDLC_INT_XPR 0x80
62 #define HDLC_INT_XDU 0x40
63 #define HDLC_INT_RPR 0x20
64 #define HDLC_INT_MASK 0xE0
65
66 #define HDLC_STAT_RME 0x01
67 #define HDLC_STAT_RDO 0x10
68 #define HDLC_STAT_CRCVFRRAB 0x0E
69 #define HDLC_STAT_CRCVFR 0x06
70 #define HDLC_STAT_RML_MASK 0x3f00
71
72 #define HDLC_CMD_XRS 0x80
73 #define HDLC_CMD_XME 0x01
74 #define HDLC_CMD_RRS 0x20
75 #define HDLC_CMD_XML_MASK 0x3f00
76
77
78 /* Interface functions */
79
80 static u_char
81 ReadISAC(struct IsdnCardState *cs, u_char offset)
82 {
83 register u_char idx = (offset > 0x2f) ? AVM_ISAC_REG_HIGH : AVM_ISAC_REG_LOW;
84 register u_char val;
85 register long flags;
86
87 save_flags(flags);
88 cli();
89 outb(idx, cs->hw.avm.cfg_reg + 4);
90 val = inb(cs->hw.avm.isac + (offset & 0xf));
91 restore_flags(flags);
92 return (val);
93 }
94
95 static void
96 WriteISAC(struct IsdnCardState *cs, u_char offset, u_char value)
97 {
98 register u_char idx = (offset > 0x2f) ? AVM_ISAC_REG_HIGH : AVM_ISAC_REG_LOW;
99 register long flags;
100
101 save_flags(flags);
102 cli();
103 outb(idx, cs->hw.avm.cfg_reg + 4);
104 outb(value, cs->hw.avm.isac + (offset & 0xf));
105 restore_flags(flags);
106 }
107
108 static void
109 ReadISACfifo(struct IsdnCardState *cs, u_char * data, int size)
110 {
111 outb(AVM_ISAC_FIFO, cs->hw.avm.cfg_reg + 4);
112 insb(cs->hw.avm.isac, data, size);
113 }
114
115 static void
116 WriteISACfifo(struct IsdnCardState *cs, u_char * data, int size)
117 {
118 outb(AVM_ISAC_FIFO, cs->hw.avm.cfg_reg + 4);
119 outsb(cs->hw.avm.isac, data, size);
120 }
121
122 static inline u_int
123 ReadHDLCPCI(struct IsdnCardState *cs, int chan, u_char offset)
124 {
125 register u_int idx = chan ? AVM_HDLC_2 : AVM_HDLC_1;
126 register u_int val;
127 register long flags;
128
129 save_flags(flags);
130 cli();
131 outl(idx, cs->hw.avm.cfg_reg + 4);
132 val = inl(cs->hw.avm.isac + offset);
133 restore_flags(flags);
134 return (val);
135 }
136
137 static inline void
138 WriteHDLCPCI(struct IsdnCardState *cs, int chan, u_char offset, u_int value)
139 {
140 register u_int idx = chan ? AVM_HDLC_2 : AVM_HDLC_1;
141 register long flags;
142
143 save_flags(flags);
144 cli();
145 outl(idx, cs->hw.avm.cfg_reg + 4);
146 outl(value, cs->hw.avm.isac + offset);
147 restore_flags(flags);
148 }
149
150 static inline u_char
151 ReadHDLCPnP(struct IsdnCardState *cs, int chan, u_char offset)
152 {
153 register u_char idx = chan ? AVM_HDLC_2 : AVM_HDLC_1;
154 register u_char val;
155 register long flags;
156
157 save_flags(flags);
158 cli();
159 outb(idx, cs->hw.avm.cfg_reg + 4);
160 val = inb(cs->hw.avm.isac + offset);
161 restore_flags(flags);
162 return (val);
163 }
164
165 static inline void
166 WriteHDLCPnP(struct IsdnCardState *cs, int chan, u_char offset, u_char value)
167 {
168 register u_char idx = chan ? AVM_HDLC_2 : AVM_HDLC_1;
169 register long flags;
170
171 save_flags(flags);
172 cli();
173 outb(idx, cs->hw.avm.cfg_reg + 4);
174 outb(value, cs->hw.avm.isac + offset);
175 restore_flags(flags);
176 }
177
178 static u_char
179 ReadHDLC_s(struct IsdnCardState *cs, int chan, u_char offset)
180 {
181 return(0xff & ReadHDLCPCI(cs, chan, offset));
182 }
183
184 static void
185 WriteHDLC_s(struct IsdnCardState *cs, int chan, u_char offset, u_char value)
186 {
187 WriteHDLCPCI(cs, chan, offset, value);
188 }
189
190 static inline
191 struct BCState *Sel_BCS(struct IsdnCardState *cs, int channel)
192 {
193 if (cs->bcs[0].mode && (cs->bcs[0].channel == channel))
194 return(&cs->bcs[0]);
195 else if (cs->bcs[1].mode && (cs->bcs[1].channel == channel))
196 return(&cs->bcs[1]);
197 else
198 return(NULL);
199 }
200
201 void inline
202 hdlc_sched_event(struct BCState *bcs, int event)
203 {
204 bcs->event |= 1 << event;
205 queue_task(&bcs->tqueue, &tq_immediate);
206 mark_bh(IMMEDIATE_BH);
207 }
208
209 void
210 write_ctrl(struct BCState *bcs, int which) {
211
212 if (bcs->cs->debug & L1_DEB_HSCX)
213 debugl1(bcs->cs, "hdlc %c wr%x ctrl %x",
214 'A' + bcs->channel, which, bcs->hw.hdlc.ctrl.ctrl);
215 if (bcs->cs->subtyp == AVM_FRITZ_PCI) {
216 WriteHDLCPCI(bcs->cs, bcs->channel, HDLC_STATUS, bcs->hw.hdlc.ctrl.ctrl);
217 } else {
218 if (which & 4)
219 WriteHDLCPnP(bcs->cs, bcs->channel, HDLC_STATUS + 2,
220 bcs->hw.hdlc.ctrl.sr.mode);
221 if (which & 2)
222 WriteHDLCPnP(bcs->cs, bcs->channel, HDLC_STATUS + 1,
223 bcs->hw.hdlc.ctrl.sr.xml);
224 if (which & 1)
225 WriteHDLCPnP(bcs->cs, bcs->channel, HDLC_STATUS,
226 bcs->hw.hdlc.ctrl.sr.cmd);
227 }
228 }
229
230 void
231 modehdlc(struct BCState *bcs, int mode, int bc)
232 {
233 struct IsdnCardState *cs = bcs->cs;
234 int hdlc = bcs->channel;
235
236 if (cs->debug & L1_DEB_HSCX)
237 debugl1(cs, "hdlc %c mode %d --> %d ichan %d --> %d",
238 'A' + hdlc, bcs->mode, mode, hdlc, bc);
239 bcs->hw.hdlc.ctrl.ctrl = 0;
240 switch (mode) {
241 case (-1): /* used for init */
242 bcs->mode = 1;
243 bcs->channel = bc;
244 bc = 0;
245 case (L1_MODE_NULL):
246 if (bcs->mode == L1_MODE_NULL)
247 return;
248 bcs->hw.hdlc.ctrl.sr.cmd = HDLC_CMD_XRS | HDLC_CMD_RRS;
249 bcs->hw.hdlc.ctrl.sr.mode = HDLC_MODE_TRANS;
250 write_ctrl(bcs, 5);
251 bcs->mode = L1_MODE_NULL;
252 bcs->channel = bc;
253 break;
254 case (L1_MODE_TRANS):
255 bcs->mode = mode;
256 bcs->channel = bc;
257 bcs->hw.hdlc.ctrl.sr.cmd = HDLC_CMD_XRS | HDLC_CMD_RRS;
258 bcs->hw.hdlc.ctrl.sr.mode = HDLC_MODE_TRANS;
259 write_ctrl(bcs, 5);
260 bcs->hw.hdlc.ctrl.sr.cmd = HDLC_CMD_XRS;
261 write_ctrl(bcs, 1);
262 bcs->hw.hdlc.ctrl.sr.cmd = 0;
263 hdlc_sched_event(bcs, B_XMTBUFREADY);
264 break;
265 case (L1_MODE_HDLC):
266 bcs->mode = mode;
267 bcs->channel = bc;
268 bcs->hw.hdlc.ctrl.sr.cmd = HDLC_CMD_XRS | HDLC_CMD_RRS;
269 bcs->hw.hdlc.ctrl.sr.mode = HDLC_MODE_ITF_FLG;
270 write_ctrl(bcs, 5);
271 bcs->hw.hdlc.ctrl.sr.cmd = HDLC_CMD_XRS;
272 write_ctrl(bcs, 1);
273 bcs->hw.hdlc.ctrl.sr.cmd = 0;
274 hdlc_sched_event(bcs, B_XMTBUFREADY);
275 break;
276 }
277 }
278
279 static inline void
280 hdlc_empty_fifo(struct BCState *bcs, int count)
281 {
282 register u_int *ptr;
283 u_char *p;
284 u_char idx = bcs->channel ? AVM_HDLC_2 : AVM_HDLC_1;
285 int cnt=0;
286 struct IsdnCardState *cs = bcs->cs;
287
288 if ((cs->debug & L1_DEB_HSCX) && !(cs->debug & L1_DEB_HSCX_FIFO))
289 debugl1(cs, "hdlc_empty_fifo %d", count);
290 if (bcs->hw.hdlc.rcvidx + count > HSCX_BUFMAX) {
291 if (cs->debug & L1_DEB_WARN)
292 debugl1(cs, "hdlc_empty_fifo: incoming packet too large");
293 return;
294 }
295 ptr = (u_int *) p = bcs->hw.hdlc.rcvbuf + bcs->hw.hdlc.rcvidx;
296 bcs->hw.hdlc.rcvidx += count;
297 if (cs->subtyp == AVM_FRITZ_PCI) {
298 outl(idx, cs->hw.avm.cfg_reg + 4);
299 while (cnt < count) {
300 #ifdef __powerpc__
301 #ifdef CONFIG_APUS
302 *ptr++ = in_le32((unsigned *)(cs->hw.avm.isac +_IO_BASE));
303 #else
304 *ptr++ = in_be32((unsigned *)(cs->hw.avm.isac +_IO_BASE));
305 #endif /* CONFIG_APUS */
306 #else
307 *ptr++ = inl(cs->hw.avm.isac);
308 #endif /* __powerpc__ */
309 cnt += 4;
310 }
311 } else {
312 outb(idx, cs->hw.avm.cfg_reg + 4);
313 while (cnt < count) {
314 *p++ = inb(cs->hw.avm.isac);
315 cnt++;
316 }
317 }
318 if (cs->debug & L1_DEB_HSCX_FIFO) {
319 char *t = bcs->blog;
320
321 if (cs->subtyp == AVM_FRITZ_PNP)
322 p = (u_char *) ptr;
323 t += sprintf(t, "hdlc_empty_fifo %c cnt %d",
324 bcs->channel ? 'B' : 'A', count);
325 QuickHex(t, p, count);
326 debugl1(cs, bcs->blog);
327 }
328 }
329
330 static inline void
331 hdlc_fill_fifo(struct BCState *bcs)
332 {
333 struct IsdnCardState *cs = bcs->cs;
334 int count, cnt =0;
335 int fifo_size = 32;
336 u_char *p;
337 u_int *ptr;
338
339 if ((cs->debug & L1_DEB_HSCX) && !(cs->debug & L1_DEB_HSCX_FIFO))
340 debugl1(cs, "hdlc_fill_fifo");
341 if (!bcs->tx_skb)
342 return;
343 if (bcs->tx_skb->len <= 0)
344 return;
345
346 bcs->hw.hdlc.ctrl.sr.cmd &= ~HDLC_CMD_XME;
347 if (bcs->tx_skb->len > fifo_size) {
348 count = fifo_size;
349 } else {
350 count = bcs->tx_skb->len;
351 if (bcs->mode != L1_MODE_TRANS)
352 bcs->hw.hdlc.ctrl.sr.cmd |= HDLC_CMD_XME;
353 }
354 if ((cs->debug & L1_DEB_HSCX) && !(cs->debug & L1_DEB_HSCX_FIFO))
355 debugl1(cs, "hdlc_fill_fifo %d/%ld", count, bcs->tx_skb->len);
356 ptr = (u_int *) p = bcs->tx_skb->data;
357 skb_pull(bcs->tx_skb, count);
358 bcs->tx_cnt -= count;
359 bcs->hw.hdlc.count += count;
360 bcs->hw.hdlc.ctrl.sr.xml = ((count == fifo_size) ? 0 : count);
361 write_ctrl(bcs, 3); /* sets the correct index too */
362 if (cs->subtyp == AVM_FRITZ_PCI) {
363 while (cnt<count) {
364 #ifdef __powerpc__
365 #ifdef CONFIG_APUS
366 out_le32((unsigned *)(cs->hw.avm.isac +_IO_BASE), *ptr++);
367 #else
368 out_be32((unsigned *)(cs->hw.avm.isac +_IO_BASE), *ptr++);
369 #endif /* CONFIG_APUS */
370 #else
371 outl(*ptr++, cs->hw.avm.isac);
372 #endif /* __powerpc__ */
373 cnt += 4;
374 }
375 } else {
376 while (cnt<count) {
377 outb(*p++, cs->hw.avm.isac);
378 cnt++;
379 }
380 }
381 if (cs->debug & L1_DEB_HSCX_FIFO) {
382 char *t = bcs->blog;
383
384 if (cs->subtyp == AVM_FRITZ_PNP)
385 p = (u_char *) ptr;
386 t += sprintf(t, "hdlc_fill_fifo %c cnt %d",
387 bcs->channel ? 'B' : 'A', count);
388 QuickHex(t, p, count);
389 debugl1(cs, bcs->blog);
390 }
391 }
392
393 static void
394 fill_hdlc(struct BCState *bcs)
395 {
396 long flags;
397 save_flags(flags);
398 cli();
399 hdlc_fill_fifo(bcs);
400 restore_flags(flags);
401 }
402
403 static inline void
404 HDLC_irq(struct BCState *bcs, u_int stat) {
405 int len;
406 struct sk_buff *skb;
407
408 if (bcs->cs->debug & L1_DEB_HSCX)
409 debugl1(bcs->cs, "ch%d stat %#x", bcs->channel, stat);
410 if (stat & HDLC_INT_RPR) {
411 if (stat & HDLC_STAT_RDO) {
412 if (bcs->cs->debug & L1_DEB_HSCX)
413 debugl1(bcs->cs, "RDO");
414 else
415 debugl1(bcs->cs, "ch%d stat %#x", bcs->channel, stat);
416 bcs->hw.hdlc.ctrl.sr.xml = 0;
417 bcs->hw.hdlc.ctrl.sr.cmd |= HDLC_CMD_RRS;
418 write_ctrl(bcs, 1);
419 bcs->hw.hdlc.ctrl.sr.cmd &= ~HDLC_CMD_RRS;
420 write_ctrl(bcs, 1);
421 bcs->hw.hdlc.rcvidx = 0;
422 } else {
423 if (!(len = (stat & HDLC_STAT_RML_MASK)>>8))
424 len = 32;
425 hdlc_empty_fifo(bcs, len);
426 if ((stat & HDLC_STAT_RME) || (bcs->mode == L1_MODE_TRANS)) {
427 if (((stat & HDLC_STAT_CRCVFRRAB)==HDLC_STAT_CRCVFR) ||
428 (bcs->mode == L1_MODE_TRANS)) {
429 if (!(skb = dev_alloc_skb(bcs->hw.hdlc.rcvidx)))
430 printk(KERN_WARNING "HDLC: receive out of memory\n");
431 else {
432 memcpy(skb_put(skb, bcs->hw.hdlc.rcvidx),
433 bcs->hw.hdlc.rcvbuf, bcs->hw.hdlc.rcvidx);
434 skb_queue_tail(&bcs->rqueue, skb);
435 }
436 bcs->hw.hdlc.rcvidx = 0;
437 hdlc_sched_event(bcs, B_RCVBUFREADY);
438 } else {
439 if (bcs->cs->debug & L1_DEB_HSCX)
440 debugl1(bcs->cs, "invalid frame");
441 else
442 debugl1(bcs->cs, "ch%d invalid frame %#x", bcs->channel, stat);
443 bcs->hw.hdlc.rcvidx = 0;
444 }
445 }
446 }
447 }
448 if (stat & HDLC_INT_XDU) {
449 /* Here we lost an TX interrupt, so
450 * restart transmitting the whole frame.
451 */
452 if (bcs->tx_skb) {
453 skb_push(bcs->tx_skb, bcs->hw.hdlc.count);
454 bcs->tx_cnt += bcs->hw.hdlc.count;
455 bcs->hw.hdlc.count = 0;
456 // hdlc_sched_event(bcs, B_XMTBUFREADY);
457 if (bcs->cs->debug & L1_DEB_WARN)
458 debugl1(bcs->cs, "ch%d XDU", bcs->channel);
459 } else if (bcs->cs->debug & L1_DEB_WARN)
460 debugl1(bcs->cs, "ch%d XDU without skb", bcs->channel);
461 bcs->hw.hdlc.ctrl.sr.xml = 0;
462 bcs->hw.hdlc.ctrl.sr.cmd |= HDLC_CMD_XRS;
463 write_ctrl(bcs, 1);
464 bcs->hw.hdlc.ctrl.sr.cmd &= ~HDLC_CMD_XRS;
465 write_ctrl(bcs, 1);
466 hdlc_fill_fifo(bcs);
467 } else if (stat & HDLC_INT_XPR) {
468 if (bcs->tx_skb) {
469 if (bcs->tx_skb->len) {
470 hdlc_fill_fifo(bcs);
471 return;
472 } else {
473 if (bcs->st->lli.l1writewakeup &&
474 (PACKET_NOACK != bcs->tx_skb->pkt_type))
475 bcs->st->lli.l1writewakeup(bcs->st, bcs->hw.hdlc.count);
476 dev_kfree_skb_irq(bcs->tx_skb);
477 bcs->hw.hdlc.count = 0;
478 bcs->tx_skb = NULL;
479 }
480 }
481 if ((bcs->tx_skb = skb_dequeue(&bcs->squeue))) {
482 bcs->hw.hdlc.count = 0;
483 test_and_set_bit(BC_FLG_BUSY, &bcs->Flag);
484 hdlc_fill_fifo(bcs);
485 } else {
486 test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
487 hdlc_sched_event(bcs, B_XMTBUFREADY);
488 }
489 }
490 }
491
492 inline void
493 HDLC_irq_main(struct IsdnCardState *cs)
494 {
495 u_int stat;
496 long flags;
497 struct BCState *bcs;
498
499 save_flags(flags);
500 cli();
501 if (cs->subtyp == AVM_FRITZ_PCI) {
502 stat = ReadHDLCPCI(cs, 0, HDLC_STATUS);
503 } else {
504 stat = ReadHDLCPnP(cs, 0, HDLC_STATUS);
505 if (stat & HDLC_INT_RPR)
506 stat |= (ReadHDLCPnP(cs, 0, HDLC_STATUS+1))<<8;
507 }
508 if (stat & HDLC_INT_MASK) {
509 if (!(bcs = Sel_BCS(cs, 0))) {
510 if (cs->debug)
511 debugl1(cs, "hdlc spurious channel 0 IRQ");
512 } else
513 HDLC_irq(bcs, stat);
514 }
515 if (cs->subtyp == AVM_FRITZ_PCI) {
516 stat = ReadHDLCPCI(cs, 1, HDLC_STATUS);
517 } else {
518 stat = ReadHDLCPnP(cs, 1, HDLC_STATUS);
519 if (stat & HDLC_INT_RPR)
520 stat |= (ReadHDLCPnP(cs, 1, HDLC_STATUS+1))<<8;
521 }
522 if (stat & HDLC_INT_MASK) {
523 if (!(bcs = Sel_BCS(cs, 1))) {
524 if (cs->debug)
525 debugl1(cs, "hdlc spurious channel 1 IRQ");
526 } else
527 HDLC_irq(bcs, stat);
528 }
529 restore_flags(flags);
530 }
531
532 void
533 hdlc_l2l1(struct PStack *st, int pr, void *arg)
534 {
535 struct sk_buff *skb = arg;
536 long flags;
537
538 switch (pr) {
539 case (PH_DATA | REQUEST):
540 save_flags(flags);
541 cli();
542 if (st->l1.bcs->tx_skb) {
543 skb_queue_tail(&st->l1.bcs->squeue, skb);
544 restore_flags(flags);
545 } else {
546 st->l1.bcs->tx_skb = skb;
547 test_and_set_bit(BC_FLG_BUSY, &st->l1.bcs->Flag);
548 st->l1.bcs->hw.hdlc.count = 0;
549 restore_flags(flags);
550 st->l1.bcs->cs->BC_Send_Data(st->l1.bcs);
551 }
552 break;
553 case (PH_PULL | INDICATION):
554 if (st->l1.bcs->tx_skb) {
555 printk(KERN_WARNING "hdlc_l2l1: this shouldn't happen\n");
556 break;
557 }
558 test_and_set_bit(BC_FLG_BUSY, &st->l1.bcs->Flag);
559 st->l1.bcs->tx_skb = skb;
560 st->l1.bcs->hw.hdlc.count = 0;
561 st->l1.bcs->cs->BC_Send_Data(st->l1.bcs);
562 break;
563 case (PH_PULL | REQUEST):
564 if (!st->l1.bcs->tx_skb) {
565 test_and_clear_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
566 st->l1.l1l2(st, PH_PULL | CONFIRM, NULL);
567 } else
568 test_and_set_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
569 break;
570 case (PH_ACTIVATE | REQUEST):
571 test_and_set_bit(BC_FLG_ACTIV, &st->l1.bcs->Flag);
572 modehdlc(st->l1.bcs, st->l1.mode, st->l1.bc);
573 l1_msg_b(st, pr, arg);
574 break;
575 case (PH_DEACTIVATE | REQUEST):
576 l1_msg_b(st, pr, arg);
577 break;
578 case (PH_DEACTIVATE | CONFIRM):
579 test_and_clear_bit(BC_FLG_ACTIV, &st->l1.bcs->Flag);
580 test_and_clear_bit(BC_FLG_BUSY, &st->l1.bcs->Flag);
581 modehdlc(st->l1.bcs, 0, st->l1.bc);
582 st->l1.l1l2(st, PH_DEACTIVATE | CONFIRM, NULL);
583 break;
584 }
585 }
586
587 void
588 close_hdlcstate(struct BCState *bcs)
589 {
590 modehdlc(bcs, 0, 0);
591 if (test_and_clear_bit(BC_FLG_INIT, &bcs->Flag)) {
592 if (bcs->hw.hdlc.rcvbuf) {
593 kfree(bcs->hw.hdlc.rcvbuf);
594 bcs->hw.hdlc.rcvbuf = NULL;
595 }
596 if (bcs->blog) {
597 kfree(bcs->blog);
598 bcs->blog = NULL;
599 }
600 discard_queue(&bcs->rqueue);
601 discard_queue(&bcs->squeue);
602 if (bcs->tx_skb) {
603 dev_kfree_skb_any(bcs->tx_skb);
604 bcs->tx_skb = NULL;
605 test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
606 }
607 }
608 }
609
610 int
611 open_hdlcstate(struct IsdnCardState *cs, struct BCState *bcs)
612 {
613 if (!test_and_set_bit(BC_FLG_INIT, &bcs->Flag)) {
614 if (!(bcs->hw.hdlc.rcvbuf = kmalloc(HSCX_BUFMAX, GFP_ATOMIC))) {
615 printk(KERN_WARNING
616 "HiSax: No memory for hdlc.rcvbuf\n");
617 return (1);
618 }
619 if (!(bcs->blog = kmalloc(MAX_BLOG_SPACE, GFP_ATOMIC))) {
620 printk(KERN_WARNING
621 "HiSax: No memory for bcs->blog\n");
622 test_and_clear_bit(BC_FLG_INIT, &bcs->Flag);
623 kfree(bcs->hw.hdlc.rcvbuf);
624 bcs->hw.hdlc.rcvbuf = NULL;
625 return (2);
626 }
627 skb_queue_head_init(&bcs->rqueue);
628 skb_queue_head_init(&bcs->squeue);
629 }
630 bcs->tx_skb = NULL;
631 test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
632 bcs->event = 0;
633 bcs->hw.hdlc.rcvidx = 0;
634 bcs->tx_cnt = 0;
635 return (0);
636 }
637
638 int
639 setstack_hdlc(struct PStack *st, struct BCState *bcs)
640 {
641 bcs->channel = st->l1.bc;
642 if (open_hdlcstate(st->l1.hardware, bcs))
643 return (-1);
644 st->l1.bcs = bcs;
645 st->l2.l2l1 = hdlc_l2l1;
646 setstack_manager(st);
647 bcs->st = st;
648 setstack_l1_B(st);
649 return (0);
650 }
651
652 HISAX_INITFUNC(void
653 clear_pending_hdlc_ints(struct IsdnCardState *cs))
654 {
655 u_int val;
656
657 if (cs->subtyp == AVM_FRITZ_PCI) {
658 val = ReadHDLCPCI(cs, 0, HDLC_STATUS);
659 debugl1(cs, "HDLC 1 STA %x", val);
660 val = ReadHDLCPCI(cs, 1, HDLC_STATUS);
661 debugl1(cs, "HDLC 2 STA %x", val);
662 } else {
663 val = ReadHDLCPnP(cs, 0, HDLC_STATUS);
664 debugl1(cs, "HDLC 1 STA %x", val);
665 val = ReadHDLCPnP(cs, 0, HDLC_STATUS + 1);
666 debugl1(cs, "HDLC 1 RML %x", val);
667 val = ReadHDLCPnP(cs, 0, HDLC_STATUS + 2);
668 debugl1(cs, "HDLC 1 MODE %x", val);
669 val = ReadHDLCPnP(cs, 0, HDLC_STATUS + 3);
670 debugl1(cs, "HDLC 1 VIN %x", val);
671 val = ReadHDLCPnP(cs, 1, HDLC_STATUS);
672 debugl1(cs, "HDLC 2 STA %x", val);
673 val = ReadHDLCPnP(cs, 1, HDLC_STATUS + 1);
674 debugl1(cs, "HDLC 2 RML %x", val);
675 val = ReadHDLCPnP(cs, 1, HDLC_STATUS + 2);
676 debugl1(cs, "HDLC 2 MODE %x", val);
677 val = ReadHDLCPnP(cs, 1, HDLC_STATUS + 3);
678 debugl1(cs, "HDLC 2 VIN %x", val);
679 }
680 }
681
682 HISAX_INITFUNC(void
683 inithdlc(struct IsdnCardState *cs))
684 {
685 cs->bcs[0].BC_SetStack = setstack_hdlc;
686 cs->bcs[1].BC_SetStack = setstack_hdlc;
687 cs->bcs[0].BC_Close = close_hdlcstate;
688 cs->bcs[1].BC_Close = close_hdlcstate;
689 modehdlc(cs->bcs, -1, 0);
690 modehdlc(cs->bcs + 1, -1, 1);
691 }
692
693 static void
694 avm_pcipnp_interrupt(int intno, void *dev_id, struct pt_regs *regs)
695 {
696 struct IsdnCardState *cs = dev_id;
697 u_char val;
698 u_char sval;
699
700 if (!cs) {
701 printk(KERN_WARNING "AVM PCI: Spurious interrupt!\n");
702 return;
703 }
704 sval = inb(cs->hw.avm.cfg_reg + 2);
705 if ((sval & AVM_STATUS0_IRQ_MASK) == AVM_STATUS0_IRQ_MASK)
706 /* possible a shared IRQ reqest */
707 return;
708 if (!(sval & AVM_STATUS0_IRQ_ISAC)) {
709 val = ReadISAC(cs, ISAC_ISTA);
710 isac_interrupt(cs, val);
711 }
712 if (!(sval & AVM_STATUS0_IRQ_HDLC)) {
713 HDLC_irq_main(cs);
714 }
715 WriteISAC(cs, ISAC_MASK, 0xFF);
716 WriteISAC(cs, ISAC_MASK, 0x0);
717 }
718
719 static void
720 reset_avmpcipnp(struct IsdnCardState *cs)
721 {
722 long flags;
723
724 printk(KERN_INFO "AVM PCI/PnP: reset\n");
725 save_flags(flags);
726 sti();
727 outb(AVM_STATUS0_RESET | AVM_STATUS0_DIS_TIMER, cs->hw.avm.cfg_reg + 2);
728 set_current_state(TASK_UNINTERRUPTIBLE);
729 schedule_timeout((10*HZ)/1000); /* Timeout 10ms */
730 outb(AVM_STATUS0_DIS_TIMER | AVM_STATUS0_RES_TIMER | AVM_STATUS0_ENA_IRQ, cs->hw.avm.cfg_reg + 2);
731 outb(AVM_STATUS1_ENA_IOM | cs->irq, cs->hw.avm.cfg_reg + 3);
732 set_current_state(TASK_UNINTERRUPTIBLE);
733 schedule_timeout((10*HZ)/1000); /* Timeout 10ms */
734 printk(KERN_INFO "AVM PCI/PnP: S1 %x\n", inb(cs->hw.avm.cfg_reg + 3));
735 }
736
737 static int
738 AVM_card_msg(struct IsdnCardState *cs, int mt, void *arg)
739 {
740 switch (mt) {
741 case CARD_RESET:
742 reset_avmpcipnp(cs);
743 return(0);
744 case CARD_RELEASE:
745 outb(0, cs->hw.avm.cfg_reg + 2);
746 release_region(cs->hw.avm.cfg_reg, 32);
747 return(0);
748 case CARD_INIT:
749 clear_pending_isac_ints(cs);
750 initisac(cs);
751 clear_pending_hdlc_ints(cs);
752 inithdlc(cs);
753 outb(AVM_STATUS0_DIS_TIMER | AVM_STATUS0_RES_TIMER,
754 cs->hw.avm.cfg_reg + 2);
755 WriteISAC(cs, ISAC_MASK, 0);
756 outb(AVM_STATUS0_DIS_TIMER | AVM_STATUS0_RES_TIMER |
757 AVM_STATUS0_ENA_IRQ, cs->hw.avm.cfg_reg + 2);
758 /* RESET Receiver and Transmitter */
759 WriteISAC(cs, ISAC_CMDR, 0x41);
760 return(0);
761 case CARD_TEST:
762 return(0);
763 }
764 return(0);
765 }
766
767 static struct pci_dev *dev_avm __initdata = NULL;
768
769 __initfunc(int
770 setup_avm_pcipnp(struct IsdnCard *card))
771 {
772 u_int val, ver;
773 struct IsdnCardState *cs = card->cs;
774 char tmp[64];
775
776 strcpy(tmp, avm_pci_rev);
777 printk(KERN_INFO "HiSax: AVM PCI driver Rev. %s\n", HiSax_getrev(tmp));
778 if (cs->typ != ISDN_CTYPE_FRITZPCI)
779 return (0);
780 if (card->para[1]) {
781 cs->hw.avm.cfg_reg = card->para[1];
782 cs->irq = card->para[0];
783 cs->subtyp = AVM_FRITZ_PNP;
784 } else {
785 #if CONFIG_PCI
786 if (!pci_present()) {
787 printk(KERN_ERR "FritzPCI: no PCI bus present\n");
788 return(0);
789 }
790 if ((dev_avm = pci_find_device(PCI_VENDOR_ID_AVM,
791 PCI_DEVICE_ID_AVM_FRITZ, dev_avm))) {
792 cs->irq = dev_avm->irq;
793 if (!cs->irq) {
794 printk(KERN_ERR "FritzPCI: No IRQ for PCI card found\n");
795 return(0);
796 }
797 if (pci_enable_device(dev_avm))
798 return(0);
799 cs->hw.avm.cfg_reg = pci_resource_start(dev_avm, 1);
800 if (!cs->hw.avm.cfg_reg) {
801 printk(KERN_ERR "FritzPCI: No IO-Adr for PCI card found\n");
802 return(0);
803 }
804 cs->subtyp = AVM_FRITZ_PCI;
805 } else {
806 printk(KERN_WARNING "FritzPCI: No PCI card found\n");
807 return(0);
808 }
809 cs->irq_flags |= SA_SHIRQ;
810 #else
811 printk(KERN_WARNING "FritzPCI: NO_PCI_BIOS\n");
812 return (0);
813 #endif /* CONFIG_PCI */
814 }
815 cs->hw.avm.isac = cs->hw.avm.cfg_reg + 0x10;
816 if (check_region((cs->hw.avm.cfg_reg), 32)) {
817 printk(KERN_WARNING
818 "HiSax: %s config port %x-%x already in use\n",
819 CardType[card->typ],
820 cs->hw.avm.cfg_reg,
821 cs->hw.avm.cfg_reg + 31);
822 return (0);
823 } else {
824 request_region(cs->hw.avm.cfg_reg, 32,
825 (cs->subtyp == AVM_FRITZ_PCI) ? "avm PCI" : "avm PnP");
826 }
827 switch (cs->subtyp) {
828 case AVM_FRITZ_PCI:
829 val = inl(cs->hw.avm.cfg_reg);
830 printk(KERN_INFO "AVM PCI: stat %#x\n", val);
831 printk(KERN_INFO "AVM PCI: Class %X Rev %d\n",
832 val & 0xff, (val>>8) & 0xff);
833 cs->BC_Read_Reg = &ReadHDLC_s;
834 cs->BC_Write_Reg = &WriteHDLC_s;
835 break;
836 case AVM_FRITZ_PNP:
837 val = inb(cs->hw.avm.cfg_reg);
838 ver = inb(cs->hw.avm.cfg_reg + 1);
839 printk(KERN_INFO "AVM PnP: Class %X Rev %d\n", val, ver);
840 reset_avmpcipnp(cs);
841 cs->BC_Read_Reg = &ReadHDLCPnP;
842 cs->BC_Write_Reg = &WriteHDLCPnP;
843 break;
844 default:
845 printk(KERN_WARNING "AVM unknown subtype %d\n", cs->subtyp);
846 return(0);
847 }
848 printk(KERN_INFO "HiSax: %s config irq:%d base:0x%X\n",
849 (cs->subtyp == AVM_FRITZ_PCI) ? "AVM Fritz!PCI" : "AVM Fritz!PnP",
850 cs->irq, cs->hw.avm.cfg_reg);
851
852 cs->readisac = &ReadISAC;
853 cs->writeisac = &WriteISAC;
854 cs->readisacfifo = &ReadISACfifo;
855 cs->writeisacfifo = &WriteISACfifo;
856 cs->BC_Send_Data = &fill_hdlc;
857 cs->cardmsg = &AVM_card_msg;
858 cs->irq_func = &avm_pcipnp_interrupt;
859 ISACVersion(cs, (cs->subtyp == AVM_FRITZ_PCI) ? "AVM PCI:" : "AVM PnP:");
860 return (1);
861 }
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