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Import 2.3.1pre1
[davej-history.git] / drivers / video / imsttfb.c
blob99ebadf4b9d53e2099f720096c1bf5cf28e89a9c
1 /*
2 * drivers/video/imsttfb.c -- frame buffer device for IMS TwinTurbo
3 *
4 * This file is derived from the powermac console "imstt" driver:
5 * Copyright (C) 1997 Sigurdur Asgeirsson
6 * With additional hacking by Jeffrey Kuskin (jsk@mojave.stanford.edu)
7 * Modified by Danilo Beuche 1998
8 * Some register values added by Damien Doligez, INRIA Rocquencourt
9 *
10 * This file was written by Ryan Nielsen (ran@krazynet.com)
11 * Most of the frame buffer device stuff was copied from atyfb.c
12 *
13 * This file is subject to the terms and conditions of the GNU General Public
14 * License. See the file COPYING in the main directory of this archive for
15 * more details.
16 */
17
18 #include <linux/config.h>
19 #include <linux/module.h>
20 #include <linux/kernel.h>
21 #include <linux/errno.h>
22 #include <linux/string.h>
23 #include <linux/mm.h>
24 #include <linux/tty.h>
25 #include <linux/malloc.h>
26 #include <linux/vmalloc.h>
27 #include <linux/delay.h>
28 #include <linux/interrupt.h>
29 #include <linux/fb.h>
30 #include <linux/console.h>
31 #include <linux/selection.h>
32 #include <linux/init.h>
33 #include <linux/pci.h>
34 #include <asm/io.h>
35 #include <asm/uaccess.h>
36
37 #if defined(CONFIG_PPC)
38 #include <linux/nvram.h>
39 #include <asm/prom.h>
40 #include <asm/pci-bridge.h>
41 #include <video/macmodes.h>
42 #endif
43
44 #include <video/fbcon.h>
45 #include <video/fbcon-cfb8.h>
46 #include <video/fbcon-cfb16.h>
47 #include <video/fbcon-cfb24.h>
48 #include <video/fbcon-cfb32.h>
49
50 #ifndef __powerpc__
51 #define eieio() /* Enforce In-order Execution of I/O */
52 #endif
53
54 /* TwinTurbo (Cosmo) registers */
55 enum {
56 S1SA = 0, /* 0x00 */
57 S2SA = 1, /* 0x04 */
58 SP = 2, /* 0x08 */
59 DSA = 3, /* 0x0C */
60 CNT = 4, /* 0x10 */
61 DP_OCTL = 5, /* 0x14 */
62 CLR = 6, /* 0x18 */
63 BI = 8, /* 0x20 */
64 MBC = 9, /* 0x24 */
65 BLTCTL = 10, /* 0x28 */
66
67 /* Scan Timing Generator Registers */
68 HES = 12, /* 0x30 */
69 HEB = 13, /* 0x34 */
70 HSB = 14, /* 0x38 */
71 HT = 15, /* 0x3C */
72 VES = 16, /* 0x40 */
73 VEB = 17, /* 0x44 */
74 VSB = 18, /* 0x48 */
75 VT = 19, /* 0x4C */
76 HCIV = 20, /* 0x50 */
77 VCIV = 21, /* 0x54 */
78 TCDR = 22, /* 0x58 */
79 VIL = 23, /* 0x5C */
80 STGCTL = 24, /* 0x60 */
81
82 /* Screen Refresh Generator Registers */
83 SSR = 25, /* 0x64 */
84 HRIR = 26, /* 0x68 */
85 SPR = 27, /* 0x6C */
86 CMR = 28, /* 0x70 */
87 SRGCTL = 29, /* 0x74 */
88
89 /* RAM Refresh Generator Registers */
90 RRCIV = 30, /* 0x78 */
91 RRSC = 31, /* 0x7C */
92 RRCR = 34, /* 0x88 */
93
94 /* System Registers */
95 GIOE = 32, /* 0x80 */
96 GIO = 33, /* 0x84 */
97 SCR = 35, /* 0x8C */
98 SSTATUS = 36, /* 0x90 */
99 PRC = 37, /* 0x94 */
100
101 #if 0
102 /* PCI Registers */
103 DVID = 0x00000000L,
104 SC = 0x00000004L,
105 CCR = 0x00000008L,
106 OG = 0x0000000CL,
107 BARM = 0x00000010L,
108 BARER = 0x00000030L,
109 #endif
110 };
111
112 /* IBM 624 RAMDAC Direct Registers */
113 enum {
114 PADDRW = 0x00,
115 PDATA = 0x04,
116 PPMASK = 0x08,
117 PADDRR = 0x0c,
118 PIDXLO = 0x10,
119 PIDXHI = 0x14,
120 PIDXDATA= 0x18,
121 PIDXCTL = 0x1c
122 };
123
124 /* IBM 624 RAMDAC Indirect Registers */
125 enum {
126 CLKCTL = 0x02, /* (0x01) Miscellaneous Clock Control */
127 SYNCCTL = 0x03, /* (0x00) Sync Control */
128 HSYNCPOS = 0x04, /* (0x00) Horizontal Sync Position */
129 PWRMNGMT = 0x05, /* (0x00) Power Management */
130 DACOP = 0x06, /* (0x02) DAC Operation */
131 PALETCTL = 0x07, /* (0x00) Palette Control */
132 SYSCLKCTL = 0x08, /* (0x01) System Clock Control */
133 PIXFMT = 0x0a, /* () Pixel Format [bpp >> 3 + 2] */
134 BPP8 = 0x0b, /* () 8 Bits/Pixel Control */
135 BPP16 = 0x0c, /* () 16 Bits/Pixel Control [bit 1=1 for 565] */
136 BPP24 = 0x0d, /* () 24 Bits/Pixel Control */
137 BPP32 = 0x0e, /* () 32 Bits/Pixel Control */
138 PIXCTL1 = 0x10, /* (0x05) Pixel PLL Control 1 */
139 PIXCTL2 = 0x11, /* (0x00) Pixel PLL Control 2 */
140 SYSCLKN = 0x15, /* () System Clock N (System PLL Reference Divider) */
141 SYSCLKM = 0x16, /* () System Clock M (System PLL VCO Divider) */
142 SYSCLKP = 0x17, /* () System Clock P */
143 SYSCLKC = 0x18, /* () System Clock C */
144 /*
145 * Dot clock rate is 20MHz * (m + 1) / ((n + 1) * (p ? 2 * p : 1)
146 * c is charge pump bias which depends on the VCO frequency
147 */
148 PIXM0 = 0x20, /* () Pixel M 0 */
149 PIXN0 = 0x21, /* () Pixel N 0 */
150 PIXP0 = 0x22, /* () Pixel P 0 */
151 PIXC0 = 0x23, /* () Pixel C 0 */
152 CURSCTL = 0x30, /* (0x00) Cursor Control */
153 CURSXLO = 0x31, /* () Cursor X position, low 8 bits */
154 CURSXHI = 0x32, /* () Cursor X position, high 8 bits */
155 CURSYLO = 0x33, /* () Cursor Y position, low 8 bits */
156 CURSYHI = 0x34, /* () Cursor Y position, high 8 bits */
157 CURSHOTX = 0x35, /* () Cursor Hot Spot X */
158 CURSHOTY = 0x36, /* () Cursor Hot Spot Y */
159 CURSACCTL = 0x37, /* () Advanced Cursor Control Enable */
160 CURSACATTR = 0x38, /* () Advanced Cursor Attribute */
161 CURS1R = 0x40, /* () Cursor 1 Red */
162 CURS1G = 0x41, /* () Cursor 1 Green */
163 CURS1B = 0x42, /* () Cursor 1 Blue */
164 CURS2R = 0x43, /* () Cursor 2 Red */
165 CURS2G = 0x44, /* () Cursor 2 Green */
166 CURS2B = 0x45, /* () Cursor 2 Blue */
167 CURS3R = 0x46, /* () Cursor 3 Red */
168 CURS3G = 0x47, /* () Cursor 3 Green */
169 CURS3B = 0x48, /* () Cursor 3 Blue */
170 BORDR = 0x60, /* () Border Color Red */
171 BORDG = 0x61, /* () Border Color Green */
172 BORDB = 0x62, /* () Border Color Blue */
173 MISCTL1 = 0x70, /* (0x00) Miscellaneous Control 1 */
174 MISCTL2 = 0x71, /* (0x00) Miscellaneous Control 2 */
175 MISCTL3 = 0x72, /* (0x00) Miscellaneous Control 3 */
176 KEYCTL = 0x78 /* (0x00) Key Control/DB Operation */
177 };
178
179 /* TI TVP 3030 RAMDAC Direct Registers */
180 enum {
181 TVPADDRW = 0x00, /* 0 Palette/Cursor RAM Write Adress/Index */
182 TVPPDATA = 0x04, /* 1 Palette Data RAM Data */
183 TVPPMASK = 0x08, /* 2 Pixel Read-Mask */
184 TVPPADRR = 0x0c, /* 3 Palette/Cursor RAM Read Adress */
185 TVPCADRW = 0x10, /* 4 Cursor/Overscan Color Write Address */
186 TVPCDATA = 0x14, /* 5 Cursor/Overscan Color Data */
187 /* 6 reserved */
188 TVPCADRR = 0x1c, /* 7 Cursor/Overscan Color Read Address */
189 /* 8 reserved */
190 TVPDCCTL = 0x24, /* 9 Direct Cursor Control */
191 TVPIDATA = 0x28, /* 10 Index Data */
192 TVPCRDAT = 0x2c, /* 11 Cursor RAM Data */
193 TVPCXPOL = 0x30, /* 12 Cursor-Position X LSB */
194 TVPCXPOH = 0x34, /* 13 Cursor-Position X MSB */
195 TVPCYPOL = 0x38, /* 14 Cursor-Position Y LSB */
196 TVPCYPOH = 0x3c, /* 15 Cursor-Position Y MSB */
197 };
198
199 /* TI TVP 3030 RAMDAC Indirect Registers */
200 enum {
201 TVPIRREV = 0x01, /* Silicon Revision [RO] */
202 TVPIRICC = 0x06, /* Indirect Cursor Control (0x00) */
203 TVPIRBRC = 0x07, /* Byte Router Control (0xe4) */
204 TVPIRLAC = 0x0f, /* Latch Control (0x06) */
205 TVPIRTCC = 0x18, /* True Color Control (0x80) */
206 TVPIRMXC = 0x19, /* Multiplex Control (0x98) */
207 TVPIRCLS = 0x1a, /* Clock Selection (0x07) */
208 TVPIRPPG = 0x1c, /* Palette Page (0x00) */
209 TVPIRGEC = 0x1d, /* General Control (0x00) */
210 TVPIRMIC = 0x1e, /* Miscellaneous Control (0x00) */
211 TVPIRPLA = 0x2c, /* PLL Address */
212 TVPIRPPD = 0x2d, /* Pixel Clock PLL Data */
213 TVPIRMPD = 0x2e, /* Memory Clock PLL Data */
214 TVPIRLPD = 0x2f, /* Loop Clock PLL Data */
215 TVPIRCKL = 0x30, /* Color-Key Overlay Low */
216 TVPIRCKH = 0x31, /* Color-Key Overlay High */
217 TVPIRCRL = 0x32, /* Color-Key Red Low */
218 TVPIRCRH = 0x33, /* Color-Key Red High */
219 TVPIRCGL = 0x34, /* Color-Key Green Low */
220 TVPIRCGH = 0x35, /* Color-Key Green High */
221 TVPIRCBL = 0x36, /* Color-Key Blue Low */
222 TVPIRCBH = 0x37, /* Color-Key Blue High */
223 TVPIRCKC = 0x38, /* Color-Key Control (0x00) */
224 TVPIRMLC = 0x39, /* MCLK/Loop Clock Control (0x18) */
225 TVPIRSEN = 0x3a, /* Sense Test (0x00) */
226 TVPIRTMD = 0x3b, /* Test Mode Data */
227 TVPIRRML = 0x3c, /* CRC Remainder LSB [RO] */
228 TVPIRRMM = 0x3d, /* CRC Remainder MSB [RO] */
229 TVPIRRMS = 0x3e, /* CRC Bit Select [WO] */
230 TVPIRDID = 0x3f, /* Device ID [RO] (0x30) */
231 TVPIRRES = 0xff /* Software Reset [WO] */
232 };
233
234 struct initvalues {
235 __u8 addr, value;
236 };
237
238 static struct initvalues ibm_initregs[] __initdata = {
239 { CLKCTL, 0x21 },
240 { SYNCCTL, 0x00 },
241 { HSYNCPOS, 0x00 },
242 { PWRMNGMT, 0x00 },
243 { DACOP, 0x02 },
244 { PALETCTL, 0x00 },
245 { SYSCLKCTL, 0x01 },
246
247 /*
248 * Note that colors in X are correct only if all video data is
249 * passed through the palette in the DAC. That is, "indirect
250 * color" must be configured. This is the case for the IBM DAC
251 * used in the 2MB and 4MB cards, at least.
252 */
253 { BPP8, 0x00 },
254 { BPP16, 0x01 },
255 { BPP24, 0x00 },
256 { BPP32, 0x00 },
257
258 { PIXCTL1, 0x05 },
259 { PIXCTL2, 0x00 },
260 { SYSCLKN, 0x08 },
261 { SYSCLKM, 0x4f },
262 { SYSCLKP, 0x00 },
263 { SYSCLKC, 0x00 },
264 { CURSCTL, 0x00 },
265 { CURSACCTL, 0x01 },
266 { CURSACATTR, 0xa8 },
267 { CURS1R, 0xff },
268 { CURS1G, 0xff },
269 { CURS1B, 0xff },
270 { CURS2R, 0xff },
271 { CURS2G, 0xff },
272 { CURS2B, 0xff },
273 { CURS3R, 0xff },
274 { CURS3G, 0xff },
275 { CURS3B, 0xff },
276 { BORDR, 0xff },
277 { BORDG, 0xff },
278 { BORDB, 0xff },
279 { MISCTL1, 0x01 },
280 { MISCTL2, 0x45 },
281 { MISCTL3, 0x00 },
282 { KEYCTL, 0x00 }
283 };
284
285 static struct initvalues tvp_initregs[] __initdata = {
286 { TVPIRICC, 0x00 },
287 { TVPIRBRC, 0xe4 },
288 { TVPIRLAC, 0x06 },
289 { TVPIRTCC, 0x80 },
290 { TVPIRMXC, 0x4d },
291 { TVPIRCLS, 0x05 },
292 { TVPIRPPG, 0x00 },
293 { TVPIRGEC, 0x00 },
294 { TVPIRMIC, 0x08 },
295 { TVPIRCKL, 0xff },
296 { TVPIRCKH, 0xff },
297 { TVPIRCRL, 0xff },
298 { TVPIRCRH, 0xff },
299 { TVPIRCGL, 0xff },
300 { TVPIRCGH, 0xff },
301 { TVPIRCBL, 0xff },
302 { TVPIRCBH, 0xff },
303 { TVPIRCKC, 0x00 },
304 { TVPIRPLA, 0x00 },
305 { TVPIRPPD, 0xc0 },
306 { TVPIRPPD, 0xd5 },
307 { TVPIRPPD, 0xea },
308 { TVPIRPLA, 0x00 },
309 { TVPIRMPD, 0xb9 },
310 { TVPIRMPD, 0x3a },
311 { TVPIRMPD, 0xb1 },
312 { TVPIRPLA, 0x00 },
313 { TVPIRLPD, 0xc1 },
314 { TVPIRLPD, 0x3d },
315 { TVPIRLPD, 0xf3 },
316 };
317
318 struct imstt_regvals {
319 __u32 pitch;
320 __u16 hes, heb, hsb, ht, ves, veb, vsb, vt, vil;
321 __u8 pclk_m, pclk_n, pclk_p;
322 /* Values of the tvp which change depending on colormode x resolution */
323 __u8 mlc[3]; /* Memory Loop Config 0x39 */
324 __u8 lckl_p[3]; /* P value of LCKL PLL */
325 };
326
327 struct imstt_cursor {
328 struct timer_list timer;
329 int enable;
330 int on;
331 int vbl_cnt;
332 int blink_rate;
333 __u16 x, y, width, height;
334 };
335
336 struct fb_info_imstt {
337 struct fb_info info;
338 struct fb_fix_screeninfo fix;
339 struct display disp;
340 struct display_switch dispsw;
341 union {
342 #ifdef FBCON_HAS_CFB16
343 __u16 cfb16[16];
344 #endif
345 #ifdef FBCON_HAS_CFB24
346 __u32 cfb24[16];
347 #endif
348 #ifdef FBCON_HAS_CFB32
349 __u32 cfb32[16];
350 #endif
351 } fbcon_cmap;
352 struct {
353 __u8 red, green, blue;
354 } palette[256];
355 struct imstt_regvals init;
356 struct imstt_cursor cursor;
357 __u8 *frame_buffer_phys, *frame_buffer;
358 __u32 *dc_regs_phys, *dc_regs;
359 __u8 *cmap_regs_phys, *cmap_regs;
360 __u32 total_vram;
361 __u32 ramdac;
362 };
363
364 enum {
365 IBM = 0,
366 TVP = 1
367 };
368
369 #define USE_NV_MODES 1
370 #define INIT_BPP 8
371 #define INIT_XRES 640
372 #define INIT_YRES 480
373 #define CURSOR_BLINK_RATE 20
374 #define CURSOR_DRAW_DELAY 2
375
376 static int currcon = 0;
377 static char fontname[40] __initdata = { 0 };
378 static char curblink __initdata = 1;
379 static char noaccel __initdata = 0;
380 #if defined(CONFIG_PPC)
381 static signed char init_vmode __initdata = -1, init_cmode __initdata = -1;
382 #endif
383 #ifdef MODULE
384 static struct fb_info_imstt *fb_info_imstt_p[FB_MAX] = { 0, 0, 0, 0, 0, 0, 0, 0 };
385 #endif
386
387 static struct imstt_regvals tvp_reg_init_2 = {
388 512,
389 0x0002, 0x0006, 0x0026, 0x0028, 0x0003, 0x0016, 0x0196, 0x0197, 0x0196,
390 0xec, 0x2a, 0xf3,
391 { 0x3c, 0x3b, 0x39 }, { 0xf3, 0xf3, 0xf3 }
392 };
393
394 static struct imstt_regvals tvp_reg_init_6 = {
395 640,
396 0x0004, 0x0009, 0x0031, 0x0036, 0x0003, 0x002a, 0x020a, 0x020d, 0x020a,
397 0xef, 0x2e, 0xb2,
398 { 0x39, 0x39, 0x38 }, { 0xf3, 0xf3, 0xf3 }
399 };
400
401 static struct imstt_regvals tvp_reg_init_12 = {
402 800,
403 0x0005, 0x000e, 0x0040, 0x0042, 0x0003, 0x018, 0x270, 0x271, 0x270,
404 0xf6, 0x2e, 0xf2,
405 { 0x3a, 0x39, 0x38 }, { 0xf3, 0xf3, 0xf3 }
406 };
407
408 static struct imstt_regvals tvp_reg_init_13 = {
409 832,
410 0x0004, 0x0011, 0x0045, 0x0048, 0x0003, 0x002a, 0x029a, 0x029b, 0x0000,
411 0xfe, 0x3e, 0xf1,
412 { 0x39, 0x38, 0x38 }, { 0xf3, 0xf3, 0xf2 }
413 };
414
415 static struct imstt_regvals tvp_reg_init_17 = {
416 1024,
417 0x0006, 0x0210, 0x0250, 0x0053, 0x1003, 0x0021, 0x0321, 0x0324, 0x0000,
418 0xfc, 0x3a, 0xf1,
419 { 0x39, 0x38, 0x38 }, { 0xf3, 0xf3, 0xf2 }
420 };
421
422 static struct imstt_regvals tvp_reg_init_18 = {
423 1152,
424 0x0009, 0x0011, 0x059, 0x5b, 0x0003, 0x0031, 0x0397, 0x039a, 0x0000,
425 0xfd, 0x3a, 0xf1,
426 { 0x39, 0x38, 0x38 }, { 0xf3, 0xf3, 0xf2 }
427 };
428
429 static struct imstt_regvals tvp_reg_init_19 = {
430 1280,
431 0x0009, 0x0016, 0x0066, 0x0069, 0x0003, 0x0027, 0x03e7, 0x03e8, 0x03e7,
432 0xf7, 0x36, 0xf0,
433 { 0x38, 0x38, 0x38 }, { 0xf3, 0xf2, 0xf1 }
434 };
435
436 static struct imstt_regvals tvp_reg_init_20 = {
437 1280,
438 0x0009, 0x0018, 0x0068, 0x006a, 0x0003, 0x0029, 0x0429, 0x042a, 0x0000,
439 0xf0, 0x2d, 0xf0,
440 { 0x38, 0x38, 0x38 }, { 0xf3, 0xf2, 0xf1 }
441 };
442
443 static __u32
444 getclkMHz (struct fb_info_imstt *p)
445 {
446 __u32 clk_m, clk_n, clk_p;
447
448 clk_m = p->init.pclk_m;
449 clk_n = p->init.pclk_n;
450 clk_p = p->init.pclk_p;
451
452 return 20 * (clk_m + 1) / ((clk_n + 1) * (clk_p ? 2 * clk_p : 1));
453 }
454
455 static void
456 setclkMHz (struct fb_info_imstt *p, __u32 MHz)
457 {
458 __u32 clk_m, clk_n, clk_p, x, stage, spilled;
459
460 clk_m = clk_n = clk_p = 0;
461 stage = spilled = 0;
462 for (;;) {
463 switch (stage) {
464 case 0:
465 clk_m++;
466 break;
467 case 1:
468 clk_n++;
469 break;
470 }
471 x = 20 * (clk_m + 1) / ((clk_n + 1) * (clk_p ? 2 * clk_p : 1));
472 if (x == MHz)
473 break;
474 if (x > MHz) {
475 spilled = 1;
476 stage = 1;
477 } else if (spilled && x < MHz) {
478 stage = 0;
479 }
480 }
481
482 p->init.pclk_m = clk_m;
483 p->init.pclk_n = clk_n;
484 p->init.pclk_p = clk_p;
485 }
486
487 static struct imstt_regvals *
488 compute_imstt_regvals_ibm (struct fb_info_imstt *p, int xres, int yres)
489 {
490 struct imstt_regvals *init = &p->init;
491 __u32 MHz, hes, heb, veb, htp, vtp;
492
493 switch (xres) {
494 case 640:
495 hes = 0x0008; heb = 0x0012; veb = 0x002a; htp = 10; vtp = 2;
496 MHz = 30 /* .25 */ ;
497 break;
498 case 832:
499 hes = 0x0005; heb = 0x0020; veb = 0x0028; htp = 8; vtp = 3;
500 MHz = 57 /* .27_ */ ;
501 break;
502 case 1024:
503 hes = 0x000a; heb = 0x001c; veb = 0x0020; htp = 8; vtp = 3;
504 MHz = 80;
505 break;
506 case 1152:
507 hes = 0x0012; heb = 0x0022; veb = 0x0031; htp = 4; vtp = 3;
508 MHz = 101 /* .6_ */ ;
509 break;
510 case 1280:
511 hes = 0x0012; heb = 0x002f; veb = 0x0029; htp = 4; vtp = 1;
512 MHz = yres == 960 ? 126 : 135;
513 break;
514 case 1600:
515 hes = 0x0018; heb = 0x0040; veb = 0x002a; htp = 4; vtp = 3;
516 MHz = 200;
517 break;
518 default:
519 return 0;
520 }
521
522 setclkMHz(p, MHz);
523
524 init->hes = hes;
525 init->heb = heb;
526 init->hsb = init->heb + (xres >> 3);
527 init->ht = init->hsb + htp;
528 init->ves = 0x0003;
529 init->veb = veb;
530 init->vsb = init->veb + yres;
531 init->vt = init->vsb + vtp;
532 init->vil = init->vsb;
533
534 init->pitch = xres;
535
536 return init;
537 }
538
539 static struct imstt_regvals *
540 compute_imstt_regvals_tvp (struct fb_info_imstt *p, int xres, int yres)
541 {
542 struct imstt_regvals *init;
543
544 switch (xres) {
545 case 512:
546 init = &tvp_reg_init_2;
547 break;
548 case 640:
549 init = &tvp_reg_init_6;
550 break;
551 case 800:
552 init = &tvp_reg_init_12;
553 break;
554 case 832:
555 init = &tvp_reg_init_13;
556 break;
557 case 1024:
558 init = &tvp_reg_init_17;
559 break;
560 case 1152:
561 init = &tvp_reg_init_18;
562 break;
563 case 1280:
564 init = yres == 960 ? &tvp_reg_init_19 : &tvp_reg_init_20;
565 break;
566 default:
567 return 0;
568 }
569 p->init = *init;
570
571 return init;
572 }
573
574 static struct imstt_regvals *
575 compute_imstt_regvals (struct fb_info_imstt *p, u_int xres, u_int yres)
576 {
577 if (p->ramdac == IBM)
578 return compute_imstt_regvals_ibm(p, xres, yres);
579 else
580 return compute_imstt_regvals_tvp(p, xres, yres);
581 }
582
583 static void
584 set_imstt_regvals_ibm (struct fb_info_imstt *p, u_int bpp)
585 {
586 struct imstt_regvals *init = &p->init;
587 __u8 pformat = (bpp >> 3) + 2;
588
589 p->cmap_regs[PIDXHI] = 0; eieio();
590 p->cmap_regs[PIDXLO] = PIXM0; eieio();
591 p->cmap_regs[PIDXDATA] = init->pclk_m; eieio();
592 p->cmap_regs[PIDXLO] = PIXN0; eieio();
593 p->cmap_regs[PIDXDATA] = init->pclk_n; eieio();
594 p->cmap_regs[PIDXLO] = PIXP0; eieio();
595 p->cmap_regs[PIDXDATA] = init->pclk_p; eieio();
596 p->cmap_regs[PIDXLO] = PIXC0; eieio();
597 p->cmap_regs[PIDXDATA] = 0x02; eieio();
598
599 p->cmap_regs[PIDXLO] = PIXFMT; eieio();
600 p->cmap_regs[PIDXDATA] = pformat; eieio();
601 }
602
603 static void
604 set_imstt_regvals_tvp (struct fb_info_imstt *p, u_int bpp)
605 {
606 struct imstt_regvals *init = &p->init;
607 __u8 tcc, mxc, lckl_n, mic;
608 __u8 mlc, lckl_p;
609
610 switch (bpp) {
611 case 8:
612 tcc = 0x80;
613 mxc = 0x4d;
614 lckl_n = 0xc1;
615 mlc = init->mlc[0];
616 lckl_p = init->lckl_p[0];
617 break;
618 case 16:
619 tcc = 0x44;
620 mxc = 0x55;
621 lckl_n = 0xe1;
622 mlc = init->mlc[1];
623 lckl_p = init->lckl_p[1];
624 break;
625 case 24:
626 tcc = 0x5e;
627 mxc = 0x5d;
628 lckl_n = 0xf1;
629 mlc = init->mlc[2];
630 lckl_p = init->lckl_p[2];
631 break;
632 case 32:
633 tcc = 0x46;
634 mxc = 0x5d;
635 lckl_n = 0xf1;
636 mlc = init->mlc[2];
637 lckl_p = init->lckl_p[2];
638 break;
639 }
640 mic = 0x08;
641
642 p->cmap_regs[TVPADDRW] = TVPIRPLA; eieio();
643 p->cmap_regs[TVPIDATA] = 0x00; eieio();
644 p->cmap_regs[TVPADDRW] = TVPIRPPD; eieio();
645 p->cmap_regs[TVPIDATA] = init->pclk_m; eieio();
646 p->cmap_regs[TVPADDRW] = TVPIRPPD; eieio();
647 p->cmap_regs[TVPIDATA] = init->pclk_n; eieio();
648 p->cmap_regs[TVPADDRW] = TVPIRPPD; eieio();
649 p->cmap_regs[TVPIDATA] = init->pclk_p; eieio();
650
651 p->cmap_regs[TVPADDRW] = TVPIRTCC; eieio();
652 p->cmap_regs[TVPIDATA] = tcc; eieio();
653 p->cmap_regs[TVPADDRW] = TVPIRMXC; eieio();
654 p->cmap_regs[TVPIDATA] = mxc; eieio();
655 p->cmap_regs[TVPADDRW] = TVPIRMIC; eieio();
656 p->cmap_regs[TVPIDATA] = mic; eieio();
657
658 p->cmap_regs[TVPADDRW] = TVPIRPLA; eieio();
659 p->cmap_regs[TVPIDATA] = 0x00; eieio();
660 p->cmap_regs[TVPADDRW] = TVPIRLPD; eieio();
661 p->cmap_regs[TVPIDATA] = lckl_n; eieio();
662
663 p->cmap_regs[TVPADDRW] = TVPIRPLA; eieio();
664 p->cmap_regs[TVPIDATA] = 0x15; eieio();
665 p->cmap_regs[TVPADDRW] = TVPIRMLC; eieio();
666 p->cmap_regs[TVPIDATA] = mlc; eieio();
667
668 p->cmap_regs[TVPADDRW] = TVPIRPLA; eieio();
669 p->cmap_regs[TVPIDATA] = 0x2a; eieio();
670 p->cmap_regs[TVPADDRW] = TVPIRLPD; eieio();
671 p->cmap_regs[TVPIDATA] = lckl_p; eieio();
672 }
673
674 static void
675 set_imstt_regvals (struct fb_info_imstt *p, u_int bpp)
676 {
677 struct imstt_regvals *init = &p->init;
678 __u32 ctl, pitch, byteswap, scr;
679
680 if (p->ramdac == IBM)
681 set_imstt_regvals_ibm(p, bpp);
682 else
683 set_imstt_regvals_tvp(p, bpp);
684
685 /*
686 * From what I (jsk) can gather poking around with MacsBug,
687 * bits 8 and 9 in the SCR register control endianness
688 * correction (byte swapping). These bits must be set according
689 * to the color depth as follows:
690 * Color depth Bit 9 Bit 8
691 * ========== ===== =====
692 * 8bpp 0 0
693 * 16bpp 0 1
694 * 32bpp 1 1
695 */
696 switch (bpp) {
697 case 8:
698 ctl = 0x17b1;
699 pitch = init->pitch >> 2;
700 byteswap = 0x000;
701 break;
702 case 16:
703 ctl = 0x17b3;
704 pitch = init->pitch >> 1;
705 byteswap = 0x100;
706 break;
707 case 24:
708 ctl = 0x17b9;
709 pitch = init->pitch - (p->init.pitch >> 2);
710 byteswap = 0x200;
711 break;
712 case 32:
713 ctl = 0x17b5;
714 pitch = init->pitch;
715 byteswap = 0x300;
716 break;
717 }
718 if (p->ramdac == TVP)
719 ctl -= 0x30;
720
721 out_le32(&p->dc_regs[HES], init->hes);
722 out_le32(&p->dc_regs[HEB], init->heb);
723 out_le32(&p->dc_regs[HSB], init->hsb);
724 out_le32(&p->dc_regs[HT], init->ht);
725 out_le32(&p->dc_regs[VES], init->ves);
726 out_le32(&p->dc_regs[VEB], init->veb);
727 out_le32(&p->dc_regs[VSB], init->vsb);
728 out_le32(&p->dc_regs[VT], init->vt);
729 out_le32(&p->dc_regs[VIL], init->vil);
730 out_le32(&p->dc_regs[HCIV], 1);
731 out_le32(&p->dc_regs[VCIV], 1);
732 out_le32(&p->dc_regs[TCDR], 4);
733 out_le32(&p->dc_regs[RRCIV], 1);
734 out_le32(&p->dc_regs[RRSC], 0x980);
735 out_le32(&p->dc_regs[RRCR], 0x11);
736
737 if (p->ramdac == IBM) {
738 out_le32(&p->dc_regs[HRIR], 0x0100);
739 out_le32(&p->dc_regs[CMR], 0x00ff);
740 out_le32(&p->dc_regs[SRGCTL], 0x0073);
741 } else {
742 out_le32(&p->dc_regs[HRIR], 0x0200);
743 out_le32(&p->dc_regs[CMR], 0x01ff);
744 out_le32(&p->dc_regs[SRGCTL], 0x0003);
745 }
746
747 switch (p->total_vram) {
748 case 0x200000:
749 scr = 0x059d | byteswap;
750 break;
751 /* case 0x400000:
752 case 0x800000: */
753 default:
754 pitch >>= 1;
755 scr = 0x150dd | byteswap;
756 break;
757 }
758
759 out_le32(&p->dc_regs[SCR], scr);
760 out_le32(&p->dc_regs[SPR], pitch);
761 out_le32(&p->dc_regs[STGCTL], ctl);
762 }
763
764 static inline void
765 set_offset (struct display *disp, struct fb_info_imstt *p)
766 {
767 __u32 off = disp->var.yoffset * (disp->line_length >> 3)
768 + ((disp->var.xoffset * (disp->var.bits_per_pixel >> 3)) >> 3);
769 out_le32(&p->dc_regs[SSR], off);
770 }
771
772 static inline void
773 set_555 (struct fb_info_imstt *p)
774 {
775 if (p->ramdac == IBM) {
776 p->cmap_regs[PIDXHI] = 0; eieio();
777 p->cmap_regs[PIDXLO] = BPP16; eieio();
778 p->cmap_regs[PIDXDATA] = 0x01; eieio();
779 } else {
780 p->cmap_regs[TVPADDRW] = TVPIRTCC; eieio();
781 p->cmap_regs[TVPIDATA] = 0x44; eieio();
782 }
783 }
784
785 static inline void
786 set_565 (struct fb_info_imstt *p)
787 {
788 if (p->ramdac == IBM) {
789 p->cmap_regs[PIDXHI] = 0; eieio();
790 p->cmap_regs[PIDXLO] = BPP16; eieio();
791 p->cmap_regs[PIDXDATA] = 0x03; eieio();
792 } else {
793 p->cmap_regs[TVPADDRW] = TVPIRTCC; eieio();
794 p->cmap_regs[TVPIDATA] = 0x45; eieio();
795 }
796 }
797
798 static void
799 imstt_set_cursor (struct fb_info_imstt *p, int on)
800 {
801 struct imstt_cursor *c = &p->cursor;
802
803 if (p->ramdac == IBM) {
804 p->cmap_regs[PIDXHI] = 0; eieio();
805 if (!on) {
806 p->cmap_regs[PIDXLO] = CURSCTL; eieio();
807 p->cmap_regs[PIDXDATA] = 0x00; eieio();
808 } else {
809 p->cmap_regs[PIDXLO] = CURSXHI; eieio();
810 p->cmap_regs[PIDXDATA] = c->x >> 8; eieio();
811 p->cmap_regs[PIDXLO] = CURSXLO; eieio();
812 p->cmap_regs[PIDXDATA] = c->x & 0xff; eieio();
813 p->cmap_regs[PIDXLO] = CURSYHI; eieio();
814 p->cmap_regs[PIDXDATA] = c->y >> 8; eieio();
815 p->cmap_regs[PIDXLO] = CURSYLO; eieio();
816 p->cmap_regs[PIDXDATA] = c->y & 0xff; eieio();
817 p->cmap_regs[PIDXLO] = CURSCTL; eieio();
818 p->cmap_regs[PIDXDATA] = 0x02; eieio();
819 }
820 } else {
821 if (!on) {
822 p->cmap_regs[TVPADDRW] = TVPIRICC; eieio();
823 p->cmap_regs[TVPIDATA] = 0x00; eieio();
824 } else {
825 __u16 x = c->x + 0x40, y = c->y + 0x40;
826
827 p->cmap_regs[TVPCXPOH] = x >> 8; eieio();
828 p->cmap_regs[TVPCXPOL] = x & 0xff; eieio();
829 p->cmap_regs[TVPCYPOH] = y >> 8; eieio();
830 p->cmap_regs[TVPCYPOL] = y & 0xff; eieio();
831 p->cmap_regs[TVPADDRW] = TVPIRICC; eieio();
832 p->cmap_regs[TVPIDATA] = 0x02; eieio();
833 }
834 }
835 }
836
837 static void
838 imsttfbcon_cursor (struct display *disp, int mode, int x, int y)
839 {
840 struct fb_info_imstt *p = (struct fb_info_imstt *)disp->fb_info;
841 struct imstt_cursor *c = &p->cursor;
842
843 x *= fontwidth(disp);
844 y *= fontheight(disp);
845
846 if (c->x == x && c->y == y && (mode == CM_ERASE) == !c->enable)
847 return;
848
849 c->enable = 0;
850 if (c->on)
851 imstt_set_cursor(p, 0);
852 c->x = x - disp->var.xoffset;
853 c->y = y - disp->var.yoffset;
854
855 switch (mode) {
856 case CM_ERASE:
857 c->on = 0;
858 break;
859 case CM_DRAW:
860 case CM_MOVE:
861 if (c->on)
862 imstt_set_cursor(p, c->on);
863 else
864 c->vbl_cnt = CURSOR_DRAW_DELAY;
865 c->enable = 1;
866 break;
867 }
868 }
869
870 static int
871 imsttfbcon_set_font (struct display *disp, int width, int height)
872 {
873 struct fb_info_imstt *p = (struct fb_info_imstt *)disp->fb_info;
874 struct imstt_cursor *c = &p->cursor;
875 u_int x, y;
876 __u8 fgc;
877
878 if (width > 32 || height > 32)
879 return -EINVAL;
880
881 c->height = height;
882 c->width = width;
883
884 fgc = ~attr_bgcol_ec(disp, disp->conp);
885
886 if (p->ramdac == IBM) {
887 p->cmap_regs[PIDXHI] = 1; eieio();
888 for (x = 0; x < 0x100; x++) {
889 p->cmap_regs[PIDXLO] = x; eieio();
890 p->cmap_regs[PIDXDATA] = 0x00; eieio();
891 }
892 p->cmap_regs[PIDXHI] = 1; eieio();
893 for (y = 0; y < height; y++)
894 for (x = 0; x < width >> 2; x++) {
895 p->cmap_regs[PIDXLO] = x + y * 8; eieio();
896 p->cmap_regs[PIDXDATA] = 0xff; eieio();
897 }
898 p->cmap_regs[PIDXHI] = 0; eieio();
899 p->cmap_regs[PIDXLO] = CURS1R; eieio();
900 p->cmap_regs[PIDXDATA] = fgc; eieio();
901 p->cmap_regs[PIDXLO] = CURS1G; eieio();
902 p->cmap_regs[PIDXDATA] = fgc; eieio();
903 p->cmap_regs[PIDXLO] = CURS1B; eieio();
904 p->cmap_regs[PIDXDATA] = fgc; eieio();
905 p->cmap_regs[PIDXLO] = CURS2R; eieio();
906 p->cmap_regs[PIDXDATA] = fgc; eieio();
907 p->cmap_regs[PIDXLO] = CURS2G; eieio();
908 p->cmap_regs[PIDXDATA] = fgc; eieio();
909 p->cmap_regs[PIDXLO] = CURS2B; eieio();
910 p->cmap_regs[PIDXDATA] = fgc; eieio();
911 p->cmap_regs[PIDXLO] = CURS3R; eieio();
912 p->cmap_regs[PIDXDATA] = fgc; eieio();
913 p->cmap_regs[PIDXLO] = CURS3G; eieio();
914 p->cmap_regs[PIDXDATA] = fgc; eieio();
915 p->cmap_regs[PIDXLO] = CURS3B; eieio();
916 p->cmap_regs[PIDXDATA] = fgc; eieio();
917 } else {
918 p->cmap_regs[TVPADDRW] = TVPIRICC; eieio();
919 p->cmap_regs[TVPIDATA] &= 0x03; eieio();
920 p->cmap_regs[TVPADDRW] = 0; eieio();
921 for (x = 0; x < 0x200; x++) {
922 p->cmap_regs[TVPCRDAT] = 0x00; eieio();
923 }
924 for (x = 0; x < 0x200; x++) {
925 p->cmap_regs[TVPCRDAT] = 0xff; eieio();
926 }
927 p->cmap_regs[TVPADDRW] = TVPIRICC; eieio();
928 p->cmap_regs[TVPIDATA] &= 0x03; eieio();
929 for (y = 0; y < height; y++)
930 for (x = 0; x < width >> 3; x++) {
931 p->cmap_regs[TVPADDRW] = x + y * 8; eieio();
932 p->cmap_regs[TVPCRDAT] = 0xff; eieio();
933 }
934 p->cmap_regs[TVPADDRW] = TVPIRICC; eieio();
935 p->cmap_regs[TVPIDATA] |= 0x08; eieio();
936 for (y = 0; y < height; y++)
937 for (x = 0; x < width >> 3; x++) {
938 p->cmap_regs[TVPADDRW] = x + y * 8; eieio();
939 p->cmap_regs[TVPCRDAT] = 0xff; eieio();
940 }
941 p->cmap_regs[TVPCADRW] = 0x00; eieio();
942 for (x = 0; x < 12; x++) {
943 p->cmap_regs[TVPCDATA] = fgc; eieio();
944 }
945 }
946
947 return 1;
948 }
949
950 static void
951 imstt_cursor_timer_handler (unsigned long dev_addr)
952 {
953 struct fb_info_imstt *p = (struct fb_info_imstt *)dev_addr;
954 struct imstt_cursor *c = &p->cursor;
955
956 if (!c->enable)
957 goto out;
958
959 if (c->vbl_cnt && --c->vbl_cnt == 0) {
960 c->on ^= 1;
961 imstt_set_cursor(p, c->on);
962 c->vbl_cnt = c->blink_rate;
963 }
964
965 out:
966 c->timer.expires = jiffies + (HZ / 50);
967 add_timer(&c->timer);
968 }
969
970 __initfunc(static void
971 imstt_cursor_init (struct fb_info_imstt *p))
972 {
973 struct imstt_cursor *c = &p->cursor;
974
975 imsttfbcon_set_font(&p->disp, fontwidth(&p->disp), fontheight(&p->disp));
976
977 c->enable = 1;
978 c->on = 1;
979 c->x = c->y = 0;
980 c->blink_rate = 0;
981 c->vbl_cnt = CURSOR_DRAW_DELAY;
982
983 if (curblink) {
984 c->blink_rate = CURSOR_BLINK_RATE;
985 init_timer(&c->timer);
986 c->timer.expires = jiffies + (HZ / 50);
987 c->timer.data = (unsigned long)p;
988 c->timer.function = imstt_cursor_timer_handler;
989 add_timer(&c->timer);
990 }
991 }
992
993 static void
994 imsttfbcon_bmove (struct display *disp, int sy, int sx, int dy, int dx, int height, int width)
995 {
996 struct fb_info_imstt *p = (struct fb_info_imstt *)disp->fb_info;
997 __u32 Bpp, line_pitch,
998 fb_offset_old, fb_offset_new,
999 sp, dp_octl, cnt, bltctl;
1000
1001 Bpp = disp->var.bits_per_pixel >> 3,
1002
1003 sy *= fontheight(disp);
1004 sx *= fontwidth(disp);
1005 sx *= Bpp;
1006 dy *= fontheight(disp);
1007 dx *= fontwidth(disp);
1008 dx *= Bpp;
1009 height *= fontheight(disp);
1010 height--;
1011 width *= fontwidth(disp);
1012 width *= Bpp;
1013 width--;
1014
1015 line_pitch = disp->line_length;
1016 bltctl = 0x05;
1017 sp = line_pitch << 16;
1018 cnt = height << 16;
1019
1020 if (sy < dy) {
1021 sy += height;
1022 dy += height;
1023 sp |= -(line_pitch) & 0xffff;
1024 dp_octl = -(line_pitch) & 0xffff;
1025 } else {
1026 sp |= line_pitch;
1027 dp_octl = line_pitch;
1028 }
1029 if (sx < dx) {
1030 sx += width;
1031 dx += width;
1032 bltctl |= 0x80;
1033 cnt |= -(width) & 0xffff;
1034 } else {
1035 cnt |= width;
1036 }
1037 fb_offset_old = sy * line_pitch + sx;
1038 fb_offset_new = dy * line_pitch + dx;
1039
1040 while(in_le32(&p->dc_regs[SSTATUS]) & 0x80);
1041 out_le32(&p->dc_regs[S1SA], fb_offset_old);
1042 out_le32(&p->dc_regs[SP], sp);
1043 out_le32(&p->dc_regs[DSA], fb_offset_new);
1044 out_le32(&p->dc_regs[CNT], cnt);
1045 out_le32(&p->dc_regs[DP_OCTL], dp_octl);
1046 out_le32(&p->dc_regs[BLTCTL], bltctl);
1047 while(in_le32(&p->dc_regs[SSTATUS]) & 0x80);
1048 while(in_le32(&p->dc_regs[SSTATUS]) & 0x40);
1049 }
1050
1051 static void
1052 imsttfbcon_clear (struct vc_data *conp, struct display *disp,
1053 int sy, int sx, int height, int width)
1054 {
1055 struct fb_info_imstt *p = (struct fb_info_imstt *)disp->fb_info;
1056 __u32 Bpp, line_pitch, bgc;
1057
1058 bgc = attr_bgcol_ec(disp, conp);
1059 bgc |= (bgc << 8);
1060 bgc |= (bgc << 16);
1061
1062 Bpp = disp->var.bits_per_pixel >> 3,
1063 line_pitch = disp->line_length;
1064
1065 sy *= fontheight(disp);
1066 sy *= line_pitch;
1067 sx *= fontwidth(disp);
1068 sx *= Bpp;
1069 height *= fontheight(disp);
1070 height--;
1071 width *= fontwidth(disp);
1072 width *= Bpp;
1073 width--;
1074
1075 while(in_le32(&p->dc_regs[SSTATUS]) & 0x80);
1076 out_le32(&p->dc_regs[DSA], sy + sx);
1077 out_le32(&p->dc_regs[CNT], (height << 16) | width);
1078 out_le32(&p->dc_regs[DP_OCTL], line_pitch);
1079 out_le32(&p->dc_regs[BI], 0xffffffff);
1080 out_le32(&p->dc_regs[MBC], 0xffffffff);
1081 out_le32(&p->dc_regs[CLR], bgc);
1082 out_le32(&p->dc_regs[BLTCTL], 0x200000);
1083 while(in_le32(&p->dc_regs[SSTATUS]) & 0x80);
1084 while(in_le32(&p->dc_regs[SSTATUS]) & 0x40);
1085 }
1086
1087 static void
1088 imsttfbcon_revc (struct display *disp, int sx, int sy)
1089 {
1090 struct fb_info_imstt *p = (struct fb_info_imstt *)disp->fb_info;
1091 __u32 Bpp, line_pitch, height, width;
1092
1093 Bpp = disp->var.bits_per_pixel >> 3,
1094 line_pitch = disp->line_length;
1095
1096 height = fontheight(disp);
1097 width = fontwidth(disp) * Bpp;
1098 sy *= height;
1099 sy *= line_pitch;
1100 sx *= width;
1101 height--;
1102 width--;
1103
1104 while(in_le32(&p->dc_regs[SSTATUS]) & 0x80);
1105 out_le32(&p->dc_regs[DSA], sy + sx);
1106 out_le32(&p->dc_regs[S1SA], sy + sx);
1107 out_le32(&p->dc_regs[CNT], (height << 16) | width);
1108 out_le32(&p->dc_regs[DP_OCTL], line_pitch);
1109 out_le32(&p->dc_regs[SP], line_pitch);
1110 out_le32(&p->dc_regs[BLTCTL], 0x40005);
1111 while(in_le32(&p->dc_regs[SSTATUS]) & 0x80);
1112 while(in_le32(&p->dc_regs[SSTATUS]) & 0x40);
1113 }
1114
1115 #ifdef FBCON_HAS_CFB8
1116 static struct display_switch fbcon_imstt8 = {
1117 fbcon_cfb8_setup, imsttfbcon_bmove, imsttfbcon_clear, fbcon_cfb8_putc,
1118 fbcon_cfb8_putcs, imsttfbcon_revc, imsttfbcon_cursor, imsttfbcon_set_font, fbcon_cfb8_clear_margins,
1119 FONTWIDTH(4)|FONTWIDTH(8)|FONTWIDTH(12)|FONTWIDTH(16)
1120 };
1121 #endif
1122 #ifdef FBCON_HAS_CFB16
1123 static struct display_switch fbcon_imstt16 = {
1124 fbcon_cfb16_setup, imsttfbcon_bmove, imsttfbcon_clear, fbcon_cfb16_putc,
1125 fbcon_cfb16_putcs, imsttfbcon_revc, imsttfbcon_cursor, imsttfbcon_set_font, fbcon_cfb16_clear_margins,
1126 FONTWIDTH(4)|FONTWIDTH(8)|FONTWIDTH(12)|FONTWIDTH(16)
1127 };
1128 #endif
1129 #ifdef FBCON_HAS_CFB24
1130 static struct display_switch fbcon_imstt24 = {
1131 fbcon_cfb24_setup, imsttfbcon_bmove, imsttfbcon_clear, fbcon_cfb24_putc,
1132 fbcon_cfb24_putcs, imsttfbcon_revc, imsttfbcon_cursor, imsttfbcon_set_font, fbcon_cfb24_clear_margins,
1133 FONTWIDTH(4)|FONTWIDTH(8)|FONTWIDTH(12)|FONTWIDTH(16)
1134 };
1135 #endif
1136 #ifdef FBCON_HAS_CFB32
1137 static struct display_switch fbcon_imstt32 = {
1138 fbcon_cfb32_setup, imsttfbcon_bmove, imsttfbcon_clear, fbcon_cfb32_putc,
1139 fbcon_cfb32_putcs, imsttfbcon_revc, imsttfbcon_cursor, imsttfbcon_set_font, fbcon_cfb32_clear_margins,
1140 FONTWIDTH(4)|FONTWIDTH(8)|FONTWIDTH(12)|FONTWIDTH(16)
1141 };
1142 #endif
1143
1144 #ifdef CONFIG_FB_COMPAT_XPMAC
1145 #include <asm/vc_ioctl.h>
1146
1147 extern struct vc_mode display_info;
1148 extern struct fb_info *console_fb_info;
1149
1150 static void
1151 set_display_info (struct display *disp)
1152 {
1153 display_info.width = disp->var.xres;
1154 display_info.height = disp->var.yres;
1155 display_info.depth = disp->var.bits_per_pixel;
1156 display_info.pitch = disp->line_length;
1157
1158 switch (disp->var.xres) {
1159 case 512:
1160 display_info.mode = 2;
1161 break;
1162 case 640:
1163 display_info.mode = 6;
1164 break;
1165 case 800:
1166 display_info.mode = 12;
1167 break;
1168 case 832:
1169 display_info.mode = 13;
1170 break;
1171 case 1024:
1172 display_info.mode = 17;
1173 break;
1174 case 1152:
1175 display_info.mode = 18;
1176 break;
1177 case 1280:
1178 display_info.mode = disp->var.yres == 960 ? 19 : 20;
1179 break;
1180 default:
1181 display_info.mode = 0;
1182 }
1183 }
1184 #endif
1185
1186 static int
1187 imsttfb_getcolreg (u_int regno, u_int *red, u_int *green,
1188 u_int *blue, u_int *transp, struct fb_info *info)
1189 {
1190 struct fb_info_imstt *p = (struct fb_info_imstt *)info;
1191
1192 if (regno > 255)
1193 return 1;
1194 *red = (p->palette[regno].red << 8) | p->palette[regno].red;
1195 *green = (p->palette[regno].green << 8) | p->palette[regno].green;
1196 *blue = (p->palette[regno].blue << 8) | p->palette[regno].blue;
1197 *transp = 0;
1198
1199 return 0;
1200 }
1201
1202 static int
1203 imsttfb_setcolreg (u_int regno, u_int red, u_int green, u_int blue,
1204 u_int transp, struct fb_info *info)
1205 {
1206 struct fb_info_imstt *p = (struct fb_info_imstt *)info;
1207 u_int bpp = fb_display[currcon].var.bits_per_pixel;
1208 u_int i;
1209
1210 if (regno > 255)
1211 return 1;
1212
1213 red >>= 8;
1214 green >>= 8;
1215 blue >>= 8;
1216
1217 p->palette[regno].red = red;
1218 p->palette[regno].green = green;
1219 p->palette[regno].blue = blue;
1220
1221 /* PADDRW/PDATA are the same as TVPPADDRW/TVPPDATA */
1222 if (0 && bpp == 16) /* screws up X */
1223 p->cmap_regs[PADDRW] = regno << 3;
1224 else
1225 p->cmap_regs[PADDRW] = regno;
1226 eieio();
1227
1228 p->cmap_regs[PDATA] = red; eieio();
1229 p->cmap_regs[PDATA] = green; eieio();
1230 p->cmap_regs[PDATA] = blue; eieio();
1231
1232 if (regno < 16)
1233 switch (bpp) {
1234 #ifdef FBCON_HAS_CFB16
1235 case 16:
1236 p->fbcon_cmap.cfb16[regno] = (regno << (fb_display[currcon].var.green.length == 5 ? 10 : 11)) | (regno << 5) | regno;
1237 break;
1238 #endif
1239 #ifdef FBCON_HAS_CFB24
1240 case 24:
1241 p->fbcon_cmap.cfb24[regno] = (regno << 16) | (regno << 8) | regno;
1242 break;
1243 #endif
1244 #ifdef FBCON_HAS_CFB32
1245 case 32:
1246 i = (regno << 8) | regno;
1247 p->fbcon_cmap.cfb32[regno] = (i << 16) | i;
1248 break;
1249 #endif
1250 }
1251
1252 return 0;
1253 }
1254
1255 static void
1256 do_install_cmap (int con, struct fb_info *info)
1257 {
1258 if (fb_display[con].cmap.len)
1259 fb_set_cmap(&fb_display[con].cmap, 1, imsttfb_setcolreg, info);
1260 else {
1261 u_int size = fb_display[con].var.bits_per_pixel == 16 ? 32 : 256;
1262 fb_set_cmap(fb_default_cmap(size), 1, imsttfb_setcolreg, info);
1263 }
1264 }
1265
1266 static int
1267 imsttfb_open (struct fb_info *info, int user)
1268 {
1269 MOD_INC_USE_COUNT;
1270 return 0;
1271 }
1272
1273 static int
1274 imsttfb_release (struct fb_info *info, int user)
1275 {
1276 MOD_DEC_USE_COUNT;
1277 return 0;
1278 }
1279
1280 static int
1281 imsttfb_get_fix (struct fb_fix_screeninfo *fix, int con, struct fb_info *info)
1282 {
1283 struct fb_info_imstt *p = (struct fb_info_imstt *)info;
1284 struct fb_var_screeninfo *var = &fb_display[con].var;
1285
1286 *fix = p->fix;
1287 fix->visual = var->bits_per_pixel == 8 ? FB_VISUAL_PSEUDOCOLOR
1288 : FB_VISUAL_DIRECTCOLOR;
1289 fix->line_length = var->xres * (var->bits_per_pixel >> 3);
1290
1291 return 0;
1292 }
1293
1294 static int
1295 imsttfb_get_var (struct fb_var_screeninfo *var, int con, struct fb_info *info)
1296 {
1297 *var = fb_display[con].var;
1298
1299 return 0;
1300 }
1301
1302 static void
1303 set_dispsw (struct display *disp, struct fb_info_imstt *p)
1304 {
1305 u_int accel = disp->var.accel_flags & FB_ACCELF_TEXT;
1306
1307 if (disp->conp && disp->conp->vc_sw && disp->conp->vc_sw->con_cursor)
1308 disp->conp->vc_sw->con_cursor(disp->conp, CM_ERASE);
1309
1310 p->dispsw = fbcon_dummy;
1311 disp->dispsw = &p->dispsw;
1312 disp->dispsw_data = 0;
1313 switch (disp->var.bits_per_pixel) {
1314 case 8:
1315 disp->var.red.offset = 0;
1316 disp->var.red.length = 8;
1317 disp->var.green.offset = 0;
1318 disp->var.green.length = 8;
1319 disp->var.blue.offset = 0;
1320 disp->var.blue.length = 8;
1321 disp->var.transp.offset = 0;
1322 disp->var.transp.length = 0;
1323 #ifdef FBCON_HAS_CFB8
1324 p->dispsw = accel ? fbcon_imstt8 : fbcon_cfb8;
1325 #endif
1326 break;
1327 case 16: /* RGB 555 or 565 */
1328 if (disp->var.green.length != 6)
1329 disp->var.red.offset = 10;
1330 disp->var.red.length = 5;
1331 disp->var.green.offset = 5;
1332 if (disp->var.green.length != 6)
1333 disp->var.green.length = 5;
1334 disp->var.blue.offset = 0;
1335 disp->var.blue.length = 5;
1336 disp->var.transp.offset = 0;
1337 disp->var.transp.length = 0;
1338 #ifdef FBCON_HAS_CFB16
1339 p->dispsw = accel ? fbcon_imstt16 : fbcon_cfb16;
1340 disp->dispsw_data = p->fbcon_cmap.cfb16;
1341 #endif
1342 break;
1343 case 24: /* RGB 888 */
1344 disp->var.red.offset = 16;
1345 disp->var.red.length = 8;
1346 disp->var.green.offset = 8;
1347 disp->var.green.length = 8;
1348 disp->var.blue.offset = 0;
1349 disp->var.blue.length = 8;
1350 disp->var.transp.offset = 0;
1351 disp->var.transp.length = 0;
1352 #ifdef FBCON_HAS_CFB24
1353 p->dispsw = accel ? fbcon_imstt24 : fbcon_cfb24;
1354 disp->dispsw_data = p->fbcon_cmap.cfb24;
1355 #endif
1356 break;
1357 case 32: /* RGBA 8888 */
1358 disp->var.red.offset = 16;
1359 disp->var.red.length = 8;
1360 disp->var.green.offset = 8;
1361 disp->var.green.length = 8;
1362 disp->var.blue.offset = 0;
1363 disp->var.blue.length = 8;
1364 disp->var.transp.offset = 24;
1365 disp->var.transp.length = 8;
1366 #ifdef FBCON_HAS_CFB32
1367 p->dispsw = accel ? fbcon_imstt32 : fbcon_cfb32;
1368 disp->dispsw_data = p->fbcon_cmap.cfb32;
1369 #endif
1370 break;
1371 }
1372
1373 if (accel && p->ramdac != IBM) {
1374 p->dispsw.cursor = 0;
1375 p->dispsw.set_font = 0;
1376 }
1377
1378 #ifdef CONFIG_FB_COMPAT_XPMAC
1379 set_display_info(disp);
1380 #endif
1381 }
1382
1383 static void
1384 set_disp (struct display *disp, struct fb_info_imstt *p)
1385 {
1386 u_int accel = disp->var.accel_flags & FB_ACCELF_TEXT;
1387
1388 disp->fb_info = &p->info;
1389
1390 set_dispsw(disp, p);
1391
1392 disp->visual = disp->var.bits_per_pixel == 8 ? FB_VISUAL_PSEUDOCOLOR
1393 : FB_VISUAL_DIRECTCOLOR;
1394 disp->screen_base = (__u8 *)p->frame_buffer;
1395 disp->visual = p->fix.visual;
1396 disp->type = p->fix.type;
1397 disp->type_aux = p->fix.type_aux;
1398 disp->line_length = disp->var.xres * (disp->var.bits_per_pixel >> 3);
1399 disp->can_soft_blank = 1;
1400 disp->inverse = 0;
1401 disp->ypanstep = 1;
1402 disp->ywrapstep = 0;
1403 if (accel) {
1404 disp->scrollmode = SCROLL_YNOMOVE;
1405 if (disp->var.yres == disp->var.yres_virtual) {
1406 __u32 vram = (p->total_vram - (PAGE_SIZE << 2));
1407 disp->var.yres_virtual = ((vram << 3) / disp->var.bits_per_pixel) / disp->var.xres_virtual;
1408 if (disp->var.yres_virtual < disp->var.yres)
1409 disp->var.yres_virtual = disp->var.yres;
1410 }
1411 } else {
1412 disp->scrollmode = SCROLL_YREDRAW;
1413 }
1414
1415 disp->var.activate = 0;
1416 disp->var.red.msb_right = 0;
1417 disp->var.green.msb_right = 0;
1418 disp->var.blue.msb_right = 0;
1419 disp->var.transp.msb_right = 0;
1420 disp->var.height = -1;
1421 disp->var.width = -1;
1422 disp->var.vmode = FB_VMODE_NONINTERLACED;
1423 disp->var.left_margin = disp->var.right_margin = 16;
1424 disp->var.upper_margin = disp->var.lower_margin = 16;
1425 disp->var.hsync_len = disp->var.vsync_len = 8;
1426 }
1427
1428 static int
1429 imsttfb_set_var (struct fb_var_screeninfo *var, int con, struct fb_info *info)
1430 {
1431 struct fb_info_imstt *p = (struct fb_info_imstt *)info;
1432 struct display *disp;
1433 u_int oldbpp, oldxres, oldyres, oldgreenlen, oldaccel;
1434
1435 disp = &fb_display[con];
1436
1437 if ((var->bits_per_pixel != 8 && var->bits_per_pixel != 16
1438 && var->bits_per_pixel != 24 && var->bits_per_pixel != 32)
1439 || var->xres_virtual < var->xres || var->yres_virtual < var->yres
1440 || var->nonstd
1441 || (var->vmode & FB_VMODE_MASK) != FB_VMODE_NONINTERLACED)
1442 return -EINVAL;
1443
1444 if ((var->xres * var->yres) * (var->bits_per_pixel >> 3) > p->total_vram
1445 || (var->xres_virtual * var->yres_virtual) * (var->bits_per_pixel >> 3) > p->total_vram)
1446 return -EINVAL;
1447
1448 if (!((var->activate & FB_ACTIVATE_MASK) == FB_ACTIVATE_NOW))
1449 return 0;
1450
1451 if (!compute_imstt_regvals(p, var->xres, var->yres))
1452 return -EINVAL;
1453
1454 oldbpp = disp->var.bits_per_pixel;
1455 oldxres = disp->var.xres;
1456 oldyres = disp->var.yres;
1457 oldgreenlen = disp->var.green.length;
1458 oldaccel = disp->var.accel_flags;
1459
1460 disp->var.bits_per_pixel = var->bits_per_pixel;
1461 disp->var.xres = var->xres;
1462 disp->var.yres = var->yres;
1463 disp->var.xres_virtual = var->xres_virtual;
1464 disp->var.yres_virtual = var->yres_virtual;
1465 disp->var.green.length = var->green.length;
1466 disp->var.accel_flags = var->accel_flags;
1467
1468 set_disp(disp, p);
1469
1470 if (info->changevar)
1471 (*info->changevar)(con);
1472
1473 if (con == currcon) {
1474 if (oldgreenlen != disp->var.green.length) {
1475 if (disp->var.green.length == 6)
1476 set_565(p);
1477 else
1478 set_555(p);
1479 }
1480 if (oldxres != disp->var.xres || oldyres != disp->var.yres || oldbpp != disp->var.bits_per_pixel)
1481 set_imstt_regvals(p, disp->var.bits_per_pixel);
1482
1483 }
1484 disp->var.pixclock = 1000000 / getclkMHz(p);
1485
1486 if (oldbpp != disp->var.bits_per_pixel) {
1487 int err = fb_alloc_cmap(&disp->cmap, 0, 0);
1488 if (err)
1489 return err;
1490 do_install_cmap(con, info);
1491 }
1492 *var = disp->var;
1493
1494 return 0;
1495 }
1496
1497 static int
1498 imsttfb_pan_display (struct fb_var_screeninfo *var, int con, struct fb_info *info)
1499 {
1500 struct fb_info_imstt *p = (struct fb_info_imstt *)info;
1501 struct display *disp = &fb_display[con];
1502
1503 if (var->xoffset + disp->var.xres > disp->var.xres_virtual
1504 || var->yoffset + disp->var.yres > disp->var.yres_virtual)
1505 return -EINVAL;
1506
1507 disp->var.xoffset = var->xoffset;
1508 disp->var.yoffset = var->yoffset;
1509 if (con == currcon)
1510 set_offset(disp, p);
1511
1512 return 0;
1513 }
1514
1515 static int
1516 imsttfb_get_cmap (struct fb_cmap *cmap, int kspc, int con, struct fb_info *info)
1517 {
1518 if (con == currcon) /* current console? */
1519 return fb_get_cmap(cmap, kspc, imsttfb_getcolreg, info);
1520 else if (fb_display[con].cmap.len) /* non default colormap? */
1521 fb_copy_cmap(&fb_display[con].cmap, cmap, kspc ? 0 : 2);
1522 else {
1523 u_int size = fb_display[con].var.bits_per_pixel == 16 ? 32 : 256;
1524 fb_copy_cmap(fb_default_cmap(size), cmap, kspc ? 0 : 2);
1525 }
1526
1527 return 0;
1528 }
1529
1530 static int
1531 imsttfb_set_cmap (struct fb_cmap *cmap, int kspc, int con, struct fb_info *info)
1532 {
1533 int err;
1534
1535 if (!fb_display[con].cmap.len) { /* no colormap allocated? */
1536 int size = fb_display[con].var.bits_per_pixel == 16 ? 32 : 256;
1537 if ((err = fb_alloc_cmap(&fb_display[con].cmap, size, 0)))
1538 return err;
1539 }
1540 if (con == currcon) /* current console? */
1541 return fb_set_cmap(cmap, kspc, imsttfb_setcolreg, info);
1542 else
1543 fb_copy_cmap(cmap, &fb_display[con].cmap, kspc ? 0 : 1);
1544
1545 return 0;
1546 }
1547
1548 #define FBIMSTT_SETREG 0x545401
1549 #define FBIMSTT_GETREG 0x545402
1550 #define FBIMSTT_SETCMAPREG 0x545403
1551 #define FBIMSTT_GETCMAPREG 0x545404
1552 #define FBIMSTT_SETIDXREG 0x545405
1553 #define FBIMSTT_GETIDXREG 0x545406
1554
1555 static int
1556 imsttfb_ioctl (struct inode *inode, struct file *file, u_int cmd,
1557 u_long arg, int con, struct fb_info *info)
1558 {
1559 struct fb_info_imstt *p = (struct fb_info_imstt *)info;
1560 __u8 idx[2];
1561 __u32 reg[2];
1562
1563 switch (cmd) {
1564 case FBIMSTT_SETREG:
1565 if (copy_from_user(reg, (void *)arg, 8) || reg[0] > (0x1000 - sizeof(reg[0])) / sizeof(reg[0]))
1566 return -EFAULT;
1567 out_le32(&p->dc_regs[reg[0]], reg[1]);
1568 return 0;
1569 case FBIMSTT_GETREG:
1570 if (copy_from_user(reg, (void *)arg, 4) || reg[0] > (0x1000 - sizeof(reg[0])) / sizeof(reg[0]))
1571 return -EFAULT;
1572 reg[1] = in_le32(&p->dc_regs[reg[0]]);
1573 if (copy_to_user((void *)(arg + 4), &reg[1], 4))
1574 return -EFAULT;
1575 return 0;
1576 case FBIMSTT_SETCMAPREG:
1577 if (copy_from_user(reg, (void *)arg, 8) || reg[0] > (0x1000 - sizeof(reg[0])) / sizeof(reg[0]))
1578 return -EFAULT;
1579 out_le32(&((u_int *)p->cmap_regs)[reg[0]], reg[1]);
1580 return 0;
1581 case FBIMSTT_GETCMAPREG:
1582 if (copy_from_user(reg, (void *)arg, 4) || reg[0] > (0x1000 - sizeof(reg[0])) / sizeof(reg[0]))
1583 return -EFAULT;
1584 reg[1] = in_le32(&((u_int *)p->cmap_regs)[reg[0]]);
1585 if (copy_to_user((void *)(arg + 4), &reg[1], 4))
1586 return -EFAULT;
1587 return 0;
1588 case FBIMSTT_SETIDXREG:
1589 if (copy_from_user(idx, (void *)arg, 2))
1590 return -EFAULT;
1591 p->cmap_regs[PIDXHI] = 0; eieio();
1592 p->cmap_regs[PIDXLO] = idx[0]; eieio();
1593 p->cmap_regs[PIDXDATA] = idx[1]; eieio();
1594 return 0;
1595 case FBIMSTT_GETIDXREG:
1596 if (copy_from_user(idx, (void *)arg, 1))
1597 return -EFAULT;
1598 p->cmap_regs[PIDXHI] = 0; eieio();
1599 p->cmap_regs[PIDXLO] = idx[0]; eieio();
1600 idx[1] = p->cmap_regs[PIDXDATA];
1601 if (copy_to_user((void *)(arg + 1), &idx[1], 1))
1602 return -EFAULT;
1603 return 0;
1604 default:
1605 return -ENOIOCTLCMD;
1606 }
1607 }
1608
1609 static struct fb_ops imsttfb_ops = {
1610 imsttfb_open,
1611 imsttfb_release,
1612 imsttfb_get_fix,
1613 imsttfb_get_var,
1614 imsttfb_set_var,
1615 imsttfb_get_cmap,
1616 imsttfb_set_cmap,
1617 imsttfb_pan_display,
1618 imsttfb_ioctl
1619 };
1620
1621 static int
1622 imsttfbcon_switch (int con, struct fb_info *info)
1623 {
1624 struct fb_info_imstt *p = (struct fb_info_imstt *)info;
1625 struct display *old = &fb_display[currcon], *new = &fb_display[con];
1626
1627 if (old->cmap.len)
1628 fb_get_cmap(&old->cmap, 1, imsttfb_getcolreg, info);
1629
1630 if (old->conp && old->conp->vc_sw && old->conp->vc_sw->con_cursor)
1631 old->conp->vc_sw->con_cursor(old->conp, CM_ERASE);
1632
1633 currcon = con;
1634
1635 if (old->var.xres != new->var.xres
1636 || old->var.yres != new->var.yres
1637 || old->var.bits_per_pixel != new->var.bits_per_pixel
1638 || old->var.green.length != new->var.green.length
1639 || old->var.accel_flags != new->var.accel_flags) {
1640 set_dispsw(new, p);
1641 if (!compute_imstt_regvals(p, new->var.xres, new->var.yres))
1642 return -1;
1643 if (new->var.bits_per_pixel == 16) {
1644 if (new->var.green.length == 6)
1645 set_565(p);
1646 else
1647 set_555(p);
1648 }
1649 set_imstt_regvals(p, new->var.bits_per_pixel);
1650 }
1651 set_offset(new, p);
1652
1653 imsttfbcon_set_font(new, fontwidth(new), fontheight(new));
1654
1655 do_install_cmap(con, info);
1656
1657 return 0;
1658 }
1659
1660 static int
1661 imsttfbcon_updatevar (int con, struct fb_info *info)
1662 {
1663 struct fb_info_imstt *p = (struct fb_info_imstt *)info;
1664 struct display *disp = &fb_display[con];
1665
1666 if (con != currcon)
1667 goto out;
1668
1669 if (p->ramdac == IBM)
1670 imsttfbcon_cursor(disp, CM_ERASE, p->cursor.x, p->cursor.y);
1671
1672 set_offset(disp, p);
1673
1674 out:
1675 return 0;
1676 }
1677
1678 static void
1679 imsttfbcon_blank (int blank, struct fb_info *info)
1680 {
1681 struct fb_info_imstt *p = (struct fb_info_imstt *)info;
1682 __u32 ctrl;
1683
1684 ctrl = in_le32(&p->dc_regs[STGCTL]);
1685 if (blank > 0) {
1686 switch (blank - 1) {
1687 case VESA_NO_BLANKING:
1688 case VESA_POWERDOWN:
1689 ctrl &= ~0x00000380;
1690 if (p->ramdac == IBM) {
1691 p->cmap_regs[PIDXHI] = 0; eieio();
1692 p->cmap_regs[PIDXLO] = MISCTL2; eieio();
1693 p->cmap_regs[PIDXDATA] = 0x55; eieio();
1694 p->cmap_regs[PIDXLO] = MISCTL1; eieio();
1695 p->cmap_regs[PIDXDATA] = 0x11; eieio();
1696 p->cmap_regs[PIDXLO] = SYNCCTL; eieio();
1697 p->cmap_regs[PIDXDATA] = 0x0f; eieio();
1698 p->cmap_regs[PIDXLO] = PWRMNGMT;eieio();
1699 p->cmap_regs[PIDXDATA] = 0x1f; eieio();
1700 p->cmap_regs[PIDXLO] = CLKCTL; eieio();
1701 p->cmap_regs[PIDXDATA] = 0xc0;
1702 }
1703 break;
1704 case VESA_VSYNC_SUSPEND:
1705 ctrl &= ~0x00000020;
1706 break;
1707 case VESA_HSYNC_SUSPEND:
1708 ctrl &= ~0x00000010;
1709 break;
1710 }
1711 } else {
1712 if (p->ramdac == IBM) {
1713 ctrl |= 0x000017b0;
1714 p->cmap_regs[PIDXHI] = 0; eieio();
1715 p->cmap_regs[PIDXLO] = CLKCTL; eieio();
1716 p->cmap_regs[PIDXDATA] = 0x01; eieio();
1717 p->cmap_regs[PIDXLO] = PWRMNGMT;eieio();
1718 p->cmap_regs[PIDXDATA] = 0x00; eieio();
1719 p->cmap_regs[PIDXLO] = SYNCCTL; eieio();
1720 p->cmap_regs[PIDXDATA] = 0x00; eieio();
1721 p->cmap_regs[PIDXLO] = MISCTL1; eieio();
1722 p->cmap_regs[PIDXDATA] = 0x01; eieio();
1723 p->cmap_regs[PIDXLO] = MISCTL2; eieio();
1724 p->cmap_regs[PIDXDATA] = 0x45; eieio();
1725 } else
1726 ctrl |= 0x00001780;
1727 }
1728 out_le32(&p->dc_regs[STGCTL], ctrl);
1729 }
1730
1731 __initfunc(static void
1732 init_imstt(struct fb_info_imstt *p))
1733 {
1734 __u32 i, tmp;
1735 __u32 *ip, *end;
1736
1737 tmp = in_le32(&p->dc_regs[PRC]);
1738 if (p->ramdac == IBM)
1739 p->total_vram = (tmp & 0x0004) ? 0x400000 : 0x200000;
1740 else
1741 p->total_vram = 0x800000;
1742
1743 ip = (__u32 *)p->frame_buffer;
1744 end = (__u32 *)(p->frame_buffer + p->total_vram);
1745 while (ip < end)
1746 *ip++ = 0;
1747
1748 /* initialize the card */
1749 tmp = in_le32(&p->dc_regs[STGCTL]);
1750 out_le32(&p->dc_regs[STGCTL], tmp & ~0x1);
1751 out_le32(&p->dc_regs[SSR], 0);
1752
1753 /* set default values for DAC registers */
1754 if (p->ramdac == IBM) {
1755 p->cmap_regs[PPMASK] = 0xff; eieio();
1756 p->cmap_regs[PIDXHI] = 0; eieio();
1757 for (i = 0; i < sizeof(ibm_initregs) / sizeof(*ibm_initregs); i++) {
1758 p->cmap_regs[PIDXLO] = ibm_initregs[i].addr; eieio();
1759 p->cmap_regs[PIDXDATA] = ibm_initregs[i].value; eieio();
1760 }
1761 } else {
1762 for (i = 0; i < sizeof(tvp_initregs) / sizeof(*tvp_initregs); i++) {
1763 p->cmap_regs[TVPADDRW] = tvp_initregs[i].addr; eieio();
1764 p->cmap_regs[TVPIDATA] = tvp_initregs[i].value; eieio();
1765 }
1766 }
1767
1768 #if USE_NV_MODES && defined(CONFIG_PPC)
1769 {
1770 int vmode = init_vmode, cmode = init_cmode;
1771
1772 if (vmode == -1) {
1773 vmode = nvram_read_byte(NV_VMODE);
1774 if (vmode <= 0 || vmode > VMODE_MAX)
1775 vmode = VMODE_640_480_67;
1776 }
1777 if (cmode == -1) {
1778 cmode = nvram_read_byte(NV_CMODE);
1779 if (cmode < CMODE_8 || cmode > CMODE_32)
1780 cmode = CMODE_8;
1781 }
1782 if (mac_vmode_to_var(vmode, cmode, &p->disp.var)) {
1783 p->disp.var.xres = p->disp.var.xres_virtual = INIT_XRES;
1784 p->disp.var.yres = p->disp.var.yres_virtual = INIT_YRES;
1785 p->disp.var.bits_per_pixel = INIT_BPP;
1786 }
1787 }
1788 #else
1789 p->disp.var.xres = p->disp.var.xres_virtual = INIT_XRES;
1790 p->disp.var.yres = p->disp.var.yres_virtual = INIT_YRES;
1791 p->disp.var.bits_per_pixel = INIT_BPP;
1792 #endif
1793
1794 if ((p->disp.var.xres * p->disp.var.yres) * (p->disp.var.bits_per_pixel >> 3) > p->total_vram
1795 || !(compute_imstt_regvals(p, p->disp.var.xres, p->disp.var.yres))) {
1796 printk("imsttfb: %ux%ux%u not supported\n", p->disp.var.xres, p->disp.var.yres, p->disp.var.bits_per_pixel);
1797 kfree(p);
1798 return;
1799 }
1800
1801 sprintf(p->fix.id, "IMS TT (%s)", p->ramdac == IBM ? "IBM" : "TVP");
1802 p->fix.smem_start = (__u8 *)p->frame_buffer_phys;
1803 p->fix.smem_len = p->total_vram;
1804 p->fix.mmio_start = (__u8 *)p->dc_regs_phys;
1805 p->fix.mmio_len = 0x40000;
1806 p->fix.accel = FB_ACCEL_IMS_TWINTURBO;
1807 p->fix.type = FB_TYPE_PACKED_PIXELS;
1808 p->fix.visual = p->disp.var.bits_per_pixel == 8 ? FB_VISUAL_PSEUDOCOLOR
1809 : FB_VISUAL_DIRECTCOLOR;
1810 p->fix.line_length = p->disp.var.xres * (p->disp.var.bits_per_pixel >> 3);
1811 p->fix.xpanstep = 8;
1812 p->fix.ypanstep = 1;
1813 p->fix.ywrapstep = 0;
1814
1815 p->disp.var.accel_flags = noaccel ? 0 : FB_ACCELF_TEXT;
1816 set_disp(&p->disp, p);
1817
1818 if (!noaccel && p->ramdac == IBM)
1819 imstt_cursor_init(p);
1820 if (p->disp.var.green.length == 6)
1821 set_565(p);
1822 else
1823 set_555(p);
1824 set_imstt_regvals(p, p->disp.var.bits_per_pixel);
1825
1826 p->disp.var.pixclock = 1000000 / getclkMHz(p);
1827
1828 strcpy(p->info.modename, p->fix.id);
1829 strcpy(p->info.fontname, fontname);
1830 p->info.node = -1;
1831 p->info.fbops = &imsttfb_ops;
1832 p->info.disp = &p->disp;
1833 p->info.changevar = 0;
1834 p->info.switch_con = &imsttfbcon_switch;
1835 p->info.updatevar = &imsttfbcon_updatevar;
1836 p->info.blank = &imsttfbcon_blank;
1837 p->info.flags = FBINFO_FLAG_DEFAULT;
1838
1839 for (i = 0; i < 16; i++) {
1840 u_int j = color_table[i];
1841 p->palette[i].red = default_red[j];
1842 p->palette[i].green = default_grn[j];
1843 p->palette[i].blue = default_blu[j];
1844 }
1845
1846 if (register_framebuffer(&p->info) < 0) {
1847 kfree(p);
1848 return;
1849 }
1850
1851 i = GET_FB_IDX(p->info.node);
1852 tmp = (in_le32(&p->dc_regs[SSTATUS]) & 0x0f00) >> 8;
1853 printk("fb%u: %s frame buffer; %uMB vram; chip version %u\n",
1854 i, p->fix.id, p->total_vram >> 20, tmp);
1855
1856 #ifdef MODULE
1857 fb_info_imstt_p[i] = p;
1858 #endif
1859 #ifdef CONFIG_FB_COMPAT_XPMAC
1860 strncpy(display_info.name, "IMS,tt128mb", sizeof(display_info.name));
1861 display_info.fb_address = (__u32)p->frame_buffer_phys;
1862 display_info.cmap_adr_address = (__u32)&p->cmap_regs_phys[PADDRW];
1863 display_info.cmap_data_address = (__u32)&p->cmap_regs_phys[PDATA];
1864 display_info.disp_reg_address = (__u32)p->dc_regs_phys;
1865 if (!console_fb_info)
1866 console_fb_info = &p->info;
1867 #endif /* CONFIG_FB_COMPAT_XPMAC */
1868 }
1869
1870 #if defined(CONFIG_FB_OF) && !defined(MODULE)
1871 __initfunc(void
1872 imsttfb_of_init(struct device_node *dp))
1873 {
1874 struct fb_info_imstt *p;
1875 int i;
1876 __u32 addr = 0;
1877 __u8 bus, devfn;
1878 __u16 cmd;
1879
1880 for (i = 0; i < dp->n_addrs; i++) {
1881 if (dp->addrs[i].size >= 0x02000000)
1882 addr = dp->addrs[i].address;
1883 }
1884 if (!addr)
1885 return;
1886
1887 if (!pci_device_loc(dp, &bus, &devfn)) {
1888 if (!pcibios_read_config_word(bus, devfn, PCI_COMMAND, &cmd) && !(cmd & PCI_COMMAND_MEMORY)) {
1889 cmd |= PCI_COMMAND_MEMORY;
1890 pcibios_write_config_word(bus, devfn, PCI_COMMAND, cmd);
1891 }
1892 }
1893
1894 p = kmalloc(sizeof(struct fb_info_imstt), GFP_ATOMIC);
1895 if (!p)
1896 return;
1897 memset(p, 0, sizeof(struct fb_info_imstt));
1898
1899 if (dp->name[11] == '8' || (dp->name[6] == '3' && dp->name[7] == 'd'))
1900 p->ramdac = TVP;
1901 else
1902 p->ramdac = IBM;
1903
1904 p->frame_buffer_phys = (__u8 *)addr;
1905 p->frame_buffer = (__u8 *)ioremap(addr, p->ramdac == IBM ? 0x400000 : 0x800000);
1906 p->dc_regs_phys = (__u32 *)(addr + 0x800000);
1907 p->dc_regs = (__u32 *)ioremap(addr + 0x800000, 0x1000);
1908 p->cmap_regs_phys = (__u8 *)(addr + 0x840000);
1909 p->cmap_regs = (__u8 *)ioremap(addr + 0x840000, 0x1000);
1910
1911 init_imstt(p);
1912 }
1913 #endif
1914
1915 __initfunc(void
1916 imsttfb_init(void))
1917 {
1918 #if defined(CONFIG_FB_OF) && !defined(MODULE)
1919 /* We don't want to be called like this. */
1920 /* We rely on Open Firmware (offb) instead. */
1921 #elif defined(CONFIG_PCI)
1922 struct pci_dev *pdev;
1923 struct fb_info_imstt *p;
1924 __u32 addr;
1925 __u16 cmd;
1926
1927 for (pdev = pci_devices; pdev; pdev = pdev->next) {
1928 if (!(((pdev->class >> 16) == PCI_BASE_CLASS_DISPLAY)
1929 && (pdev->vendor == PCI_VENDOR_ID_IMS)))
1930 continue;
1931
1932 pci_read_config_word(pdev, PCI_COMMAND, &cmd);
1933 if (!(cmd & PCI_COMMAND_MEMORY)) {
1934 cmd |= PCI_COMMAND_MEMORY;
1935 pci_write_config_word(pdev, PCI_COMMAND, cmd);
1936 }
1937
1938 addr = pdev->base_address[0] & PCI_BASE_ADDRESS_MEM_MASK;
1939 if (!addr)
1940 continue;
1941
1942 p = kmalloc(sizeof(struct fb_info_imstt), GFP_ATOMIC);
1943 if (!p)
1944 return;
1945 memset(p, 0, sizeof(struct fb_info_imstt));
1946
1947 printk("imsttfb: device=%04x\n", pdev->device);
1948
1949 switch (pdev->device) {
1950 case 0x9128: /* IMS,tt128mbA */
1951 p->ramdac = IBM;
1952 break;
1953 case 0x9135: /* IMS,tt3d */
1954 default:
1955 p->ramdac = TVP;
1956 break;
1957 }
1958
1959 p->frame_buffer_phys = (__u8 *)addr;
1960 p->frame_buffer = (__u8 *)ioremap(addr, p->ramdac == IBM ? 0x400000 : 0x800000);
1961 p->dc_regs_phys = (__u32 *)(addr + 0x800000);
1962 p->dc_regs = (__u32 *)ioremap(addr + 0x800000, 0x1000);
1963 p->cmap_regs_phys = (__u8 *)(addr + 0x840000);
1964 p->cmap_regs = (__u8 *)ioremap(addr + 0x840000, 0x1000);
1965
1966 init_imstt(p);
1967 }
1968 #endif /* CONFIG_PCI */
1969 }
1970
1971 #ifndef MODULE
1972 __initfunc(void
1973 imsttfb_setup(char *options, int *ints))
1974 {
1975 char *this_opt;
1976
1977 if (!options || !*options)
1978 return;
1979
1980 for (this_opt = strtok(options, ","); this_opt;
1981 this_opt = strtok(NULL, ",")) {
1982 if (!strncmp(this_opt, "font:", 5)) {
1983 char *p;
1984 int i;
1985
1986 p = this_opt + 5;
1987 for (i = 0; i < sizeof(fontname) - 1; i++)
1988 if (!*p || *p == ' ' || *p == ',')
1989 break;
1990 memcpy(fontname, this_opt + 5, i);
1991 fontname[i] = 0;
1992 } else if (!strncmp(this_opt, "noblink", 7)) {
1993 curblink = 0;
1994 } else if (!strncmp(this_opt, "noaccel", 7)) {
1995 noaccel = 1;
1996 }
1997 #if defined(CONFIG_PPC)
1998 else if (!strncmp(this_opt, "vmode:", 6)) {
1999 int vmode = simple_strtoul(this_opt+6, NULL, 0);
2000 if (vmode > 0 && vmode <= VMODE_MAX)
2001 init_vmode = vmode;
2002 } else if (!strncmp(this_opt, "cmode:", 6)) {
2003 int cmode = simple_strtoul(this_opt+6, NULL, 0);
2004 switch (cmode) {
2005 case CMODE_8:
2006 case 8:
2007 init_cmode = CMODE_8;
2008 break;
2009 case CMODE_16:
2010 case 15:
2011 case 16:
2012 init_cmode = CMODE_16;
2013 break;
2014 case CMODE_32:
2015 case 24:
2016 case 32:
2017 init_cmode = CMODE_32;
2018 break;
2019 }
2020 }
2021 #endif
2022 }
2023 }
2024
2025 #else /* MODULE */
2026
2027 int
2028 init_module (void)
2029 {
2030 struct fb_info_imstt *p;
2031 __u32 i;
2032
2033 imsttfb_init();
2034
2035 for (i = 0; i < FB_MAX; i++) {
2036 p = fb_info_imstt_p[i];
2037 if (p)
2038 return 0;
2039 }
2040
2041 return -ENXIO;
2042 }
2043
2044 void
2045 cleanup_module (void)
2046 {
2047 struct fb_info_imstt *p;
2048 __u32 i;
2049
2050 for (i = 0; i < FB_MAX; i++) {
2051 p = fb_info_imstt_p[i];
2052 if (!p)
2053 continue;
2054 iounmap(p->cmap_regs);
2055 iounmap(p->dc_regs);
2056 iounmap(p->frame_buffer);
2057 kfree(p);
2058 }
2059 }
2060
2061 #include "macmodes.c"
2062 #endif /* MODULE */
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