include/asm-i386/pgtable.h

   1 #ifndef _I386_PGTABLE_H
   2 #define _I386_PGTABLE_H
   3
   4 #include <linux/config.h>
   5
   6 /*
   7  * The Linux memory management assumes a three-level page table setup. On
   8  * the i386, we use that, but "fold" the mid level into the top-level page
   9  * table, so that we physically have the same two-level page table as the
  10  * i386 mmu expects.
  11  *
  12  * This file contains the functions and defines necessary to modify and use
  13  * the i386 page table tree.
  14  */
  15 #ifndef __ASSEMBLY__
  16 #include <asm/processor.h>
  17 #include <linux/tasks.h>
  18
  19 /* Caches aren't brain-dead on the intel. */
  20 #define flush_cache_all()                       do { } while (0)
  21 #define flush_cache_mm(mm)                      do { } while (0)
  22 #define flush_cache_range(mm, start, end)       do { } while (0)
  23 #define flush_cache_page(vma, vmaddr)           do { } while (0)
  24 #define flush_page_to_ram(page)                 do { } while (0)
  25 #define flush_icache_range(start, end)          do { } while (0)
  26
  27 /*
  28  * TLB flushing:
  29  *
  30  *  - flush_tlb() flushes the current mm struct TLBs
  31  *  - flush_tlb_all() flushes all processes TLBs
  32  *  - flush_tlb_mm(mm) flushes the specified mm context TLB's
  33  *  - flush_tlb_page(vma, vmaddr) flushes one page
  34  *  - flush_tlb_range(mm, start, end) flushes a range of pages
  35  *
  36  * ..but the i386 has somewhat limited tlb flushing capabilities,
  37  * and page-granular flushes are available only on i486 and up.
  38  */
  39
  40 #define __flush_tlb() \
  41 do { unsigned long tmpreg; __asm__ __volatile__("movl %%cr3,%0\n\tmovl %0,%%cr3":"=r" (tmpreg) : :"memory"); } while (0)
  42
  43 #ifdef CONFIG_M386
  44 #define __flush_tlb_one(addr) flush_tlb()
  45 #else
  46 #define __flush_tlb_one(addr) \
  47 __asm__ __volatile__("invlpg %0": :"m" (*(char *) addr))
  48 #endif
  49
  50 #ifndef __SMP__
  51
  52 #define flush_tlb() __flush_tlb()
  53 #define flush_tlb_all() __flush_tlb()
  54 #define local_flush_tlb() __flush_tlb()
  55
  56 static inline void flush_tlb_mm(struct mm_struct *mm)
  57 {
  58         if (mm == current->mm)
  59                 __flush_tlb();
  60 }
  61
  62 static inline void flush_tlb_page(struct vm_area_struct *vma,
  63         unsigned long addr)
  64 {
  65         if (vma->vm_mm == current->mm)
  66                 __flush_tlb_one(addr);
  67 }
  68
  69 static inline void flush_tlb_range(struct mm_struct *mm,
  70         unsigned long start, unsigned long end)
  71 {
  72         if (mm == current->mm)
  73                 __flush_tlb();
  74 }
  75
  76 #else
  77
  78 /*
  79  * We aren't very clever about this yet -  SMP could certainly
  80  * avoid some global flushes..
  81  */
  82
  83 #include <asm/smp.h>
  84
  85 #define local_flush_tlb() \
  86         __flush_tlb()
  87
  88
  89 #define CLEVER_SMP_INVALIDATE
  90 #ifdef CLEVER_SMP_INVALIDATE
  91
  92 /*
  93  *      Smarter SMP flushing macros.
  94  *              c/o Linus Torvalds.
  95  *
  96  *      These mean you can really definitely utterly forget about
  97  *      writing to user space from interrupts. (Its not allowed anyway).
  98  */
  99
 100 static inline void flush_tlb_current_task(void)
 101 {
 102         if (current->mm->count == 1)    /* just one copy of this mm */
 103                 local_flush_tlb();      /* and that's us, so.. */
 104         else
 105                 smp_flush_tlb();
 106 }
 107
 108 #define flush_tlb() flush_tlb_current_task()
 109
 110 #define flush_tlb_all() smp_flush_tlb()
 111
 112 static inline void flush_tlb_mm(struct mm_struct * mm)
 113 {
 114         if (mm == current->mm && mm->count == 1)
 115                 local_flush_tlb();
 116         else
 117                 smp_flush_tlb();
 118 }
 119
 120 static inline void flush_tlb_page(struct vm_area_struct * vma,
 121         unsigned long va)
 122 {
 123         if (vma->vm_mm == current->mm && current->mm->count == 1)
 124                 __flush_tlb_one(va);
 125         else
 126                 smp_flush_tlb();
 127 }
 128
 129 static inline void flush_tlb_range(struct mm_struct * mm,
 130         unsigned long start, unsigned long end)
 131 {
 132         flush_tlb_mm(mm);
 133 }
 134
 135
 136 #else
 137
 138 #define flush_tlb() \
 139         smp_flush_tlb()
 140
 141 #define flush_tlb_all() flush_tlb()
 142
 143 static inline void flush_tlb_mm(struct mm_struct *mm)
 144 {
 145         flush_tlb();
 146 }
 147
 148 static inline void flush_tlb_page(struct vm_area_struct *vma,
 149         unsigned long addr)
 150 {
 151         flush_tlb();
 152 }
 153
 154 static inline void flush_tlb_range(struct mm_struct *mm,
 155         unsigned long start, unsigned long end)
 156 {
 157         flush_tlb();
 158 }
 159 #endif
 160 #endif
 161 #endif /* !__ASSEMBLY__ */
 162
 163
 164 /* Certain architectures need to do special things when PTEs
 165  * within a page table are directly modified.  Thus, the following
 166  * hook is made available.
 167  */
 168 #define set_pte(pteptr, pteval) ((*(pteptr)) = (pteval))
 169
 170 /* PMD_SHIFT determines the size of the area a second-level page table can map */
 171 #define PMD_SHIFT       22
 172 #define PMD_SIZE        (1UL << PMD_SHIFT)
 173 #define PMD_MASK        (~(PMD_SIZE-1))
 174
 175 /* PGDIR_SHIFT determines what a third-level page table entry can map */
 176 #define PGDIR_SHIFT     22
 177 #define PGDIR_SIZE      (1UL << PGDIR_SHIFT)
 178 #define PGDIR_MASK      (~(PGDIR_SIZE-1))
 179
 180 /*
 181  * entries per page directory level: the i386 is two-level, so
 182  * we don't really have any PMD directory physically.
 183  */
 184 #define PTRS_PER_PTE    1024
 185 #define PTRS_PER_PMD    1
 186 #define PTRS_PER_PGD    1024
 187 #define USER_PTRS_PER_PGD       (TASK_SIZE/PGDIR_SIZE)
 188
 189 /*
 190  * pgd entries used up by user/kernel:
 191  */
 192
 193 #define USER_PGD_PTRS (PAGE_OFFSET >> PGDIR_SHIFT)
 194 #define KERNEL_PGD_PTRS (PTRS_PER_PGD-USER_PGD_PTRS)
 195 #define __USER_PGD_PTRS ((__PAGE_OFFSET >> PGDIR_SHIFT) & 0x3ff)
 196 #define __KERNEL_PGD_PTRS (PTRS_PER_PGD-__USER_PGD_PTRS)
 197
 198 #ifndef __ASSEMBLY__
 199 /* Just any arbitrary offset to the start of the vmalloc VM area: the
 200  * current 8MB value just means that there will be a 8MB "hole" after the
 201  * physical memory until the kernel virtual memory starts.  That means that
 202  * any out-of-bounds memory accesses will hopefully be caught.
 203  * The vmalloc() routines leaves a hole of 4kB between each vmalloced
 204  * area for the same reason. ;)
 205  */
 206 #define VMALLOC_OFFSET  (8*1024*1024)
 207 #define VMALLOC_START   (((unsigned long) high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1))
 208 #define VMALLOC_VMADDR(x) ((unsigned long)(x))
 209
 210 /*
 211  * The 4MB page is guessing..  Detailed in the infamous "Chapter H"
 212  * of the Pentium details, but assuming intel did the straightforward
 213  * thing, this bit set in the page directory entry just means that
 214  * the page directory entry points directly to a 4MB-aligned block of
 215  * memory.
 216  */
 217 #define _PAGE_PRESENT   0x001
 218 #define _PAGE_PROTNONE  0x002           /* If not present */
 219 #define _PAGE_RW        0x002           /* If present */
 220 #define _PAGE_USER      0x004
 221 #define _PAGE_WT        0x008
 222 #define _PAGE_PCD       0x010
 223 #define _PAGE_ACCESSED  0x020
 224 #define _PAGE_DIRTY     0x040
 225 #define _PAGE_4M        0x080   /* 4 MB page, Pentium+.. */
 226 #define _PAGE_GLOBAL    0x100   /* Global TLB entry PPro+ */
 227
 228 #define _PAGE_READABLE  (_PAGE_PRESENT)
 229 #define _PAGE_WRITABLE  (_PAGE_PRESENT | _PAGE_RW)
 230
 231 #define _PAGE_TABLE     (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER | _PAGE_ACCESSED | _PAGE_DIRTY)
 232 #define _KERNPG_TABLE   (_PAGE_PRESENT | _PAGE_RW | _PAGE_ACCESSED | _PAGE_DIRTY)
 233 #define _PAGE_CHG_MASK  (PAGE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY)
 234
 235 #define PAGE_NONE       __pgprot(_PAGE_PROTNONE | _PAGE_ACCESSED)
 236 #define PAGE_SHARED     __pgprot(_PAGE_PRESENT | _PAGE_RW | _PAGE_USER | _PAGE_ACCESSED)
 237 #define PAGE_COPY       __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_ACCESSED)
 238 #define PAGE_READONLY   __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_ACCESSED)
 239 #define PAGE_KERNEL     __pgprot(_PAGE_PRESENT | _PAGE_RW | _PAGE_DIRTY | _PAGE_ACCESSED)
 240
 241 /*
 242  * The i386 can't do page protection for execute, and considers that the same are read.
 243  * Also, write permissions imply read permissions. This is the closest we can get..
 244  */
 245 #define __P000  PAGE_NONE
 246 #define __P001  PAGE_READONLY
 247 #define __P010  PAGE_COPY
 248 #define __P011  PAGE_COPY
 249 #define __P100  PAGE_READONLY
 250 #define __P101  PAGE_READONLY
 251 #define __P110  PAGE_COPY
 252 #define __P111  PAGE_COPY
 253
 254 #define __S000  PAGE_NONE
 255 #define __S001  PAGE_READONLY
 256 #define __S010  PAGE_SHARED
 257 #define __S011  PAGE_SHARED
 258 #define __S100  PAGE_READONLY
 259 #define __S101  PAGE_READONLY
 260 #define __S110  PAGE_SHARED
 261 #define __S111  PAGE_SHARED
 262
 263 /*
 264  * Define this if things work differently on an i386 and an i486:
 265  * it will (on an i486) warn about kernel memory accesses that are
 266  * done without a 'verify_area(VERIFY_WRITE,..)'
 267  */
 268 #undef TEST_VERIFY_AREA
 269
 270 /* page table for 0-4MB for everybody */
 271 extern unsigned long pg0[1024];
 272 /* zero page used for uninitialized stuff */
 273 extern unsigned long empty_zero_page[1024];
 274
 275 /*
 276  * BAD_PAGETABLE is used when we need a bogus page-table, while
 277  * BAD_PAGE is used for a bogus page.
 278  *
 279  * ZERO_PAGE is a global shared page that is always zero: used
 280  * for zero-mapped memory areas etc..
 281  */
 282 extern pte_t __bad_page(void);
 283 extern pte_t * __bad_pagetable(void);
 284
 285 #define BAD_PAGETABLE __bad_pagetable()
 286 #define BAD_PAGE __bad_page()
 287 #define ZERO_PAGE ((unsigned long) empty_zero_page)
 288
 289 /* number of bits that fit into a memory pointer */
 290 #define BITS_PER_PTR                    (8*sizeof(unsigned long))
 291
 292 /* to align the pointer to a pointer address */
 293 #define PTR_MASK                        (~(sizeof(void*)-1))
 294
 295 /* sizeof(void*)==1<<SIZEOF_PTR_LOG2 */
 296 /* 64-bit machines, beware!  SRB. */
 297 #define SIZEOF_PTR_LOG2                 2
 298
 299 /* to find an entry in a page-table */
 300 #define PAGE_PTR(address) \
 301 ((unsigned long)(address)>>(PAGE_SHIFT-SIZEOF_PTR_LOG2)&PTR_MASK&~PAGE_MASK)
 302
 303 /* to set the page-dir */
 304 #define SET_PAGE_DIR(tsk,pgdir) \
 305 do { \
 306         unsigned long __pgdir = __pa(pgdir); \
 307         (tsk)->tss.cr3 = __pgdir; \
 308         if ((tsk) == current) \
 309                 __asm__ __volatile__("movl %0,%%cr3": :"r" (__pgdir)); \
 310 } while (0)
 311
 312 #define pte_none(x)     (!pte_val(x))
 313 #define pte_present(x)  (pte_val(x) & (_PAGE_PRESENT | _PAGE_PROTNONE))
 314 #define pte_clear(xp)   do { pte_val(*(xp)) = 0; } while (0)
 315
 316 #define pmd_none(x)     (!pmd_val(x))
 317 #define pmd_bad(x)      ((pmd_val(x) & (~PAGE_MASK & ~_PAGE_USER)) != _KERNPG_TABLE)
 318 #define pmd_present(x)  (pmd_val(x) & _PAGE_PRESENT)
 319 #define pmd_clear(xp)   do { pmd_val(*(xp)) = 0; } while (0)
 320
 321 /*
 322  * The "pgd_xxx()" functions here are trivial for a folded two-level
 323  * setup: the pgd is never bad, and a pmd always exists (as it's folded
 324  * into the pgd entry)
 325  */
 326 extern inline int pgd_none(pgd_t pgd)           { return 0; }
 327 extern inline int pgd_bad(pgd_t pgd)            { return 0; }
 328 extern inline int pgd_present(pgd_t pgd)        { return 1; }
 329 extern inline void pgd_clear(pgd_t * pgdp)      { }
 330
 331 /*
 332  * The following only work if pte_present() is true.
 333  * Undefined behaviour if not..
 334  */
 335 extern inline int pte_read(pte_t pte)           { return pte_val(pte) & _PAGE_USER; }
 336 extern inline int pte_exec(pte_t pte)           { return pte_val(pte) & _PAGE_USER; }
 337 extern inline int pte_dirty(pte_t pte)          { return pte_val(pte) & _PAGE_DIRTY; }
 338 extern inline int pte_young(pte_t pte)          { return pte_val(pte) & _PAGE_ACCESSED; }
 339
 340 extern inline pte_t pte_rdprotect(pte_t pte)    { pte_val(pte) &= ~_PAGE_USER; return pte; }
 341 extern inline pte_t pte_exprotect(pte_t pte)    { pte_val(pte) &= ~_PAGE_USER; return pte; }
 342 extern inline pte_t pte_mkclean(pte_t pte)      { pte_val(pte) &= ~_PAGE_DIRTY; return pte; }
 343 extern inline pte_t pte_mkold(pte_t pte)        { pte_val(pte) &= ~_PAGE_ACCESSED; return pte; }
 344 extern inline pte_t pte_mkread(pte_t pte)       { pte_val(pte) |= _PAGE_USER; return pte; }
 345 extern inline pte_t pte_mkexec(pte_t pte)       { pte_val(pte) |= _PAGE_USER; return pte; }
 346 extern inline pte_t pte_mkdirty(pte_t pte)      { pte_val(pte) |= _PAGE_DIRTY; return pte; }
 347 extern inline pte_t pte_mkyoung(pte_t pte)      { pte_val(pte) |= _PAGE_ACCESSED; return pte; }
 348
 349 /*
 350  * These are harder, as writability is two bits, not one..
 351  */
 352 extern inline int pte_write(pte_t pte)          { return (pte_val(pte) & _PAGE_WRITABLE) == _PAGE_WRITABLE; }
 353 extern inline pte_t pte_wrprotect(pte_t pte)    { pte_val(pte) &= ~((pte_val(pte) & _PAGE_PRESENT) << 1); return pte; }
 354 extern inline pte_t pte_mkwrite(pte_t pte)      { pte_val(pte) |= _PAGE_RW; return pte; }
 355
 356 /*
 357  * Conversion functions: convert a page and protection to a page entry,
 358  * and a page entry and page directory to the page they refer to.
 359  */
 360 #define mk_pte(page, pgprot) \
 361 ({ pte_t __pte; pte_val(__pte) = __pa(page) + pgprot_val(pgprot); __pte; })
 362
 363 /* This takes a physical page address that is used by the remapping functions */
 364 #define mk_pte_phys(physpage, pgprot) \
 365 ({ pte_t __pte; pte_val(__pte) = physpage + pgprot_val(pgprot); __pte; })
 366
 367 extern inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
 368 { pte_val(pte) = (pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot); return pte; }
 369
 370 #define pte_page(pte) \
 371 ((unsigned long) __va(pte_val(pte) & PAGE_MASK))
 372
 373 #define pmd_page(pmd) \
 374 ((unsigned long) __va(pmd_val(pmd) & PAGE_MASK))
 375
 376 /* to find an entry in a page-table-directory */
 377 #define pgd_offset(mm, address) \
 378 ((mm)->pgd + ((address) >> PGDIR_SHIFT))
 379
 380 /* to find an entry in a kernel page-table-directory */
 381 #define pgd_offset_k(address) pgd_offset(&init_mm, address)
 382
 383 /* Find an entry in the second-level page table.. */
 384 extern inline pmd_t * pmd_offset(pgd_t * dir, unsigned long address)
 385 {
 386         return (pmd_t *) dir;
 387 }
 388
 389 /* Find an entry in the third-level page table.. */
 390 #define pte_offset(pmd, address) \
 391 ((pte_t *) (pmd_page(*pmd) + ((address>>10) & ((PTRS_PER_PTE-1)<<2))))
 392
 393 /*
 394  * Allocate and free page tables. The xxx_kernel() versions are
 395  * used to allocate a kernel page table - this turns on ASN bits
 396  * if any.
 397  */
 398
 399 #define pgd_quicklist (current_cpu_data.pgd_quick)
 400 #define pmd_quicklist ((unsigned long *)0)
 401 #define pte_quicklist (current_cpu_data.pte_quick)
 402 #define pgtable_cache_size (current_cpu_data.pgtable_cache_sz)
 403
 404 extern __inline__ pgd_t *get_pgd_slow(void)
 405 {
 406         pgd_t *ret = (pgd_t *)__get_free_page(GFP_KERNEL), *init;
 407
 408         if (ret) {
 409                 init = pgd_offset(&init_mm, 0);
 410                 memset (ret, 0, USER_PTRS_PER_PGD * sizeof(pgd_t));
 411                 memcpy (ret + USER_PTRS_PER_PGD, init + USER_PTRS_PER_PGD,
 412                         (PTRS_PER_PGD - USER_PTRS_PER_PGD) * sizeof(pgd_t));
 413         }
 414         return ret;
 415 }
 416
 417 extern __inline__ pgd_t *get_pgd_fast(void)
 418 {
 419         unsigned long *ret;
 420
 421         if((ret = pgd_quicklist) != NULL) {
 422                 pgd_quicklist = (unsigned long *)(*ret);
 423                 ret[0] = ret[1];
 424                 pgtable_cache_size--;
 425         } else
 426                 ret = (unsigned long *)get_pgd_slow();
 427         return (pgd_t *)ret;
 428 }
 429
 430 extern __inline__ void free_pgd_fast(pgd_t *pgd)
 431 {
 432         *(unsigned long *)pgd = (unsigned long) pgd_quicklist;
 433         pgd_quicklist = (unsigned long *) pgd;
 434         pgtable_cache_size++;
 435 }
 436
 437 extern __inline__ void free_pgd_slow(pgd_t *pgd)
 438 {
 439         free_page((unsigned long)pgd);
 440 }
 441
 442 extern pte_t *get_pte_slow(pmd_t *pmd, unsigned long address_preadjusted);
 443 extern pte_t *get_pte_kernel_slow(pmd_t *pmd, unsigned long address_preadjusted);
 444
 445 extern __inline__ pte_t *get_pte_fast(void)
 446 {
 447         unsigned long *ret;
 448
 449         if((ret = (unsigned long *)pte_quicklist) != NULL) {
 450                 pte_quicklist = (unsigned long *)(*ret);
 451                 ret[0] = ret[1];
 452                 pgtable_cache_size--;
 453         }
 454         return (pte_t *)ret;
 455 }
 456
 457 extern __inline__ void free_pte_fast(pte_t *pte)
 458 {
 459         *(unsigned long *)pte = (unsigned long) pte_quicklist;
 460         pte_quicklist = (unsigned long *) pte;
 461         pgtable_cache_size++;
 462 }
 463
 464 extern __inline__ void free_pte_slow(pte_t *pte)
 465 {
 466         free_page((unsigned long)pte);
 467 }
 468
 469 /* We don't use pmd cache, so these are dummy routines */
 470 extern __inline__ pmd_t *get_pmd_fast(void)
 471 {
 472         return (pmd_t *)0;
 473 }
 474
 475 extern __inline__ void free_pmd_fast(pmd_t *pmd)
 476 {
 477 }
 478
 479 extern __inline__ void free_pmd_slow(pmd_t *pmd)
 480 {
 481 }
 482
 483 extern void __bad_pte(pmd_t *pmd);
 484 extern void __bad_pte_kernel(pmd_t *pmd);
 485
 486 #define pte_free_kernel(pte)    free_pte_fast(pte)
 487 #define pte_free(pte)           free_pte_fast(pte)
 488 #define pgd_free(pgd)           free_pgd_fast(pgd)
 489 #define pgd_alloc()             get_pgd_fast()
 490
 491 extern inline pte_t * pte_alloc_kernel(pmd_t * pmd, unsigned long address)
 492 {
 493         address = (address >> PAGE_SHIFT) & (PTRS_PER_PTE - 1);
 494         if (pmd_none(*pmd)) {
 495                 pte_t * page = (pte_t *) get_pte_fast();
 496
 497                 if (!page)
 498                         return get_pte_kernel_slow(pmd, address);
 499                 pmd_val(*pmd) = _KERNPG_TABLE + __pa(page);
 500                 return page + address;
 501         }
 502         if (pmd_bad(*pmd)) {
 503                 __bad_pte_kernel(pmd);
 504                 return NULL;
 505         }
 506         return (pte_t *) pmd_page(*pmd) + address;
 507 }
 508
 509 extern inline pte_t * pte_alloc(pmd_t * pmd, unsigned long address)
 510 {
 511         address = (address >> (PAGE_SHIFT-2)) & 4*(PTRS_PER_PTE - 1);
 512
 513         if (pmd_none(*pmd))
 514                 goto getnew;
 515         if (pmd_bad(*pmd))
 516                 goto fix;
 517         return (pte_t *) (pmd_page(*pmd) + address);
 518 getnew:
 519 {
 520         unsigned long page = (unsigned long) get_pte_fast();
 521
 522         if (!page)
 523                 return get_pte_slow(pmd, address);
 524         pmd_val(*pmd) = _PAGE_TABLE + __pa(page);
 525         return (pte_t *) (page + address);
 526 }
 527 fix:
 528         __bad_pte(pmd);
 529         return NULL;
 530 }
 531
 532 /*
 533  * allocating and freeing a pmd is trivial: the 1-entry pmd is
 534  * inside the pgd, so has no extra memory associated with it.
 535  */
 536 extern inline void pmd_free(pmd_t * pmd)
 537 {
 538 }
 539
 540 extern inline pmd_t * pmd_alloc(pgd_t * pgd, unsigned long address)
 541 {
 542         return (pmd_t *) pgd;
 543 }
 544
 545 #define pmd_free_kernel         pmd_free
 546 #define pmd_alloc_kernel        pmd_alloc
 547
 548 extern inline void set_pgdir(unsigned long address, pgd_t entry)
 549 {
 550         struct task_struct * p;
 551         pgd_t *pgd;
 552 #ifdef __SMP__
 553         int i;
 554 #endif
 555
 556         read_lock(&tasklist_lock);
 557         for_each_task(p) {
 558                 if (!p->mm)
 559                         continue;
 560                 *pgd_offset(p->mm,address) = entry;
 561         }
 562         read_unlock(&tasklist_lock);
 563 #ifndef __SMP__
 564         for (pgd = (pgd_t *)pgd_quicklist; pgd; pgd = (pgd_t *)*(unsigned long *)pgd)
 565                 pgd[address >> PGDIR_SHIFT] = entry;
 566 #else
 567         /* To pgd_alloc/pgd_free, one holds master kernel lock and so does our callee, so we can
 568            modify pgd caches of other CPUs as well. -jj */
 569         for (i = 0; i < NR_CPUS; i++)
 570                 for (pgd = (pgd_t *)cpu_data[i].pgd_quick; pgd; pgd = (pgd_t *)*(unsigned long *)pgd)
 571                         pgd[address >> PGDIR_SHIFT] = entry;
 572 #endif
 573 }
 574
 575 extern pgd_t swapper_pg_dir[1024];
 576
 577 /*
 578  * The i386 doesn't have any external MMU info: the kernel page
 579  * tables contain all the necessary information.
 580  */
 581 extern inline void update_mmu_cache(struct vm_area_struct * vma,
 582         unsigned long address, pte_t pte)
 583 {
 584 }
 585
 586 #define SWP_TYPE(entry) (((entry) >> 2) & 0x3f)
 587 #define SWP_OFFSET(entry) ((entry) >> 8)
 588 #define SWP_ENTRY(type,offset) (((type) << 2) | ((offset) << 8))
 589
 590 #define module_map      vmalloc
 591 #define module_unmap    vfree
 592
 593 #endif /* !__ASSEMBLY__ */
 594
 595 #endif /* _I386_PAGE_H */