include/asm-sparc/irq.h

   1 /* $Id: irq.h,v 1.32 2000/08/26 02:42:28 anton Exp $
   2  * irq.h: IRQ registers on the Sparc.
   3  *
   4  * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
   5  */
   6
   7 #ifndef _SPARC_IRQ_H
   8 #define _SPARC_IRQ_H
   9
  10 #include <linux/config.h>
  11 #include <linux/linkage.h>
  12 #include <linux/threads.h>     /* For NR_CPUS */
  13
  14 #include <asm/system.h>     /* For SUN4M_NCPUS */
  15 #include <asm/btfixup.h>
  16
  17 #define __irq_ino(irq) irq
  18 #define __irq_pil(irq) irq
  19 BTFIXUPDEF_CALL(char *, __irq_itoa, unsigned int)
  20 #define __irq_itoa(irq) BTFIXUP_CALL(__irq_itoa)(irq)
  21
  22 #define NR_IRQS    15
  23
  24 /* Dave Redman (djhr@tadpole.co.uk)
  25  * changed these to function pointers.. it saves cycles and will allow
  26  * the irq dependencies to be split into different files at a later date
  27  * sun4c_irq.c, sun4m_irq.c etc so we could reduce the kernel size.
  28  * Jakub Jelinek (jj@sunsite.mff.cuni.cz)
  29  * Changed these to btfixup entities... It saves cycles :)
  30  */
  31 BTFIXUPDEF_CALL(void, disable_irq, unsigned int)
  32 BTFIXUPDEF_CALL(void, enable_irq, unsigned int)
  33 BTFIXUPDEF_CALL(void, disable_pil_irq, unsigned int)
  34 BTFIXUPDEF_CALL(void, enable_pil_irq, unsigned int)
  35 BTFIXUPDEF_CALL(void, clear_clock_irq, void)
  36 BTFIXUPDEF_CALL(void, clear_profile_irq, int)
  37 BTFIXUPDEF_CALL(void, load_profile_irq, int, unsigned int)
  38
  39 #define disable_irq_nosync disable_irq
  40 #define disable_irq(irq) BTFIXUP_CALL(disable_irq)(irq)
  41 #define enable_irq(irq) BTFIXUP_CALL(enable_irq)(irq)
  42 #define disable_pil_irq(irq) BTFIXUP_CALL(disable_pil_irq)(irq)
  43 #define enable_pil_irq(irq) BTFIXUP_CALL(enable_pil_irq)(irq)
  44 #define clear_clock_irq() BTFIXUP_CALL(clear_clock_irq)()
  45 #define clear_profile_irq(cpu) BTFIXUP_CALL(clear_profile_irq)(cpu)
  46 #define load_profile_irq(cpu,limit) BTFIXUP_CALL(load_profile_irq)(cpu,limit)
  47
  48 extern void (*init_timers)(void (*lvl10_irq)(int, void *, struct pt_regs *));
  49 extern void claim_ticker14(void (*irq_handler)(int, void *, struct pt_regs *),
  50                            int irq,
  51                            unsigned int timeout);
  52
  53 #ifdef CONFIG_SMP
  54 BTFIXUPDEF_CALL(void, set_cpu_int, int, int)
  55 BTFIXUPDEF_CALL(void, clear_cpu_int, int, int)
  56 BTFIXUPDEF_CALL(void, set_irq_udt, int)
  57
  58 #define set_cpu_int(cpu,level) BTFIXUP_CALL(set_cpu_int)(cpu,level)
  59 #define clear_cpu_int(cpu,level) BTFIXUP_CALL(clear_cpu_int)(cpu,level)
  60 #define set_irq_udt(cpu) BTFIXUP_CALL(set_irq_udt)(cpu)
  61 #endif
  62
  63 extern int request_fast_irq(unsigned int irq, void (*handler)(int, void *, struct pt_regs *), unsigned long flags, __const__ char *devname);
  64
  65 /* On the sun4m, just like the timers, we have both per-cpu and master
  66  * interrupt registers.
  67  */
  68
  69 /* These registers are used for sending/receiving irqs from/to
  70  * different cpu's.
  71  */
  72 struct sun4m_intreg_percpu {
  73         unsigned int tbt;        /* Interrupts still pending for this cpu. */
  74
  75         /* These next two registers are WRITE-ONLY and are only
  76          * "on bit" sensitive, "off bits" written have NO affect.
  77          */
  78         unsigned int clear;  /* Clear this cpus irqs here. */
  79         unsigned int set;    /* Set this cpus irqs here. */
  80         unsigned char space[PAGE_SIZE - 12];
  81 };
  82
  83 /*
  84  * djhr
  85  * Actually the clear and set fields in this struct are misleading..
  86  * according to the SLAVIO manual (and the same applies for the SEC)
  87  * the clear field clears bits in the mask which will ENABLE that IRQ
  88  * the set field sets bits in the mask to DISABLE the IRQ.
  89  *
  90  * Also the undirected_xx address in the SLAVIO is defined as
  91  * RESERVED and write only..
  92  *
  93  * DAVEM_NOTE: The SLAVIO only specifies behavior on uniprocessor
  94  *             sun4m machines, for MP the layout makes more sense.
  95  */
  96 struct sun4m_intregs {
  97         struct sun4m_intreg_percpu cpu_intregs[SUN4M_NCPUS];
  98         unsigned int tbt;                /* IRQ's that are still pending. */
  99         unsigned int irqs;               /* Master IRQ bits. */
 100
 101         /* Again, like the above, two these registers are WRITE-ONLY. */
 102         unsigned int clear;              /* Clear master IRQ's by setting bits here. */
 103         unsigned int set;                /* Set master IRQ's by setting bits here. */
 104
 105         /* This register is both READ and WRITE. */
 106         unsigned int undirected_target;  /* Which cpu gets undirected irqs. */
 107 };
 108
 109 extern struct sun4m_intregs *sun4m_interrupts;
 110
 111 /*
 112  * Bit field defines for the interrupt registers on various
 113  * Sparc machines.
 114  */
 115
 116 /* The sun4c interrupt register. */
 117 #define SUN4C_INT_ENABLE  0x01     /* Allow interrupts. */
 118 #define SUN4C_INT_E14     0x80     /* Enable level 14 IRQ. */
 119 #define SUN4C_INT_E10     0x20     /* Enable level 10 IRQ. */
 120 #define SUN4C_INT_E8      0x10     /* Enable level 8 IRQ. */
 121 #define SUN4C_INT_E6      0x08     /* Enable level 6 IRQ. */
 122 #define SUN4C_INT_E4      0x04     /* Enable level 4 IRQ. */
 123 #define SUN4C_INT_E1      0x02     /* Enable level 1 IRQ. */
 124
 125 /* Dave Redman (djhr@tadpole.co.uk)
 126  * The sun4m interrupt registers.
 127  */
 128 #define SUN4M_INT_ENABLE        0x80000000
 129 #define SUN4M_INT_E14           0x00000080
 130 #define SUN4M_INT_E10           0x00080000
 131
 132 #define SUN4M_HARD_INT(x)       (0x000000001 << (x))
 133 #define SUN4M_SOFT_INT(x)       (0x000010000 << (x))
 134
 135 #define SUN4M_INT_MASKALL       0x80000000        /* mask all interrupts */
 136 #define SUN4M_INT_MODULE_ERR    0x40000000        /* module error */
 137 #define SUN4M_INT_M2S_WRITE     0x20000000        /* write buffer error */
 138 #define SUN4M_INT_ECC           0x10000000        /* ecc memory error */
 139 #define SUN4M_INT_FLOPPY        0x00400000        /* floppy disk */
 140 #define SUN4M_INT_MODULE        0x00200000        /* module interrupt */
 141 #define SUN4M_INT_VIDEO         0x00100000        /* onboard video */
 142 #define SUN4M_INT_REALTIME      0x00080000        /* system timer */
 143 #define SUN4M_INT_SCSI          0x00040000        /* onboard scsi */
 144 #define SUN4M_INT_AUDIO         0x00020000        /* audio/isdn */
 145 #define SUN4M_INT_ETHERNET      0x00010000        /* onboard ethernet */
 146 #define SUN4M_INT_SERIAL        0x00008000        /* serial ports */
 147 #define SUN4M_INT_KBDMS         0x00004000        /* keyboard/mouse */
 148 #define SUN4M_INT_SBUSBITS      0x00003F80        /* sbus int bits */
 149
 150 #define SUN4M_INT_SBUS(x)       (1 << (x+7))
 151 #define SUN4M_INT_VME(x)        (1 << (x))
 152
 153 #endif