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[davej-history.git] / drivers / video / matrox / matroxfb_Ti3026.c
blob7c65eaa0f982da4d7729c55fd8c216bfa9cfce6e
1 /*
2 *
3 * Hardware accelerated Matrox Millennium I, II, Mystique, G100, G200 and G400
4 *
5 * (c) 1998,1999,2000 Petr Vandrovec <vandrove@vc.cvut.cz>
6 *
7 * Version: 1.50 2000/08/10
8 *
9 * MTRR stuff: 1998 Tom Rini <trini@kernel.crashing.org>
10 *
11 * Contributors: "menion?" <menion@mindless.com>
12 * Betatesting, fixes, ideas
13 *
14 * "Kurt Garloff" <garloff@suse.de>
15 * Betatesting, fixes, ideas, videomodes, videomodes timmings
16 *
17 * "Tom Rini" <trini@kernel.crashing.org>
18 * MTRR stuff, PPC cleanups, betatesting, fixes, ideas
19 *
20 * "Bibek Sahu" <scorpio@dodds.net>
21 * Access device through readb|w|l and write b|w|l
22 * Extensive debugging stuff
23 *
24 * "Daniel Haun" <haund@usa.net>
25 * Testing, hardware cursor fixes
26 *
27 * "Scott Wood" <sawst46+@pitt.edu>
28 * Fixes
29 *
30 * "Gerd Knorr" <kraxel@goldbach.isdn.cs.tu-berlin.de>
31 * Betatesting
32 *
33 * "Kelly French" <targon@hazmat.com>
34 * "Fernando Herrera" <fherrera@eurielec.etsit.upm.es>
35 * Betatesting, bug reporting
36 *
37 * "Pablo Bianucci" <pbian@pccp.com.ar>
38 * Fixes, ideas, betatesting
39 *
40 * "Inaky Perez Gonzalez" <inaky@peloncho.fis.ucm.es>
41 * Fixes, enhandcements, ideas, betatesting
42 *
43 * "Ryuichi Oikawa" <roikawa@rr.iiij4u.or.jp>
44 * PPC betatesting, PPC support, backward compatibility
45 *
46 * "Paul Womar" <Paul@pwomar.demon.co.uk>
47 * "Owen Waller" <O.Waller@ee.qub.ac.uk>
48 * PPC betatesting
49 *
50 * "Thomas Pornin" <pornin@bolet.ens.fr>
51 * Alpha betatesting
52 *
53 * "Pieter van Leuven" <pvl@iae.nl>
54 * "Ulf Jaenicke-Roessler" <ujr@physik.phy.tu-dresden.de>
55 * G100 testing
56 *
57 * "H. Peter Arvin" <hpa@transmeta.com>
58 * Ideas
59 *
60 * "Cort Dougan" <cort@cs.nmt.edu>
61 * CHRP fixes and PReP cleanup
62 *
63 * "Mark Vojkovich" <mvojkovi@ucsd.edu>
64 * G400 support
65 *
66 * (following author is not in any relation with this code, but his code
67 * is included in this driver)
68 *
69 * Based on framebuffer driver for VBE 2.0 compliant graphic boards
70 * (c) 1998 Gerd Knorr <kraxel@cs.tu-berlin.de>
71 *
72 * (following author is not in any relation with this code, but his ideas
73 * were used when writting this driver)
74 *
75 * FreeVBE/AF (Matrox), "Shawn Hargreaves" <shawn@talula.demon.co.uk>
76 *
77 */
78
79 /* make checkconfig does not verify included files... */
80 #include <linux/config.h>
81
82 #include "matroxfb_Ti3026.h"
83 #include "matroxfb_misc.h"
84 #include "matroxfb_accel.h"
85
86 #ifdef CONFIG_FB_MATROX_MILLENIUM
87 #define outTi3026 matroxfb_DAC_out
88 #define inTi3026 matroxfb_DAC_in
89
90 #define TVP3026_INDEX 0x00
91 #define TVP3026_PALWRADD 0x00
92 #define TVP3026_PALDATA 0x01
93 #define TVP3026_PIXRDMSK 0x02
94 #define TVP3026_PALRDADD 0x03
95 #define TVP3026_CURCOLWRADD 0x04
96 #define TVP3026_CLOVERSCAN 0x00
97 #define TVP3026_CLCOLOR0 0x01
98 #define TVP3026_CLCOLOR1 0x02
99 #define TVP3026_CLCOLOR2 0x03
100 #define TVP3026_CURCOLDATA 0x05
101 #define TVP3026_CURCOLRDADD 0x07
102 #define TVP3026_CURCTRL 0x09
103 #define TVP3026_X_DATAREG 0x0A
104 #define TVP3026_CURRAMDATA 0x0B
105 #define TVP3026_CURPOSXL 0x0C
106 #define TVP3026_CURPOSXH 0x0D
107 #define TVP3026_CURPOSYL 0x0E
108 #define TVP3026_CURPOSYH 0x0F
109
110 #define TVP3026_XSILICONREV 0x01
111 #define TVP3026_XCURCTRL 0x06
112 #define TVP3026_XCURCTRL_DIS 0x00 /* transparent, transparent, transparent, transparent */
113 #define TVP3026_XCURCTRL_3COLOR 0x01 /* transparent, 0, 1, 2 */
114 #define TVP3026_XCURCTRL_XGA 0x02 /* 0, 1, transparent, complement */
115 #define TVP3026_XCURCTRL_XWIN 0x03 /* transparent, transparent, 0, 1 */
116 #define TVP3026_XCURCTRL_BLANK2048 0x00
117 #define TVP3026_XCURCTRL_BLANK4096 0x10
118 #define TVP3026_XCURCTRL_INTERLACED 0x20
119 #define TVP3026_XCURCTRL_ODD 0x00 /* ext.signal ODD/\EVEN */
120 #define TVP3026_XCURCTRL_EVEN 0x40 /* ext.signal EVEN/\ODD */
121 #define TVP3026_XCURCTRL_INDIRECT 0x00
122 #define TVP3026_XCURCTRL_DIRECT 0x80
123 #define TVP3026_XLATCHCTRL 0x0F
124 #define TVP3026_XLATCHCTRL_1_1 0x06
125 #define TVP3026_XLATCHCTRL_2_1 0x07
126 #define TVP3026_XLATCHCTRL_4_1 0x06
127 #define TVP3026_XLATCHCTRL_8_1 0x06
128 #define TVP3026_XLATCHCTRL_16_1 0x06
129 #define TVP3026A_XLATCHCTRL_4_3 0x06 /* ??? do not understand... but it works... !!! */
130 #define TVP3026A_XLATCHCTRL_8_3 0x07
131 #define TVP3026B_XLATCHCTRL_4_3 0x08
132 #define TVP3026B_XLATCHCTRL_8_3 0x06 /* ??? do not understand... but it works... !!! */
133 #define TVP3026_XTRUECOLORCTRL 0x18
134 #define TVP3026_XTRUECOLORCTRL_VRAM_SHIFT_ACCEL 0x00
135 #define TVP3026_XTRUECOLORCTRL_VRAM_SHIFT_TVP 0x20
136 #define TVP3026_XTRUECOLORCTRL_PSEUDOCOLOR 0x80
137 #define TVP3026_XTRUECOLORCTRL_TRUECOLOR 0x40 /* paletized */
138 #define TVP3026_XTRUECOLORCTRL_DIRECTCOLOR 0x00
139 #define TVP3026_XTRUECOLORCTRL_24_ALTERNATE 0x08 /* 5:4/5:2 instead of 4:3/8:3 */
140 #define TVP3026_XTRUECOLORCTRL_RGB_888 0x16 /* 4:3/8:3 (or 5:4/5:2) */
141 #define TVP3026_XTRUECOLORCTRL_BGR_888 0x17
142 #define TVP3026_XTRUECOLORCTRL_ORGB_8888 0x06
143 #define TVP3026_XTRUECOLORCTRL_BGRO_8888 0x07
144 #define TVP3026_XTRUECOLORCTRL_RGB_565 0x05
145 #define TVP3026_XTRUECOLORCTRL_ORGB_1555 0x04
146 #define TVP3026_XTRUECOLORCTRL_RGB_664 0x03
147 #define TVP3026_XTRUECOLORCTRL_RGBO_4444 0x01
148 #define TVP3026_XMUXCTRL 0x19
149 #define TVP3026_XMUXCTRL_MEMORY_8BIT 0x01 /* - */
150 #define TVP3026_XMUXCTRL_MEMORY_16BIT 0x02 /* - */
151 #define TVP3026_XMUXCTRL_MEMORY_32BIT 0x03 /* 2MB RAM, 512K * 4 */
152 #define TVP3026_XMUXCTRL_MEMORY_64BIT 0x04 /* >2MB RAM, 512K * 8 & more */
153 #define TVP3026_XMUXCTRL_PIXEL_4BIT 0x40 /* L0,H0,L1,H1... */
154 #define TVP3026_XMUXCTRL_PIXEL_4BIT_SWAPPED 0x60 /* H0,L0,H1,L1... */
155 #define TVP3026_XMUXCTRL_PIXEL_8BIT 0x48
156 #define TVP3026_XMUXCTRL_PIXEL_16BIT 0x50
157 #define TVP3026_XMUXCTRL_PIXEL_32BIT 0x58
158 #define TVP3026_XMUXCTRL_VGA 0x98 /* VGA MEMORY, 8BIT PIXEL */
159 #define TVP3026_XCLKCTRL 0x1A
160 #define TVP3026_XCLKCTRL_DIV1 0x00
161 #define TVP3026_XCLKCTRL_DIV2 0x10
162 #define TVP3026_XCLKCTRL_DIV4 0x20
163 #define TVP3026_XCLKCTRL_DIV8 0x30
164 #define TVP3026_XCLKCTRL_DIV16 0x40
165 #define TVP3026_XCLKCTRL_DIV32 0x50
166 #define TVP3026_XCLKCTRL_DIV64 0x60
167 #define TVP3026_XCLKCTRL_CLKSTOPPED 0x70
168 #define TVP3026_XCLKCTRL_SRC_CLK0 0x00
169 #define TVP3026_XCLKCTRL_SRC_CLK1 0x01
170 #define TVP3026_XCLKCTRL_SRC_CLK2 0x02 /* CLK2 is TTL source*/
171 #define TVP3026_XCLKCTRL_SRC_NCLK2 0x03 /* not CLK2 is TTL source */
172 #define TVP3026_XCLKCTRL_SRC_ECLK2 0x04 /* CLK2 and not CLK2 is ECL source */
173 #define TVP3026_XCLKCTRL_SRC_PLL 0x05
174 #define TVP3026_XCLKCTRL_SRC_DIS 0x06 /* disable & poweroff internal clock */
175 #define TVP3026_XCLKCTRL_SRC_CLK0VGA 0x07
176 #define TVP3026_XPALETTEPAGE 0x1C
177 #define TVP3026_XGENCTRL 0x1D
178 #define TVP3026_XGENCTRL_HSYNC_POS 0x00
179 #define TVP3026_XGENCTRL_HSYNC_NEG 0x01
180 #define TVP3026_XGENCTRL_VSYNC_POS 0x00
181 #define TVP3026_XGENCTRL_VSYNC_NEG 0x02
182 #define TVP3026_XGENCTRL_LITTLE_ENDIAN 0x00
183 #define TVP3026_XGENCTRL_BIG_ENDIAN 0x08
184 #define TVP3026_XGENCTRL_BLACK_0IRE 0x00
185 #define TVP3026_XGENCTRL_BLACK_75IRE 0x10
186 #define TVP3026_XGENCTRL_NO_SYNC_ON_GREEN 0x00
187 #define TVP3026_XGENCTRL_SYNC_ON_GREEN 0x20
188 #define TVP3026_XGENCTRL_OVERSCAN_DIS 0x00
189 #define TVP3026_XGENCTRL_OVERSCAN_EN 0x40
190 #define TVP3026_XMISCCTRL 0x1E
191 #define TVP3026_XMISCCTRL_DAC_PUP 0x00
192 #define TVP3026_XMISCCTRL_DAC_PDOWN 0x01
193 #define TVP3026_XMISCCTRL_DAC_EXT 0x00 /* or 8, bit 3 is ignored */
194 #define TVP3026_XMISCCTRL_DAC_6BIT 0x04
195 #define TVP3026_XMISCCTRL_DAC_8BIT 0x0C
196 #define TVP3026_XMISCCTRL_PSEL_DIS 0x00
197 #define TVP3026_XMISCCTRL_PSEL_EN 0x10
198 #define TVP3026_XMISCCTRL_PSEL_LOW 0x00 /* PSEL high selects directcolor */
199 #define TVP3026_XMISCCTRL_PSEL_HIGH 0x20 /* PSEL high selects truecolor or pseudocolor */
200 #define TVP3026_XGENIOCTRL 0x2A
201 #define TVP3026_XGENIODATA 0x2B
202 #define TVP3026_XPLLADDR 0x2C
203 #define TVP3026_XPLLADDR_X(LOOP,MCLK,PIX) (((LOOP)<<4) | ((MCLK)<<2) | (PIX))
204 #define TVP3026_XPLLDATA_N 0x00
205 #define TVP3026_XPLLDATA_M 0x01
206 #define TVP3026_XPLLDATA_P 0x02
207 #define TVP3026_XPLLDATA_STAT 0x03
208 #define TVP3026_XPIXPLLDATA 0x2D
209 #define TVP3026_XMEMPLLDATA 0x2E
210 #define TVP3026_XLOOPPLLDATA 0x2F
211 #define TVP3026_XCOLKEYOVRMIN 0x30
212 #define TVP3026_XCOLKEYOVRMAX 0x31
213 #define TVP3026_XCOLKEYREDMIN 0x32
214 #define TVP3026_XCOLKEYREDMAX 0x33
215 #define TVP3026_XCOLKEYGREENMIN 0x34
216 #define TVP3026_XCOLKEYGREENMAX 0x35
217 #define TVP3026_XCOLKEYBLUEMIN 0x36
218 #define TVP3026_XCOLKEYBLUEMAX 0x37
219 #define TVP3026_XCOLKEYCTRL 0x38
220 #define TVP3026_XCOLKEYCTRL_OVR_EN 0x01
221 #define TVP3026_XCOLKEYCTRL_RED_EN 0x02
222 #define TVP3026_XCOLKEYCTRL_GREEN_EN 0x04
223 #define TVP3026_XCOLKEYCTRL_BLUE_EN 0x08
224 #define TVP3026_XCOLKEYCTRL_NEGATE 0x10
225 #define TVP3026_XCOLKEYCTRL_ZOOM1 0x00
226 #define TVP3026_XCOLKEYCTRL_ZOOM2 0x20
227 #define TVP3026_XCOLKEYCTRL_ZOOM4 0x40
228 #define TVP3026_XCOLKEYCTRL_ZOOM8 0x60
229 #define TVP3026_XCOLKEYCTRL_ZOOM16 0x80
230 #define TVP3026_XCOLKEYCTRL_ZOOM32 0xA0
231 #define TVP3026_XMEMPLLCTRL 0x39
232 #define TVP3026_XMEMPLLCTRL_DIV(X) (((X)-1)>>1) /* 2,4,6,8,10,12,14,16, division applied to LOOP PLL after divide by 2^P */
233 #define TVP3026_XMEMPLLCTRL_STROBEMKC4 0x08
234 #define TVP3026_XMEMPLLCTRL_MCLK_DOTCLOCK 0x00 /* MKC4 */
235 #define TVP3026_XMEMPLLCTRL_MCLK_MCLKPLL 0x10 /* MKC4 */
236 #define TVP3026_XMEMPLLCTRL_RCLK_PIXPLL 0x00
237 #define TVP3026_XMEMPLLCTRL_RCLK_LOOPPLL 0x20
238 #define TVP3026_XMEMPLLCTRL_RCLK_DOTDIVN 0x40 /* dot clock divided by loop pclk N prescaler */
239 #define TVP3026_XSENSETEST 0x3A
240 #define TVP3026_XTESTMODEDATA 0x3B
241 #define TVP3026_XCRCREML 0x3C
242 #define TVP3026_XCRCREMH 0x3D
243 #define TVP3026_XCRCBITSEL 0x3E
244 #define TVP3026_XID 0x3F
245
246 static const unsigned char DACseq[] =
247 { TVP3026_XLATCHCTRL, TVP3026_XTRUECOLORCTRL,
248 TVP3026_XMUXCTRL, TVP3026_XCLKCTRL,
249 TVP3026_XPALETTEPAGE,
250 TVP3026_XGENCTRL,
251 TVP3026_XMISCCTRL,
252 TVP3026_XGENIOCTRL,
253 TVP3026_XGENIODATA,
254 TVP3026_XCOLKEYOVRMIN, TVP3026_XCOLKEYOVRMAX, TVP3026_XCOLKEYREDMIN, TVP3026_XCOLKEYREDMAX,
255 TVP3026_XCOLKEYGREENMIN, TVP3026_XCOLKEYGREENMAX, TVP3026_XCOLKEYBLUEMIN, TVP3026_XCOLKEYBLUEMAX,
256 TVP3026_XCOLKEYCTRL,
257 TVP3026_XMEMPLLCTRL, TVP3026_XSENSETEST, TVP3026_XCURCTRL };
258
259 #define POS3026_XLATCHCTRL 0
260 #define POS3026_XTRUECOLORCTRL 1
261 #define POS3026_XMUXCTRL 2
262 #define POS3026_XCLKCTRL 3
263 #define POS3026_XGENCTRL 5
264 #define POS3026_XMISCCTRL 6
265 #define POS3026_XMEMPLLCTRL 18
266 #define POS3026_XCURCTRL 20
267
268 static const unsigned char MGADACbpp32[] =
269 { TVP3026_XLATCHCTRL_2_1, TVP3026_XTRUECOLORCTRL_DIRECTCOLOR | TVP3026_XTRUECOLORCTRL_ORGB_8888,
270 0x00, TVP3026_XCLKCTRL_DIV1 | TVP3026_XCLKCTRL_SRC_PLL,
271 0x00,
272 TVP3026_XGENCTRL_HSYNC_POS | TVP3026_XGENCTRL_VSYNC_POS | TVP3026_XGENCTRL_LITTLE_ENDIAN | TVP3026_XGENCTRL_BLACK_0IRE | TVP3026_XGENCTRL_NO_SYNC_ON_GREEN | TVP3026_XGENCTRL_OVERSCAN_DIS,
273 TVP3026_XMISCCTRL_DAC_PUP | TVP3026_XMISCCTRL_DAC_8BIT | TVP3026_XMISCCTRL_PSEL_DIS | TVP3026_XMISCCTRL_PSEL_HIGH,
274 0x00,
275 0x1E,
276 0xFF, 0xFF, 0xFF, 0xFF,
277 0xFF, 0xFF, 0xFF, 0xFF,
278 TVP3026_XCOLKEYCTRL_ZOOM1,
279 0x00, 0x00, TVP3026_XCURCTRL_DIS };
280
281 static void matroxfb_ti3026_flashcursor(unsigned long ptr) {
282 #define minfo ((struct matrox_fb_info*)ptr)
283 matroxfb_DAC_lock();
284 outTi3026(PMINFO TVP3026_XCURCTRL, inTi3026(PMINFO TVP3026_XCURCTRL) ^ TVP3026_XCURCTRL_DIS ^ TVP3026_XCURCTRL_XGA);
285 ACCESS_FBINFO(cursor.timer.expires) = jiffies + HZ/2;
286 add_timer(&ACCESS_FBINFO(cursor.timer));
287 matroxfb_DAC_unlock();
288 #undef minfo
289 }
290
291 static void matroxfb_ti3026_createcursor(WPMINFO struct display* p) {
292 unsigned long flags;
293 u_int32_t xline;
294 unsigned int i;
295 unsigned int to;
296
297 if (ACCESS_FBINFO(currcon_display) != p)
298 return;
299
300 DBG("matroxfb_ti3026_createcursor");
301
302 matroxfb_createcursorshape(PMINFO p, p->var.vmode);
303
304 xline = (~0) << (32 - ACCESS_FBINFO(cursor.w));
305 matroxfb_DAC_lock_irqsave(flags);
306 mga_outb(M_RAMDAC_BASE+TVP3026_INDEX, 0);
307 to = ACCESS_FBINFO(cursor.u);
308 for (i = 0; i < to; i++) {
309 mga_outb(M_RAMDAC_BASE+TVP3026_CURRAMDATA, 0);
310 mga_outb(M_RAMDAC_BASE+TVP3026_CURRAMDATA, 0);
311 mga_outb(M_RAMDAC_BASE+TVP3026_CURRAMDATA, 0);
312 mga_outb(M_RAMDAC_BASE+TVP3026_CURRAMDATA, 0);
313 mga_outb(M_RAMDAC_BASE+TVP3026_CURRAMDATA, 0);
314 mga_outb(M_RAMDAC_BASE+TVP3026_CURRAMDATA, 0);
315 mga_outb(M_RAMDAC_BASE+TVP3026_CURRAMDATA, 0);
316 mga_outb(M_RAMDAC_BASE+TVP3026_CURRAMDATA, 0);
317 }
318 to = ACCESS_FBINFO(cursor.d);
319 for (; i < to; i++) {
320 mga_outb(M_RAMDAC_BASE+TVP3026_CURRAMDATA, xline >> 24);
321 mga_outb(M_RAMDAC_BASE+TVP3026_CURRAMDATA, xline >> 16);
322 mga_outb(M_RAMDAC_BASE+TVP3026_CURRAMDATA, xline >> 8);
323 mga_outb(M_RAMDAC_BASE+TVP3026_CURRAMDATA, xline);
324 mga_outb(M_RAMDAC_BASE+TVP3026_CURRAMDATA, 0);
325 mga_outb(M_RAMDAC_BASE+TVP3026_CURRAMDATA, 0);
326 mga_outb(M_RAMDAC_BASE+TVP3026_CURRAMDATA, 0);
327 mga_outb(M_RAMDAC_BASE+TVP3026_CURRAMDATA, 0);
328 }
329 for (; i < 64; i++) {
330 mga_outb(M_RAMDAC_BASE+TVP3026_CURRAMDATA, 0);
331 mga_outb(M_RAMDAC_BASE+TVP3026_CURRAMDATA, 0);
332 mga_outb(M_RAMDAC_BASE+TVP3026_CURRAMDATA, 0);
333 mga_outb(M_RAMDAC_BASE+TVP3026_CURRAMDATA, 0);
334 mga_outb(M_RAMDAC_BASE+TVP3026_CURRAMDATA, 0);
335 mga_outb(M_RAMDAC_BASE+TVP3026_CURRAMDATA, 0);
336 mga_outb(M_RAMDAC_BASE+TVP3026_CURRAMDATA, 0);
337 mga_outb(M_RAMDAC_BASE+TVP3026_CURRAMDATA, 0);
338 }
339 for (i = 0; i < 512; i++)
340 mga_outb(M_RAMDAC_BASE+TVP3026_CURRAMDATA, 0xFF);
341 matroxfb_DAC_unlock_irqrestore(flags);
342 }
343
344 static void matroxfb_ti3026_cursor(struct display* p, int mode, int x, int y) {
345 unsigned long flags;
346 MINFO_FROM_DISP(p);
347
348 DBG("matroxfb_ti3026_cursor")
349
350 if (ACCESS_FBINFO(currcon_display) != p)
351 return;
352
353 if (mode == CM_ERASE) {
354 if (ACCESS_FBINFO(cursor.state) != CM_ERASE) {
355 del_timer_sync(&ACCESS_FBINFO(cursor.timer));
356 matroxfb_DAC_lock_irqsave(flags);
357 ACCESS_FBINFO(cursor.state) = CM_ERASE;
358 outTi3026(PMINFO TVP3026_XCURCTRL, ACCESS_FBINFO(currenthw->DACreg[POS3026_XCURCTRL]));
359 matroxfb_DAC_unlock_irqrestore(flags);
360 }
361 return;
362 }
363 if ((p->conp->vc_cursor_type & CUR_HWMASK) != ACCESS_FBINFO(cursor.type))
364 matroxfb_ti3026_createcursor(PMINFO p);
365 x *= fontwidth(p);
366 y *= fontheight(p);
367 y -= p->var.yoffset;
368 if (p->var.vmode & FB_VMODE_DOUBLE)
369 y *= 2;
370 del_timer_sync(&ACCESS_FBINFO(cursor.timer));
371 matroxfb_DAC_lock_irqsave(flags);
372 if ((x != ACCESS_FBINFO(cursor.x)) || (y != ACCESS_FBINFO(cursor.y)) || ACCESS_FBINFO(cursor.redraw)) {
373 ACCESS_FBINFO(cursor.redraw) = 0;
374 ACCESS_FBINFO(cursor.x) = x;
375 ACCESS_FBINFO(cursor.y) = y;
376 x += 64;
377 y += 64;
378 outTi3026(PMINFO TVP3026_XCURCTRL, ACCESS_FBINFO(currenthw->DACreg[POS3026_XCURCTRL]));
379 mga_outb(M_RAMDAC_BASE+TVP3026_CURPOSXL, x);
380 mga_outb(M_RAMDAC_BASE+TVP3026_CURPOSXH, x >> 8);
381 mga_outb(M_RAMDAC_BASE+TVP3026_CURPOSYL, y);
382 mga_outb(M_RAMDAC_BASE+TVP3026_CURPOSYH, y >> 8);
383 }
384 ACCESS_FBINFO(cursor.state) = CM_DRAW;
385 if (ACCESS_FBINFO(devflags.blink))
386 mod_timer(&ACCESS_FBINFO(cursor.timer), jiffies + HZ/2);
387 outTi3026(PMINFO TVP3026_XCURCTRL, ACCESS_FBINFO(currenthw->DACreg[POS3026_XCURCTRL]) | TVP3026_XCURCTRL_XGA);
388 matroxfb_DAC_unlock_irqrestore(flags);
389 }
390
391 static int matroxfb_ti3026_setfont(struct display* p, int width, int height) {
392
393 DBG("matrox_ti3026_setfont");
394
395 if (p && p->conp)
396 matroxfb_ti3026_createcursor(PMXINFO(p) p);
397 return 0;
398 }
399
400 static int matroxfb_ti3026_selhwcursor(WPMINFO struct display* p) {
401 ACCESS_FBINFO(dispsw.cursor) = matroxfb_ti3026_cursor;
402 ACCESS_FBINFO(dispsw.set_font) = matroxfb_ti3026_setfont;
403 return 0;
404 }
405
406 static int Ti3026_calcclock(CPMINFO unsigned int freq, unsigned int fmax, int* in, int* feed, int* post) {
407 unsigned int fvco;
408 unsigned int lin, lfeed, lpost;
409
410 DBG("Ti3026_calcclock")
411
412 fvco = PLL_calcclock(PMINFO freq, fmax, &lin, &lfeed, &lpost);
413 fvco >>= (*post = lpost);
414 *in = 64 - lin;
415 *feed = 64 - lfeed;
416 return fvco;
417 }
418
419 static int Ti3026_setpclk(CPMINFO struct matrox_hw_state* hw, int clk, struct display* p) {
420 unsigned int f_pll;
421 unsigned int pixfeed, pixin, pixpost;
422
423 DBG("Ti3026_setpclk")
424
425 f_pll = Ti3026_calcclock(PMINFO clk, ACCESS_FBINFO(max_pixel_clock), &pixin, &pixfeed, &pixpost);
426
427 hw->DACclk[0] = pixin | 0xC0;
428 hw->DACclk[1] = pixfeed;
429 hw->DACclk[2] = pixpost | 0xB0;
430
431 if (p->type == FB_TYPE_TEXT) {
432 hw->DACreg[POS3026_XMEMPLLCTRL] = TVP3026_XMEMPLLCTRL_MCLK_MCLKPLL | TVP3026_XMEMPLLCTRL_RCLK_PIXPLL;
433 hw->DACclk[3] = 0xFD;
434 hw->DACclk[4] = 0x3D;
435 hw->DACclk[5] = 0x70;
436 } else {
437 unsigned int loopfeed, loopin, looppost, loopdiv, z;
438 unsigned int Bpp;
439
440 Bpp = ACCESS_FBINFO(curr.final_bppShift);
441
442 if (p->var.bits_per_pixel == 24) {
443 loopfeed = 3; /* set lm to any possible value */
444 loopin = 3 * 32 / Bpp;
445 } else {
446 loopfeed = 4;
447 loopin = 4 * 32 / Bpp;
448 }
449 z = (110000 * loopin) / (f_pll * loopfeed);
450 loopdiv = 0; /* div 2 */
451 if (z < 2)
452 looppost = 0;
453 else if (z < 4)
454 looppost = 1;
455 else if (z < 8)
456 looppost = 2;
457 else {
458 looppost = 3;
459 loopdiv = z/16;
460 }
461 if (p->var.bits_per_pixel == 24) {
462 hw->DACclk[3] = ((65 - loopin) & 0x3F) | 0xC0;
463 hw->DACclk[4] = (65 - loopfeed) | 0x80;
464 if (ACCESS_FBINFO(accel.ramdac_rev) > 0x20) {
465 if (isInterleave(MINFO))
466 hw->DACreg[POS3026_XLATCHCTRL] = TVP3026B_XLATCHCTRL_8_3;
467 else {
468 hw->DACclk[4] &= ~0xC0;
469 hw->DACreg[POS3026_XLATCHCTRL] = TVP3026B_XLATCHCTRL_4_3;
470 }
471 } else {
472 if (isInterleave(MINFO))
473 ; /* default... */
474 else {
475 hw->DACclk[4] ^= 0xC0; /* change from 0x80 to 0x40 */
476 hw->DACreg[POS3026_XLATCHCTRL] = TVP3026A_XLATCHCTRL_4_3;
477 }
478 }
479 hw->DACclk[5] = looppost | 0xF8;
480 if (ACCESS_FBINFO(devflags.mga_24bpp_fix))
481 hw->DACclk[5] ^= 0x40;
482 } else {
483 hw->DACclk[3] = ((65 - loopin) & 0x3F) | 0xC0;
484 hw->DACclk[4] = 65 - loopfeed;
485 hw->DACclk[5] = looppost | 0xF0;
486 }
487 hw->DACreg[POS3026_XMEMPLLCTRL] = loopdiv | TVP3026_XMEMPLLCTRL_MCLK_MCLKPLL | TVP3026_XMEMPLLCTRL_RCLK_LOOPPLL;
488 }
489 return 0;
490 }
491
492 static int Ti3026_init(CPMINFO struct matrox_hw_state* hw, struct my_timming* m, struct display* p) {
493 u_int8_t muxctrl = isInterleave(MINFO) ? TVP3026_XMUXCTRL_MEMORY_64BIT : TVP3026_XMUXCTRL_MEMORY_32BIT;
494
495 DBG("Ti3026_init")
496
497 memcpy(hw->DACreg, MGADACbpp32, sizeof(hw->DACreg));
498 if (p->type == FB_TYPE_TEXT) {
499 hw->DACreg[POS3026_XLATCHCTRL] = TVP3026_XLATCHCTRL_8_1;
500 hw->DACreg[POS3026_XTRUECOLORCTRL] = TVP3026_XTRUECOLORCTRL_PSEUDOCOLOR;
501 hw->DACreg[POS3026_XMUXCTRL] = TVP3026_XMUXCTRL_VGA;
502 hw->DACreg[POS3026_XCLKCTRL] = TVP3026_XCLKCTRL_SRC_PLL |
503 TVP3026_XCLKCTRL_DIV4;
504 hw->DACreg[POS3026_XMISCCTRL] = TVP3026_XMISCCTRL_DAC_PUP | TVP3026_XMISCCTRL_DAC_6BIT | TVP3026_XMISCCTRL_PSEL_DIS | TVP3026_XMISCCTRL_PSEL_LOW;
505 } else {
506 switch (p->var.bits_per_pixel) {
507 case 4: hw->DACreg[POS3026_XLATCHCTRL] = TVP3026_XLATCHCTRL_16_1; /* or _8_1, they are same */
508 hw->DACreg[POS3026_XTRUECOLORCTRL] = TVP3026_XTRUECOLORCTRL_PSEUDOCOLOR;
509 hw->DACreg[POS3026_XMUXCTRL] = muxctrl | TVP3026_XMUXCTRL_PIXEL_4BIT;
510 hw->DACreg[POS3026_XCLKCTRL] = TVP3026_XCLKCTRL_SRC_PLL | TVP3026_XCLKCTRL_DIV8;
511 hw->DACreg[POS3026_XMISCCTRL] = TVP3026_XMISCCTRL_DAC_PUP | TVP3026_XMISCCTRL_DAC_8BIT | TVP3026_XMISCCTRL_PSEL_DIS | TVP3026_XMISCCTRL_PSEL_LOW;
512 break;
513 case 8: hw->DACreg[POS3026_XLATCHCTRL] = TVP3026_XLATCHCTRL_8_1; /* or _4_1, they are same */
514 hw->DACreg[POS3026_XTRUECOLORCTRL] = TVP3026_XTRUECOLORCTRL_PSEUDOCOLOR;
515 hw->DACreg[POS3026_XMUXCTRL] = muxctrl | TVP3026_XMUXCTRL_PIXEL_8BIT;
516 hw->DACreg[POS3026_XCLKCTRL] = TVP3026_XCLKCTRL_SRC_PLL | TVP3026_XCLKCTRL_DIV4;
517 hw->DACreg[POS3026_XMISCCTRL] = TVP3026_XMISCCTRL_DAC_PUP | TVP3026_XMISCCTRL_DAC_8BIT | TVP3026_XMISCCTRL_PSEL_DIS | TVP3026_XMISCCTRL_PSEL_LOW;
518 break;
519 case 16:
520 /* XLATCHCTRL should be _4_1 / _2_1... Why is not? (_2_1 is used everytime) */
521 hw->DACreg[POS3026_XTRUECOLORCTRL] = (p->var.green.length == 5)? (TVP3026_XTRUECOLORCTRL_DIRECTCOLOR | TVP3026_XTRUECOLORCTRL_ORGB_1555 ) : (TVP3026_XTRUECOLORCTRL_DIRECTCOLOR | TVP3026_XTRUECOLORCTRL_RGB_565);
522 hw->DACreg[POS3026_XMUXCTRL] = muxctrl | TVP3026_XMUXCTRL_PIXEL_16BIT;
523 hw->DACreg[POS3026_XCLKCTRL] = TVP3026_XCLKCTRL_SRC_PLL | TVP3026_XCLKCTRL_DIV2;
524 break;
525 case 24:
526 /* XLATCHCTRL is: for (A) use _4_3 (?_8_3 is same? TBD), for (B) it is set in setpclk */
527 hw->DACreg[POS3026_XTRUECOLORCTRL] = TVP3026_XTRUECOLORCTRL_DIRECTCOLOR | TVP3026_XTRUECOLORCTRL_RGB_888;
528 hw->DACreg[POS3026_XMUXCTRL] = muxctrl | TVP3026_XMUXCTRL_PIXEL_32BIT;
529 hw->DACreg[POS3026_XCLKCTRL] = TVP3026_XCLKCTRL_SRC_PLL | TVP3026_XCLKCTRL_DIV4;
530 break;
531 case 32:
532 /* XLATCHCTRL should be _2_1 / _1_1... Why is not? (_2_1 is used everytime) */
533 hw->DACreg[POS3026_XMUXCTRL] = muxctrl | TVP3026_XMUXCTRL_PIXEL_32BIT;
534 break;
535 default:
536 return 1; /* TODO: failed */
537 }
538 }
539 if (matroxfb_vgaHWinit(PMINFO hw, m, p)) return 1;
540
541 /* set SYNC */
542 hw->MiscOutReg = 0xCB;
543 if (m->sync & FB_SYNC_HOR_HIGH_ACT)
544 hw->DACreg[POS3026_XGENCTRL] |= TVP3026_XGENCTRL_HSYNC_NEG;
545 if (m->sync & FB_SYNC_VERT_HIGH_ACT)
546 hw->DACreg[POS3026_XGENCTRL] |= TVP3026_XGENCTRL_VSYNC_NEG;
547 if (m->sync & FB_SYNC_ON_GREEN)
548 hw->DACreg[POS3026_XGENCTRL] |= TVP3026_XGENCTRL_SYNC_ON_GREEN;
549
550 /* set DELAY */
551 if (ACCESS_FBINFO(video.len) < 0x400000)
552 hw->CRTCEXT[3] |= 0x08;
553 else if (ACCESS_FBINFO(video.len) > 0x400000)
554 hw->CRTCEXT[3] |= 0x10;
555
556 /* set HWCURSOR */
557 if (m->interlaced) {
558 hw->DACreg[POS3026_XCURCTRL] |= TVP3026_XCURCTRL_INTERLACED;
559 }
560 if (m->HTotal >= 1536)
561 hw->DACreg[POS3026_XCURCTRL] |= TVP3026_XCURCTRL_BLANK4096;
562
563 /* set interleaving */
564 hw->MXoptionReg &= ~0x00001000;
565 if ((p->type != FB_TYPE_TEXT) && isInterleave(MINFO)) hw->MXoptionReg |= 0x00001000;
566
567 /* set DAC */
568 Ti3026_setpclk(PMINFO hw, m->pixclock, p);
569 return 0;
570 }
571
572 static void ti3026_setMCLK(CPMINFO struct matrox_hw_state* hw, int fout){
573 unsigned int f_pll;
574 unsigned int pclk_m, pclk_n, pclk_p;
575 unsigned int mclk_m, mclk_n, mclk_p;
576 unsigned int rfhcnt, mclk_ctl;
577 int tmout;
578
579 DBG("ti3026_setMCLK")
580
581 f_pll = Ti3026_calcclock(PMINFO fout, ACCESS_FBINFO(max_pixel_clock), &mclk_n, &mclk_m, &mclk_p);
582
583 /* save pclk */
584 outTi3026(PMINFO TVP3026_XPLLADDR, 0xFC);
585 pclk_n = inTi3026(PMINFO TVP3026_XPIXPLLDATA);
586 outTi3026(PMINFO TVP3026_XPLLADDR, 0xFD);
587 pclk_m = inTi3026(PMINFO TVP3026_XPIXPLLDATA);
588 outTi3026(PMINFO TVP3026_XPLLADDR, 0xFE);
589 pclk_p = inTi3026(PMINFO TVP3026_XPIXPLLDATA);
590
591 /* stop pclk */
592 outTi3026(PMINFO TVP3026_XPLLADDR, 0xFE);
593 outTi3026(PMINFO TVP3026_XPIXPLLDATA, 0x00);
594
595 /* set pclk to new mclk */
596 outTi3026(PMINFO TVP3026_XPLLADDR, 0xFC);
597 outTi3026(PMINFO TVP3026_XPIXPLLDATA, mclk_n | 0xC0);
598 outTi3026(PMINFO TVP3026_XPIXPLLDATA, mclk_m);
599 outTi3026(PMINFO TVP3026_XPIXPLLDATA, mclk_p | 0xB0);
600
601 /* wait for PLL to lock */
602 for (tmout = 500000; tmout; tmout--) {
603 if (inTi3026(PMINFO TVP3026_XPIXPLLDATA) & 0x40)
604 break;
605 udelay(10);
606 };
607 if (!tmout)
608 printk(KERN_ERR "matroxfb: Temporary pixel PLL not locked after 5 secs\n");
609
610 /* output pclk on mclk pin */
611 mclk_ctl = inTi3026(PMINFO TVP3026_XMEMPLLCTRL);
612 outTi3026(PMINFO TVP3026_XMEMPLLCTRL, mclk_ctl & 0xE7);
613 outTi3026(PMINFO TVP3026_XMEMPLLCTRL, (mclk_ctl & 0xE7) | TVP3026_XMEMPLLCTRL_STROBEMKC4);
614
615 /* stop MCLK */
616 outTi3026(PMINFO TVP3026_XPLLADDR, 0xFB);
617 outTi3026(PMINFO TVP3026_XMEMPLLDATA, 0x00);
618
619 /* set mclk to new freq */
620 outTi3026(PMINFO TVP3026_XPLLADDR, 0xF3);
621 outTi3026(PMINFO TVP3026_XMEMPLLDATA, mclk_n | 0xC0);
622 outTi3026(PMINFO TVP3026_XMEMPLLDATA, mclk_m);
623 outTi3026(PMINFO TVP3026_XMEMPLLDATA, mclk_p | 0xB0);
624
625 /* wait for PLL to lock */
626 for (tmout = 500000; tmout; tmout--) {
627 if (inTi3026(PMINFO TVP3026_XMEMPLLDATA) & 0x40)
628 break;
629 udelay(10);
630 }
631 if (!tmout)
632 printk(KERN_ERR "matroxfb: Memory PLL not locked after 5 secs\n");
633
634 f_pll = f_pll * 333 / (10000 << mclk_p);
635 if (isMilleniumII(MINFO)) {
636 rfhcnt = (f_pll - 128) / 256;
637 if (rfhcnt > 15)
638 rfhcnt = 15;
639 } else {
640 rfhcnt = (f_pll - 64) / 128;
641 if (rfhcnt > 15)
642 rfhcnt = 0;
643 }
644 hw->MXoptionReg = (hw->MXoptionReg & ~0x000F0000) | (rfhcnt << 16);
645 pci_write_config_dword(ACCESS_FBINFO(pcidev), PCI_OPTION_REG, hw->MXoptionReg);
646
647 /* output MCLK to MCLK pin */
648 outTi3026(PMINFO TVP3026_XMEMPLLCTRL, (mclk_ctl & 0xE7) | TVP3026_XMEMPLLCTRL_MCLK_MCLKPLL);
649 outTi3026(PMINFO TVP3026_XMEMPLLCTRL, (mclk_ctl ) | TVP3026_XMEMPLLCTRL_MCLK_MCLKPLL | TVP3026_XMEMPLLCTRL_STROBEMKC4);
650
651 /* stop PCLK */
652 outTi3026(PMINFO TVP3026_XPLLADDR, 0xFE);
653 outTi3026(PMINFO TVP3026_XPIXPLLDATA, 0x00);
654
655 /* restore pclk */
656 outTi3026(PMINFO TVP3026_XPLLADDR, 0xFC);
657 outTi3026(PMINFO TVP3026_XPIXPLLDATA, pclk_n);
658 outTi3026(PMINFO TVP3026_XPIXPLLDATA, pclk_m);
659 outTi3026(PMINFO TVP3026_XPIXPLLDATA, pclk_p);
660
661 /* wait for PLL to lock */
662 for (tmout = 500000; tmout; tmout--) {
663 if (inTi3026(PMINFO TVP3026_XPIXPLLDATA) & 0x40)
664 break;
665 udelay(10);
666 }
667 if (!tmout)
668 printk(KERN_ERR "matroxfb: Pixel PLL not locked after 5 secs\n");
669 }
670
671 static void ti3026_ramdac_init(WPMINFO struct matrox_hw_state* hw){
672
673 DBG("ti3026_ramdac_init")
674
675 ACCESS_FBINFO(features.pll.vco_freq_min) = 110000;
676 ACCESS_FBINFO(features.pll.ref_freq) = 114545;
677 ACCESS_FBINFO(features.pll.feed_div_min) = 2;
678 ACCESS_FBINFO(features.pll.feed_div_max) = 24;
679 ACCESS_FBINFO(features.pll.in_div_min) = 2;
680 ACCESS_FBINFO(features.pll.in_div_max) = 63;
681 ACCESS_FBINFO(features.pll.post_shift_max) = 3;
682 if (ACCESS_FBINFO(devflags.noinit))
683 return;
684 ti3026_setMCLK(PMINFO hw, 60000);
685 }
686
687 static void Ti3026_restore(WPMINFO struct matrox_hw_state* hw, struct matrox_hw_state* oldhw, struct display* p) {
688 int i;
689 CRITFLAGS
690
691 DBG("Ti3026_restore")
692
693 #ifdef DEBUG
694 dprintk(KERN_INFO "EXTVGA regs: ");
695 for (i = 0; i < 6; i++)
696 dprintk("%02X:", hw->CRTCEXT[i]);
697 dprintk("\n");
698 #endif
699
700 CRITBEGIN
701
702 pci_write_config_dword(ACCESS_FBINFO(pcidev), PCI_OPTION_REG, hw->MXoptionReg);
703
704 CRITEND
705
706 matroxfb_vgaHWrestore(PMINFO hw, oldhw);
707
708 CRITBEGIN
709
710 for (i = 0; i < 6; i++)
711 mga_setr(M_EXTVGA_INDEX, i, hw->CRTCEXT[i]);
712
713 for (i = 0; i < 21; i++) {
714 outTi3026(PMINFO DACseq[i], hw->DACreg[i]);
715 }
716 if (oldhw) {
717 outTi3026(PMINFO TVP3026_XPLLADDR, 0x00);
718 oldhw->DACclk[0] = inTi3026(PMINFO TVP3026_XPIXPLLDATA);
719 oldhw->DACclk[3] = inTi3026(PMINFO TVP3026_XLOOPPLLDATA);
720 outTi3026(PMINFO TVP3026_XPLLADDR, 0x15);
721 oldhw->DACclk[1] = inTi3026(PMINFO TVP3026_XPIXPLLDATA);
722 oldhw->DACclk[4] = inTi3026(PMINFO TVP3026_XLOOPPLLDATA);
723 outTi3026(PMINFO TVP3026_XPLLADDR, 0x2A);
724 oldhw->DACclk[2] = inTi3026(PMINFO TVP3026_XPIXPLLDATA);
725 oldhw->DACclk[5] = inTi3026(PMINFO TVP3026_XLOOPPLLDATA);
726 }
727 CRITEND
728 if (!oldhw || memcmp(hw->DACclk, oldhw->DACclk, 6)) {
729 /* agrhh... setting up PLL is very slow on Millennium... */
730 /* Mystique PLL is locked in few ms, but Millennium PLL lock takes about 0.15 s... */
731 /* Maybe even we should call schedule() ? */
732
733 CRITBEGIN
734 outTi3026(PMINFO TVP3026_XCLKCTRL, hw->DACreg[POS3026_XCLKCTRL]);
735 outTi3026(PMINFO TVP3026_XPLLADDR, 0x2A);
736 outTi3026(PMINFO TVP3026_XLOOPPLLDATA, 0);
737 outTi3026(PMINFO TVP3026_XPIXPLLDATA, 0);
738
739 outTi3026(PMINFO TVP3026_XPLLADDR, 0x00);
740 for (i = 0; i < 3; i++)
741 outTi3026(PMINFO TVP3026_XPIXPLLDATA, hw->DACclk[i]);
742 /* wait for PLL only if PLL clock requested (always for PowerMode, never for VGA) */
743 if (hw->MiscOutReg & 0x08) {
744 int tmout;
745 outTi3026(PMINFO TVP3026_XPLLADDR, 0x3F);
746 for (tmout = 500000; tmout; --tmout) {
747 if (inTi3026(PMINFO TVP3026_XPIXPLLDATA) & 0x40)
748 break;
749 udelay(10);
750 }
751
752 CRITEND
753
754 if (!tmout)
755 printk(KERN_ERR "matroxfb: Pixel PLL not locked after 5 secs\n");
756 else
757 dprintk(KERN_INFO "PixelPLL: %d\n", 500000-tmout);
758 CRITBEGIN
759 }
760 outTi3026(PMINFO TVP3026_XMEMPLLCTRL, hw->DACreg[POS3026_XMEMPLLCTRL]);
761 outTi3026(PMINFO TVP3026_XPLLADDR, 0x00);
762 for (i = 3; i < 6; i++)
763 outTi3026(PMINFO TVP3026_XLOOPPLLDATA, hw->DACclk[i]);
764 CRITEND
765 if ((hw->MiscOutReg & 0x08) && ((hw->DACclk[5] & 0x80) == 0x80)) {
766 int tmout;
767
768 CRITBEGIN
769 outTi3026(PMINFO TVP3026_XPLLADDR, 0x3F);
770 for (tmout = 500000; tmout; --tmout) {
771 if (inTi3026(PMINFO TVP3026_XLOOPPLLDATA) & 0x40)
772 break;
773 udelay(10);
774 }
775 CRITEND
776 if (!tmout)
777 printk(KERN_ERR "matroxfb: Loop PLL not locked after 5 secs\n");
778 else
779 dprintk(KERN_INFO "LoopPLL: %d\n", 500000-tmout);
780 }
781 }
782 matrox_init_putc(PMINFO p, matroxfb_ti3026_createcursor);
783
784 #ifdef DEBUG
785 dprintk(KERN_DEBUG "3026DACregs ");
786 for (i = 0; i < 21; i++) {
787 dprintk("R%02X=%02X ", DACseq[i], hw->DACreg[i]);
788 if ((i & 0x7) == 0x7) dprintk("\n" KERN_DEBUG "continuing... ");
789 }
790 dprintk("\n" KERN_DEBUG "DACclk ");
791 for (i = 0; i < 6; i++)
792 dprintk("C%02X=%02X ", i, hw->DACclk[i]);
793 dprintk("\n");
794 #endif
795 }
796
797 static void Ti3026_reset(WPMINFO struct matrox_hw_state* hw){
798
799 DBG("Ti3026_reset")
800
801 matroxfb_fastfont_init(MINFO);
802
803 ti3026_ramdac_init(PMINFO hw);
804 }
805
806 static int Ti3026_preinit(WPMINFO struct matrox_hw_state* hw){
807 static const int vxres_mill2[] = { 512, 640, 768, 800, 832, 960,
808 1024, 1152, 1280, 1600, 1664, 1920,
809 2048, 0};
810 static const int vxres_mill1[] = { 640, 768, 800, 960,
811 1024, 1152, 1280, 1600, 1920,
812 2048, 0};
813
814 DBG("Ti3026_preinit")
815
816 ACCESS_FBINFO(millenium) = 1;
817 ACCESS_FBINFO(milleniumII) = (ACCESS_FBINFO(pcidev)->device != PCI_DEVICE_ID_MATROX_MIL);
818 ACCESS_FBINFO(capable.cfb4) = 1;
819 ACCESS_FBINFO(capable.text) = 1; /* isMilleniumII(MINFO); */
820 ACCESS_FBINFO(capable.vxres) = isMilleniumII(MINFO)?vxres_mill2:vxres_mill1;
821 ACCESS_FBINFO(cursor.timer.function) = matroxfb_ti3026_flashcursor;
822
823 if (ACCESS_FBINFO(devflags.noinit))
824 return 0;
825 /* preserve VGA I/O, BIOS and PPC */
826 hw->MXoptionReg &= 0xC0000100;
827 hw->MXoptionReg |= 0x002C0000;
828 if (ACCESS_FBINFO(devflags.novga))
829 hw->MXoptionReg &= ~0x00000100;
830 if (ACCESS_FBINFO(devflags.nobios))
831 hw->MXoptionReg &= ~0x40000000;
832 if (ACCESS_FBINFO(devflags.nopciretry))
833 hw->MXoptionReg |= 0x20000000;
834 pci_write_config_dword(ACCESS_FBINFO(pcidev), PCI_OPTION_REG, hw->MXoptionReg);
835
836 ACCESS_FBINFO(accel.ramdac_rev) = inTi3026(PMINFO TVP3026_XSILICONREV);
837
838 outTi3026(PMINFO TVP3026_XCLKCTRL, TVP3026_XCLKCTRL_SRC_CLK0VGA | TVP3026_XCLKCTRL_CLKSTOPPED);
839 outTi3026(PMINFO TVP3026_XTRUECOLORCTRL, TVP3026_XTRUECOLORCTRL_PSEUDOCOLOR);
840 outTi3026(PMINFO TVP3026_XMUXCTRL, TVP3026_XMUXCTRL_VGA);
841
842 outTi3026(PMINFO TVP3026_XPLLADDR, 0x2A);
843 outTi3026(PMINFO TVP3026_XLOOPPLLDATA, 0x00);
844 outTi3026(PMINFO TVP3026_XPIXPLLDATA, 0x00);
845
846 mga_outb(M_MISC_REG, 0x67);
847
848 outTi3026(PMINFO TVP3026_XMEMPLLCTRL, TVP3026_XMEMPLLCTRL_STROBEMKC4 | TVP3026_XMEMPLLCTRL_MCLK_MCLKPLL);
849
850 mga_outl(M_RESET, 1);
851 udelay(250);
852 mga_outl(M_RESET, 0);
853 udelay(250);
854 mga_outl(M_MACCESS, 0x00008000);
855 udelay(10);
856 return 0;
857 }
858
859 struct matrox_switch matrox_millennium = {
860 Ti3026_preinit, Ti3026_reset, Ti3026_init, Ti3026_restore, matroxfb_ti3026_selhwcursor
861 };
862 EXPORT_SYMBOL(matrox_millennium);
863 #endif
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