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[davej-history.git] / drivers / sound / maestro.c
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1 /*****************************************************************************
2 *
3 * ESS Maestro/Maestro-2/Maestro-2E driver for Linux 2.[23].x
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
18 *
19 * (c) Copyright 1999 Alan Cox <alan.cox@linux.org>
20 *
21 * Based heavily on SonicVibes.c:
22 * Copyright (C) 1998-1999 Thomas Sailer (sailer@ife.ee.ethz.ch)
23 *
24 * Heavily modified by Zach Brown <zab@zabbo.net> based on lunch
25 * with ESS engineers. Many thanks to Howard Kim for providing
26 * contacts and hardware. Honorable mention goes to Eric
27 * Brombaugh for all sorts of things. Best regards to the
28 * proprietors of Hack Central for fine lodging.
29 *
30 * Supported devices:
31 * /dev/dsp0-3 standard /dev/dsp device, (mostly) OSS compatible
32 * /dev/mixer standard /dev/mixer device, (mostly) OSS compatible
33 *
34 * Hardware Description
35 *
36 * A working Maestro setup contains the Maestro chip wired to a
37 * codec or 2. In the Maestro we have the APUs, the ASSP, and the
38 * Wavecache. The APUs can be though of as virtual audio routing
39 * channels. They can take data from a number of sources and perform
40 * basic encodings of the data. The wavecache is a storehouse for
41 * PCM data. Typically it deals with PCI and interracts with the
42 * APUs. The ASSP is a wacky DSP like device that ESS is loth
43 * to release docs on. Thankfully it isn't required on the Maestro
44 * until you start doing insane things like FM emulation and surround
45 * encoding. The codecs are almost always AC-97 compliant codecs,
46 * but it appears that early Maestros may have had PT101 (an ESS
47 * part?) wired to them. The only real difference in the Maestro
48 * families is external goop like docking capability, memory for
49 * the ASSP, and initialization differences.
50 *
51 * Driver Operation
52 *
53 * We only drive the APU/Wavecache as typical DACs and drive the
54 * mixers in the codecs. There are 64 APUs. We assign 6 to each
55 * /dev/dsp? device. 2 channels for output, and 4 channels for
56 * input.
57 *
58 * Each APU can do a number of things, but we only really use
59 * 3 basic functions. For playback we use them to convert PCM
60 * data fetched over PCI by the wavecahche into analog data that
61 * is handed to the codec. One APU for mono, and a pair for stereo.
62 * When in stereo, the combination of smarts in the APU and Wavecache
63 * decide which wavecache gets the left or right channel.
64 *
65 * For record we still use the old overly mono system. For each in
66 * coming channel the data comes in from the codec, through a 'input'
67 * APU, through another rate converter APU, and then into memory via
68 * the wavecache and PCI. If its stereo, we mash it back into LRLR in
69 * software. The pass between the 2 APUs is supposedly what requires us
70 * to have a 512 byte buffer sitting around in wavecache/memory.
71 *
72 * The wavecache makes our life even more fun. First off, it can
73 * only address the first 28 bits of PCI address space, making it
74 * useless on quite a few architectures. Secondly, its insane.
75 * It claims to fetch from 4 regions of PCI space, each 4 meg in length.
76 * But that doesn't really work. You can only use 1 region. So all our
77 * allocations have to be in 4meg of each other. Booo. Hiss.
78 * So we have a module parameter, dsps_order, that is the order of
79 * the number of dsps to provide. All their buffer space is allocated
80 * on open time. The sonicvibes OSS routines we inherited really want
81 * power of 2 buffers, so we have all those next to each other, then
82 * 512 byte regions for the recording wavecaches. This ends up
83 * wasting quite a bit of memory. The only fixes I can see would be
84 * getting a kernel allocator that could work in zones, or figuring out
85 * just how to coerce the WP into doing what we want.
86 *
87 * The indirection of the various registers means we have to spinlock
88 * nearly all register accesses. We have the main register indirection
89 * like the wave cache, maestro registers, etc. Then we have beasts
90 * like the APU interface that is indirect registers gotten at through
91 * the main maestro indirection. Ouch. We spinlock around the actual
92 * ports on a per card basis. This means spinlock activity at each IO
93 * operation, but the only IO operation clusters are in non critical
94 * paths and it makes the code far easier to follow. Interrupts are
95 * blocked while holding the locks because the int handler has to
96 * get at some of them :(. The mixer interface doesn't, however.
97 * We also have an OSS state lock that is thrown around in a few
98 * places.
99 *
100 * This driver has brute force APM suspend support. We catch suspend
101 * notifications and stop all work being done on the chip. Any people
102 * that try between this shutdown and the real suspend operation will
103 * be put to sleep. When we resume we restore our software state on
104 * the chip and wake up the people that were using it. The code thats
105 * being used now is quite dirty and assumes we're on a uni-processor
106 * machine. Much of it will need to be cleaned up for SMP ACPI or
107 * similar.
108 *
109 * We also pay attention to PCI power management now. The driver
110 * will power down units of the chip that it knows aren't needed.
111 * The WaveProcessor and company are only powered on when people
112 * have /dev/dsp*s open. On removal the driver will
113 * power down the maestro entirely. There could still be
114 * trouble with BIOSen that magically change power states
115 * themselves, but we'll see.
116 *
117 * History
118 * (still based on v0.14) Mar 29 2000 - Zach Brown <zab@redhat.com>
119 * move to 2.3 power management interface, which
120 * required hacking some suspend/resume/check paths
121 * make static compilation work
122 * v0.14 - Jan 28 2000 - Zach Brown <zab@redhat.com>
123 * add PCI power management through ACPI regs.
124 * we now shut down on machine reboot/halt
125 * leave scary PCI config items alone (isa stuff, mostly)
126 * enable 1921s, it seems only mine was broke.
127 * fix swapped left/right pcm dac. har har.
128 * up bob freq, increase buffers, fix pointers at underflow
129 * silly compilation problems
130 * v0.13 - Nov 18 1999 - Zach Brown <zab@redhat.com>
131 * fix nec Versas? man would that be cool.
132 * v0.12 - Nov 12 1999 - Zach Brown <zab@redhat.com>
133 * brown bag volume max fix..
134 * v0.11 - Nov 11 1999 - Zach Brown <zab@redhat.com>
135 * use proper stereo apu decoding, mmap/write should work.
136 * make volume sliders more useful, tweak rate calculation.
137 * fix lame 8bit format reporting bug. duh. apm apu saving buglet also
138 * fix maestro 1 clock freq "bug", remove pt101 support
139 * v0.10 - Oct 28 1999 - Zach Brown <zab@redhat.com>
140 * aha, so, sometimes the WP writes a status word to offset 0
141 * from one of the PCMBARs. rearrange allocation accordingly..
142 * cheers again to Eric for being a good hacker in investigating this.
143 * Jeroen Hoogervorst submits 7500 fix out of nowhere. yay. :)
144 * v0.09 - Oct 23 1999 - Zach Brown <zab@redhat.com>
145 * added APM support.
146 * re-order something such that some 2Es now work. Magic!
147 * new codec reset routine. made some codecs come to life.
148 * fix clear_advance, sync some control with ESS.
149 * now write to all base regs to be paranoid.
150 * v0.08 - Oct 20 1999 - Zach Brown <zab@redhat.com>
151 * Fix initial buflen bug. I am so smart. also smp compiling..
152 * I owe Eric yet another beer: fixed recmask, igain,
153 * muting, and adc sync consistency. Go Team.
154 * v0.07 - Oct 4 1999 - Zach Brown <zab@redhat.com>
155 * tweak adc/dac, formating, and stuff to allow full duplex
156 * allocate dsps memory at open() so we can fit in the wavecache window
157 * fix wavecache braindamage. again. no more scribbling?
158 * fix ess 1921 codec bug on some laptops.
159 * fix dumb pci scanning bug
160 * started 2.3 cleanup, redid spinlocks, little cleanups
161 * v0.06 - Sep 20 1999 - Zach Brown <zab@redhat.com>
162 * fix wavecache thinkos. limit to 1 /dev/dsp.
163 * eric is wearing his thinking toque this week.
164 * spotted apu mode bugs and gain ramping problem
165 * don't touch weird mixer regs, make recmask optional
166 * fixed igain inversion, defaults for mixers, clean up rec_start
167 * make mono recording work.
168 * report subsystem stuff, please send reports.
169 * littles: parallel out, amp now
170 * v0.05 - Sep 17 1999 - Zach Brown <zab@redhat.com>
171 * merged and fixed up Eric's initial recording code
172 * munged format handling to catch misuse, needs rewrite.
173 * revert ring bus init, fixup shared int, add pci busmaster setting
174 * fix mixer oss interface, fix mic mute and recmask
175 * mask off unsupported mixers, reset with all 1s, modularize defaults
176 * make sure bob is running while we need it
177 * got rid of device limit, initial minimal apm hooks
178 * pull out dead code/includes, only allow multimedia/audio maestros
179 * v0.04 - Sep 01 1999 - Zach Brown <zab@redhat.com>
180 * copied memory leak fix from sonicvibes driver
181 * different ac97 reset, play with 2.0 ac97, simplify ring bus setup
182 * bob freq code, region sanity, jitter sync fix; all from Eric
183 *
184 * TODO
185 * fix bob frequency
186 * endianness
187 * do smart things with ac97 2.0 bits.
188 * docking and dual codecs and 978?
189 * leave 54->61 open
190 *
191 * it also would be fun to have a mode that would not use pci dma at all
192 * but would copy into the wavecache on board memory and use that
193 * on architectures that don't like the maestro's pci dma ickiness.
194 */
195
196 /*****************************************************************************/
197
198 #include <linux/version.h>
199 #include <linux/module.h>
200 #include <linux/sched.h>
201 #include <linux/smp_lock.h>
202 #include <linux/wrapper.h>
203
204 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,3,0)
205
206 #define DECLARE_WAITQUEUE(QUEUE,INIT) struct wait_queue QUEUE = {INIT, NULL}
207 #define wait_queue_head_t struct wait_queue *
208 #define SILLY_PCI_BASE_ADDRESS(PCIDEV) (PCIDEV->base_address[0] & PCI_BASE_ADDRESS_IO_MASK)
209 #define SILLY_INIT_SEM(SEM) SEM=MUTEX;
210 #define init_waitqueue_head init_waitqueue
211 #define SILLY_MAKE_INIT(FUNC) __initfunc(FUNC)
212 #define SILLY_OFFSET(VMA) ((VMA)->vm_offset)
213
214
215 #else
216
217 #define SILLY_PCI_BASE_ADDRESS(PCIDEV) (PCIDEV->resource[0].start)
218 #define SILLY_INIT_SEM(SEM) init_MUTEX(&SEM)
219 #define SILLY_MAKE_INIT(FUNC) __init FUNC
220 #define SILLY_OFFSET(VMA) ((VMA)->vm_pgoff)
221
222
223 #endif
224
225 #include <linux/string.h>
226 #include <linux/ctype.h>
227 #include <linux/ioport.h>
228 #include <linux/delay.h>
229 #include <linux/sound.h>
230 #include <linux/malloc.h>
231 #include <linux/soundcard.h>
232 #include <linux/pci.h>
233 #include <linux/spinlock.h>
234 #include <asm/io.h>
235 #include <asm/dma.h>
236 #include <linux/init.h>
237 #include <linux/poll.h>
238 #include <linux/reboot.h>
239 #include <asm/uaccess.h>
240 #include <asm/hardirq.h>
241 #include <linux/bitops.h>
242
243 #include <linux/pm.h>
244 static int maestro_pm_callback(struct pm_dev *dev, pm_request_t rqst, void *d);
245
246 #include "maestro.h"
247
248 /* --------------------------------------------------------------------- */
249
250 #define M_DEBUG 1
251
252 #ifdef M_DEBUG
253 static int debug=0;
254 #define M_printk(args...) {if (debug) printk(args);}
255 #else
256 #define M_printk(x)
257 #endif
258
259 /* we try to setup 2^(dsps_order) /dev/dsp devices */
260 static int dsps_order=0;
261 /* wether or not we mess around with power management */
262 static int use_pm=2; /* set to 1 for force */
263
264 /* --------------------------------------------------------------------- */
265 #define DRIVER_VERSION "0.14"
266
267 #ifndef PCI_VENDOR_ESS
268 #define PCI_VENDOR_ESS 0x125D
269 #define PCI_DEVICE_ID_ESS_ESS1968 0x1968 /* Maestro 2 */
270 #define PCI_DEVICE_ID_ESS_ESS1978 0x1978 /* Maestro 2E */
271
272 #define PCI_VENDOR_ESS_OLD 0x1285 /* Platform Tech,
273 the people the maestro
274 was bought from */
275 #define PCI_DEVICE_ID_ESS_ESS0100 0x0100 /* maestro 1 */
276 #endif /* PCI_VENDOR_ESS */
277
278 #define ESS_CHAN_HARD 0x100
279
280 /* NEC Versas ? */
281 #define NEC_VERSA_SUBID1 0x80581033
282 #define NEC_VERSA_SUBID2 0x803c1033
283
284
285 /* changed so that I could actually find all the
286 references and fix them up. its a little more readable now. */
287 #define ESS_FMT_STEREO 0x01
288 #define ESS_FMT_16BIT 0x02
289 #define ESS_FMT_MASK 0x03
290 #define ESS_DAC_SHIFT 0
291 #define ESS_ADC_SHIFT 4
292
293 #define ESS_STATE_MAGIC 0x125D1968
294 #define ESS_CARD_MAGIC 0x19283746
295
296 #define DAC_RUNNING 1
297 #define ADC_RUNNING 2
298
299 #define MAX_DSP_ORDER 2
300 #define MAX_DSPS (1<<MAX_DSP_ORDER)
301 #define NR_DSPS (1<<dsps_order)
302 #define NR_IDRS 32
303
304 #define NR_APUS 64
305 #define NR_APU_REGS 16
306
307 /* acpi states */
308 enum {
309 ACPI_D0=0,
310 ACPI_D1,
311 ACPI_D2,
312 ACPI_D3
313 };
314
315 /* bits in the acpi masks */
316 #define ACPI_12MHZ ( 1 << 15)
317 #define ACPI_24MHZ ( 1 << 14)
318 #define ACPI_978 ( 1 << 13)
319 #define ACPI_SPDIF ( 1 << 12)
320 #define ACPI_GLUE ( 1 << 11)
321 #define ACPI__10 ( 1 << 10) /* reserved */
322 #define ACPI_PCIINT ( 1 << 9)
323 #define ACPI_HV ( 1 << 8) /* hardware volume */
324 #define ACPI_GPIO ( 1 << 7)
325 #define ACPI_ASSP ( 1 << 6)
326 #define ACPI_SB ( 1 << 5) /* sb emul */
327 #define ACPI_FM ( 1 << 4) /* fm emul */
328 #define ACPI_RB ( 1 << 3) /* ringbus / aclink */
329 #define ACPI_MIDI ( 1 << 2)
330 #define ACPI_GP ( 1 << 1) /* game port */
331 #define ACPI_WP ( 1 << 0) /* wave processor */
332
333 #define ACPI_ALL (0xffff)
334 #define ACPI_SLEEP (~(ACPI_SPDIF|ACPI_ASSP|ACPI_SB|ACPI_FM| \
335 ACPI_MIDI|ACPI_GP|ACPI_WP))
336 #define ACPI_NONE (ACPI__10)
337
338 /* these masks indicate which units we care about at
339 which states */
340 u16 acpi_state_mask[] = {
341 [ACPI_D0] = ACPI_ALL,
342 [ACPI_D1] = ACPI_SLEEP,
343 [ACPI_D2] = ACPI_SLEEP,
344 [ACPI_D3] = ACPI_NONE
345 };
346
347 static const unsigned sample_size[] = { 1, 2, 2, 4 };
348 static const unsigned sample_shift[] = { 0, 1, 1, 2 };
349
350 enum card_types_t {
351 TYPE_MAESTRO,
352 TYPE_MAESTRO2,
353 TYPE_MAESTRO2E
354 };
355
356 static const char *card_names[]={
357 [TYPE_MAESTRO] = "ESS Maestro",
358 [TYPE_MAESTRO2] = "ESS Maestro 2",
359 [TYPE_MAESTRO2E] = "ESS Maestro 2E"
360 };
361
362 static int clock_freq[]={
363 [TYPE_MAESTRO] = (49152000L / 1024L),
364 [TYPE_MAESTRO2] = (50000000L / 1024L),
365 [TYPE_MAESTRO2E] = (50000000L / 1024L)
366 };
367
368 static int maestro_notifier(struct notifier_block *nb, unsigned long event, void *buf);
369
370 static struct notifier_block maestro_nb = {maestro_notifier, NULL, 0};
371
372 /* --------------------------------------------------------------------- */
373
374 struct ess_state {
375 unsigned int magic;
376 /* FIXME: we probably want submixers in here, but only one record pair */
377 u8 apu[6]; /* l/r output, l/r intput converters, l/r input apus */
378 u8 apu_mode[6]; /* Running mode for this APU */
379 u8 apu_pan[6]; /* Panning setup for this APU */
380 u32 apu_base[6]; /* base address for this apu */
381 struct ess_card *card; /* Card info */
382 /* wave stuff */
383 unsigned int rateadc, ratedac;
384 unsigned char fmt, enable;
385
386 int index;
387
388 /* this locks around the oss state in the driver */
389 spinlock_t lock;
390 /* only let 1 be opening at a time */
391 struct semaphore open_sem;
392 wait_queue_head_t open_wait;
393 mode_t open_mode;
394
395 /* soundcore stuff */
396 int dev_audio;
397
398 struct dmabuf {
399 void *rawbuf;
400 unsigned buforder;
401 unsigned numfrag;
402 unsigned fragshift;
403 /* XXX zab - swptr only in here so that it can be referenced by
404 clear_advance, as far as I can tell :( */
405 unsigned hwptr, swptr;
406 unsigned total_bytes;
407 int count;
408 unsigned error; /* over/underrun */
409 wait_queue_head_t wait;
410 /* redundant, but makes calculations easier */
411 unsigned fragsize;
412 unsigned dmasize;
413 unsigned fragsamples;
414 /* OSS stuff */
415 unsigned mapped:1;
416 unsigned ready:1; /* our oss buffers are ready to go */
417 unsigned endcleared:1;
418 unsigned ossfragshift;
419 int ossmaxfrags;
420 unsigned subdivision;
421 u16 base; /* Offset for ptr */
422 } dma_dac, dma_adc;
423
424 /* pointer to each dsp?s piece of the apu->src buffer page */
425 void *mixbuf;
426
427 };
428
429 struct ess_card {
430 unsigned int magic;
431
432 /* We keep maestro cards in a linked list */
433 struct ess_card *next;
434
435 int dev_mixer;
436
437 int card_type;
438
439 /* as most of this is static,
440 perhaps it should be a pointer to a global struct */
441 struct mixer_goo {
442 int modcnt;
443 int supported_mixers;
444 int stereo_mixers;
445 int record_sources;
446 /* the caller must guarantee arg sanity before calling these */
447 /* int (*read_mixer)(struct ess_card *card, int index);*/
448 void (*write_mixer)(struct ess_card *card,int mixer, unsigned int left,unsigned int right);
449 int (*recmask_io)(struct ess_card *card,int rw,int mask);
450 unsigned int mixer_state[SOUND_MIXER_NRDEVICES];
451 } mix;
452
453 int power_regs;
454
455 int in_suspend;
456 wait_queue_head_t suspend_queue;
457
458 struct ess_state channels[MAX_DSPS];
459 u16 maestro_map[NR_IDRS]; /* Register map */
460 /* we have to store this junk so that we can come back from a
461 suspend */
462 u16 apu_map[NR_APUS][NR_APU_REGS]; /* contents of apu regs */
463
464 /* this locks around the physical registers on the card */
465 spinlock_t lock;
466
467 /* memory for this card.. wavecache limited :(*/
468 void *dmapages;
469 int dmaorder;
470
471 /* hardware resources */
472 struct pci_dev *pcidev;
473 u32 iobase;
474 u32 irq;
475
476 int bob_freq;
477 char dsps_open;
478 };
479
480 static unsigned
481 ld2(unsigned int x)
482 {
483 unsigned r = 0;
484
485 if (x >= 0x10000) {
486 x >>= 16;
487 r += 16;
488 }
489 if (x >= 0x100) {
490 x >>= 8;
491 r += 8;
492 }
493 if (x >= 0x10) {
494 x >>= 4;
495 r += 4;
496 }
497 if (x >= 4) {
498 x >>= 2;
499 r += 2;
500 }
501 if (x >= 2)
502 r++;
503 return r;
504 }
505
506
507 /* --------------------------------------------------------------------- */
508
509 static void check_suspend(struct ess_card *card);
510
511 static struct ess_card *devs = NULL;
512
513 /* --------------------------------------------------------------------- */
514
515
516 /*
517 * ESS Maestro AC97 codec programming interface.
518 */
519
520 static void maestro_ac97_set(struct ess_card *card, u8 cmd, u16 val)
521 {
522 int io = card->iobase;
523 int i;
524 /*
525 * Wait for the codec bus to be free
526 */
527
528 check_suspend(card);
529
530 for(i=0;i<10000;i++)
531 {
532 if(!(inb(io+ESS_AC97_INDEX)&1))
533 break;
534 }
535 /*
536 * Write the bus
537 */
538 outw(val, io+ESS_AC97_DATA);
539 mdelay(1);
540 outb(cmd, io+ESS_AC97_INDEX);
541 mdelay(1);
542 }
543
544 static u16 maestro_ac97_get(struct ess_card *card, u8 cmd)
545 {
546 int io = card->iobase;
547 int sanity=10000;
548 u16 data;
549 int i;
550
551 check_suspend(card);
552 /*
553 * Wait for the codec bus to be free
554 */
555
556 for(i=0;i<10000;i++)
557 {
558 if(!(inb(io+ESS_AC97_INDEX)&1))
559 break;
560 }
561
562 outb(cmd|0x80, io+ESS_AC97_INDEX);
563 mdelay(1);
564
565 while(inb(io+ESS_AC97_INDEX)&1)
566 {
567 sanity--;
568 if(!sanity)
569 {
570 printk(KERN_ERR "maestro: ac97 codec timeout reading 0x%x.\n",cmd);
571 return 0;
572 }
573 }
574 data=inw(io+ESS_AC97_DATA);
575 mdelay(1);
576 return data;
577 }
578
579 /* OSS interface to the ac97s.. */
580
581 #define AC97_STEREO_MASK (SOUND_MASK_VOLUME|\
582 SOUND_MASK_PCM|SOUND_MASK_LINE|SOUND_MASK_CD|\
583 SOUND_MASK_VIDEO|SOUND_MASK_LINE1|SOUND_MASK_IGAIN)
584
585 #define AC97_SUPPORTED_MASK (AC97_STEREO_MASK | \
586 SOUND_MASK_BASS|SOUND_MASK_TREBLE|SOUND_MASK_MIC|\
587 SOUND_MASK_SPEAKER)
588
589 #define AC97_RECORD_MASK (SOUND_MASK_MIC|\
590 SOUND_MASK_CD| SOUND_MASK_VIDEO| SOUND_MASK_LINE1| SOUND_MASK_LINE|\
591 SOUND_MASK_PHONEIN)
592
593 #define supported_mixer(CARD,FOO) ( CARD->mix.supported_mixers & (1<<FOO) )
594
595 /* this table has default mixer values for all OSS mixers.
596 be sure to fill it in if you add oss mixers
597 to anyone's supported mixer defines */
598
599 unsigned int mixer_defaults[SOUND_MIXER_NRDEVICES] = {
600 [SOUND_MIXER_VOLUME] = 0x3232,
601 [SOUND_MIXER_BASS] = 0x3232,
602 [SOUND_MIXER_TREBLE] = 0x3232,
603 [SOUND_MIXER_SPEAKER] = 0x3232,
604 [SOUND_MIXER_MIC] = 0x8000, /* annoying */
605 [SOUND_MIXER_LINE] = 0x3232,
606 [SOUND_MIXER_CD] = 0x3232,
607 [SOUND_MIXER_VIDEO] = 0x3232,
608 [SOUND_MIXER_LINE1] = 0x3232,
609 [SOUND_MIXER_PCM] = 0x3232,
610 [SOUND_MIXER_IGAIN] = 0x3232
611 };
612
613 static struct ac97_mixer_hw {
614 unsigned char offset;
615 int scale;
616 } ac97_hw[SOUND_MIXER_NRDEVICES]= {
617 [SOUND_MIXER_VOLUME] = {0x02,63},
618 [SOUND_MIXER_BASS] = {0x08,15},
619 [SOUND_MIXER_TREBLE] = {0x08,15},
620 [SOUND_MIXER_SPEAKER] = {0x0a,15},
621 [SOUND_MIXER_MIC] = {0x0e,31},
622 [SOUND_MIXER_LINE] = {0x10,31},
623 [SOUND_MIXER_CD] = {0x12,31},
624 [SOUND_MIXER_VIDEO] = {0x14,31},
625 [SOUND_MIXER_LINE1] = {0x16,31},
626 [SOUND_MIXER_PCM] = {0x18,31},
627 [SOUND_MIXER_IGAIN] = {0x1c,15}
628 };
629
630 #if 0 /* *shrug* removed simply because we never used it.
631 feel free to implement again if needed */
632
633 /* reads the given OSS mixer from the ac97
634 the caller must have insured that the ac97 knows
635 about that given mixer, and should be holding a
636 spinlock for the card */
637 static int ac97_read_mixer(struct ess_card *card, int mixer)
638 {
639 u16 val;
640 int ret=0;
641 struct ac97_mixer_hw *mh = &ac97_hw[mixer];
642
643 val = maestro_ac97_get(card, mh->offset);
644
645 if(AC97_STEREO_MASK & (1<<mixer)) {
646 /* nice stereo mixers .. */
647 int left,right;
648
649 left = (val >> 8) & 0x7f;
650 right = val & 0x7f;
651
652 if (mixer == SOUND_MIXER_IGAIN) {
653 right = (right * 100) / mh->scale;
654 left = (left * 100) / mh->scale;
655 else {
656 right = 100 - ((right * 100) / mh->scale);
657 left = 100 - ((left * 100) / mh->scale);
658 }
659
660 ret = left | (right << 8);
661 } else if (mixer == SOUND_MIXER_SPEAKER) {
662 ret = 100 - ((((val & 0x1e)>>1) * 100) / mh->scale);
663 } else if (mixer == SOUND_MIXER_MIC) {
664 ret = 100 - (((val & 0x1f) * 100) / mh->scale);
665 /* the low bit is optional in the tone sliders and masking
666 it lets is avoid the 0xf 'bypass'.. */
667 } else if (mixer == SOUND_MIXER_BASS) {
668 ret = 100 - ((((val >> 8) & 0xe) * 100) / mh->scale);
669 } else if (mixer == SOUND_MIXER_TREBLE) {
670 ret = 100 - (((val & 0xe) * 100) / mh->scale);
671 }
672
673 M_printk("read mixer %d (0x%x) %x -> %x\n",mixer,mh->offset,val,ret);
674
675 return ret;
676 }
677 #endif
678
679 /* write the OSS encoded volume to the given OSS encoded mixer,
680 again caller's job to make sure all is well in arg land,
681 call with spinlock held */
682
683 /* linear scale -> log */
684 static unsigned char lin2log[101] =
685 {
686 0, 0 , 15 , 23 , 30 , 34 , 38 , 42 , 45 , 47 ,
687 50 , 52 , 53 , 55 , 57 , 58 , 60 , 61 , 62 ,
688 63 , 65 , 66 , 67 , 68 , 69 , 69 , 70 , 71 ,
689 72 , 73 , 73 , 74 , 75 , 75 , 76 , 77 , 77 ,
690 78 , 78 , 79 , 80 , 80 , 81 , 81 , 82 , 82 ,
691 83 , 83 , 84 , 84 , 84 , 85 , 85 , 86 , 86 ,
692 87 , 87 , 87 , 88 , 88 , 88 , 89 , 89 , 89 ,
693 90 , 90 , 90 , 91 , 91 , 91 , 92 , 92 , 92 ,
694 93 , 93 , 93 , 94 , 94 , 94 , 94 , 95 , 95 ,
695 95 , 95 , 96 , 96 , 96 , 96 , 97 , 97 , 97 ,
696 97 , 98 , 98 , 98 , 98 , 99 , 99 , 99 , 99 , 99
697 };
698
699 static void ac97_write_mixer(struct ess_card *card,int mixer, unsigned int left, unsigned int right)
700 {
701 u16 val=0;
702 struct ac97_mixer_hw *mh = &ac97_hw[mixer];
703
704 M_printk("wrote mixer %d (0x%x) %d,%d",mixer,mh->offset,left,right);
705
706 if(AC97_STEREO_MASK & (1<<mixer)) {
707 /* stereo mixers, mute them if we can */
708
709 if (mixer == SOUND_MIXER_IGAIN) {
710 /* igain's slider is reversed.. */
711 right = (right * mh->scale) / 100;
712 left = (left * mh->scale) / 100;
713 if ((left == 0) && (right == 0))
714 val |= 0x8000;
715 } else {
716 /* log conversion for the stereo controls */
717 if((left == 0) && (right == 0))
718 val = 0x8000;
719 right = ((100 - lin2log[right]) * mh->scale) / 100;
720 left = ((100 - lin2log[left]) * mh->scale) / 100;
721 }
722
723 val |= (left << 8) | right;
724
725 } else if (mixer == SOUND_MIXER_SPEAKER) {
726 val = (((100 - left) * mh->scale) / 100) << 1;
727 } else if (mixer == SOUND_MIXER_MIC) {
728 val = maestro_ac97_get(card, mh->offset) & ~0x801f;
729 val |= (((100 - left) * mh->scale) / 100);
730 /* the low bit is optional in the tone sliders and masking
731 it lets is avoid the 0xf 'bypass'.. */
732 } else if (mixer == SOUND_MIXER_BASS) {
733 val = maestro_ac97_get(card , mh->offset) & ~0x0f00;
734 val |= ((((100 - left) * mh->scale) / 100) << 8) & 0x0e00;
735 } else if (mixer == SOUND_MIXER_TREBLE) {
736 val = maestro_ac97_get(card , mh->offset) & ~0x000f;
737 val |= (((100 - left) * mh->scale) / 100) & 0x000e;
738 }
739
740 maestro_ac97_set(card , mh->offset, val);
741
742 M_printk(" -> %x\n",val);
743 }
744
745 /* the following tables allow us to go from
746 OSS <-> ac97 quickly. */
747
748 enum ac97_recsettings {
749 AC97_REC_MIC=0,
750 AC97_REC_CD,
751 AC97_REC_VIDEO,
752 AC97_REC_AUX,
753 AC97_REC_LINE,
754 AC97_REC_STEREO, /* combination of all enabled outputs.. */
755 AC97_REC_MONO, /*.. or the mono equivalent */
756 AC97_REC_PHONE
757 };
758
759 static unsigned int ac97_oss_mask[] = {
760 [AC97_REC_MIC] = SOUND_MASK_MIC,
761 [AC97_REC_CD] = SOUND_MASK_CD,
762 [AC97_REC_VIDEO] = SOUND_MASK_VIDEO,
763 [AC97_REC_AUX] = SOUND_MASK_LINE1,
764 [AC97_REC_LINE] = SOUND_MASK_LINE,
765 [AC97_REC_PHONE] = SOUND_MASK_PHONEIN
766 };
767
768 /* indexed by bit position */
769 static unsigned int ac97_oss_rm[] = {
770 [SOUND_MIXER_MIC] = AC97_REC_MIC,
771 [SOUND_MIXER_CD] = AC97_REC_CD,
772 [SOUND_MIXER_VIDEO] = AC97_REC_VIDEO,
773 [SOUND_MIXER_LINE1] = AC97_REC_AUX,
774 [SOUND_MIXER_LINE] = AC97_REC_LINE,
775 [SOUND_MIXER_PHONEIN] = AC97_REC_PHONE
776 };
777
778 /* read or write the recmask
779 the ac97 can really have left and right recording
780 inputs independantly set, but OSS doesn't seem to
781 want us to express that to the user.
782 the caller guarantees that we have a supported bit set,
783 and they must be holding the card's spinlock */
784 static int
785 ac97_recmask_io(struct ess_card *card, int read, int mask)
786 {
787 unsigned int val = ac97_oss_mask[ maestro_ac97_get(card, 0x1a) & 0x7 ];
788
789 if (read) return val;
790
791 /* oss can have many inputs, maestro cant. try
792 to pick the 'new' one */
793
794 if (mask != val) mask &= ~val;
795
796 val = ffs(mask) - 1;
797 val = ac97_oss_rm[val];
798 val |= val << 8; /* set both channels */
799
800 M_printk("maestro: setting ac97 recmask to 0x%x\n",val);
801
802 maestro_ac97_set(card,0x1a,val);
803
804 return 0;
805 };
806
807 /*
808 * The Maestro can be wired to a standard AC97 compliant codec
809 * (see www.intel.com for the pdf's on this), or to a PT101 codec
810 * which appears to be the ES1918 (data sheet on the esstech.com.tw site)
811 *
812 * The PT101 setup is untested.
813 */
814
815 static u16 maestro_ac97_init(struct ess_card *card)
816 {
817 u16 vend1, vend2, caps;
818
819 card->mix.supported_mixers = AC97_SUPPORTED_MASK;
820 card->mix.stereo_mixers = AC97_STEREO_MASK;
821 card->mix.record_sources = AC97_RECORD_MASK;
822 /* card->mix.read_mixer = ac97_read_mixer;*/
823 card->mix.write_mixer = ac97_write_mixer;
824 card->mix.recmask_io = ac97_recmask_io;
825
826 vend1 = maestro_ac97_get(card, 0x7c);
827 vend2 = maestro_ac97_get(card, 0x7e);
828
829 caps = maestro_ac97_get(card, 0x00);
830
831 printk(KERN_INFO "maestro: AC97 Codec detected: v: 0x%2x%2x caps: 0x%x pwr: 0x%x\n",
832 vend1,vend2,caps,maestro_ac97_get(card,0x26) & 0xf);
833
834 if (! (caps & 0x4) ) {
835 /* no bass/treble nobs */
836 card->mix.supported_mixers &= ~(SOUND_MASK_BASS|SOUND_MASK_TREBLE);
837 }
838
839 /* XXX endianness, dork head. */
840 /* vendor specifc bits.. */
841 switch ((long)(vend1 << 16) | vend2) {
842 case 0x545200ff: /* TriTech */
843 /* no idea what this does */
844 maestro_ac97_set(card,0x2a,0x0001);
845 maestro_ac97_set(card,0x2c,0x0000);
846 maestro_ac97_set(card,0x2c,0xffff);
847 break;
848 #if 0 /* i thought the problems I was seeing were with
849 the 1921, but apparently they were with the pci board
850 it was on, so this code is commented out.
851 lets see if this holds true. */
852 case 0x83847609: /* ESS 1921 */
853 /* writing to 0xe (mic) or 0x1a (recmask) seems
854 to hang this codec */
855 card->mix.supported_mixers &= ~(SOUND_MASK_MIC);
856 card->mix.record_sources = 0;
857 card->mix.recmask_io = NULL;
858 #if 0 /* don't ask. I have yet to see what these actually do. */
859 maestro_ac97_set(card,0x76,0xABBA); /* o/~ Take a chance on me o/~ */
860 udelay(20);
861 maestro_ac97_set(card,0x78,0x3002);
862 udelay(20);
863 maestro_ac97_set(card,0x78,0x3802);
864 udelay(20);
865 #endif
866 break;
867 #endif
868 default: break;
869 }
870
871 maestro_ac97_set(card, 0x1E, 0x0404);
872 /* null misc stuff */
873 maestro_ac97_set(card, 0x20, 0x0000);
874
875 return 0;
876 }
877
878 #if 0 /* there has been 1 person on the planet with a pt101 that we
879 know of. If they care, they can put this back in :) */
880 static u16 maestro_pt101_init(struct ess_card *card,int iobase)
881 {
882 printk(KERN_INFO "maestro: PT101 Codec detected, initializing but _not_ installing mixer device.\n");
883 /* who knows.. */
884 maestro_ac97_set(iobase, 0x2A, 0x0001);
885 maestro_ac97_set(iobase, 0x2C, 0x0000);
886 maestro_ac97_set(iobase, 0x2C, 0xFFFF);
887 maestro_ac97_set(iobase, 0x10, 0x9F1F);
888 maestro_ac97_set(iobase, 0x12, 0x0808);
889 maestro_ac97_set(iobase, 0x14, 0x9F1F);
890 maestro_ac97_set(iobase, 0x16, 0x9F1F);
891 maestro_ac97_set(iobase, 0x18, 0x0404);
892 maestro_ac97_set(iobase, 0x1A, 0x0000);
893 maestro_ac97_set(iobase, 0x1C, 0x0000);
894 maestro_ac97_set(iobase, 0x02, 0x0404);
895 maestro_ac97_set(iobase, 0x04, 0x0808);
896 maestro_ac97_set(iobase, 0x0C, 0x801F);
897 maestro_ac97_set(iobase, 0x0E, 0x801F);
898 return 0;
899 }
900 #endif
901
902 /* this is very magic, and very slow.. */
903 static void
904 maestro_ac97_reset(int ioaddr, struct pci_dev *pcidev)
905 {
906 u16 save_68;
907 u16 w;
908 u32 vend;
909
910 outw( inw(ioaddr + 0x38) & 0xfffc, ioaddr + 0x38);
911 outw( inw(ioaddr + 0x3a) & 0xfffc, ioaddr + 0x3a);
912 outw( inw(ioaddr + 0x3c) & 0xfffc, ioaddr + 0x3c);
913
914 /* reset the first codec */
915 outw(0x0000, ioaddr+0x36);
916 save_68 = inw(ioaddr+0x68);
917 pci_read_config_word(pcidev, 0x58, &w); /* something magical with gpio and bus arb. */
918 pci_read_config_dword(pcidev, PCI_SUBSYSTEM_VENDOR_ID, &vend);
919 if( w & 0x1)
920 save_68 |= 0x10;
921 outw(0xfffe, ioaddr + 0x64); /* tickly gpio 0.. */
922 outw(0x0001, ioaddr + 0x68);
923 outw(0x0000, ioaddr + 0x60);
924 udelay(20);
925 outw(0x0001, ioaddr + 0x60);
926 mdelay(20);
927
928 outw(save_68 | 0x1, ioaddr + 0x68); /* now restore .. */
929 outw( (inw(ioaddr + 0x38) & 0xfffc)|0x1, ioaddr + 0x38);
930 outw( (inw(ioaddr + 0x3a) & 0xfffc)|0x1, ioaddr + 0x3a);
931 outw( (inw(ioaddr + 0x3c) & 0xfffc)|0x1, ioaddr + 0x3c);
932
933 /* now the second codec */
934 outw(0x0000, ioaddr+0x36);
935 outw(0xfff7, ioaddr + 0x64);
936 save_68 = inw(ioaddr+0x68);
937 outw(0x0009, ioaddr + 0x68);
938 outw(0x0001, ioaddr + 0x60);
939 udelay(20);
940 outw(0x0009, ioaddr + 0x60);
941 mdelay(500); /* .. ouch.. */
942 outw( inw(ioaddr + 0x38) & 0xfffc, ioaddr + 0x38);
943 outw( inw(ioaddr + 0x3a) & 0xfffc, ioaddr + 0x3a);
944 outw( inw(ioaddr + 0x3c) & 0xfffc, ioaddr + 0x3c);
945
946 #if 0 /* the loop here needs to be much better if we want it.. */
947 M_printk("trying software reset\n");
948 /* try and do a software reset */
949 outb(0x80|0x7c, ioaddr + 0x30);
950 for (w=0; ; w++) {
951 if ((inw(ioaddr+ 0x30) & 1) == 0) {
952 if(inb(ioaddr + 0x32) !=0) break;
953
954 outb(0x80|0x7d, ioaddr + 0x30);
955 if (((inw(ioaddr+ 0x30) & 1) == 0) && (inb(ioaddr + 0x32) !=0)) break;
956 outb(0x80|0x7f, ioaddr + 0x30);
957 if (((inw(ioaddr+ 0x30) & 1) == 0) && (inb(ioaddr + 0x32) !=0)) break;
958 }
959
960 if( w > 10000) {
961 outb( inb(ioaddr + 0x37) | 0x08, ioaddr + 0x37); /* do a software reset */
962 mdelay(500); /* oh my.. */
963 outb( inb(ioaddr + 0x37) & ~0x08, ioaddr + 0x37);
964 udelay(1);
965 outw( 0x80, ioaddr+0x30);
966 for(w = 0 ; w < 10000; w++) {
967 if((inw(ioaddr + 0x30) & 1) ==0) break;
968 }
969 }
970 }
971 #endif
972 if ( vend == NEC_VERSA_SUBID1 || vend == NEC_VERSA_SUBID2) {
973 /* turn on external amp? */
974 outw(0xf9ff, ioaddr + 0x64);
975 outw(inw(ioaddr+0x68) | 0x600, ioaddr + 0x68);
976 outw(0x0209, ioaddr + 0x60);
977 }
978 }
979 /*
980 * Indirect register access. Not all registers are readable so we
981 * need to keep register state ourselves
982 */
983
984 #define WRITEABLE_MAP 0xEFFFFF
985 #define READABLE_MAP 0x64003F
986
987 /*
988 * The Maestro engineers were a little indirection happy. These indirected
989 * registers themselves include indirect registers at another layer
990 */
991
992 static void __maestro_write(struct ess_card *card, u16 reg, u16 data)
993 {
994 long ioaddr = card->iobase;
995
996 outw(reg, ioaddr+0x02);
997 outw(data, ioaddr+0x00);
998 if( reg >= NR_IDRS) printk("maestro: IDR %d out of bounds!\n",reg);
999 else card->maestro_map[reg]=data;
1000
1001 }
1002
1003 static void maestro_write(struct ess_state *s, u16 reg, u16 data)
1004 {
1005 unsigned long flags;
1006
1007 check_suspend(s->card);
1008 spin_lock_irqsave(&s->card->lock,flags);
1009
1010 __maestro_write(s->card,reg,data);
1011
1012 spin_unlock_irqrestore(&s->card->lock,flags);
1013 }
1014
1015 static u16 __maestro_read(struct ess_card *card, u16 reg)
1016 {
1017 long ioaddr = card->iobase;
1018
1019 outw(reg, ioaddr+0x02);
1020 return card->maestro_map[reg]=inw(ioaddr+0x00);
1021 }
1022
1023 static u16 maestro_read(struct ess_state *s, u16 reg)
1024 {
1025 if(READABLE_MAP & (1<<reg))
1026 {
1027 unsigned long flags;
1028 check_suspend(s->card);
1029 spin_lock_irqsave(&s->card->lock,flags);
1030
1031 __maestro_read(s->card,reg);
1032
1033 spin_unlock_irqrestore(&s->card->lock,flags);
1034 }
1035 return s->card->maestro_map[reg];
1036 }
1037
1038 /*
1039 * These routines handle accessing the second level indirections to the
1040 * wave ram.
1041 */
1042
1043 /*
1044 * The register names are the ones ESS uses (see 104T31.ZIP)
1045 */
1046
1047 #define IDR0_DATA_PORT 0x00
1048 #define IDR1_CRAM_POINTER 0x01
1049 #define IDR2_CRAM_DATA 0x02
1050 #define IDR3_WAVE_DATA 0x03
1051 #define IDR4_WAVE_PTR_LOW 0x04
1052 #define IDR5_WAVE_PTR_HI 0x05
1053 #define IDR6_TIMER_CTRL 0x06
1054 #define IDR7_WAVE_ROMRAM 0x07
1055
1056 static void apu_index_set(struct ess_card *card, u16 index)
1057 {
1058 int i;
1059 __maestro_write(card, IDR1_CRAM_POINTER, index);
1060 for(i=0;i<1000;i++)
1061 if(__maestro_read(card, IDR1_CRAM_POINTER)==index)
1062 return;
1063 printk(KERN_WARNING "maestro: APU register select failed.\n");
1064 }
1065
1066 static void apu_data_set(struct ess_card *card, u16 data)
1067 {
1068 int i;
1069 for(i=0;i<1000;i++)
1070 {
1071 if(__maestro_read(card, IDR0_DATA_PORT)==data)
1072 return;
1073 __maestro_write(card, IDR0_DATA_PORT, data);
1074 }
1075 }
1076
1077 /*
1078 * This is the public interface for APU manipulation. It handles the
1079 * interlock to avoid two APU writes in parallel etc. Don't diddle
1080 * directly with the stuff above.
1081 */
1082
1083 static void apu_set_register(struct ess_state *s, u16 channel, u8 reg, u16 data)
1084 {
1085 unsigned long flags;
1086
1087 check_suspend(s->card);
1088
1089 if(channel&ESS_CHAN_HARD)
1090 channel&=~ESS_CHAN_HARD;
1091 else
1092 {
1093 if(channel>5)
1094 printk("BAD CHANNEL %d.\n",channel);
1095 else
1096 channel = s->apu[channel];
1097 /* store based on real hardware apu/reg */
1098 s->card->apu_map[channel][reg]=data;
1099 }
1100 reg|=(channel<<4);
1101
1102 /* hooray for double indirection!! */
1103 spin_lock_irqsave(&s->card->lock,flags);
1104
1105 apu_index_set(s->card, reg);
1106 apu_data_set(s->card, data);
1107
1108 spin_unlock_irqrestore(&s->card->lock,flags);
1109 }
1110
1111 static u16 apu_get_register(struct ess_state *s, u16 channel, u8 reg)
1112 {
1113 unsigned long flags;
1114 u16 v;
1115
1116 check_suspend(s->card);
1117
1118 if(channel&ESS_CHAN_HARD)
1119 channel&=~ESS_CHAN_HARD;
1120 else
1121 channel = s->apu[channel];
1122
1123 reg|=(channel<<4);
1124
1125 spin_lock_irqsave(&s->card->lock,flags);
1126
1127 apu_index_set(s->card, reg);
1128 v=__maestro_read(s->card, IDR0_DATA_PORT);
1129
1130 spin_unlock_irqrestore(&s->card->lock,flags);
1131 return v;
1132 }
1133
1134
1135 /*
1136 * The wavecache buffers between the APUs and
1137 * pci bus mastering
1138 */
1139
1140 static void wave_set_register(struct ess_state *s, u16 reg, u16 value)
1141 {
1142 long ioaddr = s->card->iobase;
1143 unsigned long flags;
1144 check_suspend(s->card);
1145
1146 spin_lock_irqsave(&s->card->lock,flags);
1147
1148 outw(reg, ioaddr+0x10);
1149 outw(value, ioaddr+0x12);
1150
1151 spin_unlock_irqrestore(&s->card->lock,flags);
1152 }
1153
1154 static u16 wave_get_register(struct ess_state *s, u16 reg)
1155 {
1156 long ioaddr = s->card->iobase;
1157 unsigned long flags;
1158 u16 value;
1159 check_suspend(s->card);
1160
1161 spin_lock_irqsave(&s->card->lock,flags);
1162 outw(reg, ioaddr+0x10);
1163 value=inw(ioaddr+0x12);
1164 spin_unlock_irqrestore(&s->card->lock,flags);
1165
1166 return value;
1167 }
1168
1169 static void sound_reset(int ioaddr)
1170 {
1171 outw(0x2000, 0x18+ioaddr);
1172 udelay(1);
1173 outw(0x0000, 0x18+ioaddr);
1174 udelay(1);
1175 }
1176
1177 /* sets the play formats of these apus, should be passed the already shifted format */
1178 static void set_apu_fmt(struct ess_state *s, int apu, int mode)
1179 {
1180 int apu_fmt = 0x10;
1181
1182 if(!(mode&ESS_FMT_16BIT)) apu_fmt+=0x20;
1183 if((mode&ESS_FMT_STEREO)) apu_fmt+=0x10;
1184 s->apu_mode[apu] = apu_fmt;
1185 s->apu_mode[apu+1] = apu_fmt;
1186 }
1187
1188 /* this only fixes the output apu mode to be later set by start_dac and
1189 company. output apu modes are set in ess_rec_setup */
1190 static void set_fmt(struct ess_state *s, unsigned char mask, unsigned char data)
1191 {
1192 s->fmt = (s->fmt & mask) | data;
1193 set_apu_fmt(s, 0, (s->fmt >> ESS_DAC_SHIFT) & ESS_FMT_MASK);
1194 }
1195
1196 /* this is off by a little bit.. */
1197 static u32 compute_rate(struct ess_state *s, u32 freq)
1198 {
1199 u32 clock = clock_freq[s->card->card_type];
1200
1201 if (freq == 48000) return 0x10000;
1202
1203 return ((freq / clock) <<16 )+
1204 (((freq % clock) << 16) / clock);
1205 }
1206
1207 static void set_dac_rate(struct ess_state *s, unsigned int rate)
1208 {
1209 u32 freq;
1210 int fmt = (s->fmt >> ESS_DAC_SHIFT) & ESS_FMT_MASK;
1211
1212 if (rate > 48000)
1213 rate = 48000;
1214 if (rate < 4000)
1215 rate = 4000;
1216
1217 s->ratedac = rate;
1218
1219 if(! (fmt & ESS_FMT_16BIT) && !(fmt & ESS_FMT_STEREO))
1220 rate >>= 1;
1221
1222 /* M_printk("computing dac rate %d with mode %d\n",rate,s->fmt);*/
1223
1224 freq = compute_rate(s, rate);
1225
1226 /* Load the frequency, turn on 6dB */
1227 apu_set_register(s, 0, 2,(apu_get_register(s, 0, 2)&0x00FF)|
1228 ( ((freq&0xFF)<<8)|0x10 ));
1229 apu_set_register(s, 0, 3, freq>>8);
1230 apu_set_register(s, 1, 2,(apu_get_register(s, 1, 2)&0x00FF)|
1231 ( ((freq&0xFF)<<8)|0x10 ));
1232 apu_set_register(s, 1, 3, freq>>8);
1233 }
1234
1235 static void set_adc_rate(struct ess_state *s, unsigned rate)
1236 {
1237 u32 freq;
1238
1239 /* Sample Rate conversion APUs don't like 0x10000 for their rate */
1240 if (rate > 47999)
1241 rate = 47999;
1242 if (rate < 4000)
1243 rate = 4000;
1244
1245 s->rateadc = rate;
1246
1247 freq = compute_rate(s, rate);
1248
1249 /* Load the frequency, turn on 6dB */
1250 apu_set_register(s, 2, 2,(apu_get_register(s, 2, 2)&0x00FF)|
1251 ( ((freq&0xFF)<<8)|0x10 ));
1252 apu_set_register(s, 2, 3, freq>>8);
1253 apu_set_register(s, 3, 2,(apu_get_register(s, 3, 2)&0x00FF)|
1254 ( ((freq&0xFF)<<8)|0x10 ));
1255 apu_set_register(s, 3, 3, freq>>8);
1256
1257 /* fix mixer rate at 48khz. and its _must_ be 0x10000. */
1258 freq = 0x10000;
1259
1260 apu_set_register(s, 4, 2,(apu_get_register(s, 4, 2)&0x00FF)|
1261 ( ((freq&0xFF)<<8)|0x10 ));
1262 apu_set_register(s, 4, 3, freq>>8);
1263 apu_set_register(s, 5, 2,(apu_get_register(s, 5, 2)&0x00FF)|
1264 ( ((freq&0xFF)<<8)|0x10 ));
1265 apu_set_register(s, 5, 3, freq>>8);
1266 }
1267
1268 /* Stop our host of recording apus */
1269 extern inline void stop_adc(struct ess_state *s)
1270 {
1271 /* XXX lets hope we don't have to lock around this */
1272 if (! (s->enable & ADC_RUNNING)) return;
1273
1274 s->enable &= ~ADC_RUNNING;
1275 apu_set_register(s, 2, 0, apu_get_register(s, 2, 0)&0xFF0F);
1276 apu_set_register(s, 3, 0, apu_get_register(s, 3, 0)&0xFF0F);
1277 apu_set_register(s, 4, 0, apu_get_register(s, 2, 0)&0xFF0F);
1278 apu_set_register(s, 5, 0, apu_get_register(s, 3, 0)&0xFF0F);
1279 }
1280
1281 /* stop output apus */
1282 static void stop_dac(struct ess_state *s)
1283 {
1284 /* XXX have to lock around this? */
1285 if (! (s->enable & DAC_RUNNING)) return;
1286
1287 s->enable &= ~DAC_RUNNING;
1288 apu_set_register(s, 0, 0, apu_get_register(s, 0, 0)&0xFF0F);
1289 apu_set_register(s, 1, 0, apu_get_register(s, 1, 0)&0xFF0F);
1290 }
1291
1292 static void start_dac(struct ess_state *s)
1293 {
1294 /* XXX locks? */
1295 if ( (s->dma_dac.mapped || s->dma_dac.count > 0) &&
1296 s->dma_dac.ready &&
1297 (! (s->enable & DAC_RUNNING)) ) {
1298
1299 s->enable |= DAC_RUNNING;
1300
1301 apu_set_register(s, 0, 0,
1302 (apu_get_register(s, 0, 0)&0xFF0F)|s->apu_mode[0]);
1303
1304 if((s->fmt >> ESS_DAC_SHIFT) & ESS_FMT_STEREO)
1305 apu_set_register(s, 1, 0,
1306 (apu_get_register(s, 1, 0)&0xFF0F)|s->apu_mode[1]);
1307 }
1308 }
1309
1310 static void start_adc(struct ess_state *s)
1311 {
1312 /* XXX locks? */
1313 if ((s->dma_adc.mapped || s->dma_adc.count < (signed)(s->dma_adc.dmasize - 2*s->dma_adc.fragsize))
1314 && s->dma_adc.ready && (! (s->enable & ADC_RUNNING)) ) {
1315
1316 s->enable |= ADC_RUNNING;
1317 apu_set_register(s, 2, 0,
1318 (apu_get_register(s, 2, 0)&0xFF0F)|s->apu_mode[2]);
1319 apu_set_register(s, 4, 0,
1320 (apu_get_register(s, 4, 0)&0xFF0F)|s->apu_mode[4]);
1321
1322 if( s->fmt & (ESS_FMT_STEREO << ESS_ADC_SHIFT)) {
1323 apu_set_register(s, 3, 0,
1324 (apu_get_register(s, 3, 0)&0xFF0F)|s->apu_mode[3]);
1325 apu_set_register(s, 5, 0,
1326 (apu_get_register(s, 5, 0)&0xFF0F)|s->apu_mode[5]);
1327 }
1328
1329 }
1330 }
1331
1332
1333 /*
1334 * Native play back driver
1335 */
1336
1337 /* the mode passed should be already shifted and masked */
1338 static void
1339 ess_play_setup(struct ess_state *ess, int mode, u32 rate, void *buffer, int size)
1340 {
1341 u32 pa;
1342 u32 tmpval;
1343 int high_apu = 0;
1344 int channel;
1345
1346 M_printk("mode=%d rate=%d buf=%p len=%d.\n",
1347 mode, rate, buffer, size);
1348
1349 /* all maestro sizes are in 16bit words */
1350 size >>=1;
1351
1352 if(mode&ESS_FMT_STEREO) {
1353 high_apu++;
1354 /* only 16/stereo gets size divided */
1355 if(mode&ESS_FMT_16BIT)
1356 size>>=1;
1357 }
1358
1359 for(channel=0; channel <= high_apu; channel++)
1360 {
1361 pa = virt_to_bus(buffer);
1362
1363 /* set the wavecache control reg */
1364 tmpval = (pa - 0x10) & 0xFFF8;
1365 if(!(mode & ESS_FMT_16BIT)) tmpval |= 4;
1366 if(mode & ESS_FMT_STEREO) tmpval |= 2;
1367 ess->apu_base[channel]=tmpval;
1368 wave_set_register(ess, ess->apu[channel]<<3, tmpval);
1369
1370 pa -= virt_to_bus(ess->card->dmapages);
1371 pa>>=1; /* words */
1372
1373 /* base offset of dma calcs when reading the pointer
1374 on the left one */
1375 if(!channel) ess->dma_dac.base = pa&0xFFFF;
1376
1377 pa|=0x00400000; /* System RAM */
1378
1379 /* XXX the 16bit here might not be needed.. */
1380 if((mode & ESS_FMT_STEREO) && (mode & ESS_FMT_16BIT)) {
1381 if(channel)
1382 pa|=0x00800000; /* Stereo */
1383 pa>>=1;
1384 }
1385
1386 /* XXX think about endianess when writing these registers */
1387 M_printk("maestro: ess_play_setup: APU[%d] pa = 0x%x\n", ess->apu[channel], pa);
1388 /* start of sample */
1389 apu_set_register(ess, channel, 4, ((pa>>16)&0xFF)<<8);
1390 apu_set_register(ess, channel, 5, pa&0xFFFF);
1391 /* sample end */
1392 apu_set_register(ess, channel, 6, (pa+size)&0xFFFF);
1393 /* setting loop len == sample len */
1394 apu_set_register(ess, channel, 7, size);
1395
1396 /* clear effects/env.. */
1397 apu_set_register(ess, channel, 8, 0x0000);
1398 /* set amp now to 0xd0 (?), low byte is 'amplitude dest'? */
1399 apu_set_register(ess, channel, 9, 0xD000);
1400
1401 /* clear routing stuff */
1402 apu_set_register(ess, channel, 11, 0x0000);
1403 /* dma on, no envelopes, filter to all 1s) */
1404 apu_set_register(ess, channel, 0, 0x400F);
1405
1406 if(mode&ESS_FMT_16BIT)
1407 ess->apu_mode[channel]=0x10;
1408 else
1409 ess->apu_mode[channel]=0x30;
1410
1411 if(mode&ESS_FMT_STEREO) {
1412 /* set panning: left or right */
1413 apu_set_register(ess, channel, 10, 0x8F00 | (channel ? 0 : 0x10));
1414 ess->apu_mode[channel] += 0x10;
1415 } else
1416 apu_set_register(ess, channel, 10, 0x8F08);
1417 }
1418
1419 /* clear WP interupts */
1420 outw(1, ess->card->iobase+0x04);
1421 /* enable WP ints */
1422 outw(inw(ess->card->iobase+0x18)|4, ess->card->iobase+0x18);
1423
1424 /* go team! */
1425 set_dac_rate(ess,rate);
1426 start_dac(ess);
1427 }
1428
1429 /*
1430 * Native record driver
1431 */
1432
1433 /* again, passed mode is alrady shifted/masked */
1434 static void
1435 ess_rec_setup(struct ess_state *ess, int mode, u32 rate, void *buffer, int size)
1436 {
1437 int apu_step = 2;
1438 int channel;
1439
1440 M_printk("maestro: ess_rec_setup: mode=%d rate=%d buf=0x%p len=%d.\n",
1441 mode, rate, buffer, size);
1442
1443 /* all maestro sizes are in 16bit words */
1444 size >>=1;
1445
1446 /* we're given the full size of the buffer, but
1447 in stereo each channel will only use its half */
1448 if(mode&ESS_FMT_STEREO) {
1449 size >>=1;
1450 apu_step = 1;
1451 }
1452
1453 /* APU assignments: 2 = mono/left SRC
1454 3 = right SRC
1455 4 = mono/left Input Mixer
1456 5 = right Input Mixer */
1457 for(channel=2;channel<6;channel+=apu_step)
1458 {
1459 int i;
1460 int bsize, route;
1461 u32 pa;
1462 u32 tmpval;
1463
1464 /* data seems to flow from the codec, through an apu into
1465 the 'mixbuf' bit of page, then through the SRC apu
1466 and out to the real 'buffer'. ok. sure. */
1467
1468 if(channel & 0x04) {
1469 /* ok, we're an input mixer going from adc
1470 through the mixbuf to the other apus */
1471
1472 if(!(channel & 0x01)) {
1473 pa = virt_to_bus(ess->mixbuf);
1474 } else {
1475 pa = virt_to_bus(ess->mixbuf + (PAGE_SIZE >> 4));
1476 }
1477
1478 /* we source from a 'magic' apu */
1479 bsize = PAGE_SIZE >> 5; /* half of this channels alloc, in words */
1480 route = 0x14 + (channel - 4); /* parallel in crap, see maestro reg 0xC [8-11] */
1481 ess->apu_mode[channel] = 0x90; /* Input Mixer */
1482
1483 } else {
1484 /* we're a rate converter taking
1485 input from the input apus and outputing it to
1486 system memory */
1487 if(!(channel & 0x01)) {
1488 pa = virt_to_bus(buffer);
1489 } else {
1490 /* right channel records its split half.
1491 *2 accomodates for rampant shifting earlier */
1492 pa = virt_to_bus(buffer + size*2);
1493 }
1494
1495 ess->apu_mode[channel] = 0xB0; /* Sample Rate Converter */
1496
1497 bsize = size;
1498 /* get input from inputing apu */
1499 route = channel + 2;
1500 }
1501
1502 M_printk("maestro: ess_rec_setup: getting pa 0x%x from %d\n",pa,channel);
1503
1504 /* set the wavecache control reg */
1505 tmpval = (pa - 0x10) & 0xFFF8;
1506 ess->apu_base[channel]=tmpval;
1507 wave_set_register(ess, ess->apu[channel]<<3, tmpval);
1508
1509 pa -= virt_to_bus(ess->card->dmapages);
1510 pa>>=1; /* words */
1511
1512 /* base offset of dma calcs when reading the pointer
1513 on this left one */
1514 if(channel==2) ess->dma_adc.base = pa&0xFFFF;
1515
1516 pa|=0x00400000; /* bit 22 -> System RAM */
1517
1518 M_printk("maestro: ess_rec_setup: APU[%d] pa = 0x%x size = 0x%x route = 0x%x\n",
1519 ess->apu[channel], pa, bsize, route);
1520
1521 /* Begin loading the APU */
1522 for(i=0;i<15;i++) /* clear all PBRs */
1523 apu_set_register(ess, channel, i, 0x0000);
1524
1525 apu_set_register(ess, channel, 0, 0x400F);
1526
1527 /* need to enable subgroups.. and we should probably
1528 have different groups for different /dev/dsps.. */
1529 apu_set_register(ess, channel, 2, 0x8);
1530
1531 /* Load the buffer into the wave engine */
1532 apu_set_register(ess, channel, 4, ((pa>>16)&0xFF)<<8);
1533 /* XXX reg is little endian.. */
1534 apu_set_register(ess, channel, 5, pa&0xFFFF);
1535 apu_set_register(ess, channel, 6, (pa+bsize)&0xFFFF);
1536 apu_set_register(ess, channel, 7, bsize);
1537
1538 /* clear effects/env.. */
1539 apu_set_register(ess, channel, 8, 0x00F0);
1540
1541 /* amplitude now? sure. why not. */
1542 apu_set_register(ess, channel, 9, 0x0000);
1543
1544 /* set filter tune, radius, polar pan */
1545 apu_set_register(ess, channel, 10, 0x8F08);
1546
1547 /* route input */
1548 apu_set_register(ess, channel, 11, route);
1549 }
1550
1551 /* clear WP interupts */
1552 outw(1, ess->card->iobase+0x04);
1553 /* enable WP ints */
1554 outw(inw(ess->card->iobase+0x18)|4, ess->card->iobase+0x18);
1555
1556 /* let 'er rip */
1557 set_adc_rate(ess,rate);
1558 start_adc(ess);
1559 }
1560 /* --------------------------------------------------------------------- */
1561
1562 static void set_dmaa(struct ess_state *s, unsigned int addr, unsigned int count)
1563 {
1564 M_printk("set_dmaa??\n");
1565 }
1566
1567 static void set_dmac(struct ess_state *s, unsigned int addr, unsigned int count)
1568 {
1569 M_printk("set_dmac??\n");
1570 }
1571
1572 /* Playback pointer */
1573 extern __inline__ unsigned get_dmaa(struct ess_state *s)
1574 {
1575 int offset;
1576
1577 offset = apu_get_register(s,0,5);
1578
1579 /* M_printk("dmaa: offset: %d, base: %d\n",offset,s->dma_dac.base); */
1580
1581 offset-=s->dma_dac.base;
1582
1583 return (offset&0xFFFE)<<1; /* hardware is in words */
1584 }
1585
1586 /* Record pointer */
1587 extern __inline__ unsigned get_dmac(struct ess_state *s)
1588 {
1589 int offset;
1590
1591 offset = apu_get_register(s,2,5);
1592
1593 /* M_printk("dmac: offset: %d, base: %d\n",offset,s->dma_adc.base); */
1594
1595 /* The offset is an address not a position relative to base */
1596 offset-=s->dma_adc.base;
1597
1598 return (offset&0xFFFE)<<1; /* hardware is in words */
1599 }
1600
1601 /*
1602 * Meet Bob, the timer...
1603 */
1604
1605 static void ess_interrupt(int irq, void *dev_id, struct pt_regs *regs);
1606
1607 static void stop_bob(struct ess_state *s)
1608 {
1609 /* Mask IDR 11,17 */
1610 maestro_write(s, 0x11, maestro_read(s, 0x11)&~1);
1611 maestro_write(s, 0x17, maestro_read(s, 0x17)&~1);
1612 }
1613
1614 /* eventually we could be clever and limit bob ints
1615 to the frequency at which our smallest duration
1616 chunks may expire */
1617 #define ESS_SYSCLK 50000000
1618 static void start_bob(struct ess_state *s)
1619 {
1620 int prescale;
1621 int divide;
1622
1623 /* XXX make freq selector much smarter, see calc_bob_rate */
1624 int freq = 200;
1625
1626 /* compute ideal interrupt frequency for buffer size & play rate */
1627 /* first, find best prescaler value to match freq */
1628 for(prescale=5;prescale<12;prescale++)
1629 if(freq > (ESS_SYSCLK>>(prescale+9)))
1630 break;
1631
1632 /* next, back off prescaler whilst getting divider into optimum range */
1633 divide=1;
1634 while((prescale > 5) && (divide<32))
1635 {
1636 prescale--;
1637 divide <<=1;
1638 }
1639 divide>>=1;
1640
1641 /* now fine-tune the divider for best match */
1642 for(;divide<31;divide++)
1643 if(freq >= ((ESS_SYSCLK>>(prescale+9))/(divide+1)))
1644 break;
1645
1646 /* divide = 0 is illegal, but don't let prescale = 4! */
1647 if(divide == 0)
1648 {
1649 divide++;
1650 if(prescale>5)
1651 prescale--;
1652 }
1653
1654 maestro_write(s, 6, 0x9000 | (prescale<<5) | divide); /* set reg */
1655
1656 /* Now set IDR 11/17 */
1657 maestro_write(s, 0x11, maestro_read(s, 0x11)|1);
1658 maestro_write(s, 0x17, maestro_read(s, 0x17)|1);
1659 }
1660 /* --------------------------------------------------------------------- */
1661
1662 /* this quickly calculates the frequency needed for bob
1663 and sets it if its different than what bob is
1664 currently running at. its called often so
1665 needs to be fairly quick. */
1666 #define BOB_MIN 50
1667 #define BOB_MAX 400
1668 static void calc_bob_rate(struct ess_state *s) {
1669 #if 0 /* this thing tries to set the frequency of bob such that
1670 there are 2 interrupts / buffer walked by the dac/adc. That
1671 is probably very wrong for people who actually care about
1672 mid buffer positioning. it should be calculated as bytes/interrupt
1673 and that needs to be decided :) so for now just use the static 150
1674 in start_bob.*/
1675
1676 unsigned int dac_rate=2,adc_rate=1,newrate;
1677 static int israte=-1;
1678
1679 if (s->dma_dac.fragsize == 0) dac_rate = BOB_MIN;
1680 else {
1681 dac_rate = (2 * s->ratedac * sample_size[(s->fmt >> ESS_DAC_SHIFT) & ESS_FMT_MASK]) /
1682 (s->dma_dac.fragsize) ;
1683 }
1684
1685 if (s->dma_adc.fragsize == 0) adc_rate = BOB_MIN;
1686 else {
1687 adc_rate = (2 * s->rateadc * sample_size[(s->fmt >> ESS_DAC_SHIFT) & ESS_FMT_MASK]) /
1688 (s->dma_adc.fragsize) ;
1689 }
1690
1691 if(dac_rate > adc_rate) newrate = adc_rate;
1692 else newrate=dac_rate;
1693
1694 if(newrate > BOB_MAX) newrate = BOB_MAX;
1695 else {
1696 if(newrate < BOB_MIN)
1697 newrate = BOB_MIN;
1698 }
1699
1700 if( israte != newrate) {
1701 printk("dac: %d adc: %d rate: %d\n",dac_rate,adc_rate,israte);
1702 israte=newrate;
1703 }
1704 #endif
1705
1706 }
1707
1708 static int
1709 prog_dmabuf(struct ess_state *s, unsigned rec)
1710 {
1711 struct dmabuf *db = rec ? &s->dma_adc : &s->dma_dac;
1712 unsigned rate = rec ? s->rateadc : s->ratedac;
1713 unsigned bytepersec;
1714 unsigned bufs;
1715 unsigned char fmt;
1716 unsigned long flags;
1717
1718 spin_lock_irqsave(&s->lock, flags);
1719 fmt = s->fmt;
1720 if (rec) {
1721 stop_adc(s);
1722 fmt >>= ESS_ADC_SHIFT;
1723 } else {
1724 stop_dac(s);
1725 fmt >>= ESS_DAC_SHIFT;
1726 }
1727 spin_unlock_irqrestore(&s->lock, flags);
1728 fmt &= ESS_FMT_MASK;
1729
1730 db->hwptr = db->swptr = db->total_bytes = db->count = db->error = db->endcleared = 0;
1731
1732 /* this algorithm is a little nuts.. where did /1000 come from? */
1733 bytepersec = rate << sample_shift[fmt];
1734 bufs = PAGE_SIZE << db->buforder;
1735 if (db->ossfragshift) {
1736 if ((1000 << db->ossfragshift) < bytepersec)
1737 db->fragshift = ld2(bytepersec/1000);
1738 else
1739 db->fragshift = db->ossfragshift;
1740 } else {
1741 db->fragshift = ld2(bytepersec/100/(db->subdivision ? db->subdivision : 1));
1742 if (db->fragshift < 3)
1743 db->fragshift = 3;
1744 }
1745 db->numfrag = bufs >> db->fragshift;
1746 while (db->numfrag < 4 && db->fragshift > 3) {
1747 db->fragshift--;
1748 db->numfrag = bufs >> db->fragshift;
1749 }
1750 db->fragsize = 1 << db->fragshift;
1751 if (db->ossmaxfrags >= 4 && db->ossmaxfrags < db->numfrag)
1752 db->numfrag = db->ossmaxfrags;
1753 db->fragsamples = db->fragsize >> sample_shift[fmt];
1754 db->dmasize = db->numfrag << db->fragshift;
1755
1756 M_printk("maestro: setup oss: numfrag: %d fragsize: %d dmasize: %d\n",db->numfrag,db->fragsize,db->dmasize);
1757
1758 memset(db->rawbuf, (fmt & ESS_FMT_16BIT) ? 0 : 0x80, db->dmasize);
1759
1760 spin_lock_irqsave(&s->lock, flags);
1761 if (rec)
1762 ess_rec_setup(s, fmt, s->rateadc, db->rawbuf, db->dmasize);
1763 else
1764 ess_play_setup(s, fmt, s->ratedac, db->rawbuf, db->dmasize);
1765
1766 spin_unlock_irqrestore(&s->lock, flags);
1767 db->ready = 1;
1768
1769 return 0;
1770 }
1771
1772 static __inline__ void
1773 clear_advance(struct ess_state *s)
1774 {
1775 unsigned char c = ((s->fmt >> ESS_DAC_SHIFT) & ESS_FMT_16BIT) ? 0 : 0x80;
1776
1777 unsigned char *buf = s->dma_dac.rawbuf;
1778 unsigned bsize = s->dma_dac.dmasize;
1779 unsigned bptr = s->dma_dac.swptr;
1780 unsigned len = s->dma_dac.fragsize;
1781
1782 if (bptr + len > bsize) {
1783 unsigned x = bsize - bptr;
1784 memset(buf + bptr, c, x);
1785 /* account for wrapping? */
1786 bptr = 0;
1787 len -= x;
1788 }
1789 memset(buf + bptr, c, len);
1790 }
1791
1792 /* call with spinlock held! */
1793 static void
1794 ess_update_ptr(struct ess_state *s)
1795 {
1796 unsigned hwptr;
1797 int diff;
1798
1799 /* update ADC pointer */
1800 if (s->dma_adc.ready) {
1801 /* oh boy should this all be re-written. everything in the current code paths think
1802 that the various counters/pointers are expressed in bytes to the user but we have
1803 two apus doing stereo stuff so we fix it up here.. it propogates to all the various
1804 counters from here. */
1805 if ( s->fmt & (ESS_FMT_STEREO << ESS_ADC_SHIFT)) {
1806 hwptr = (get_dmac(s)*2) % s->dma_adc.dmasize;
1807 } else {
1808 hwptr = get_dmac(s) % s->dma_adc.dmasize;
1809 }
1810 diff = (s->dma_adc.dmasize + hwptr - s->dma_adc.hwptr) % s->dma_adc.dmasize;
1811 s->dma_adc.hwptr = hwptr;
1812 s->dma_adc.total_bytes += diff;
1813 s->dma_adc.count += diff;
1814 if (s->dma_adc.count >= (signed)s->dma_adc.fragsize)
1815 wake_up(&s->dma_adc.wait);
1816 if (!s->dma_adc.mapped) {
1817 if (s->dma_adc.count > (signed)(s->dma_adc.dmasize - ((3 * s->dma_adc.fragsize) >> 1))) {
1818 /* FILL ME
1819 wrindir(s, SV_CIENABLE, s->enable); */
1820 stop_adc(s);
1821 /* brute force everyone back in sync, sigh */
1822 s->dma_adc.count = 0;
1823 s->dma_adc.swptr = 0;
1824 s->dma_adc.hwptr = 0;
1825 s->dma_adc.error++;
1826 }
1827 }
1828 }
1829 /* update DAC pointer */
1830 if (s->dma_dac.ready) {
1831 hwptr = get_dmaa(s) % s->dma_dac.dmasize;
1832 /* the apu only reports the length it has seen, not the
1833 length of the memory that has been used (the WP
1834 knows that) */
1835 if ( ((s->fmt >> ESS_DAC_SHIFT) & ESS_FMT_MASK) == (ESS_FMT_STEREO|ESS_FMT_16BIT))
1836 hwptr<<=1;
1837
1838 diff = (s->dma_dac.dmasize + hwptr - s->dma_dac.hwptr) % s->dma_dac.dmasize;
1839 /* M_printk("updating dac: hwptr: %d diff: %d\n",hwptr,diff);*/
1840 s->dma_dac.hwptr = hwptr;
1841 s->dma_dac.total_bytes += diff;
1842 if (s->dma_dac.mapped) {
1843 s->dma_dac.count += diff;
1844 if (s->dma_dac.count >= (signed)s->dma_dac.fragsize) {
1845 wake_up(&s->dma_dac.wait);
1846 }
1847 } else {
1848 s->dma_dac.count -= diff;
1849 /* M_printk("maestro: ess_update_ptr: diff: %d, count: %d\n", diff, s->dma_dac.count); */
1850 if (s->dma_dac.count <= 0) {
1851 M_printk("underflow! diff: %d count: %d hw: %d sw: %d\n", diff, s->dma_dac.count,
1852 hwptr, s->dma_dac.swptr);
1853 /* FILL ME
1854 wrindir(s, SV_CIENABLE, s->enable); */
1855 /* XXX how on earth can calling this with the lock held work.. */
1856 stop_dac(s);
1857 /* brute force everyone back in sync, sigh */
1858 s->dma_dac.count = 0;
1859 s->dma_dac.swptr = hwptr;
1860 s->dma_dac.error++;
1861 } else if (s->dma_dac.count <= (signed)s->dma_dac.fragsize && !s->dma_dac.endcleared) {
1862 clear_advance(s);
1863 s->dma_dac.endcleared = 1;
1864 }
1865 if (s->dma_dac.count + (signed)s->dma_dac.fragsize <= (signed)s->dma_dac.dmasize) {
1866 wake_up(&s->dma_dac.wait);
1867 /* printk("waking up DAC count: %d sw: %d hw: %d\n",s->dma_dac.count, s->dma_dac.swptr,
1868 hwptr);*/
1869 }
1870 }
1871 }
1872 }
1873
1874 static void
1875 ess_interrupt(int irq, void *dev_id, struct pt_regs *regs)
1876 {
1877 struct ess_state *s;
1878 struct ess_card *c = (struct ess_card *)dev_id;
1879 int i;
1880 u32 event;
1881
1882 if ( ! (event = inb(c->iobase+0x1A)) ) return;
1883
1884 outw(inw(c->iobase+4)&1, c->iobase+4);
1885
1886 /* M_printk("maestro int: %x\n",event);*/
1887
1888 if(event&(1<<6))
1889 {
1890 /* XXX if we have a hw volume control int enable
1891 all the ints? doesn't make sense.. */
1892 event = inw(c->iobase+0x18);
1893 outb(0xFF, c->iobase+0x1A);
1894 }
1895 else
1896 {
1897 /* else ack 'em all, i imagine */
1898 outb(0xFF, c->iobase+0x1A);
1899 }
1900
1901 /*
1902 * Update the pointers for all APU's we are running.
1903 */
1904 for(i=0;i<NR_DSPS;i++)
1905 {
1906 s=&c->channels[i];
1907 if(s->dev_audio == -1)
1908 break;
1909 spin_lock(&s->lock);
1910 ess_update_ptr(s);
1911 spin_unlock(&s->lock);
1912 }
1913 }
1914
1915
1916 /* --------------------------------------------------------------------- */
1917
1918 static const char invalid_magic[] = KERN_CRIT "maestro: invalid magic value in %s\n";
1919
1920 #define VALIDATE_MAGIC(FOO,MAG) \
1921 ({ \
1922 if (!(FOO) || (FOO)->magic != MAG) { \
1923 printk(invalid_magic,__FUNCTION__); \
1924 return -ENXIO; \
1925 } \
1926 })
1927
1928 #define VALIDATE_STATE(a) VALIDATE_MAGIC(a,ESS_STATE_MAGIC)
1929 #define VALIDATE_CARD(a) VALIDATE_MAGIC(a,ESS_CARD_MAGIC)
1930
1931 static void set_mixer(struct ess_card *card,unsigned int mixer, unsigned int val )
1932 {
1933 unsigned int left,right;
1934 /* cleanse input a little */
1935 right = ((val >> 8) & 0xff) ;
1936 left = (val & 0xff) ;
1937
1938 if(right > 100) right = 100;
1939 if(left > 100) left = 100;
1940
1941 card->mix.mixer_state[mixer]=(right << 8) | left;
1942 card->mix.write_mixer(card,mixer,left,right);
1943 }
1944
1945 static void
1946 mixer_push_state(struct ess_card *card)
1947 {
1948 int i;
1949 for(i = 0 ; i < SOUND_MIXER_NRDEVICES ; i++) {
1950 if( ! supported_mixer(card,i)) continue;
1951
1952 set_mixer(card,i,card->mix.mixer_state[i]);
1953 }
1954 }
1955
1956 static int mixer_ioctl(struct ess_card *card, unsigned int cmd, unsigned long arg)
1957 {
1958 int i, val=0;
1959
1960 VALIDATE_CARD(card);
1961 if (cmd == SOUND_MIXER_INFO) {
1962 mixer_info info;
1963 strncpy(info.id, card_names[card->card_type], sizeof(info.id));
1964 strncpy(info.name,card_names[card->card_type],sizeof(info.name));
1965 info.modify_counter = card->mix.modcnt;
1966 if (copy_to_user((void *)arg, &info, sizeof(info)))
1967 return -EFAULT;
1968 return 0;
1969 }
1970 if (cmd == SOUND_OLD_MIXER_INFO) {
1971 _old_mixer_info info;
1972 strncpy(info.id, card_names[card->card_type], sizeof(info.id));
1973 strncpy(info.name,card_names[card->card_type],sizeof(info.name));
1974 if (copy_to_user((void *)arg, &info, sizeof(info)))
1975 return -EFAULT;
1976 return 0;
1977 }
1978 if (cmd == OSS_GETVERSION)
1979 return put_user(SOUND_VERSION, (int *)arg);
1980
1981 if (_IOC_TYPE(cmd) != 'M' || _IOC_SIZE(cmd) != sizeof(int))
1982 return -EINVAL;
1983
1984 if (_IOC_DIR(cmd) == _IOC_READ) {
1985 switch (_IOC_NR(cmd)) {
1986 case SOUND_MIXER_RECSRC: /* give them the current record source */
1987
1988 if(!card->mix.recmask_io) {
1989 val = 0;
1990 } else {
1991 spin_lock(&card->lock);
1992 val = card->mix.recmask_io(card,1,0);
1993 spin_unlock(&card->lock);
1994 }
1995 break;
1996
1997 case SOUND_MIXER_DEVMASK: /* give them the supported mixers */
1998 val = card->mix.supported_mixers;
1999 break;
2000
2001 case SOUND_MIXER_RECMASK: /* Arg contains a bit for each supported recording source */
2002 val = card->mix.record_sources;
2003 break;
2004
2005 case SOUND_MIXER_STEREODEVS: /* Mixer channels supporting stereo */
2006 val = card->mix.stereo_mixers;
2007 break;
2008
2009 case SOUND_MIXER_CAPS:
2010 val = SOUND_CAP_EXCL_INPUT;
2011 break;
2012
2013 default: /* read a specific mixer */
2014 i = _IOC_NR(cmd);
2015
2016 if ( ! supported_mixer(card,i))
2017 return -EINVAL;
2018
2019 /* do we ever want to touch the hardware? */
2020 /* spin_lock(&card->lock);
2021 val = card->mix.read_mixer(card,i);
2022 spin_unlock(&card->lock);*/
2023
2024 val = card->mix.mixer_state[i];
2025 /* M_printk("returned 0x%x for mixer %d\n",val,i);*/
2026
2027 break;
2028 }
2029 return put_user(val,(int *)arg);
2030 }
2031
2032 if (_IOC_DIR(cmd) != (_IOC_WRITE|_IOC_READ))
2033 return -EINVAL;
2034
2035 card->mix.modcnt++;
2036
2037 if (get_user(val, (int *)arg))
2038 return -EFAULT;
2039
2040 switch (_IOC_NR(cmd)) {
2041 case SOUND_MIXER_RECSRC: /* Arg contains a bit for each recording source */
2042
2043 if (!card->mix.recmask_io) return -EINVAL;
2044 if(!val) return 0;
2045 if(! (val &= card->mix.record_sources)) return -EINVAL;
2046
2047 spin_lock(&card->lock);
2048 card->mix.recmask_io(card,0,val);
2049 spin_unlock(&card->lock);
2050 return 0;
2051
2052 default:
2053 i = _IOC_NR(cmd);
2054
2055 if ( ! supported_mixer(card,i))
2056 return -EINVAL;
2057
2058 spin_lock(&card->lock);
2059 set_mixer(card,i,val);
2060 spin_unlock(&card->lock);
2061
2062 return 0;
2063 }
2064 }
2065
2066 /* --------------------------------------------------------------------- */
2067
2068 static loff_t ess_llseek(struct file *file, loff_t offset, int origin)
2069 {
2070 return -ESPIPE;
2071 }
2072
2073 /* --------------------------------------------------------------------- */
2074
2075 static int ess_open_mixdev(struct inode *inode, struct file *file)
2076 {
2077 int minor = MINOR(inode->i_rdev);
2078 struct ess_card *card = devs;
2079
2080 while (card && card->dev_mixer != minor)
2081 card = card->next;
2082 if (!card)
2083 return -ENODEV;
2084
2085 file->private_data = card;
2086 return 0;
2087 }
2088
2089 static int ess_release_mixdev(struct inode *inode, struct file *file)
2090 {
2091 struct ess_card *card = (struct ess_card *)file->private_data;
2092
2093 VALIDATE_CARD(card);
2094
2095 return 0;
2096 }
2097
2098 static int ess_ioctl_mixdev(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg)
2099 {
2100 struct ess_card *card = (struct ess_card *)file->private_data;
2101
2102 VALIDATE_CARD(card);
2103
2104 return mixer_ioctl(card, cmd, arg);
2105 }
2106
2107 static /*const*/ struct file_operations ess_mixer_fops = {
2108 owner: THIS_MODULE,
2109 llseek: ess_llseek,
2110 ioctl: ess_ioctl_mixdev,
2111 open: ess_open_mixdev,
2112 release: ess_release_mixdev,
2113 };
2114
2115 /* --------------------------------------------------------------------- */
2116
2117 static int drain_dac(struct ess_state *s, int nonblock)
2118 {
2119 DECLARE_WAITQUEUE(wait,current);
2120 unsigned long flags;
2121 int count;
2122 signed long tmo;
2123
2124 if (s->dma_dac.mapped || !s->dma_dac.ready)
2125 return 0;
2126 current->state = TASK_INTERRUPTIBLE;
2127 add_wait_queue(&s->dma_dac.wait, &wait);
2128 for (;;) {
2129 /* XXX uhm.. questionable locking*/
2130 spin_lock_irqsave(&s->lock, flags);
2131 count = s->dma_dac.count;
2132 spin_unlock_irqrestore(&s->lock, flags);
2133 if (count <= 0)
2134 break;
2135 if (signal_pending(current))
2136 break;
2137 if (nonblock) {
2138 remove_wait_queue(&s->dma_dac.wait, &wait);
2139 current->state = TASK_RUNNING;
2140 return -EBUSY;
2141 }
2142 tmo = (count * HZ) / s->ratedac;
2143 tmo >>= sample_shift[(s->fmt >> ESS_DAC_SHIFT) & ESS_FMT_MASK];
2144 /* XXX this is just broken. someone is waking us up alot, or schedule_timeout is broken.
2145 or something. who cares. - zach */
2146 if (!schedule_timeout(tmo ? tmo : 1) && tmo)
2147 M_printk(KERN_DEBUG "maestro: dma timed out?? %ld\n",jiffies);
2148 }
2149 remove_wait_queue(&s->dma_dac.wait, &wait);
2150 current->state = TASK_RUNNING;
2151 if (signal_pending(current))
2152 return -ERESTARTSYS;
2153 return 0;
2154 }
2155
2156 /* --------------------------------------------------------------------- */
2157 /* Zach sez: "god this is gross.." */
2158 static int
2159 comb_stereo(unsigned char *real_buffer,unsigned char *tmp_buffer, int offset,
2160 int count, int bufsize)
2161 {
2162 /* No such thing as stereo recording, so we
2163 use dual input mixers. which means we have to
2164 combine mono to stereo buffer. yuck.
2165
2166 but we don't have to be able to work a byte at a time..*/
2167
2168 unsigned char *so,*left,*right;
2169 int i;
2170
2171 so = tmp_buffer;
2172 left = real_buffer + offset;
2173 right = real_buffer + bufsize/2 + offset;
2174
2175 /* M_printk("comb_stereo writing %d to %p from %p and %p, offset: %d size: %d\n",count/2, tmp_buffer,left,right,offset,bufsize);*/
2176
2177 for(i=count/4; i ; i--) {
2178 (*(so+2)) = *(right++);
2179 (*(so+3)) = *(right++);
2180 (*so) = *(left++);
2181 (*(so+1)) = *(left++);
2182 so+=4;
2183 }
2184
2185 return 0;
2186 }
2187
2188 /* in this loop, dma_adc.count signifies the amount of data thats waiting
2189 to be copied to the user's buffer. it is filled by the interrupt
2190 handler and drained by this loop. */
2191 static ssize_t
2192 ess_read(struct file *file, char *buffer, size_t count, loff_t *ppos)
2193 {
2194 struct ess_state *s = (struct ess_state *)file->private_data;
2195 ssize_t ret;
2196 unsigned long flags;
2197 unsigned swptr;
2198 int cnt;
2199 unsigned char *combbuf = NULL;
2200
2201 VALIDATE_STATE(s);
2202 if (ppos != &file->f_pos)
2203 return -ESPIPE;
2204 if (s->dma_adc.mapped)
2205 return -ENXIO;
2206 if (!s->dma_adc.ready && (ret = prog_dmabuf(s, 1)))
2207 return ret;
2208 if (!access_ok(VERIFY_WRITE, buffer, count))
2209 return -EFAULT;
2210 if(!(combbuf = kmalloc(count,GFP_KERNEL)))
2211 return -ENOMEM;
2212 ret = 0;
2213
2214 calc_bob_rate(s);
2215
2216 while (count > 0) {
2217 spin_lock_irqsave(&s->lock, flags);
2218 /* remember, all these things are expressed in bytes to be
2219 sent to the user.. hence the evil / 2 down below */
2220 swptr = s->dma_adc.swptr;
2221 cnt = s->dma_adc.dmasize-swptr;
2222 if (s->dma_adc.count < cnt)
2223 cnt = s->dma_adc.count;
2224 spin_unlock_irqrestore(&s->lock, flags);
2225
2226 if (cnt > count)
2227 cnt = count;
2228
2229 if ( cnt > 0 ) cnt &= ~3;
2230
2231 if (cnt <= 0) {
2232 start_adc(s);
2233 if (file->f_flags & O_NONBLOCK)
2234 {
2235 ret = ret ? ret : -EAGAIN;
2236 goto rec_return_free;
2237 }
2238 if (!interruptible_sleep_on_timeout(&s->dma_adc.wait, HZ)) {
2239 if(! s->card->in_suspend) printk(KERN_DEBUG "maestro: read: chip lockup? dmasz %u fragsz %u count %i hwptr %u swptr %u\n",
2240 s->dma_adc.dmasize, s->dma_adc.fragsize, s->dma_adc.count,
2241 s->dma_adc.hwptr, s->dma_adc.swptr);
2242 stop_adc(s);
2243 spin_lock_irqsave(&s->lock, flags);
2244 set_dmac(s, virt_to_bus(s->dma_adc.rawbuf), s->dma_adc.numfrag << s->dma_adc.fragshift);
2245 /* program enhanced mode registers */
2246 /* FILL ME */
2247 /* wrindir(s, SV_CIDMACBASECOUNT1, (s->dma_adc.fragsamples-1) >> 8);
2248 wrindir(s, SV_CIDMACBASECOUNT0, s->dma_adc.fragsamples-1); */
2249 s->dma_adc.count = s->dma_adc.hwptr = s->dma_adc.swptr = 0;
2250 spin_unlock_irqrestore(&s->lock, flags);
2251 }
2252 if (signal_pending(current))
2253 {
2254 ret = ret ? ret : -ERESTARTSYS;
2255 goto rec_return_free;
2256 }
2257 continue;
2258 }
2259
2260 if(s->fmt & (ESS_FMT_STEREO << ESS_ADC_SHIFT)) {
2261 /* swptr/2 so that we know the real offset in each apu's buffer */
2262 comb_stereo(s->dma_adc.rawbuf,combbuf,swptr/2,cnt,s->dma_adc.dmasize);
2263 if (copy_to_user(buffer, combbuf, cnt)) {
2264 ret = ret ? ret : -EFAULT;
2265 goto rec_return_free;
2266 }
2267 } else {
2268 if (copy_to_user(buffer, s->dma_adc.rawbuf + swptr, cnt)) {
2269 ret = ret ? ret : -EFAULT;
2270 goto rec_return_free;
2271 }
2272 }
2273
2274 swptr = (swptr + cnt) % s->dma_adc.dmasize;
2275 spin_lock_irqsave(&s->lock, flags);
2276 s->dma_adc.swptr = swptr;
2277 s->dma_adc.count -= cnt;
2278 spin_unlock_irqrestore(&s->lock, flags);
2279 count -= cnt;
2280 buffer += cnt;
2281 ret += cnt;
2282 start_adc(s);
2283 }
2284
2285 rec_return_free:
2286 if(combbuf) kfree(combbuf);
2287 return ret;
2288 }
2289
2290 static ssize_t
2291 ess_write(struct file *file, const char *buffer, size_t count, loff_t *ppos)
2292 {
2293 struct ess_state *s = (struct ess_state *)file->private_data;
2294 ssize_t ret;
2295 unsigned long flags;
2296 unsigned swptr;
2297 int cnt;
2298
2299 VALIDATE_STATE(s);
2300 if (ppos != &file->f_pos)
2301 return -ESPIPE;
2302 if (s->dma_dac.mapped)
2303 return -ENXIO;
2304 if (!s->dma_dac.ready && (ret = prog_dmabuf(s, 0)))
2305 return ret;
2306 if (!access_ok(VERIFY_READ, buffer, count))
2307 return -EFAULT;
2308 ret = 0;
2309
2310 calc_bob_rate(s);
2311
2312 while (count > 0) {
2313 spin_lock_irqsave(&s->lock, flags);
2314
2315 if (s->dma_dac.count < 0) {
2316 s->dma_dac.count = 0;
2317 s->dma_dac.swptr = s->dma_dac.hwptr;
2318 }
2319 swptr = s->dma_dac.swptr;
2320
2321 cnt = s->dma_dac.dmasize-swptr;
2322
2323 if (s->dma_dac.count + cnt > s->dma_dac.dmasize)
2324 cnt = s->dma_dac.dmasize - s->dma_dac.count;
2325
2326 spin_unlock_irqrestore(&s->lock, flags);
2327
2328 if (cnt > count)
2329 cnt = count;
2330
2331 if (cnt <= 0) {
2332 start_dac(s);
2333 if (file->f_flags & O_NONBLOCK) {
2334 if(!ret) ret = -EAGAIN;
2335 goto return_free;
2336 }
2337 if (!interruptible_sleep_on_timeout(&s->dma_dac.wait, HZ)) {
2338 if(! s->card->in_suspend) printk(KERN_DEBUG "maestro: write: chip lockup? dmasz %u fragsz %u count %i hwptr %u swptr %u\n",
2339 s->dma_dac.dmasize, s->dma_dac.fragsize, s->dma_dac.count,
2340 s->dma_dac.hwptr, s->dma_dac.swptr);
2341 stop_dac(s);
2342 spin_lock_irqsave(&s->lock, flags);
2343 set_dmaa(s, virt_to_bus(s->dma_dac.rawbuf), s->dma_dac.numfrag << s->dma_dac.fragshift);
2344 /* program enhanced mode registers */
2345 /* wrindir(s, SV_CIDMAABASECOUNT1, (s->dma_dac.fragsamples-1) >> 8);
2346 wrindir(s, SV_CIDMAABASECOUNT0, s->dma_dac.fragsamples-1); */
2347 /* FILL ME */
2348 s->dma_dac.count = s->dma_dac.hwptr = s->dma_dac.swptr = 0;
2349 spin_unlock_irqrestore(&s->lock, flags);
2350 }
2351 if (signal_pending(current)) {
2352 if (!ret) ret = -ERESTARTSYS;
2353 goto return_free;
2354 }
2355 continue;
2356 }
2357 if (copy_from_user(s->dma_dac.rawbuf + swptr, buffer, cnt)) {
2358 if (!ret) ret = -EFAULT;
2359 goto return_free;
2360 }
2361 /* printk("wrote %d bytes at sw: %d cnt: %d while hw: %d\n",cnt, swptr, s->dma_dac.count, s->dma_dac.hwptr);*/
2362
2363 swptr = (swptr + cnt) % s->dma_dac.dmasize;
2364
2365 spin_lock_irqsave(&s->lock, flags);
2366 s->dma_dac.swptr = swptr;
2367 s->dma_dac.count += cnt;
2368 s->dma_dac.endcleared = 0;
2369 spin_unlock_irqrestore(&s->lock, flags);
2370 count -= cnt;
2371 buffer += cnt;
2372 ret += cnt;
2373 start_dac(s);
2374 }
2375 return_free:
2376 return ret;
2377 }
2378
2379 /* No kernel lock - we have our own spinlock */
2380 static unsigned int ess_poll(struct file *file, struct poll_table_struct *wait)
2381 {
2382 struct ess_state *s = (struct ess_state *)file->private_data;
2383 unsigned long flags;
2384 unsigned int mask = 0;
2385 int ret;
2386
2387 VALIDATE_STATE(s);
2388
2389 /* In 0.14 prog_dmabuf always returns success anyway ... */
2390 if (file->f_mode & FMODE_WRITE) {
2391 if (!s->dma_dac.ready && (ret = prog_dmabuf(s, 0)))
2392 return POLLERR;
2393 }
2394 if (file->f_mode & FMODE_READ) {
2395 if (!s->dma_adc.ready && (ret = prog_dmabuf(s, 1)))
2396 return POLLERR;
2397 }
2398
2399 if (file->f_mode & FMODE_WRITE)
2400 poll_wait(file, &s->dma_dac.wait, wait);
2401 if (file->f_mode & FMODE_READ)
2402 poll_wait(file, &s->dma_adc.wait, wait);
2403 spin_lock_irqsave(&s->lock, flags);
2404 ess_update_ptr(s);
2405 if (file->f_mode & FMODE_READ) {
2406 if (s->dma_adc.count >= (signed)s->dma_adc.fragsize)
2407 mask |= POLLIN | POLLRDNORM;
2408 }
2409 if (file->f_mode & FMODE_WRITE) {
2410 if (s->dma_dac.mapped) {
2411 if (s->dma_dac.count >= (signed)s->dma_dac.fragsize)
2412 mask |= POLLOUT | POLLWRNORM;
2413 } else {
2414 if ((signed)s->dma_dac.dmasize >= s->dma_dac.count + (signed)s->dma_dac.fragsize)
2415 mask |= POLLOUT | POLLWRNORM;
2416 }
2417 }
2418 spin_unlock_irqrestore(&s->lock, flags);
2419 return mask;
2420 }
2421
2422 static int ess_mmap(struct file *file, struct vm_area_struct *vma)
2423 {
2424 struct ess_state *s = (struct ess_state *)file->private_data;
2425 struct dmabuf *db;
2426 int ret = -EINVAL;
2427 unsigned long size;
2428
2429 VALIDATE_STATE(s);
2430 lock_kernel();
2431 if (vma->vm_flags & VM_WRITE) {
2432 if ((ret = prog_dmabuf(s, 1)) != 0)
2433 goto out;
2434 db = &s->dma_dac;
2435 } else
2436 #if 0
2437 /* if we can have the wp/wc do the combining
2438 we can turn this back on. */
2439 if (vma->vm_flags & VM_READ) {
2440 if ((ret = prog_dmabuf(s, 0)) != 0)
2441 goto out;
2442 db = &s->dma_adc;
2443 } else
2444 #endif
2445 goto out;
2446 ret = -EINVAL;
2447 if (SILLY_OFFSET(vma) != 0)
2448 goto out;
2449 size = vma->vm_end - vma->vm_start;
2450 if (size > (PAGE_SIZE << db->buforder))
2451 goto out;
2452 ret = -EAGAIN;
2453 if (remap_page_range(vma->vm_start, virt_to_phys(db->rawbuf), size, vma->vm_page_prot))
2454 goto out;
2455 db->mapped = 1;
2456 ret = 0;
2457 out:
2458 unlock_kernel();
2459 return ret;
2460 }
2461
2462 static int ess_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg)
2463 {
2464 struct ess_state *s = (struct ess_state *)file->private_data;
2465 unsigned long flags;
2466 audio_buf_info abinfo;
2467 count_info cinfo;
2468 int val, mapped, ret;
2469 unsigned char fmtm, fmtd;
2470
2471 /* printk("maestro: ess_ioctl: cmd %d\n", cmd);*/
2472
2473 VALIDATE_STATE(s);
2474 mapped = ((file->f_mode & FMODE_WRITE) && s->dma_dac.mapped) ||
2475 ((file->f_mode & FMODE_READ) && s->dma_adc.mapped);
2476 switch (cmd) {
2477 case OSS_GETVERSION:
2478 return put_user(SOUND_VERSION, (int *)arg);
2479
2480 case SNDCTL_DSP_SYNC:
2481 if (file->f_mode & FMODE_WRITE)
2482 return drain_dac(s, file->f_flags & O_NONBLOCK);
2483 return 0;
2484
2485 case SNDCTL_DSP_SETDUPLEX:
2486 /* XXX fix */
2487 return 0;
2488
2489 case SNDCTL_DSP_GETCAPS:
2490 return put_user(DSP_CAP_DUPLEX | DSP_CAP_REALTIME | DSP_CAP_TRIGGER | DSP_CAP_MMAP, (int *)arg);
2491
2492 case SNDCTL_DSP_RESET:
2493 if (file->f_mode & FMODE_WRITE) {
2494 stop_dac(s);
2495 synchronize_irq();
2496 s->dma_dac.swptr = s->dma_dac.hwptr = s->dma_dac.count = s->dma_dac.total_bytes = 0;
2497 }
2498 if (file->f_mode & FMODE_READ) {
2499 stop_adc(s);
2500 synchronize_irq();
2501 s->dma_adc.swptr = s->dma_adc.hwptr = s->dma_adc.count = s->dma_adc.total_bytes = 0;
2502 }
2503 return 0;
2504
2505 case SNDCTL_DSP_SPEED:
2506 if (get_user(val, (int *)arg))
2507 return -EFAULT;
2508 if (val >= 0) {
2509 if (file->f_mode & FMODE_READ) {
2510 stop_adc(s);
2511 s->dma_adc.ready = 0;
2512 set_adc_rate(s, val);
2513 }
2514 if (file->f_mode & FMODE_WRITE) {
2515 stop_dac(s);
2516 s->dma_dac.ready = 0;
2517 set_dac_rate(s, val);
2518 }
2519 }
2520 return put_user((file->f_mode & FMODE_READ) ? s->rateadc : s->ratedac, (int *)arg);
2521
2522 case SNDCTL_DSP_STEREO:
2523 if (get_user(val, (int *)arg))
2524 return -EFAULT;
2525 fmtd = 0;
2526 fmtm = ~0;
2527 if (file->f_mode & FMODE_READ) {
2528 stop_adc(s);
2529 s->dma_adc.ready = 0;
2530 if (val)
2531 fmtd |= ESS_FMT_STEREO << ESS_ADC_SHIFT;
2532 else
2533 fmtm &= ~(ESS_FMT_STEREO << ESS_ADC_SHIFT);
2534 }
2535 if (file->f_mode & FMODE_WRITE) {
2536 stop_dac(s);
2537 s->dma_dac.ready = 0;
2538 if (val)
2539 fmtd |= ESS_FMT_STEREO << ESS_DAC_SHIFT;
2540 else
2541 fmtm &= ~(ESS_FMT_STEREO << ESS_DAC_SHIFT);
2542 }
2543 set_fmt(s, fmtm, fmtd);
2544 return 0;
2545
2546 case SNDCTL_DSP_CHANNELS:
2547 if (get_user(val, (int *)arg))
2548 return -EFAULT;
2549 if (val != 0) {
2550 fmtd = 0;
2551 fmtm = ~0;
2552 if (file->f_mode & FMODE_READ) {
2553 stop_adc(s);
2554 s->dma_adc.ready = 0;
2555 if (val >= 2)
2556 fmtd |= ESS_FMT_STEREO << ESS_ADC_SHIFT;
2557 else
2558 fmtm &= ~(ESS_FMT_STEREO << ESS_ADC_SHIFT);
2559 }
2560 if (file->f_mode & FMODE_WRITE) {
2561 stop_dac(s);
2562 s->dma_dac.ready = 0;
2563 if (val >= 2)
2564 fmtd |= ESS_FMT_STEREO << ESS_DAC_SHIFT;
2565 else
2566 fmtm &= ~(ESS_FMT_STEREO << ESS_DAC_SHIFT);
2567 }
2568 set_fmt(s, fmtm, fmtd);
2569 }
2570 return put_user((s->fmt & ((file->f_mode & FMODE_READ) ? (ESS_FMT_STEREO << ESS_ADC_SHIFT)
2571 : (ESS_FMT_STEREO << ESS_DAC_SHIFT))) ? 2 : 1, (int *)arg);
2572
2573 case SNDCTL_DSP_GETFMTS: /* Returns a mask */
2574 return put_user(AFMT_U8|AFMT_S16_LE, (int *)arg);
2575
2576 case SNDCTL_DSP_SETFMT: /* Selects ONE fmt*/
2577 if (get_user(val, (int *)arg))
2578 return -EFAULT;
2579 if (val != AFMT_QUERY) {
2580 fmtd = 0;
2581 fmtm = ~0;
2582 if (file->f_mode & FMODE_READ) {
2583 stop_adc(s);
2584 s->dma_adc.ready = 0;
2585 /* fixed at 16bit for now */
2586 fmtd |= ESS_FMT_16BIT << ESS_ADC_SHIFT;
2587 #if 0
2588 if (val == AFMT_S16_LE)
2589 fmtd |= ESS_FMT_16BIT << ESS_ADC_SHIFT;
2590 else
2591 fmtm &= ~(ESS_FMT_16BIT << ESS_ADC_SHIFT);
2592 #endif
2593 }
2594 if (file->f_mode & FMODE_WRITE) {
2595 stop_dac(s);
2596 s->dma_dac.ready = 0;
2597 if (val == AFMT_S16_LE)
2598 fmtd |= ESS_FMT_16BIT << ESS_DAC_SHIFT;
2599 else
2600 fmtm &= ~(ESS_FMT_16BIT << ESS_DAC_SHIFT);
2601 }
2602 set_fmt(s, fmtm, fmtd);
2603 }
2604 return put_user((s->fmt & ((file->f_mode & FMODE_READ) ?
2605 (ESS_FMT_16BIT << ESS_ADC_SHIFT)
2606 : (ESS_FMT_16BIT << ESS_DAC_SHIFT))) ?
2607 AFMT_S16_LE :
2608 AFMT_U8,
2609 (int *)arg);
2610
2611 case SNDCTL_DSP_POST:
2612 return 0;
2613
2614 case SNDCTL_DSP_GETTRIGGER:
2615 val = 0;
2616 if ((file->f_mode & FMODE_READ) && (s->enable & ADC_RUNNING))
2617 val |= PCM_ENABLE_INPUT;
2618 if ((file->f_mode & FMODE_WRITE) && (s->enable & DAC_RUNNING))
2619 val |= PCM_ENABLE_OUTPUT;
2620 return put_user(val, (int *)arg);
2621
2622 case SNDCTL_DSP_SETTRIGGER:
2623 if (get_user(val, (int *)arg))
2624 return -EFAULT;
2625 if (file->f_mode & FMODE_READ) {
2626 if (val & PCM_ENABLE_INPUT) {
2627 if (!s->dma_adc.ready && (ret = prog_dmabuf(s, 1)))
2628 return ret;
2629 start_adc(s);
2630 } else
2631 stop_adc(s);
2632 }
2633 if (file->f_mode & FMODE_WRITE) {
2634 if (val & PCM_ENABLE_OUTPUT) {
2635 if (!s->dma_dac.ready && (ret = prog_dmabuf(s, 0)))
2636 return ret;
2637 start_dac(s);
2638 } else
2639 stop_dac(s);
2640 }
2641 return 0;
2642
2643 case SNDCTL_DSP_GETOSPACE:
2644 if (!(file->f_mode & FMODE_WRITE))
2645 return -EINVAL;
2646 if (!(s->enable & DAC_RUNNING) && (val = prog_dmabuf(s, 0)) != 0)
2647 return val;
2648 spin_lock_irqsave(&s->lock, flags);
2649 ess_update_ptr(s);
2650 abinfo.fragsize = s->dma_dac.fragsize;
2651 abinfo.bytes = s->dma_dac.dmasize - s->dma_dac.count;
2652 abinfo.fragstotal = s->dma_dac.numfrag;
2653 abinfo.fragments = abinfo.bytes >> s->dma_dac.fragshift;
2654 spin_unlock_irqrestore(&s->lock, flags);
2655 return copy_to_user((void *)arg, &abinfo, sizeof(abinfo)) ? -EFAULT : 0;
2656
2657 case SNDCTL_DSP_GETISPACE:
2658 if (!(file->f_mode & FMODE_READ))
2659 return -EINVAL;
2660 if (!(s->enable & ADC_RUNNING) && (val = prog_dmabuf(s, 1)) != 0)
2661 return val;
2662 spin_lock_irqsave(&s->lock, flags);
2663 ess_update_ptr(s);
2664 abinfo.fragsize = s->dma_adc.fragsize;
2665 abinfo.bytes = s->dma_adc.count;
2666 abinfo.fragstotal = s->dma_adc.numfrag;
2667 abinfo.fragments = abinfo.bytes >> s->dma_adc.fragshift;
2668 spin_unlock_irqrestore(&s->lock, flags);
2669 return copy_to_user((void *)arg, &abinfo, sizeof(abinfo)) ? -EFAULT : 0;
2670
2671 case SNDCTL_DSP_NONBLOCK:
2672 file->f_flags |= O_NONBLOCK;
2673 return 0;
2674
2675 case SNDCTL_DSP_GETODELAY:
2676 if (!(file->f_mode & FMODE_WRITE))
2677 return -EINVAL;
2678 spin_lock_irqsave(&s->lock, flags);
2679 ess_update_ptr(s);
2680 val = s->dma_dac.count;
2681 spin_unlock_irqrestore(&s->lock, flags);
2682 return put_user(val, (int *)arg);
2683
2684 case SNDCTL_DSP_GETIPTR:
2685 if (!(file->f_mode & FMODE_READ))
2686 return -EINVAL;
2687 spin_lock_irqsave(&s->lock, flags);
2688 ess_update_ptr(s);
2689 cinfo.bytes = s->dma_adc.total_bytes;
2690 cinfo.blocks = s->dma_adc.count >> s->dma_adc.fragshift;
2691 cinfo.ptr = s->dma_adc.hwptr;
2692 if (s->dma_adc.mapped)
2693 s->dma_adc.count &= s->dma_adc.fragsize-1;
2694 spin_unlock_irqrestore(&s->lock, flags);
2695 return copy_to_user((void *)arg, &cinfo, sizeof(cinfo));
2696
2697 case SNDCTL_DSP_GETOPTR:
2698 if (!(file->f_mode & FMODE_WRITE))
2699 return -EINVAL;
2700 spin_lock_irqsave(&s->lock, flags);
2701 ess_update_ptr(s);
2702 cinfo.bytes = s->dma_dac.total_bytes;
2703 cinfo.blocks = s->dma_dac.count >> s->dma_dac.fragshift;
2704 cinfo.ptr = s->dma_dac.hwptr;
2705 if (s->dma_dac.mapped)
2706 s->dma_dac.count &= s->dma_dac.fragsize-1;
2707 spin_unlock_irqrestore(&s->lock, flags);
2708 return copy_to_user((void *)arg, &cinfo, sizeof(cinfo));
2709
2710 case SNDCTL_DSP_GETBLKSIZE:
2711 if (file->f_mode & FMODE_WRITE) {
2712 if ((val = prog_dmabuf(s, 0)))
2713 return val;
2714 return put_user(s->dma_dac.fragsize, (int *)arg);
2715 }
2716 if ((val = prog_dmabuf(s, 1)))
2717 return val;
2718 return put_user(s->dma_adc.fragsize, (int *)arg);
2719
2720 case SNDCTL_DSP_SETFRAGMENT:
2721 if (get_user(val, (int *)arg))
2722 return -EFAULT;
2723 M_printk("maestro: SETFRAGMENT: %0x\n",val);
2724 if (file->f_mode & FMODE_READ) {
2725 s->dma_adc.ossfragshift = val & 0xffff;
2726 s->dma_adc.ossmaxfrags = (val >> 16) & 0xffff;
2727 if (s->dma_adc.ossfragshift < 4)
2728 s->dma_adc.ossfragshift = 4;
2729 if (s->dma_adc.ossfragshift > 15)
2730 s->dma_adc.ossfragshift = 15;
2731 if (s->dma_adc.ossmaxfrags < 4)
2732 s->dma_adc.ossmaxfrags = 4;
2733 }
2734 if (file->f_mode & FMODE_WRITE) {
2735 s->dma_dac.ossfragshift = val & 0xffff;
2736 s->dma_dac.ossmaxfrags = (val >> 16) & 0xffff;
2737 if (s->dma_dac.ossfragshift < 4)
2738 s->dma_dac.ossfragshift = 4;
2739 if (s->dma_dac.ossfragshift > 15)
2740 s->dma_dac.ossfragshift = 15;
2741 if (s->dma_dac.ossmaxfrags < 4)
2742 s->dma_dac.ossmaxfrags = 4;
2743 }
2744 return 0;
2745
2746 case SNDCTL_DSP_SUBDIVIDE:
2747 if ((file->f_mode & FMODE_READ && s->dma_adc.subdivision) ||
2748 (file->f_mode & FMODE_WRITE && s->dma_dac.subdivision))
2749 return -EINVAL;
2750 if (get_user(val, (int *)arg))
2751 return -EFAULT;
2752 if (val != 1 && val != 2 && val != 4)
2753 return -EINVAL;
2754 if (file->f_mode & FMODE_READ)
2755 s->dma_adc.subdivision = val;
2756 if (file->f_mode & FMODE_WRITE)
2757 s->dma_dac.subdivision = val;
2758 return 0;
2759
2760 case SOUND_PCM_READ_RATE:
2761 return put_user((file->f_mode & FMODE_READ) ? s->rateadc : s->ratedac, (int *)arg);
2762
2763 case SOUND_PCM_READ_CHANNELS:
2764 return put_user((s->fmt & ((file->f_mode & FMODE_READ) ? (ESS_FMT_STEREO << ESS_ADC_SHIFT)
2765 : (ESS_FMT_STEREO << ESS_DAC_SHIFT))) ? 2 : 1, (int *)arg);
2766
2767 case SOUND_PCM_READ_BITS:
2768 return put_user((s->fmt & ((file->f_mode & FMODE_READ) ? (ESS_FMT_16BIT << ESS_ADC_SHIFT)
2769 : (ESS_FMT_16BIT << ESS_DAC_SHIFT))) ? 16 : 8, (int *)arg);
2770
2771 case SOUND_PCM_WRITE_FILTER:
2772 case SNDCTL_DSP_SETSYNCRO:
2773 case SOUND_PCM_READ_FILTER:
2774 return -EINVAL;
2775
2776 }
2777 return -EINVAL;
2778 }
2779
2780 static void
2781 set_base_registers(struct ess_state *s,void *vaddr)
2782 {
2783 unsigned long packed_phys = virt_to_bus(vaddr)>>12;
2784 wave_set_register(s, 0x01FC , packed_phys);
2785 wave_set_register(s, 0x01FD , packed_phys);
2786 wave_set_register(s, 0x01FE , packed_phys);
2787 wave_set_register(s, 0x01FF , packed_phys);
2788 }
2789
2790 /*
2791 * this guy makes sure we're in the right power
2792 * state for what we want to be doing
2793 */
2794 static void maestro_power(struct ess_card *card, int tostate)
2795 {
2796 u16 active_mask = acpi_state_mask[tostate];
2797 u8 state;
2798
2799 if(!use_pm) return;
2800
2801 pci_read_config_byte(card->pcidev, card->power_regs+0x4, &state);
2802 state&=3;
2803
2804 /* make sure we're in the right state */
2805 if(state != tostate) {
2806 M_printk(KERN_WARNING "maestro: dev %02x:%02x.%x switching from D%d to D%d\n",
2807 card->pcidev->bus->number,
2808 PCI_SLOT(card->pcidev->devfn),
2809 PCI_FUNC(card->pcidev->devfn),
2810 state,tostate);
2811 pci_write_config_byte(card->pcidev, card->power_regs+0x4, tostate);
2812 }
2813
2814 /* and make sure the units we care about are on
2815 XXX we might want to do this before state flipping? */
2816 pci_write_config_word(card->pcidev, 0x54, ~ active_mask);
2817 pci_write_config_word(card->pcidev, 0x56, ~ active_mask);
2818 }
2819
2820 /* we allocate a large power of two for all our memory.
2821 this is cut up into (not to scale :):
2822 |silly fifo word | 512byte mixbuf per adc | dac/adc * channels |
2823 */
2824 static int
2825 allocate_buffers(struct ess_state *s)
2826 {
2827 void *rawbuf=NULL;
2828 int order,i;
2829 struct page *page, *pend;
2830
2831 /* alloc as big a chunk as we can */
2832 for (order = (dsps_order + (16-PAGE_SHIFT) + 1); order >= (dsps_order + 2 + 1); order--)
2833 if((rawbuf = (void *)__get_free_pages(GFP_KERNEL|GFP_DMA, order)))
2834 break;
2835
2836 if (!rawbuf)
2837 return 1;
2838
2839 M_printk("maestro: allocated %ld (%d) bytes at %p\n",PAGE_SIZE<<order,order, rawbuf);
2840
2841 if ((virt_to_bus(rawbuf) + (PAGE_SIZE << order) - 1) & ~((1<<28)-1)) {
2842 printk(KERN_ERR "maestro: DMA buffer beyond 256MB! busaddr 0x%lx size %ld\n",
2843 virt_to_bus(rawbuf), PAGE_SIZE << order);
2844 kfree(rawbuf);
2845 return 1;
2846 }
2847
2848 s->card->dmapages = rawbuf;
2849 s->card->dmaorder = order;
2850
2851 for(i=0;i<NR_DSPS;i++) {
2852 struct ess_state *ess = &s->card->channels[i];
2853
2854 if(ess->dev_audio == -1)
2855 continue;
2856
2857 ess->dma_dac.ready = s->dma_dac.mapped = 0;
2858 ess->dma_adc.ready = s->dma_adc.mapped = 0;
2859 ess->dma_adc.buforder = ess->dma_dac.buforder = order - 1 - dsps_order - 1;
2860
2861 /* offset dac and adc buffers starting half way through and then at each [da][ad]c's
2862 order's intervals.. */
2863 ess->dma_dac.rawbuf = rawbuf + (PAGE_SIZE<<(order-1)) + (i * ( PAGE_SIZE << (ess->dma_dac.buforder + 1 )));
2864 ess->dma_adc.rawbuf = ess->dma_dac.rawbuf + ( PAGE_SIZE << ess->dma_dac.buforder);
2865 /* offset mixbuf by a mixbuf so that the lame status fifo can
2866 happily scribble away.. */
2867 ess->mixbuf = rawbuf + (512 * (i+1));
2868
2869 M_printk("maestro: setup apu %d: dac: %p adc: %p mix: %p\n",i,ess->dma_dac.rawbuf,
2870 ess->dma_adc.rawbuf, ess->mixbuf);
2871
2872 }
2873
2874 /* now mark the pages as reserved; otherwise remap_page_range doesn't do what we want */
2875 pend = virt_to_page(rawbuf + (PAGE_SIZE << order) - 1);
2876 for (page = virt_to_page(rawbuf); page <= pend; page++)
2877 mem_map_reserve(page);
2878
2879 return 0;
2880 }
2881 static void
2882 free_buffers(struct ess_state *s)
2883 {
2884 struct page *page, *pend;
2885
2886 s->dma_dac.rawbuf = s->dma_adc.rawbuf = NULL;
2887 s->dma_dac.mapped = s->dma_adc.mapped = 0;
2888 s->dma_dac.ready = s->dma_adc.ready = 0;
2889
2890 M_printk("maestro: freeing %p\n",s->card->dmapages);
2891 /* undo marking the pages as reserved */
2892
2893 pend = virt_to_page(s->card->dmapages + (PAGE_SIZE << s->card->dmaorder) - 1);
2894 for (page = virt_to_page(s->card->dmapages); page <= pend; page++)
2895 mem_map_unreserve(page);
2896
2897 free_pages((unsigned long)s->card->dmapages,s->card->dmaorder);
2898 s->card->dmapages = NULL;
2899 }
2900
2901 static int
2902 ess_open(struct inode *inode, struct file *file)
2903 {
2904 int minor = MINOR(inode->i_rdev);
2905 struct ess_card *c = devs;
2906 struct ess_state *s = NULL, *sp;
2907 int i;
2908 unsigned char fmtm = ~0, fmts = 0;
2909
2910 /*
2911 * Scan the cards and find the channel. We only
2912 * do this at open time so it is ok
2913 */
2914
2915 while (c!=NULL)
2916 {
2917 for(i=0;i<NR_DSPS;i++)
2918 {
2919 sp=&c->channels[i];
2920 if(sp->dev_audio < 0)
2921 continue;
2922 if((sp->dev_audio ^ minor) & ~0xf)
2923 continue;
2924 s=sp;
2925 }
2926 c=c->next;
2927 }
2928
2929 if (!s)
2930 return -ENODEV;
2931
2932 VALIDATE_STATE(s);
2933 file->private_data = s;
2934 /* wait for device to become free */
2935 down(&s->open_sem);
2936 while (s->open_mode & file->f_mode) {
2937 if (file->f_flags & O_NONBLOCK) {
2938 up(&s->open_sem);
2939 return -EWOULDBLOCK;
2940 }
2941 up(&s->open_sem);
2942 interruptible_sleep_on(&s->open_wait);
2943 if (signal_pending(current))
2944 return -ERESTARTSYS;
2945 down(&s->open_sem);
2946 }
2947
2948 /* under semaphore.. */
2949 if ((s->card->dmapages==NULL) && allocate_buffers(s)) {
2950 up(&s->open_sem);
2951 return -ENOMEM;
2952 }
2953
2954 /* we're covered by the open_sem */
2955 if( ! s->card->dsps_open ) {
2956 maestro_power(s->card,ACPI_D0);
2957 start_bob(s);
2958 }
2959 s->card->dsps_open++;
2960 M_printk("maestro: open, %d bobs now\n",s->card->dsps_open);
2961
2962 /* ok, lets write WC base regs now that we've
2963 powered up the chip */
2964 M_printk("maestro: writing 0x%lx (bus 0x%lx) to the wp\n",virt_to_bus(s->card->dmapages),
2965 ((virt_to_bus(s->card->dmapages))&0xFFE00000)>>12);
2966 set_base_registers(s,s->card->dmapages);
2967
2968 if (file->f_mode & FMODE_READ) {
2969 /*
2970 fmtm &= ~((ESS_FMT_STEREO | ESS_FMT_16BIT) << ESS_ADC_SHIFT);
2971 if ((minor & 0xf) == SND_DEV_DSP16)
2972 fmts |= ESS_FMT_16BIT << ESS_ADC_SHIFT; */
2973
2974 fmtm &= ~((ESS_FMT_STEREO|ESS_FMT_16BIT) << ESS_ADC_SHIFT);
2975 fmts = (ESS_FMT_STEREO|ESS_FMT_16BIT) << ESS_ADC_SHIFT;
2976
2977 s->dma_adc.ossfragshift = s->dma_adc.ossmaxfrags = s->dma_adc.subdivision = 0;
2978 set_adc_rate(s, 8000);
2979 }
2980 if (file->f_mode & FMODE_WRITE) {
2981 fmtm &= ~((ESS_FMT_STEREO | ESS_FMT_16BIT) << ESS_DAC_SHIFT);
2982 if ((minor & 0xf) == SND_DEV_DSP16)
2983 fmts |= ESS_FMT_16BIT << ESS_DAC_SHIFT;
2984
2985 s->dma_dac.ossfragshift = s->dma_dac.ossmaxfrags = s->dma_dac.subdivision = 0;
2986 set_dac_rate(s, 8000);
2987 }
2988 set_fmt(s, fmtm, fmts);
2989 s->open_mode |= file->f_mode & (FMODE_READ | FMODE_WRITE);
2990
2991 up(&s->open_sem);
2992 return 0;
2993 }
2994
2995 static int
2996 ess_release(struct inode *inode, struct file *file)
2997 {
2998 struct ess_state *s = (struct ess_state *)file->private_data;
2999
3000 VALIDATE_STATE(s);
3001 lock_kernel();
3002 if (file->f_mode & FMODE_WRITE)
3003 drain_dac(s, file->f_flags & O_NONBLOCK);
3004 down(&s->open_sem);
3005 if (file->f_mode & FMODE_WRITE) {
3006 stop_dac(s);
3007 }
3008 if (file->f_mode & FMODE_READ) {
3009 stop_adc(s);
3010 }
3011
3012 s->open_mode &= (~file->f_mode) & (FMODE_READ|FMODE_WRITE);
3013 /* we're covered by the open_sem */
3014 M_printk("maestro: %d dsps now alive\n",s->card->dsps_open-1);
3015 if( --s->card->dsps_open <= 0) {
3016 s->card->dsps_open = 0;
3017 stop_bob(s);
3018 free_buffers(s);
3019 maestro_power(s->card,ACPI_D2);
3020 }
3021 up(&s->open_sem);
3022 wake_up(&s->open_wait);
3023 unlock_kernel();
3024 return 0;
3025 }
3026
3027 static struct file_operations ess_audio_fops = {
3028 owner: THIS_MODULE,
3029 llseek: ess_llseek,
3030 read: ess_read,
3031 write: ess_write,
3032 poll: ess_poll,
3033 ioctl: ess_ioctl,
3034 mmap: ess_mmap,
3035 open: ess_open,
3036 release: ess_release,
3037 };
3038
3039 static int
3040 maestro_config(struct ess_card *card)
3041 {
3042 struct pci_dev *pcidev = card->pcidev;
3043 struct ess_state *ess = &card->channels[0];
3044 int apu,iobase = card->iobase;
3045 u16 w;
3046 u32 n;
3047
3048 /* We used to muck around with pci config space that
3049 * we had no business messing with. We don't know enough
3050 * about the machine to know which DMA mode is appropriate,
3051 * etc. We were guessing wrong on some machines and making
3052 * them unhappy. We now trust in the BIOS to do things right,
3053 * which almost certainly means a new host of problems will
3054 * arise with broken BIOS implementations. screw 'em.
3055 * We're already intolerant of machines that don't assign
3056 * IRQs.
3057 */
3058
3059 /* do config work at full power */
3060 maestro_power(card,ACPI_D0);
3061
3062 pci_read_config_word(pcidev, 0x50, &w);
3063
3064 w&=~(1<<5); /* Don't swap left/right (undoc)*/
3065
3066 pci_write_config_word(pcidev, 0x50, w);
3067
3068 pci_read_config_word(pcidev, 0x52, &w);
3069 w&=~(1<<15); /* Turn off internal clock multiplier */
3070 /* XXX how do we know which to use? */
3071 w&=~(1<<14); /* External clock */
3072
3073 w&=~(1<<7); /* HWV off */
3074 w&=~(1<<6); /* Debounce off */
3075 w&=~(1<<5); /* GPIO 4:5 */
3076 w|= (1<<4); /* Disconnect from the CHI. Enabling this made a dell 7500 work. */
3077 w&=~(1<<2); /* MIDI fix off (undoc) */
3078 w&=~(1<<1); /* reserved, always write 0 */
3079 pci_write_config_word(pcidev, 0x52, w);
3080
3081 /*
3082 * Legacy mode
3083 */
3084
3085 pci_read_config_word(pcidev, 0x40, &w);
3086 w|=(1<<15); /* legacy decode off */
3087 w&=~(1<<14); /* Disable SIRQ */
3088 w&=~(0x1f); /* disable mpu irq/io, game port, fm, SB */
3089
3090 pci_write_config_word(pcidev, 0x40, w);
3091
3092
3093 sound_reset(iobase);
3094
3095 /*
3096 * Ring Bus Setup
3097 */
3098
3099 /* setup usual 0x34 stuff.. 0x36 may be chip specific */
3100 outw(0xC090, iobase+0x34); /* direct sound, stereo */
3101 udelay(20);
3102 outw(0x3000, iobase+0x36); /* direct sound, stereo */
3103 udelay(20);
3104
3105
3106 /*
3107 * Reset the CODEC
3108 */
3109
3110 maestro_ac97_reset(iobase,pcidev);
3111
3112 /*
3113 * Ring Bus Setup
3114 */
3115
3116 n=inl(iobase+0x34);
3117 n&=~0xF000;
3118 n|=12<<12; /* Direct Sound, Stereo */
3119 outl(n, iobase+0x34);
3120
3121 n=inl(iobase+0x34);
3122 n&=~0x0F00; /* Modem off */
3123 outl(n, iobase+0x34);
3124
3125 n=inl(iobase+0x34);
3126 n&=~0x00F0;
3127 n|=9<<4; /* DAC, Stereo */
3128 outl(n, iobase+0x34);
3129
3130 n=inl(iobase+0x34);
3131 n&=~0x000F; /* ASSP off */
3132 outl(n, iobase+0x34);
3133
3134 n=inl(iobase+0x34);
3135 n|=(1<<29); /* Enable ring bus */
3136 outl(n, iobase+0x34);
3137
3138 n=inl(iobase+0x34);
3139 n|=(1<<28); /* Enable serial bus */
3140 outl(n, iobase+0x34);
3141
3142 n=inl(iobase+0x34);
3143 n&=~0x00F00000; /* MIC off */
3144 outl(n, iobase+0x34);
3145
3146 n=inl(iobase+0x34);
3147 n&=~0x000F0000; /* I2S off */
3148 outl(n, iobase+0x34);
3149
3150
3151 w=inw(iobase+0x18);
3152 w&=~(1<<7); /* ClkRun off */
3153 outw(w, iobase+0x18);
3154
3155 w=inw(iobase+0x18);
3156 w&=~(1<<6); /* Harpo off */
3157 outw(w, iobase+0x18);
3158
3159 w=inw(iobase+0x18);
3160 w&=~(1<<4); /* ASSP irq off */
3161 outw(w, iobase+0x18);
3162
3163 w=inw(iobase+0x18);
3164 w&=~(1<<3); /* ISDN irq off */
3165 outw(w, iobase+0x18);
3166
3167 w=inw(iobase+0x18);
3168 w|=(1<<2); /* Direct Sound IRQ on */
3169 outw(w, iobase+0x18);
3170
3171 w=inw(iobase+0x18);
3172 w&=~(1<<1); /* MPU401 IRQ off */
3173 outw(w, iobase+0x18);
3174
3175 w=inw(iobase+0x18);
3176 w|=(1<<0); /* SB IRQ on */
3177 outw(w, iobase+0x18);
3178
3179 /* it appears some maestros (dell 7500) only work if these are set,
3180 regardless of wether we use the assp or not. */
3181
3182 outb(0, iobase+0xA4);
3183 outb(3, iobase+0xA2);
3184 outb(0, iobase+0xA6);
3185
3186 for(apu=0;apu<16;apu++)
3187 {
3188 /* Write 0 into the buffer area 0x1E0->1EF */
3189 outw(0x01E0+apu, 0x10+iobase);
3190 outw(0x0000, 0x12+iobase);
3191
3192 /*
3193 * The 1.10 test program seem to write 0 into the buffer area
3194 * 0x1D0-0x1DF too.
3195 */
3196 outw(0x01D0+apu, 0x10+iobase);
3197 outw(0x0000, 0x12+iobase);
3198 }
3199
3200 #if 1
3201 wave_set_register(ess, IDR7_WAVE_ROMRAM,
3202 (wave_get_register(ess, IDR7_WAVE_ROMRAM)&0xFF00));
3203 wave_set_register(ess, IDR7_WAVE_ROMRAM,
3204 wave_get_register(ess, IDR7_WAVE_ROMRAM)|0x100);
3205 wave_set_register(ess, IDR7_WAVE_ROMRAM,
3206 wave_get_register(ess, IDR7_WAVE_ROMRAM)&~0x200);
3207 wave_set_register(ess, IDR7_WAVE_ROMRAM,
3208 wave_get_register(ess, IDR7_WAVE_ROMRAM)|~0x400);
3209 #else
3210 maestro_write(ess, IDR7_WAVE_ROMRAM,
3211 (maestro_read(ess, IDR7_WAVE_ROMRAM)&0xFF00));
3212 maestro_write(ess, IDR7_WAVE_ROMRAM,
3213 maestro_read(ess, IDR7_WAVE_ROMRAM)|0x100);
3214 maestro_write(ess, IDR7_WAVE_ROMRAM,
3215 maestro_read(ess, IDR7_WAVE_ROMRAM)&~0x200);
3216 maestro_write(ess, IDR7_WAVE_ROMRAM,
3217 maestro_read(ess, IDR7_WAVE_ROMRAM)|0x400);
3218 #endif
3219
3220 maestro_write(ess, IDR2_CRAM_DATA, 0x0000);
3221 maestro_write(ess, 0x08, 0xB004);
3222 /* Now back to the DirectSound stuff */
3223 maestro_write(ess, 0x09, 0x001B);
3224 maestro_write(ess, 0x0A, 0x8000);
3225 maestro_write(ess, 0x0B, 0x3F37);
3226 maestro_write(ess, 0x0C, 0x0098);
3227
3228 /* parallel out ?? */
3229 maestro_write(ess, 0x0C,
3230 (maestro_read(ess, 0x0C)&~0xF000)|0x8000);
3231 /* parallel in, has something to do with recording :) */
3232 maestro_write(ess, 0x0C,
3233 (maestro_read(ess, 0x0C)&~0x0F00)|0x0500);
3234
3235 maestro_write(ess, 0x0D, 0x7632);
3236
3237 /* Wave cache control on - test off, sg off,
3238 enable, enable extra chans 1Mb */
3239
3240 outw(inw(0x14+iobase)|(1<<8),0x14+iobase);
3241 outw(inw(0x14+iobase)&0xFE03,0x14+iobase);
3242 outw((inw(0x14+iobase)&0xFFFC), 0x14+iobase);
3243 outw(inw(0x14+iobase)|(1<<7),0x14+iobase);
3244
3245 outw(0xA1A0, 0x14+iobase); /* 0300 ? */
3246
3247 /* Now clear the APU control ram */
3248 for(apu=0;apu<NR_APUS;apu++)
3249 {
3250 for(w=0;w<NR_APU_REGS;w++)
3251 apu_set_register(ess, apu|ESS_CHAN_HARD, w, 0);
3252
3253 }
3254
3255 return 0;
3256
3257 }
3258
3259 /* this guy tries to find the pci power management
3260 * register bank. this should really be in core
3261 * code somewhere. 1 on success. */
3262 int
3263 parse_power(struct ess_card *card, struct pci_dev *pcidev)
3264 {
3265 u32 n;
3266 u16 w;
3267 u8 next;
3268 int max = 64; /* an a 8bit guy pointing to 32bit guys
3269 can only express so much. */
3270
3271 card->power_regs = 0;
3272
3273 /* check to see if we have a capabilities list in
3274 the config register */
3275 pci_read_config_word(pcidev, PCI_STATUS, &w);
3276 if(! w & PCI_STATUS_CAP_LIST) return 0;
3277
3278 /* walk the list, starting at the head. */
3279 pci_read_config_byte(pcidev,PCI_CAPABILITY_LIST,&next);
3280
3281 while(next && max--) {
3282 pci_read_config_dword(pcidev, next & ~3, &n);
3283 if((n & 0xff) == PCI_CAP_ID_PM) {
3284 card->power_regs = next;
3285 break;
3286 }
3287 next = ((n>>8) & 0xff);
3288 }
3289
3290 return card->power_regs ? 1 : 0;
3291 }
3292
3293 static int
3294 maestro_install(struct pci_dev *pcidev, int card_type)
3295 {
3296 u32 n;
3297 int iobase;
3298 int i;
3299 struct ess_card *card;
3300 struct ess_state *ess;
3301 struct pm_dev *pmdev;
3302 int num = 0;
3303
3304 /* don't pick up weird modem maestros */
3305 if(((pcidev->class >> 8) & 0xffff) != PCI_CLASS_MULTIMEDIA_AUDIO)
3306 return 0;
3307
3308 iobase = SILLY_PCI_BASE_ADDRESS(pcidev);
3309
3310 /* stake our claim on the iospace */
3311 if( request_region(iobase, 256, card_names[card_type]) == NULL )
3312 {
3313 printk(KERN_WARNING "maestro: can't allocate 256 bytes I/O at 0x%4.4x\n", iobase);
3314 return 0;
3315 }
3316
3317 /* this was tripping up some machines */
3318 if(pcidev->irq == 0) {
3319 printk(KERN_WARNING "maestro: pci subsystem reports irq 0, this might not be correct.\n");
3320 }
3321
3322 /* just to be sure */
3323 pci_set_master(pcidev);
3324
3325 card = kmalloc(sizeof(struct ess_card), GFP_KERNEL);
3326 if(card == NULL)
3327 {
3328 printk(KERN_WARNING "maestro: out of memory\n");
3329 return 0;
3330 }
3331
3332 memset(card, 0, sizeof(*card));
3333 card->pcidev = pcidev;
3334
3335 pmdev = pm_register(PM_PCI_DEV, PM_PCI_ID(pcidev),
3336 maestro_pm_callback);
3337 if (pmdev)
3338 pmdev->data = card;
3339
3340 if (register_reboot_notifier(&maestro_nb)) {
3341 printk(KERN_WARNING "maestro: reboot notifier registration failed; may not reboot properly.\n");
3342 }
3343
3344 card->iobase = iobase;
3345 card->card_type = card_type;
3346 card->irq = pcidev->irq;
3347 card->next = devs;
3348 card->magic = ESS_CARD_MAGIC;
3349 spin_lock_init(&card->lock);
3350 init_waitqueue_head(&card->suspend_queue);
3351 devs = card;
3352
3353 /* init our groups of 6 apus */
3354 for(i=0;i<NR_DSPS;i++)
3355 {
3356 struct ess_state *s=&card->channels[i];
3357
3358 s->index = i;
3359
3360 s->card = card;
3361 init_waitqueue_head(&s->dma_adc.wait);
3362 init_waitqueue_head(&s->dma_dac.wait);
3363 init_waitqueue_head(&s->open_wait);
3364 spin_lock_init(&s->lock);
3365 SILLY_INIT_SEM(s->open_sem);
3366 s->magic = ESS_STATE_MAGIC;
3367
3368 s->apu[0] = 6*i;
3369 s->apu[1] = (6*i)+1;
3370 s->apu[2] = (6*i)+2;
3371 s->apu[3] = (6*i)+3;
3372 s->apu[4] = (6*i)+4;
3373 s->apu[5] = (6*i)+5;
3374
3375 if(s->dma_adc.ready || s->dma_dac.ready || s->dma_adc.rawbuf)
3376 printk("maestro: BOTCH!\n");
3377 /* register devices */
3378 if ((s->dev_audio = register_sound_dsp(&ess_audio_fops, -1)) < 0)
3379 break;
3380 }
3381
3382 num = i;
3383
3384 /* clear the rest if we ran out of slots to register */
3385 for(;i<NR_DSPS;i++)
3386 {
3387 struct ess_state *s=&card->channels[i];
3388 s->dev_audio = -1;
3389 }
3390
3391 ess = &card->channels[0];
3392
3393 /*
3394 * Ok card ready. Begin setup proper
3395 */
3396
3397 printk(KERN_INFO "maestro: Configuring %s found at IO 0x%04X IRQ %d\n",
3398 card_names[card_type],iobase,card->irq);
3399 pci_read_config_dword(pcidev, PCI_SUBSYSTEM_VENDOR_ID, &n);
3400 printk(KERN_INFO "maestro: subvendor id: 0x%08x\n",n);
3401
3402 /* turn off power management unless:
3403 * - the user explicitly asks for it
3404 * or
3405 * - we're not a 2e, lesser chipps seem to have problems.
3406 * - we're not on our _very_ small whitelist. some implemenetations
3407 * really dont' like the pm code, others require it.
3408 * feel free to expand this as required.
3409 */
3410 #define SUBSYSTEM_VENDOR(x) (x&0xffff)
3411 if( (use_pm != 1) &&
3412 ((card_type != TYPE_MAESTRO2E) || (SUBSYSTEM_VENDOR(n) != 0x1028)))
3413 use_pm = 0;
3414
3415 if(!use_pm)
3416 printk(KERN_INFO "maestro: not attempting power management.\n");
3417 else {
3418 if(!parse_power(card,pcidev))
3419 printk(KERN_INFO "maestro: no PCI power managment interface found.\n");
3420 else {
3421 pci_read_config_dword(pcidev, card->power_regs, &n);
3422 printk(KERN_INFO "maestro: PCI power managment capability: 0x%x\n",n>>16);
3423 }
3424 }
3425
3426 maestro_config(card);
3427
3428 if(maestro_ac97_get(card, 0x00)==0x0080) {
3429 printk(KERN_ERR "maestro: my goodness! you seem to have a pt101 codec, which is quite rare.\n"
3430 "\tyou should tell someone about this.\n");
3431 } else {
3432 maestro_ac97_init(card);
3433 }
3434
3435 if ((card->dev_mixer = register_sound_mixer(&ess_mixer_fops, -1)) < 0) {
3436 printk("maestro: couldn't register mixer!\n");
3437 } else {
3438 memcpy(card->mix.mixer_state,mixer_defaults,sizeof(card->mix.mixer_state));
3439 mixer_push_state(card);
3440 }
3441
3442 if(request_irq(card->irq, ess_interrupt, SA_SHIRQ, card_names[card_type], card))
3443 {
3444 printk(KERN_ERR "maestro: unable to allocate irq %d,\n", card->irq);
3445 unregister_sound_mixer(card->dev_mixer);
3446 for(i=0;i<NR_DSPS;i++)
3447 {
3448 struct ess_state *s = &card->channels[i];
3449 if(s->dev_audio != -1)
3450 unregister_sound_dsp(s->dev_audio);
3451 }
3452 release_region(card->iobase, 256);
3453 unregister_reboot_notifier(&maestro_nb);
3454 kfree(card);
3455 return 0;
3456 }
3457 /* now go to sleep 'till something interesting happens */
3458 maestro_power(card,ACPI_D2);
3459
3460 printk(KERN_INFO "maestro: %d channels configured.\n", num);
3461 return 1;
3462 }
3463
3464 int __init init_maestro(void)
3465 {
3466 struct pci_dev *pcidev = NULL;
3467 int foundone = 0;
3468
3469 if (!pci_present()) /* No PCI bus in this machine! */
3470 return -ENODEV;
3471 printk(KERN_INFO "maestro: version " DRIVER_VERSION " time " __TIME__ " " __DATE__ "\n");
3472
3473 pcidev = NULL;
3474
3475 if (dsps_order < 0) {
3476 dsps_order = 1;
3477 printk(KERN_WARNING "maestro: clipping dsps_order to %d\n",dsps_order);
3478 }
3479 else if (dsps_order > MAX_DSP_ORDER) {
3480 dsps_order = MAX_DSP_ORDER;
3481 printk(KERN_WARNING "maestro: clipping dsps_order to %d\n",dsps_order);
3482 }
3483
3484 /*
3485 * Find the ESS Maestro 2.
3486 */
3487
3488 while( (pcidev = pci_find_device(PCI_VENDOR_ESS, PCI_DEVICE_ID_ESS_ESS1968, pcidev))!=NULL ) {
3489 if (maestro_install(pcidev, TYPE_MAESTRO2))
3490 foundone=1;
3491 }
3492
3493 /*
3494 * Find the ESS Maestro 2E
3495 */
3496
3497 while( (pcidev = pci_find_device(PCI_VENDOR_ESS, PCI_DEVICE_ID_ESS_ESS1978, pcidev))!=NULL) {
3498 if (maestro_install(pcidev, TYPE_MAESTRO2E))
3499 foundone=1;
3500 }
3501
3502 /*
3503 * ESS Maestro 1
3504 */
3505
3506 while((pcidev = pci_find_device(PCI_VENDOR_ESS_OLD, PCI_DEVICE_ID_ESS_ESS0100, pcidev))!=NULL) {
3507 if (maestro_install(pcidev, TYPE_MAESTRO))
3508 foundone=1;
3509 }
3510 if( ! foundone ) {
3511 printk("maestro: no devices found.\n");
3512 return -ENODEV;
3513 }
3514 return 0;
3515 }
3516
3517 static void nuke_maestros(void)
3518 {
3519 struct ess_card *card;
3520
3521 /* we do these unconditionally, which is probably wrong */
3522 pm_unregister_all(maestro_pm_callback);
3523 unregister_reboot_notifier(&maestro_nb);
3524
3525 while ((card = devs)) {
3526 int i;
3527 devs = devs->next;
3528
3529 /* XXX maybe should force stop bob, but should be all
3530 stopped by _release by now */
3531 free_irq(card->irq, card);
3532 unregister_sound_mixer(card->dev_mixer);
3533 for(i=0;i<NR_DSPS;i++)
3534 {
3535 struct ess_state *ess = &card->channels[i];
3536 if(ess->dev_audio != -1)
3537 unregister_sound_dsp(ess->dev_audio);
3538 }
3539 /* Goodbye, Mr. Bond. */
3540 maestro_power(card,ACPI_D3);
3541 release_region(card->iobase, 256);
3542 kfree(card);
3543 }
3544 devs = NULL;
3545 }
3546
3547 static int maestro_notifier(struct notifier_block *nb, unsigned long event, void *buf)
3548 {
3549 /* this notifier is called when the kernel is really shut down. */
3550 M_printk("maestro: shutting down\n");
3551 nuke_maestros();
3552 return NOTIFY_OK;
3553 }
3554
3555 /* --------------------------------------------------------------------- */
3556
3557 #ifdef MODULE
3558 MODULE_AUTHOR("Zach Brown <zab@zabbo.net>, Alan Cox <alan@redhat.com>");
3559 MODULE_DESCRIPTION("ESS Maestro Driver");
3560 #ifdef M_DEBUG
3561 MODULE_PARM(debug,"i");
3562 #endif
3563 MODULE_PARM(dsps_order,"i");
3564 MODULE_PARM(use_pm,"i");
3565
3566 void cleanup_module(void) {
3567 M_printk("maestro: unloading\n");
3568 nuke_maestros();
3569 }
3570
3571 #endif
3572
3573 /* --------------------------------------------------------------------- */
3574
3575 void
3576 check_suspend(struct ess_card *card)
3577 {
3578 DECLARE_WAITQUEUE(wait, current);
3579
3580 if(!card->in_suspend) return;
3581
3582 card->in_suspend++;
3583 add_wait_queue(&(card->suspend_queue), &wait);
3584 current->state = TASK_UNINTERRUPTIBLE;
3585 schedule();
3586 remove_wait_queue(&(card->suspend_queue), &wait);
3587 current->state = TASK_RUNNING;
3588 }
3589
3590 static int
3591 maestro_suspend(struct ess_card *card)
3592 {
3593 unsigned long flags;
3594 int i,j;
3595
3596 save_flags(flags);
3597 cli(); /* over-kill */
3598
3599 M_printk("maestro: apm in dev %p\n",card);
3600
3601 /* we have to read from the apu regs, need
3602 to power it up */
3603 maestro_power(card,ACPI_D0);
3604
3605 for(i=0;i<NR_DSPS;i++) {
3606 struct ess_state *s = &card->channels[i];
3607
3608 if(s->dev_audio == -1)
3609 continue;
3610
3611 M_printk("maestro: stopping apus for device %d\n",i);
3612 stop_dac(s);
3613 stop_adc(s);
3614 for(j=0;j<6;j++)
3615 card->apu_map[s->apu[j]][5]=apu_get_register(s,j,5);
3616
3617 }
3618
3619 /* get rid of interrupts? */
3620 if( card->dsps_open > 0)
3621 stop_bob(&card->channels[0]);
3622
3623 card->in_suspend++;
3624
3625 restore_flags(flags);
3626
3627 /* we trust in the bios to power down the chip on suspend.
3628 * XXX I'm also not sure that in_suspend will protect
3629 * against all reg accesses from here on out.
3630 */
3631 return 0;
3632 }
3633 static int
3634 maestro_resume(struct ess_card *card)
3635 {
3636 unsigned long flags;
3637 int i;
3638
3639 save_flags(flags);
3640 cli(); /* over-kill */
3641
3642 card->in_suspend = 0;
3643
3644 M_printk("maestro: resuming card at %p\n",card);
3645
3646 /* restore all our config */
3647 maestro_config(card);
3648 /* need to restore the base pointers.. */
3649 if(card->dmapages)
3650 set_base_registers(&card->channels[0],card->dmapages);
3651
3652 mixer_push_state(card);
3653
3654 /* set each channels' apu control registers before
3655 * restoring audio
3656 */
3657 for(i=0;i<NR_DSPS;i++) {
3658 struct ess_state *s = &card->channels[i];
3659 int chan,reg;
3660
3661 if(s->dev_audio == -1)
3662 continue;
3663
3664 for(chan = 0 ; chan < 6 ; chan++) {
3665 wave_set_register(s,s->apu[chan]<<3,s->apu_base[chan]);
3666 for(reg = 1 ; reg < NR_APU_REGS ; reg++)
3667 apu_set_register(s,chan,reg,s->card->apu_map[s->apu[chan]][reg]);
3668 }
3669 for(chan = 0 ; chan < 6 ; chan++)
3670 apu_set_register(s,chan,0,s->card->apu_map[s->apu[chan]][0] & 0xFF0F);
3671 }
3672
3673 /* now we flip on the music */
3674
3675 if( card->dsps_open <= 0) {
3676 /* this card's idle */
3677 maestro_power(card,ACPI_D2);
3678 } else {
3679 /* ok, we're actually playing things on
3680 this card */
3681 maestro_power(card,ACPI_D0);
3682 start_bob(&card->channels[0]);
3683 for(i=0;i<NR_DSPS;i++) {
3684 struct ess_state *s = &card->channels[i];
3685
3686 /* these use the apu_mode, and can handle
3687 spurious calls */
3688 start_dac(s);
3689 start_adc(s);
3690 }
3691 }
3692
3693 restore_flags(flags);
3694
3695 /* all right, we think things are ready,
3696 wake up people who were using the device
3697 when we suspended */
3698 wake_up(&(card->suspend_queue));
3699
3700 return 0;
3701 }
3702
3703 int
3704 maestro_pm_callback(struct pm_dev *dev, pm_request_t rqst, void *data)
3705 {
3706 struct ess_card *card = (struct ess_card*) dev->data;
3707
3708 if ( ! card ) goto out;
3709
3710 M_printk("maestro: pm event 0x%x received for card %p\n", rqst, card);
3711
3712 switch (rqst) {
3713 case PM_SUSPEND:
3714 maestro_suspend(card);
3715 break;
3716 case PM_RESUME:
3717 maestro_resume(card);
3718 break;
3719 /*
3720 * we'd also like to find out about
3721 * power level changes because some biosen
3722 * do mean things to the maestro when they
3723 * change their power state.
3724 */
3725 }
3726 out:
3727 return 0;
3728 }
3729
3730 module_init(init_maestro);
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