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[davej-history.git] / drivers / sound / es1371.c
blobc32568281e6815020da294e87e20516dd9c02b53
1 /*****************************************************************************/
2
3 /*
4 * es1371.c -- Creative Ensoniq ES1371.
5 *
6 * Copyright (C) 1998-2000 Thomas Sailer (sailer@ife.ee.ethz.ch)
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 *
22 * Special thanks to Ensoniq
23 *
24 *
25 * Module command line parameters:
26 * joystick must be set to the base I/O-Port to be used for
27 * the gameport. Legal values are 0x200, 0x208, 0x210 and 0x218.
28 * The gameport is mirrored eight times.
29 *
30 * Supported devices:
31 * /dev/dsp standard /dev/dsp device, (mostly) OSS compatible
32 * /dev/mixer standard /dev/mixer device, (mostly) OSS compatible
33 * /dev/dsp1 additional DAC, like /dev/dsp, but outputs to mixer "SYNTH" setting
34 * /dev/midi simple MIDI UART interface, no ioctl
35 *
36 * NOTE: the card does not have any FM/Wavetable synthesizer, it is supposed
37 * to be done in software. That is what /dev/dac is for. By now (Q2 1998)
38 * there are several MIDI to PCM (WAV) packages, one of them is timidity.
39 *
40 * Revision history
41 * 04.06.1998 0.1 Initial release
42 * Mixer stuff should be overhauled; especially optional AC97 mixer bits
43 * should be detected. This results in strange behaviour of some mixer
44 * settings, like master volume and mic.
45 * 08.06.1998 0.2 First release using Alan Cox' soundcore instead of miscdevice
46 * 03.08.1998 0.3 Do not include modversions.h
47 * Now mixer behaviour can basically be selected between
48 * "OSS documented" and "OSS actual" behaviour
49 * 31.08.1998 0.4 Fix realplayer problems - dac.count issues
50 * 27.10.1998 0.5 Fix joystick support
51 * -- Oliver Neukum (c188@org.chemie.uni-muenchen.de)
52 * 10.12.1998 0.6 Fix drain_dac trying to wait on not yet initialized DMA
53 * 23.12.1998 0.7 Fix a few f_file & FMODE_ bugs
54 * Don't wake up app until there are fragsize bytes to read/write
55 * 06.01.1999 0.8 remove the silly SA_INTERRUPT flag.
56 * hopefully killed the egcs section type conflict
57 * 12.03.1999 0.9 cinfo.blocks should be reset after GETxPTR ioctl.
58 * reported by Johan Maes <joma@telindus.be>
59 * 22.03.1999 0.10 return EAGAIN instead of EBUSY when O_NONBLOCK
60 * read/write cannot be executed
61 * 07.04.1999 0.11 implemented the following ioctl's: SOUND_PCM_READ_RATE,
62 * SOUND_PCM_READ_CHANNELS, SOUND_PCM_READ_BITS;
63 * Alpha fixes reported by Peter Jones <pjones@redhat.com>
64 * Another Alpha fix (wait_src_ready in init routine)
65 * reported by "Ivan N. Kokshaysky" <ink@jurassic.park.msu.ru>
66 * Note: joystick address handling might still be wrong on archs
67 * other than i386
68 * 15.06.1999 0.12 Fix bad allocation bug.
69 * Thanks to Deti Fliegl <fliegl@in.tum.de>
70 * 28.06.1999 0.13 Add pci_set_master
71 * 03.08.1999 0.14 adapt to Linus' new __setup/__initcall
72 * added kernel command line option "es1371=joystickaddr"
73 * removed CONFIG_SOUND_ES1371_JOYPORT_BOOT kludge
74 * 10.08.1999 0.15 (Re)added S/PDIF module option for cards revision >= 4.
75 * Initial version by Dave Platt <dplatt@snulbug.mtview.ca.us>.
76 * module_init/__setup fixes
77 * 08.16.1999 0.16 Joe Cotellese <joec@ensoniq.com>
78 * Added detection for ES1371 revision ID so that we can
79 * detect the ES1373 and later parts.
80 * added AC97 #defines for readability
81 * added a /proc file system for dumping hardware state
82 * updated SRC and CODEC w/r functions to accomodate bugs
83 * in some versions of the ES137x chips.
84 * 31.08.1999 0.17 add spin_lock_init
85 * __initlocaldata to fix gcc 2.7.x problems
86 * replaced current->state = x with set_current_state(x)
87 * 03.09.1999 0.18 change read semantics for MIDI to match
88 * OSS more closely; remove possible wakeup race
89 * 21.10.1999 0.19 Round sampling rates, requested by
90 * Kasamatsu Kenichi <t29w0267@ip.media.kyoto-u.ac.jp>
91 * 27.10.1999 0.20 Added SigmaTel 3D enhancement string
92 * Codec ID printing changes
93 * 28.10.1999 0.21 More waitqueue races fixed
94 * Joe Cotellese <joec@ensoniq.com>
95 * Changed PCI detection routine so we can more easily
96 * detect ES137x chip and derivatives.
97 * 05.01.2000 0.22 Should now work with rev7 boards; patch by
98 * Eric Lemar, elemar@cs.washington.edu
99 * 08.01.2000 0.23 Prevent some ioctl's from returning bad count values on underrun/overrun;
100 * Tim Janik's BSE (Bedevilled Sound Engine) found this
101 * 07.02.2000 0.24 Use pci_alloc_consistent and pci_register_driver
102 * 07.02.2000 0.25 Use ac97_codec
103 * 01.03.2000 0.26 SPDIF patch by Mikael Bouillot <mikael.bouillot@bigfoot.com>
104 * Use pci_module_init
105 */
106
107 /*****************************************************************************/
108
109 #include <linux/version.h>
110 #include <linux/module.h>
111 #include <linux/string.h>
112 #include <linux/ioport.h>
113 #include <linux/sched.h>
114 #include <linux/delay.h>
115 #include <linux/sound.h>
116 #include <linux/malloc.h>
117 #include <linux/soundcard.h>
118 #include <linux/pci.h>
119 #include <linux/init.h>
120 #include <linux/poll.h>
121 #include <linux/bitops.h>
122 #include <linux/proc_fs.h>
123 #include <linux/spinlock.h>
124 #include <linux/smp_lock.h>
125 #include <linux/ac97_codec.h>
126 #include <linux/wrapper.h>
127 #include <asm/io.h>
128 #include <asm/dma.h>
129 #include <asm/uaccess.h>
130 #include <asm/hardirq.h>
131
132 /* --------------------------------------------------------------------- */
133
134 #undef OSS_DOCUMENTED_MIXER_SEMANTICS
135 #define ES1371_DEBUG
136 #define DBG(x) {}
137 /*#define DBG(x) {x}*/
138
139 /* --------------------------------------------------------------------- */
140
141 #ifndef PCI_VENDOR_ID_ENSONIQ
142 #define PCI_VENDOR_ID_ENSONIQ 0x1274
143 #endif
144
145 #ifndef PCI_VENDOR_ID_ECTIVA
146 #define PCI_VENDOR_ID_ECTIVA 0x1102
147 #endif
148
149 #ifndef PCI_DEVICE_ID_ENSONIQ_ES1371
150 #define PCI_DEVICE_ID_ENSONIQ_ES1371 0x1371
151 #endif
152
153 #ifndef PCI_DEVICE_ID_ENSONIQ_CT5880
154 #define PCI_DEVICE_ID_ENSONIQ_CT5880 0x5880
155 #endif
156
157 #ifndef PCI_DEVICE_ID_ECTIVA_EV1938
158 #define PCI_DEVICE_ID_ECTIVA_EV1938 0x8938
159 #endif
160
161 /* ES1371 chip ID */
162 /* This is a little confusing because all ES1371 compatible chips have the
163 same DEVICE_ID, the only thing differentiating them is the REV_ID field.
164 This is only significant if you want to enable features on the later parts.
165 Yes, I know it's stupid and why didn't we use the sub IDs?
166 */
167 #define ES1371REV_ES1373_A 0x04
168 #define ES1371REV_ES1373_B 0x06
169 #define ES1371REV_CT5880_A 0x07
170 #define CT5880REV_CT5880_C 0x02
171 #define ES1371REV_ES1371_B 0x09
172 #define EV1938REV_EV1938_A 0x00
173 #define ES1371REV_ES1373_8 0x08
174
175 #define ES1371_MAGIC ((PCI_VENDOR_ID_ENSONIQ<<16)|PCI_DEVICE_ID_ENSONIQ_ES1371)
176
177 #define ES1371_EXTENT 0x40
178 #define JOY_EXTENT 8
179
180 #define ES1371_REG_CONTROL 0x00
181 #define ES1371_REG_STATUS 0x04 /* on the 5880 it is control/status */
182 #define ES1371_REG_UART_DATA 0x08
183 #define ES1371_REG_UART_STATUS 0x09
184 #define ES1371_REG_UART_CONTROL 0x09
185 #define ES1371_REG_UART_TEST 0x0a
186 #define ES1371_REG_MEMPAGE 0x0c
187 #define ES1371_REG_SRCONV 0x10
188 #define ES1371_REG_CODEC 0x14
189 #define ES1371_REG_LEGACY 0x18
190 #define ES1371_REG_SERIAL_CONTROL 0x20
191 #define ES1371_REG_DAC1_SCOUNT 0x24
192 #define ES1371_REG_DAC2_SCOUNT 0x28
193 #define ES1371_REG_ADC_SCOUNT 0x2c
194
195 #define ES1371_REG_DAC1_FRAMEADR 0xc30
196 #define ES1371_REG_DAC1_FRAMECNT 0xc34
197 #define ES1371_REG_DAC2_FRAMEADR 0xc38
198 #define ES1371_REG_DAC2_FRAMECNT 0xc3c
199 #define ES1371_REG_ADC_FRAMEADR 0xd30
200 #define ES1371_REG_ADC_FRAMECNT 0xd34
201
202 #define ES1371_FMT_U8_MONO 0
203 #define ES1371_FMT_U8_STEREO 1
204 #define ES1371_FMT_S16_MONO 2
205 #define ES1371_FMT_S16_STEREO 3
206 #define ES1371_FMT_STEREO 1
207 #define ES1371_FMT_S16 2
208 #define ES1371_FMT_MASK 3
209
210 static const unsigned sample_size[] = { 1, 2, 2, 4 };
211 static const unsigned sample_shift[] = { 0, 1, 1, 2 };
212
213 #define CTRL_RECEN_B 0x08000000 /* 1 = don't mix analog in to digital out */
214 #define CTRL_SPDIFEN_B 0x04000000
215 #define CTRL_JOY_SHIFT 24
216 #define CTRL_JOY_MASK 3
217 #define CTRL_JOY_200 0x00000000 /* joystick base address */
218 #define CTRL_JOY_208 0x01000000
219 #define CTRL_JOY_210 0x02000000
220 #define CTRL_JOY_218 0x03000000
221 #define CTRL_GPIO_IN0 0x00100000 /* general purpose inputs/outputs */
222 #define CTRL_GPIO_IN1 0x00200000
223 #define CTRL_GPIO_IN2 0x00400000
224 #define CTRL_GPIO_IN3 0x00800000
225 #define CTRL_GPIO_OUT0 0x00010000
226 #define CTRL_GPIO_OUT1 0x00020000
227 #define CTRL_GPIO_OUT2 0x00040000
228 #define CTRL_GPIO_OUT3 0x00080000
229 #define CTRL_MSFMTSEL 0x00008000 /* MPEG serial data fmt: 0 = Sony, 1 = I2S */
230 #define CTRL_SYNCRES 0x00004000 /* AC97 warm reset */
231 #define CTRL_ADCSTOP 0x00002000 /* stop ADC transfers */
232 #define CTRL_PWR_INTRM 0x00001000 /* 1 = power level ints enabled */
233 #define CTRL_M_CB 0x00000800 /* recording source: 0 = ADC, 1 = MPEG */
234 #define CTRL_CCB_INTRM 0x00000400 /* 1 = CCB "voice" ints enabled */
235 #define CTRL_PDLEV0 0x00000000 /* power down level */
236 #define CTRL_PDLEV1 0x00000100
237 #define CTRL_PDLEV2 0x00000200
238 #define CTRL_PDLEV3 0x00000300
239 #define CTRL_BREQ 0x00000080 /* 1 = test mode (internal mem test) */
240 #define CTRL_DAC1_EN 0x00000040 /* enable DAC1 */
241 #define CTRL_DAC2_EN 0x00000020 /* enable DAC2 */
242 #define CTRL_ADC_EN 0x00000010 /* enable ADC */
243 #define CTRL_UART_EN 0x00000008 /* enable MIDI uart */
244 #define CTRL_JYSTK_EN 0x00000004 /* enable Joystick port */
245 #define CTRL_XTALCLKDIS 0x00000002 /* 1 = disable crystal clock input */
246 #define CTRL_PCICLKDIS 0x00000001 /* 1 = disable PCI clock distribution */
247
248
249 #define STAT_INTR 0x80000000 /* wired or of all interrupt bits */
250 #define CSTAT_5880_AC97_RST 0x20000000 /* CT5880 Reset bit */
251 #define STAT_EN_SPDIF 0x00040000 /* enable S/PDIF circuitry */
252 #define STAT_TS_SPDIF 0x00020000 /* test S/PDIF circuitry */
253 #define STAT_TESTMODE 0x00010000 /* test ASIC */
254 #define STAT_SYNC_ERR 0x00000100 /* 1 = codec sync error */
255 #define STAT_VC 0x000000c0 /* CCB int source, 0=DAC1, 1=DAC2, 2=ADC, 3=undef */
256 #define STAT_SH_VC 6
257 #define STAT_MPWR 0x00000020 /* power level interrupt */
258 #define STAT_MCCB 0x00000010 /* CCB int pending */
259 #define STAT_UART 0x00000008 /* UART int pending */
260 #define STAT_DAC1 0x00000004 /* DAC1 int pending */
261 #define STAT_DAC2 0x00000002 /* DAC2 int pending */
262 #define STAT_ADC 0x00000001 /* ADC int pending */
263
264 #define USTAT_RXINT 0x80 /* UART rx int pending */
265 #define USTAT_TXINT 0x04 /* UART tx int pending */
266 #define USTAT_TXRDY 0x02 /* UART tx ready */
267 #define USTAT_RXRDY 0x01 /* UART rx ready */
268
269 #define UCTRL_RXINTEN 0x80 /* 1 = enable RX ints */
270 #define UCTRL_TXINTEN 0x60 /* TX int enable field mask */
271 #define UCTRL_ENA_TXINT 0x20 /* enable TX int */
272 #define UCTRL_CNTRL 0x03 /* control field */
273 #define UCTRL_CNTRL_SWR 0x03 /* software reset command */
274
275 /* sample rate converter */
276 #define SRC_OKSTATE 1
277
278 #define SRC_RAMADDR_MASK 0xfe000000
279 #define SRC_RAMADDR_SHIFT 25
280 #define SRC_DAC1FREEZE (1UL << 21)
281 #define SRC_DAC2FREEZE (1UL << 20)
282 #define SRC_ADCFREEZE (1UL << 19)
283
284
285 #define SRC_WE 0x01000000 /* read/write control for SRC RAM */
286 #define SRC_BUSY 0x00800000 /* SRC busy */
287 #define SRC_DIS 0x00400000 /* 1 = disable SRC */
288 #define SRC_DDAC1 0x00200000 /* 1 = disable accum update for DAC1 */
289 #define SRC_DDAC2 0x00100000 /* 1 = disable accum update for DAC2 */
290 #define SRC_DADC 0x00080000 /* 1 = disable accum update for ADC2 */
291 #define SRC_CTLMASK 0x00780000
292 #define SRC_RAMDATA_MASK 0x0000ffff
293 #define SRC_RAMDATA_SHIFT 0
294
295 #define SRCREG_ADC 0x78
296 #define SRCREG_DAC1 0x70
297 #define SRCREG_DAC2 0x74
298 #define SRCREG_VOL_ADC 0x6c
299 #define SRCREG_VOL_DAC1 0x7c
300 #define SRCREG_VOL_DAC2 0x7e
301
302 #define SRCREG_TRUNC_N 0x00
303 #define SRCREG_INT_REGS 0x01
304 #define SRCREG_ACCUM_FRAC 0x02
305 #define SRCREG_VFREQ_FRAC 0x03
306
307 #define CODEC_PIRD 0x00800000 /* 0 = write AC97 register */
308 #define CODEC_PIADD_MASK 0x007f0000
309 #define CODEC_PIADD_SHIFT 16
310 #define CODEC_PIDAT_MASK 0x0000ffff
311 #define CODEC_PIDAT_SHIFT 0
312
313 #define CODEC_RDY 0x80000000 /* AC97 read data valid */
314 #define CODEC_WIP 0x40000000 /* AC97 write in progress */
315 #define CODEC_PORD 0x00800000 /* 0 = write AC97 register */
316 #define CODEC_POADD_MASK 0x007f0000
317 #define CODEC_POADD_SHIFT 16
318 #define CODEC_PODAT_MASK 0x0000ffff
319 #define CODEC_PODAT_SHIFT 0
320
321
322 #define LEGACY_JFAST 0x80000000 /* fast joystick timing */
323 #define LEGACY_FIRQ 0x01000000 /* force IRQ */
324
325 #define SCTRL_DACTEST 0x00400000 /* 1 = DAC test, test vector generation purposes */
326 #define SCTRL_P2ENDINC 0x00380000 /* */
327 #define SCTRL_SH_P2ENDINC 19
328 #define SCTRL_P2STINC 0x00070000 /* */
329 #define SCTRL_SH_P2STINC 16
330 #define SCTRL_R1LOOPSEL 0x00008000 /* 0 = loop mode */
331 #define SCTRL_P2LOOPSEL 0x00004000 /* 0 = loop mode */
332 #define SCTRL_P1LOOPSEL 0x00002000 /* 0 = loop mode */
333 #define SCTRL_P2PAUSE 0x00001000 /* 1 = pause mode */
334 #define SCTRL_P1PAUSE 0x00000800 /* 1 = pause mode */
335 #define SCTRL_R1INTEN 0x00000400 /* enable interrupt */
336 #define SCTRL_P2INTEN 0x00000200 /* enable interrupt */
337 #define SCTRL_P1INTEN 0x00000100 /* enable interrupt */
338 #define SCTRL_P1SCTRLD 0x00000080 /* reload sample count register for DAC1 */
339 #define SCTRL_P2DACSEN 0x00000040 /* 1 = DAC2 play back last sample when disabled */
340 #define SCTRL_R1SEB 0x00000020 /* 1 = 16bit */
341 #define SCTRL_R1SMB 0x00000010 /* 1 = stereo */
342 #define SCTRL_R1FMT 0x00000030 /* format mask */
343 #define SCTRL_SH_R1FMT 4
344 #define SCTRL_P2SEB 0x00000008 /* 1 = 16bit */
345 #define SCTRL_P2SMB 0x00000004 /* 1 = stereo */
346 #define SCTRL_P2FMT 0x0000000c /* format mask */
347 #define SCTRL_SH_P2FMT 2
348 #define SCTRL_P1SEB 0x00000002 /* 1 = 16bit */
349 #define SCTRL_P1SMB 0x00000001 /* 1 = stereo */
350 #define SCTRL_P1FMT 0x00000003 /* format mask */
351 #define SCTRL_SH_P1FMT 0
352
353
354 /* misc stuff */
355 #define POLL_COUNT 0x1000
356 #define FMODE_DAC 4 /* slight misuse of mode_t */
357
358 /* MIDI buffer sizes */
359
360 #define MIDIINBUF 256
361 #define MIDIOUTBUF 256
362
363 #define FMODE_MIDI_SHIFT 3
364 #define FMODE_MIDI_READ (FMODE_READ << FMODE_MIDI_SHIFT)
365 #define FMODE_MIDI_WRITE (FMODE_WRITE << FMODE_MIDI_SHIFT)
366
367 #define ES1371_MODULE_NAME "es1371"
368 #define PFX ES1371_MODULE_NAME ": "
369
370 /* --------------------------------------------------------------------- */
371
372 struct es1371_state {
373 /* magic */
374 unsigned int magic;
375
376 /* list of es1371 devices */
377 struct list_head devs;
378
379 /* the corresponding pci_dev structure */
380 struct pci_dev *dev;
381
382 /* soundcore stuff */
383 int dev_audio;
384 int dev_dac;
385 int dev_midi;
386
387 /* hardware resources */
388 unsigned long io; /* long for SPARC */
389 unsigned int irq;
390
391 /* PCI ID's */
392 u16 vendor;
393 u16 device;
394 u8 rev; /* the chip revision */
395
396 /* options */
397 int spdif_volume; /* S/PDIF output is enabled if != -1 */
398
399 #ifdef ES1371_DEBUG
400 /* debug /proc entry */
401 struct proc_dir_entry *ps;
402 #endif /* ES1371_DEBUG */
403
404 struct ac97_codec codec;
405
406 /* wave stuff */
407 unsigned ctrl;
408 unsigned sctrl;
409 unsigned dac1rate, dac2rate, adcrate;
410
411 spinlock_t lock;
412 struct semaphore open_sem;
413 mode_t open_mode;
414 wait_queue_head_t open_wait;
415
416 struct dmabuf {
417 void *rawbuf;
418 dma_addr_t dmaaddr;
419 unsigned buforder;
420 unsigned numfrag;
421 unsigned fragshift;
422 unsigned hwptr, swptr;
423 unsigned total_bytes;
424 int count;
425 unsigned error; /* over/underrun */
426 wait_queue_head_t wait;
427 /* redundant, but makes calculations easier */
428 unsigned fragsize;
429 unsigned dmasize;
430 unsigned fragsamples;
431 /* OSS stuff */
432 unsigned mapped:1;
433 unsigned ready:1;
434 unsigned endcleared:1;
435 unsigned ossfragshift;
436 int ossmaxfrags;
437 unsigned subdivision;
438 } dma_dac1, dma_dac2, dma_adc;
439
440 /* midi stuff */
441 struct {
442 unsigned ird, iwr, icnt;
443 unsigned ord, owr, ocnt;
444 wait_queue_head_t iwait;
445 wait_queue_head_t owait;
446 unsigned char ibuf[MIDIINBUF];
447 unsigned char obuf[MIDIOUTBUF];
448 } midi;
449 };
450
451 /* --------------------------------------------------------------------- */
452
453 static LIST_HEAD(devs);
454
455 /* --------------------------------------------------------------------- */
456
457 extern inline unsigned ld2(unsigned int x)
458 {
459 unsigned r = 0;
460
461 if (x >= 0x10000) {
462 x >>= 16;
463 r += 16;
464 }
465 if (x >= 0x100) {
466 x >>= 8;
467 r += 8;
468 }
469 if (x >= 0x10) {
470 x >>= 4;
471 r += 4;
472 }
473 if (x >= 4) {
474 x >>= 2;
475 r += 2;
476 }
477 if (x >= 2)
478 r++;
479 return r;
480 }
481
482 /* --------------------------------------------------------------------- */
483
484 static unsigned wait_src_ready(struct es1371_state *s)
485 {
486 unsigned int t, r;
487
488 for (t = 0; t < POLL_COUNT; t++) {
489 if (!((r = inl(s->io + ES1371_REG_SRCONV)) & SRC_BUSY))
490 return r;
491 udelay(1);
492 }
493 printk(KERN_DEBUG PFX "sample rate converter timeout r = 0x%08x\n", r);
494 return r;
495 }
496
497 static unsigned src_read(struct es1371_state *s, unsigned reg)
498 {
499 unsigned int temp,i,orig;
500
501 /* wait for ready */
502 temp = wait_src_ready (s);
503
504 /* we can only access the SRC at certain times, make sure
505 we're allowed to before we read */
506
507 orig = temp;
508 /* expose the SRC state bits */
509 outl ( (temp & SRC_CTLMASK) | (reg << SRC_RAMADDR_SHIFT) | 0x10000UL,
510 s->io + ES1371_REG_SRCONV);
511
512 /* now, wait for busy and the correct time to read */
513 temp = wait_src_ready (s);
514
515 if ( (temp & 0x00870000UL ) != ( SRC_OKSTATE << 16 )){
516 /* wait for the right state */
517 for (i=0; i<POLL_COUNT; i++){
518 temp = inl (s->io + ES1371_REG_SRCONV);
519 if ( (temp & 0x00870000UL ) == ( SRC_OKSTATE << 16 ))
520 break;
521 }
522 }
523
524 /* hide the state bits */
525 outl ((orig & SRC_CTLMASK) | (reg << SRC_RAMADDR_SHIFT), s->io + ES1371_REG_SRCONV);
526 return temp;
527
528
529 }
530
531 static void src_write(struct es1371_state *s, unsigned reg, unsigned data)
532 {
533
534 unsigned int r;
535
536 r = wait_src_ready(s) & (SRC_DIS | SRC_DDAC1 | SRC_DDAC2 | SRC_DADC);
537 r |= (reg << SRC_RAMADDR_SHIFT) & SRC_RAMADDR_MASK;
538 r |= (data << SRC_RAMDATA_SHIFT) & SRC_RAMDATA_MASK;
539 outl(r | SRC_WE, s->io + ES1371_REG_SRCONV);
540
541 }
542
543 /* --------------------------------------------------------------------- */
544
545 /* most of the following here is black magic */
546 static void set_adc_rate(struct es1371_state *s, unsigned rate)
547 {
548 unsigned long flags;
549 unsigned int n, truncm, freq;
550
551 if (rate > 48000)
552 rate = 48000;
553 if (rate < 4000)
554 rate = 4000;
555 n = rate / 3000;
556 if ((1 << n) & ((1 << 15) | (1 << 13) | (1 << 11) | (1 << 9)))
557 n--;
558 truncm = (21 * n - 1) | 1;
559 freq = ((48000UL << 15) / rate) * n;
560 s->adcrate = (48000UL << 15) / (freq / n);
561 spin_lock_irqsave(&s->lock, flags);
562 if (rate >= 24000) {
563 if (truncm > 239)
564 truncm = 239;
565 src_write(s, SRCREG_ADC+SRCREG_TRUNC_N,
566 (((239 - truncm) >> 1) << 9) | (n << 4));
567 } else {
568 if (truncm > 119)
569 truncm = 119;
570 src_write(s, SRCREG_ADC+SRCREG_TRUNC_N,
571 0x8000 | (((119 - truncm) >> 1) << 9) | (n << 4));
572 }
573 src_write(s, SRCREG_ADC+SRCREG_INT_REGS,
574 (src_read(s, SRCREG_ADC+SRCREG_INT_REGS) & 0x00ff) |
575 ((freq >> 5) & 0xfc00));
576 src_write(s, SRCREG_ADC+SRCREG_VFREQ_FRAC, freq & 0x7fff);
577 src_write(s, SRCREG_VOL_ADC, n << 8);
578 src_write(s, SRCREG_VOL_ADC+1, n << 8);
579 spin_unlock_irqrestore(&s->lock, flags);
580 }
581
582
583 static void set_dac1_rate(struct es1371_state *s, unsigned rate)
584 {
585 unsigned long flags;
586 unsigned int freq, r;
587
588 if (rate > 48000)
589 rate = 48000;
590 if (rate < 4000)
591 rate = 4000;
592 freq = ((rate << 15) + 1500) / 3000;
593 s->dac1rate = (freq * 3000 + 16384) >> 15;
594 spin_lock_irqsave(&s->lock, flags);
595 r = (wait_src_ready(s) & (SRC_DIS | SRC_DDAC2 | SRC_DADC)) | SRC_DDAC1;
596 outl(r, s->io + ES1371_REG_SRCONV);
597 src_write(s, SRCREG_DAC1+SRCREG_INT_REGS,
598 (src_read(s, SRCREG_DAC1+SRCREG_INT_REGS) & 0x00ff) |
599 ((freq >> 5) & 0xfc00));
600 src_write(s, SRCREG_DAC1+SRCREG_VFREQ_FRAC, freq & 0x7fff);
601 r = (wait_src_ready(s) & (SRC_DIS | SRC_DDAC2 | SRC_DADC));
602 outl(r, s->io + ES1371_REG_SRCONV);
603 spin_unlock_irqrestore(&s->lock, flags);
604 }
605
606 static void set_dac2_rate(struct es1371_state *s, unsigned rate)
607 {
608 unsigned long flags;
609 unsigned int freq, r;
610
611 if (rate > 48000)
612 rate = 48000;
613 if (rate < 4000)
614 rate = 4000;
615 freq = ((rate << 15) + 1500) / 3000;
616 s->dac2rate = (freq * 3000 + 16384) >> 15;
617 spin_lock_irqsave(&s->lock, flags);
618 r = (wait_src_ready(s) & (SRC_DIS | SRC_DDAC1 | SRC_DADC)) | SRC_DDAC2;
619 outl(r, s->io + ES1371_REG_SRCONV);
620 src_write(s, SRCREG_DAC2+SRCREG_INT_REGS,
621 (src_read(s, SRCREG_DAC2+SRCREG_INT_REGS) & 0x00ff) |
622 ((freq >> 5) & 0xfc00));
623 src_write(s, SRCREG_DAC2+SRCREG_VFREQ_FRAC, freq & 0x7fff);
624 r = (wait_src_ready(s) & (SRC_DIS | SRC_DDAC1 | SRC_DADC));
625 outl(r, s->io + ES1371_REG_SRCONV);
626 spin_unlock_irqrestore(&s->lock, flags);
627 }
628
629 /* --------------------------------------------------------------------- */
630
631 static void __init src_init(struct es1371_state *s)
632 {
633 unsigned int i;
634
635 /* before we enable or disable the SRC we need
636 to wait for it to become ready */
637 wait_src_ready(s);
638
639 outl(SRC_DIS, s->io + ES1371_REG_SRCONV);
640
641 for (i = 0; i < 0x80; i++)
642 src_write(s, i, 0);
643
644 src_write(s, SRCREG_DAC1+SRCREG_TRUNC_N, 16 << 4);
645 src_write(s, SRCREG_DAC1+SRCREG_INT_REGS, 16 << 10);
646 src_write(s, SRCREG_DAC2+SRCREG_TRUNC_N, 16 << 4);
647 src_write(s, SRCREG_DAC2+SRCREG_INT_REGS, 16 << 10);
648 src_write(s, SRCREG_VOL_ADC, 1 << 12);
649 src_write(s, SRCREG_VOL_ADC+1, 1 << 12);
650 src_write(s, SRCREG_VOL_DAC1, 1 << 12);
651 src_write(s, SRCREG_VOL_DAC1+1, 1 << 12);
652 src_write(s, SRCREG_VOL_DAC2, 1 << 12);
653 src_write(s, SRCREG_VOL_DAC2+1, 1 << 12);
654 set_adc_rate(s, 22050);
655 set_dac1_rate(s, 22050);
656 set_dac2_rate(s, 22050);
657
658 /* WARNING:
659 * enabling the sample rate converter without properly programming
660 * its parameters causes the chip to lock up (the SRC busy bit will
661 * be stuck high, and I've found no way to rectify this other than
662 * power cycle)
663 */
664 wait_src_ready(s);
665 outl(0, s->io+ES1371_REG_SRCONV);
666 }
667
668 /* --------------------------------------------------------------------- */
669
670 static void wrcodec(struct ac97_codec *codec, u8 addr, u16 data)
671 {
672 struct es1371_state *s = (struct es1371_state *)codec->private_data;
673 unsigned long flags;
674 unsigned t, x;
675
676 for (t = 0; t < POLL_COUNT; t++)
677 if (!(inl(s->io+ES1371_REG_CODEC) & CODEC_WIP))
678 break;
679 spin_lock_irqsave(&s->lock, flags);
680
681 /* save the current state for later */
682 x = wait_src_ready(s);
683
684 /* enable SRC state data in SRC mux */
685 outl((x & (SRC_DIS | SRC_DDAC1 | SRC_DDAC2 | SRC_DADC)) | 0x00010000,
686 s->io+ES1371_REG_SRCONV);
687
688 /* wait for not busy (state 0) first to avoid
689 transition states */
690 for (t=0; t<POLL_COUNT; t++){
691 if((inl(s->io+ES1371_REG_SRCONV) & 0x00870000) ==0 )
692 break;
693 udelay(1);
694 }
695
696 /* wait for a SAFE time to write addr/data and then do it, dammit */
697 for (t=0; t<POLL_COUNT; t++){
698 if((inl(s->io+ES1371_REG_SRCONV) & 0x00870000) ==0x00010000)
699 break;
700 udelay(1);
701 }
702
703 outl(((addr << CODEC_POADD_SHIFT) & CODEC_POADD_MASK) |
704 ((data << CODEC_PODAT_SHIFT) & CODEC_PODAT_MASK), s->io+ES1371_REG_CODEC);
705
706 /* restore SRC reg */
707 wait_src_ready(s);
708 outl(x, s->io+ES1371_REG_SRCONV);
709 spin_unlock_irqrestore(&s->lock, flags);
710 }
711
712 static u16 rdcodec(struct ac97_codec *codec, u8 addr)
713 {
714 struct es1371_state *s = (struct es1371_state *)codec->private_data;
715 unsigned long flags;
716 unsigned t, x;
717
718 /* wait for WIP to go away */
719 for (t = 0; t < 0x1000; t++)
720 if (!(inl(s->io+ES1371_REG_CODEC) & CODEC_WIP))
721 break;
722 spin_lock_irqsave(&s->lock, flags);
723
724 /* save the current state for later */
725 x = (wait_src_ready(s) & (SRC_DIS | SRC_DDAC1 | SRC_DDAC2 | SRC_DADC));
726
727 /* enable SRC state data in SRC mux */
728 outl( x | 0x00010000,
729 s->io+ES1371_REG_SRCONV);
730
731 /* wait for not busy (state 0) first to avoid
732 transition states */
733 for (t=0; t<POLL_COUNT; t++){
734 if((inl(s->io+ES1371_REG_SRCONV) & 0x00870000) ==0 )
735 break;
736 udelay(1);
737 }
738
739 /* wait for a SAFE time to write addr/data and then do it, dammit */
740 for (t=0; t<POLL_COUNT; t++){
741 if((inl(s->io+ES1371_REG_SRCONV) & 0x00870000) ==0x00010000)
742 break;
743 udelay(1);
744 }
745
746 outl(((addr << CODEC_POADD_SHIFT) & CODEC_POADD_MASK) | CODEC_PORD, s->io+ES1371_REG_CODEC);
747 /* restore SRC reg */
748 wait_src_ready(s);
749 outl(x, s->io+ES1371_REG_SRCONV);
750 spin_unlock_irqrestore(&s->lock, flags);
751
752 /* wait for WIP again */
753 for (t = 0; t < 0x1000; t++)
754 if (!(inl(s->io+ES1371_REG_CODEC) & CODEC_WIP))
755 break;
756
757 /* now wait for the stinkin' data (RDY) */
758 for (t = 0; t < POLL_COUNT; t++)
759 if ((x = inl(s->io+ES1371_REG_CODEC)) & CODEC_RDY)
760 break;
761
762 return ((x & CODEC_PIDAT_MASK) >> CODEC_PIDAT_SHIFT);
763 }
764
765 /* --------------------------------------------------------------------- */
766
767 extern inline void stop_adc(struct es1371_state *s)
768 {
769 unsigned long flags;
770
771 spin_lock_irqsave(&s->lock, flags);
772 s->ctrl &= ~CTRL_ADC_EN;
773 outl(s->ctrl, s->io+ES1371_REG_CONTROL);
774 spin_unlock_irqrestore(&s->lock, flags);
775 }
776
777 extern inline void stop_dac1(struct es1371_state *s)
778 {
779 unsigned long flags;
780
781 spin_lock_irqsave(&s->lock, flags);
782 s->ctrl &= ~CTRL_DAC1_EN;
783 outl(s->ctrl, s->io+ES1371_REG_CONTROL);
784 spin_unlock_irqrestore(&s->lock, flags);
785 }
786
787 extern inline void stop_dac2(struct es1371_state *s)
788 {
789 unsigned long flags;
790
791 spin_lock_irqsave(&s->lock, flags);
792 s->ctrl &= ~CTRL_DAC2_EN;
793 outl(s->ctrl, s->io+ES1371_REG_CONTROL);
794 spin_unlock_irqrestore(&s->lock, flags);
795 }
796
797 static void start_dac1(struct es1371_state *s)
798 {
799 unsigned long flags;
800 unsigned fragremain, fshift;
801
802 spin_lock_irqsave(&s->lock, flags);
803 if (!(s->ctrl & CTRL_DAC1_EN) && (s->dma_dac1.mapped || s->dma_dac1.count > 0)
804 && s->dma_dac1.ready) {
805 s->ctrl |= CTRL_DAC1_EN;
806 s->sctrl = (s->sctrl & ~(SCTRL_P1LOOPSEL | SCTRL_P1PAUSE | SCTRL_P1SCTRLD)) | SCTRL_P1INTEN;
807 outl(s->sctrl, s->io+ES1371_REG_SERIAL_CONTROL);
808 fragremain = ((- s->dma_dac1.hwptr) & (s->dma_dac1.fragsize-1));
809 fshift = sample_shift[(s->sctrl & SCTRL_P1FMT) >> SCTRL_SH_P1FMT];
810 if (fragremain < 2*fshift)
811 fragremain = s->dma_dac1.fragsize;
812 outl((fragremain >> fshift) - 1, s->io+ES1371_REG_DAC1_SCOUNT);
813 outl(s->ctrl, s->io+ES1371_REG_CONTROL);
814 outl((s->dma_dac1.fragsize >> fshift) - 1, s->io+ES1371_REG_DAC1_SCOUNT);
815 }
816 spin_unlock_irqrestore(&s->lock, flags);
817 }
818
819 static void start_dac2(struct es1371_state *s)
820 {
821 unsigned long flags;
822 unsigned fragremain, fshift;
823
824 spin_lock_irqsave(&s->lock, flags);
825 if (!(s->ctrl & CTRL_DAC2_EN) && (s->dma_dac2.mapped || s->dma_dac2.count > 0)
826 && s->dma_dac2.ready) {
827 s->ctrl |= CTRL_DAC2_EN;
828 s->sctrl = (s->sctrl & ~(SCTRL_P2LOOPSEL | SCTRL_P2PAUSE | SCTRL_P2DACSEN |
829 SCTRL_P2ENDINC | SCTRL_P2STINC)) | SCTRL_P2INTEN |
830 (((s->sctrl & SCTRL_P2FMT) ? 2 : 1) << SCTRL_SH_P2ENDINC) |
831 (0 << SCTRL_SH_P2STINC);
832 outl(s->sctrl, s->io+ES1371_REG_SERIAL_CONTROL);
833 fragremain = ((- s->dma_dac2.hwptr) & (s->dma_dac2.fragsize-1));
834 fshift = sample_shift[(s->sctrl & SCTRL_P2FMT) >> SCTRL_SH_P2FMT];
835 if (fragremain < 2*fshift)
836 fragremain = s->dma_dac2.fragsize;
837 outl((fragremain >> fshift) - 1, s->io+ES1371_REG_DAC2_SCOUNT);
838 outl(s->ctrl, s->io+ES1371_REG_CONTROL);
839 outl((s->dma_dac2.fragsize >> fshift) - 1, s->io+ES1371_REG_DAC2_SCOUNT);
840 }
841 spin_unlock_irqrestore(&s->lock, flags);
842 }
843
844 static void start_adc(struct es1371_state *s)
845 {
846 unsigned long flags;
847 unsigned fragremain, fshift;
848
849 spin_lock_irqsave(&s->lock, flags);
850 if (!(s->ctrl & CTRL_ADC_EN) && (s->dma_adc.mapped || s->dma_adc.count < (signed)(s->dma_adc.dmasize - 2*s->dma_adc.fragsize))
851 && s->dma_adc.ready) {
852 s->ctrl |= CTRL_ADC_EN;
853 s->sctrl = (s->sctrl & ~SCTRL_R1LOOPSEL) | SCTRL_R1INTEN;
854 outl(s->sctrl, s->io+ES1371_REG_SERIAL_CONTROL);
855 fragremain = ((- s->dma_adc.hwptr) & (s->dma_adc.fragsize-1));
856 fshift = sample_shift[(s->sctrl & SCTRL_R1FMT) >> SCTRL_SH_R1FMT];
857 if (fragremain < 2*fshift)
858 fragremain = s->dma_adc.fragsize;
859 outl((fragremain >> fshift) - 1, s->io+ES1371_REG_ADC_SCOUNT);
860 outl(s->ctrl, s->io+ES1371_REG_CONTROL);
861 outl((s->dma_adc.fragsize >> fshift) - 1, s->io+ES1371_REG_ADC_SCOUNT);
862 }
863 spin_unlock_irqrestore(&s->lock, flags);
864 }
865
866 /* --------------------------------------------------------------------- */
867
868 #define DMABUF_DEFAULTORDER (17-PAGE_SHIFT)
869 #define DMABUF_MINORDER 1
870
871
872 extern inline void dealloc_dmabuf(struct es1371_state *s, struct dmabuf *db)
873 {
874 struct page *page, *pend;
875
876 if (db->rawbuf) {
877 /* undo marking the pages as reserved */
878 pend = virt_to_page(db->rawbuf + (PAGE_SIZE << db->buforder) - 1);
879 for (page = virt_to_page(db->rawbuf); page <= pend; page++)
880 mem_map_unreserve(page);
881 pci_free_consistent(s->dev, PAGE_SIZE << db->buforder, db->rawbuf, db->dmaaddr);
882 }
883 db->rawbuf = NULL;
884 db->mapped = db->ready = 0;
885 }
886
887 static int prog_dmabuf(struct es1371_state *s, struct dmabuf *db, unsigned rate, unsigned fmt, unsigned reg)
888 {
889 int order;
890 unsigned bytepersec;
891 unsigned bufs;
892 struct page *page, *pend;
893
894 db->hwptr = db->swptr = db->total_bytes = db->count = db->error = db->endcleared = 0;
895 if (!db->rawbuf) {
896 db->ready = db->mapped = 0;
897 for (order = DMABUF_DEFAULTORDER; order >= DMABUF_MINORDER; order--)
898 if ((db->rawbuf = pci_alloc_consistent(s->dev, PAGE_SIZE << order, &db->dmaaddr)))
899 break;
900 if (!db->rawbuf)
901 return -ENOMEM;
902 db->buforder = order;
903 /* now mark the pages as reserved; otherwise remap_page_range doesn't do what we want */
904 pend = virt_to_page(db->rawbuf + (PAGE_SIZE << db->buforder) - 1);
905 for (page = virt_to_page(db->rawbuf); page <= pend; page++)
906 mem_map_reserve(page);
907 }
908 fmt &= ES1371_FMT_MASK;
909 bytepersec = rate << sample_shift[fmt];
910 bufs = PAGE_SIZE << db->buforder;
911 if (db->ossfragshift) {
912 if ((1000 << db->ossfragshift) < bytepersec)
913 db->fragshift = ld2(bytepersec/1000);
914 else
915 db->fragshift = db->ossfragshift;
916 } else {
917 db->fragshift = ld2(bytepersec/100/(db->subdivision ? db->subdivision : 1));
918 if (db->fragshift < 3)
919 db->fragshift = 3;
920 }
921 db->numfrag = bufs >> db->fragshift;
922 while (db->numfrag < 4 && db->fragshift > 3) {
923 db->fragshift--;
924 db->numfrag = bufs >> db->fragshift;
925 }
926 db->fragsize = 1 << db->fragshift;
927 if (db->ossmaxfrags >= 4 && db->ossmaxfrags < db->numfrag)
928 db->numfrag = db->ossmaxfrags;
929 db->fragsamples = db->fragsize >> sample_shift[fmt];
930 db->dmasize = db->numfrag << db->fragshift;
931 memset(db->rawbuf, (fmt & ES1371_FMT_S16) ? 0 : 0x80, db->dmasize);
932 outl((reg >> 8) & 15, s->io+ES1371_REG_MEMPAGE);
933 outl(db->dmaaddr, s->io+(reg & 0xff));
934 outl((db->dmasize >> 2)-1, s->io+((reg + 4) & 0xff));
935 db->ready = 1;
936 return 0;
937 }
938
939 extern inline int prog_dmabuf_adc(struct es1371_state *s)
940 {
941 stop_adc(s);
942 return prog_dmabuf(s, &s->dma_adc, s->adcrate, (s->sctrl >> SCTRL_SH_R1FMT) & ES1371_FMT_MASK,
943 ES1371_REG_ADC_FRAMEADR);
944 }
945
946 extern inline int prog_dmabuf_dac2(struct es1371_state *s)
947 {
948 stop_dac2(s);
949 return prog_dmabuf(s, &s->dma_dac2, s->dac2rate, (s->sctrl >> SCTRL_SH_P2FMT) & ES1371_FMT_MASK,
950 ES1371_REG_DAC2_FRAMEADR);
951 }
952
953 extern inline int prog_dmabuf_dac1(struct es1371_state *s)
954 {
955 stop_dac1(s);
956 return prog_dmabuf(s, &s->dma_dac1, s->dac1rate, (s->sctrl >> SCTRL_SH_P1FMT) & ES1371_FMT_MASK,
957 ES1371_REG_DAC1_FRAMEADR);
958 }
959
960 extern inline unsigned get_hwptr(struct es1371_state *s, struct dmabuf *db, unsigned reg)
961 {
962 unsigned hwptr, diff;
963
964 outl((reg >> 8) & 15, s->io+ES1371_REG_MEMPAGE);
965 hwptr = (inl(s->io+(reg & 0xff)) >> 14) & 0x3fffc;
966 diff = (db->dmasize + hwptr - db->hwptr) % db->dmasize;
967 db->hwptr = hwptr;
968 return diff;
969 }
970
971 extern inline void clear_advance(void *buf, unsigned bsize, unsigned bptr, unsigned len, unsigned char c)
972 {
973 if (bptr + len > bsize) {
974 unsigned x = bsize - bptr;
975 memset(((char *)buf) + bptr, c, x);
976 bptr = 0;
977 len -= x;
978 }
979 memset(((char *)buf) + bptr, c, len);
980 }
981
982 /* call with spinlock held! */
983 static void es1371_update_ptr(struct es1371_state *s)
984 {
985 int diff;
986
987 /* update ADC pointer */
988 if (s->ctrl & CTRL_ADC_EN) {
989 diff = get_hwptr(s, &s->dma_adc, ES1371_REG_ADC_FRAMECNT);
990 s->dma_adc.total_bytes += diff;
991 s->dma_adc.count += diff;
992 if (s->dma_adc.count >= (signed)s->dma_adc.fragsize)
993 wake_up(&s->dma_adc.wait);
994 if (!s->dma_adc.mapped) {
995 if (s->dma_adc.count > (signed)(s->dma_adc.dmasize - ((3 * s->dma_adc.fragsize) >> 1))) {
996 s->ctrl &= ~CTRL_ADC_EN;
997 outl(s->ctrl, s->io+ES1371_REG_CONTROL);
998 s->dma_adc.error++;
999 }
1000 }
1001 }
1002 /* update DAC1 pointer */
1003 if (s->ctrl & CTRL_DAC1_EN) {
1004 diff = get_hwptr(s, &s->dma_dac1, ES1371_REG_DAC1_FRAMECNT);
1005 s->dma_dac1.total_bytes += diff;
1006 if (s->dma_dac1.mapped) {
1007 s->dma_dac1.count += diff;
1008 if (s->dma_dac1.count >= (signed)s->dma_dac1.fragsize)
1009 wake_up(&s->dma_dac1.wait);
1010 } else {
1011 s->dma_dac1.count -= diff;
1012 if (s->dma_dac1.count <= 0) {
1013 s->ctrl &= ~CTRL_DAC1_EN;
1014 outl(s->ctrl, s->io+ES1371_REG_CONTROL);
1015 s->dma_dac1.error++;
1016 } else if (s->dma_dac1.count <= (signed)s->dma_dac1.fragsize && !s->dma_dac1.endcleared) {
1017 clear_advance(s->dma_dac1.rawbuf, s->dma_dac1.dmasize, s->dma_dac1.swptr,
1018 s->dma_dac1.fragsize, (s->sctrl & SCTRL_P1SEB) ? 0 : 0x80);
1019 s->dma_dac1.endcleared = 1;
1020 }
1021 if (s->dma_dac1.count + (signed)s->dma_dac1.fragsize <= (signed)s->dma_dac1.dmasize)
1022 wake_up(&s->dma_dac1.wait);
1023 }
1024 }
1025 /* update DAC2 pointer */
1026 if (s->ctrl & CTRL_DAC2_EN) {
1027 diff = get_hwptr(s, &s->dma_dac2, ES1371_REG_DAC2_FRAMECNT);
1028 s->dma_dac2.total_bytes += diff;
1029 if (s->dma_dac2.mapped) {
1030 s->dma_dac2.count += diff;
1031 if (s->dma_dac2.count >= (signed)s->dma_dac2.fragsize)
1032 wake_up(&s->dma_dac2.wait);
1033 } else {
1034 s->dma_dac2.count -= diff;
1035 if (s->dma_dac2.count <= 0) {
1036 s->ctrl &= ~CTRL_DAC2_EN;
1037 outl(s->ctrl, s->io+ES1371_REG_CONTROL);
1038 s->dma_dac2.error++;
1039 } else if (s->dma_dac2.count <= (signed)s->dma_dac2.fragsize && !s->dma_dac2.endcleared) {
1040 clear_advance(s->dma_dac2.rawbuf, s->dma_dac2.dmasize, s->dma_dac2.swptr,
1041 s->dma_dac2.fragsize, (s->sctrl & SCTRL_P2SEB) ? 0 : 0x80);
1042 s->dma_dac2.endcleared = 1;
1043 }
1044 if (s->dma_dac2.count + (signed)s->dma_dac2.fragsize <= (signed)s->dma_dac2.dmasize)
1045 wake_up(&s->dma_dac2.wait);
1046 }
1047 }
1048 }
1049
1050 /* hold spinlock for the following! */
1051 static void es1371_handle_midi(struct es1371_state *s)
1052 {
1053 unsigned char ch;
1054 int wake;
1055
1056 if (!(s->ctrl & CTRL_UART_EN))
1057 return;
1058 wake = 0;
1059 while (inb(s->io+ES1371_REG_UART_STATUS) & USTAT_RXRDY) {
1060 ch = inb(s->io+ES1371_REG_UART_DATA);
1061 if (s->midi.icnt < MIDIINBUF) {
1062 s->midi.ibuf[s->midi.iwr] = ch;
1063 s->midi.iwr = (s->midi.iwr + 1) % MIDIINBUF;
1064 s->midi.icnt++;
1065 }
1066 wake = 1;
1067 }
1068 if (wake)
1069 wake_up(&s->midi.iwait);
1070 wake = 0;
1071 while ((inb(s->io+ES1371_REG_UART_STATUS) & USTAT_TXRDY) && s->midi.ocnt > 0) {
1072 outb(s->midi.obuf[s->midi.ord], s->io+ES1371_REG_UART_DATA);
1073 s->midi.ord = (s->midi.ord + 1) % MIDIOUTBUF;
1074 s->midi.ocnt--;
1075 if (s->midi.ocnt < MIDIOUTBUF-16)
1076 wake = 1;
1077 }
1078 if (wake)
1079 wake_up(&s->midi.owait);
1080 outb((s->midi.ocnt > 0) ? UCTRL_RXINTEN | UCTRL_ENA_TXINT : UCTRL_RXINTEN, s->io+ES1371_REG_UART_CONTROL);
1081 }
1082
1083 static void es1371_interrupt(int irq, void *dev_id, struct pt_regs *regs)
1084 {
1085 struct es1371_state *s = (struct es1371_state *)dev_id;
1086 unsigned int intsrc, sctl;
1087
1088 /* fastpath out, to ease interrupt sharing */
1089 intsrc = inl(s->io+ES1371_REG_STATUS);
1090 if (!(intsrc & 0x80000000))
1091 return;
1092 spin_lock(&s->lock);
1093 /* clear audio interrupts first */
1094 sctl = s->sctrl;
1095 if (intsrc & STAT_ADC)
1096 sctl &= ~SCTRL_R1INTEN;
1097 if (intsrc & STAT_DAC1)
1098 sctl &= ~SCTRL_P1INTEN;
1099 if (intsrc & STAT_DAC2)
1100 sctl &= ~SCTRL_P2INTEN;
1101 outl(sctl, s->io+ES1371_REG_SERIAL_CONTROL);
1102 outl(s->sctrl, s->io+ES1371_REG_SERIAL_CONTROL);
1103 es1371_update_ptr(s);
1104 es1371_handle_midi(s);
1105 spin_unlock(&s->lock);
1106 }
1107
1108 /* --------------------------------------------------------------------- */
1109
1110 static const char invalid_magic[] = KERN_CRIT PFX "invalid magic value\n";
1111
1112 #define VALIDATE_STATE(s) \
1113 ({ \
1114 if (!(s) || (s)->magic != ES1371_MAGIC) { \
1115 printk(invalid_magic); \
1116 return -ENXIO; \
1117 } \
1118 })
1119
1120 /* --------------------------------------------------------------------- */
1121
1122 static loff_t es1371_llseek(struct file *file, loff_t offset, int origin)
1123 {
1124 return -ESPIPE;
1125 }
1126
1127 /* --------------------------------------------------------------------- */
1128
1129 /* Conversion table for S/PDIF PCM volume emulation through the SRC */
1130 /* dB-linear table of DAC vol values; -0dB to -46.5dB with mute */
1131 static const unsigned short DACVolTable[101] =
1132 {
1133 0x1000, 0x0f2a, 0x0e60, 0x0da0, 0x0cea, 0x0c3e, 0x0b9a, 0x0aff,
1134 0x0a6d, 0x09e1, 0x095e, 0x08e1, 0x086a, 0x07fa, 0x078f, 0x072a,
1135 0x06cb, 0x0670, 0x061a, 0x05c9, 0x057b, 0x0532, 0x04ed, 0x04ab,
1136 0x046d, 0x0432, 0x03fa, 0x03c5, 0x0392, 0x0363, 0x0335, 0x030b,
1137 0x02e2, 0x02bc, 0x0297, 0x0275, 0x0254, 0x0235, 0x0217, 0x01fb,
1138 0x01e1, 0x01c8, 0x01b0, 0x0199, 0x0184, 0x0170, 0x015d, 0x014b,
1139 0x0139, 0x0129, 0x0119, 0x010b, 0x00fd, 0x00f0, 0x00e3, 0x00d7,
1140 0x00cc, 0x00c1, 0x00b7, 0x00ae, 0x00a5, 0x009c, 0x0094, 0x008c,
1141 0x0085, 0x007e, 0x0077, 0x0071, 0x006b, 0x0066, 0x0060, 0x005b,
1142 0x0057, 0x0052, 0x004e, 0x004a, 0x0046, 0x0042, 0x003f, 0x003c,
1143 0x0038, 0x0036, 0x0033, 0x0030, 0x002e, 0x002b, 0x0029, 0x0027,
1144 0x0025, 0x0023, 0x0021, 0x001f, 0x001e, 0x001c, 0x001b, 0x0019,
1145 0x0018, 0x0017, 0x0016, 0x0014, 0x0000
1146 };
1147
1148 /*
1149 * when we are in S/PDIF mode, we want to disable any analog output so
1150 * we filter the mixer ioctls
1151 */
1152 static int mixdev_ioctl(struct ac97_codec *codec, unsigned int cmd, unsigned long arg)
1153 {
1154 struct es1371_state *s = (struct es1371_state *)codec->private_data;
1155 int val;
1156 unsigned long flags;
1157 unsigned int left, right;
1158
1159 VALIDATE_STATE(s);
1160 /* filter mixer ioctls to catch PCM and MASTER volume when in S/PDIF mode */
1161 if (s->spdif_volume == -1)
1162 return codec->mixer_ioctl(codec, cmd, arg);
1163 switch (cmd) {
1164 case SOUND_MIXER_WRITE_VOLUME:
1165 return 0;
1166
1167 case SOUND_MIXER_WRITE_PCM: /* use SRC for PCM volume */
1168 if (get_user(val, (int *)arg))
1169 return -EFAULT;
1170 right = ((val >> 8) & 0xff);
1171 left = (val & 0xff);
1172 if (right > 100)
1173 right = 100;
1174 if (left > 100)
1175 left = 100;
1176 s->spdif_volume = (right << 8) | left;
1177 spin_lock_irqsave(&s->lock, flags);
1178 src_write(s, SRCREG_VOL_DAC2, DACVolTable[100 - left]);
1179 src_write(s, SRCREG_VOL_DAC2+1, DACVolTable[100 - right]);
1180 spin_unlock_irqrestore(&s->lock, flags);
1181 return 0;
1182
1183 case SOUND_MIXER_READ_PCM:
1184 return put_user(s->spdif_volume, (int *)arg);
1185 }
1186 return codec->mixer_ioctl(codec, cmd, arg);
1187 }
1188
1189 /* --------------------------------------------------------------------- */
1190
1191 /*
1192 * AC97 Mixer Register to Connections mapping of the Concert 97 board
1193 *
1194 * AC97_MASTER_VOL_STEREO Line Out
1195 * AC97_MASTER_VOL_MONO TAD Output
1196 * AC97_PCBEEP_VOL none
1197 * AC97_PHONE_VOL TAD Input (mono)
1198 * AC97_MIC_VOL MIC Input (mono)
1199 * AC97_LINEIN_VOL Line Input (stereo)
1200 * AC97_CD_VOL CD Input (stereo)
1201 * AC97_VIDEO_VOL none
1202 * AC97_AUX_VOL Aux Input (stereo)
1203 * AC97_PCMOUT_VOL Wave Output (stereo)
1204 */
1205
1206 static int es1371_open_mixdev(struct inode *inode, struct file *file)
1207 {
1208 int minor = MINOR(inode->i_rdev);
1209 struct list_head *list;
1210 struct es1371_state *s;
1211
1212 for (list = devs.next; ; list = list->next) {
1213 if (list == &devs)
1214 return -ENODEV;
1215 s = list_entry(list, struct es1371_state, devs);
1216 if (s->codec.dev_mixer == minor)
1217 break;
1218 }
1219 VALIDATE_STATE(s);
1220 file->private_data = s;
1221 return 0;
1222 }
1223
1224 static int es1371_release_mixdev(struct inode *inode, struct file *file)
1225 {
1226 struct es1371_state *s = (struct es1371_state *)file->private_data;
1227
1228 VALIDATE_STATE(s);
1229 return 0;
1230 }
1231
1232 static int es1371_ioctl_mixdev(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg)
1233 {
1234 struct es1371_state *s = (struct es1371_state *)file->private_data;
1235 struct ac97_codec *codec = &s->codec;
1236
1237 return mixdev_ioctl(codec, cmd, arg);
1238 }
1239
1240 static /*const*/ struct file_operations es1371_mixer_fops = {
1241 owner: THIS_MODULE,
1242 llseek: es1371_llseek,
1243 ioctl: es1371_ioctl_mixdev,
1244 open: es1371_open_mixdev,
1245 release: es1371_release_mixdev,
1246 };
1247
1248 /* --------------------------------------------------------------------- */
1249
1250 static int drain_dac1(struct es1371_state *s, int nonblock)
1251 {
1252 DECLARE_WAITQUEUE(wait, current);
1253 unsigned long flags;
1254 int count, tmo;
1255
1256 if (s->dma_dac1.mapped || !s->dma_dac1.ready)
1257 return 0;
1258 add_wait_queue(&s->dma_dac1.wait, &wait);
1259 for (;;) {
1260 __set_current_state(TASK_INTERRUPTIBLE);
1261 spin_lock_irqsave(&s->lock, flags);
1262 count = s->dma_dac1.count;
1263 spin_unlock_irqrestore(&s->lock, flags);
1264 if (count <= 0)
1265 break;
1266 if (signal_pending(current))
1267 break;
1268 if (nonblock) {
1269 remove_wait_queue(&s->dma_dac1.wait, &wait);
1270 set_current_state(TASK_RUNNING);
1271 return -EBUSY;
1272 }
1273 tmo = 3 * HZ * (count + s->dma_dac1.fragsize) / 2 / s->dac1rate;
1274 tmo >>= sample_shift[(s->sctrl & SCTRL_P1FMT) >> SCTRL_SH_P1FMT];
1275 if (!schedule_timeout(tmo + 1))
1276 DBG(printk(KERN_DEBUG PFX "dac1 dma timed out??\n");)
1277 }
1278 remove_wait_queue(&s->dma_dac1.wait, &wait);
1279 set_current_state(TASK_RUNNING);
1280 if (signal_pending(current))
1281 return -ERESTARTSYS;
1282 return 0;
1283 }
1284
1285 static int drain_dac2(struct es1371_state *s, int nonblock)
1286 {
1287 DECLARE_WAITQUEUE(wait, current);
1288 unsigned long flags;
1289 int count, tmo;
1290
1291 if (s->dma_dac2.mapped || !s->dma_dac2.ready)
1292 return 0;
1293 add_wait_queue(&s->dma_dac2.wait, &wait);
1294 for (;;) {
1295 __set_current_state(TASK_UNINTERRUPTIBLE);
1296 spin_lock_irqsave(&s->lock, flags);
1297 count = s->dma_dac2.count;
1298 spin_unlock_irqrestore(&s->lock, flags);
1299 if (count <= 0)
1300 break;
1301 if (signal_pending(current))
1302 break;
1303 if (nonblock) {
1304 remove_wait_queue(&s->dma_dac2.wait, &wait);
1305 set_current_state(TASK_RUNNING);
1306 return -EBUSY;
1307 }
1308 tmo = 3 * HZ * (count + s->dma_dac2.fragsize) / 2 / s->dac2rate;
1309 tmo >>= sample_shift[(s->sctrl & SCTRL_P2FMT) >> SCTRL_SH_P2FMT];
1310 if (!schedule_timeout(tmo + 1))
1311 DBG(printk(KERN_DEBUG PFX "dac2 dma timed out??\n");)
1312 }
1313 remove_wait_queue(&s->dma_dac2.wait, &wait);
1314 set_current_state(TASK_RUNNING);
1315 if (signal_pending(current))
1316 return -ERESTARTSYS;
1317 return 0;
1318 }
1319
1320 /* --------------------------------------------------------------------- */
1321
1322 static ssize_t es1371_read(struct file *file, char *buffer, size_t count, loff_t *ppos)
1323 {
1324 struct es1371_state *s = (struct es1371_state *)file->private_data;
1325 DECLARE_WAITQUEUE(wait, current);
1326 ssize_t ret;
1327 unsigned long flags;
1328 unsigned swptr;
1329 int cnt;
1330
1331 VALIDATE_STATE(s);
1332 if (ppos != &file->f_pos)
1333 return -ESPIPE;
1334 if (s->dma_adc.mapped)
1335 return -ENXIO;
1336 if (!s->dma_adc.ready && (ret = prog_dmabuf_adc(s)))
1337 return ret;
1338 if (!access_ok(VERIFY_WRITE, buffer, count))
1339 return -EFAULT;
1340 ret = 0;
1341 add_wait_queue(&s->dma_adc.wait, &wait);
1342 while (count > 0) {
1343 spin_lock_irqsave(&s->lock, flags);
1344 swptr = s->dma_adc.swptr;
1345 cnt = s->dma_adc.dmasize-swptr;
1346 if (s->dma_adc.count < cnt)
1347 cnt = s->dma_adc.count;
1348 if (cnt <= 0)
1349 __set_current_state(TASK_INTERRUPTIBLE);
1350 spin_unlock_irqrestore(&s->lock, flags);
1351 if (cnt > count)
1352 cnt = count;
1353 if (cnt <= 0) {
1354 start_adc(s);
1355 if (file->f_flags & O_NONBLOCK) {
1356 if (!ret)
1357 ret = -EAGAIN;
1358 break;
1359 }
1360 schedule();
1361 if (signal_pending(current)) {
1362 if (!ret)
1363 ret = -ERESTARTSYS;
1364 break;
1365 }
1366 continue;
1367 }
1368 if (copy_to_user(buffer, s->dma_adc.rawbuf + swptr, cnt)) {
1369 if (!ret)
1370 ret = -EFAULT;
1371 break;
1372 }
1373 swptr = (swptr + cnt) % s->dma_adc.dmasize;
1374 spin_lock_irqsave(&s->lock, flags);
1375 s->dma_adc.swptr = swptr;
1376 s->dma_adc.count -= cnt;
1377 spin_unlock_irqrestore(&s->lock, flags);
1378 count -= cnt;
1379 buffer += cnt;
1380 ret += cnt;
1381 start_adc(s);
1382 }
1383 remove_wait_queue(&s->dma_adc.wait, &wait);
1384 set_current_state(TASK_RUNNING);
1385 return ret;
1386 }
1387
1388 static ssize_t es1371_write(struct file *file, const char *buffer, size_t count, loff_t *ppos)
1389 {
1390 struct es1371_state *s = (struct es1371_state *)file->private_data;
1391 DECLARE_WAITQUEUE(wait, current);
1392 ssize_t ret;
1393 unsigned long flags;
1394 unsigned swptr;
1395 int cnt;
1396
1397 VALIDATE_STATE(s);
1398 if (ppos != &file->f_pos)
1399 return -ESPIPE;
1400 if (s->dma_dac2.mapped)
1401 return -ENXIO;
1402 if (!s->dma_dac2.ready && (ret = prog_dmabuf_dac2(s)))
1403 return ret;
1404 if (!access_ok(VERIFY_READ, buffer, count))
1405 return -EFAULT;
1406 ret = 0;
1407 add_wait_queue(&s->dma_dac2.wait, &wait);
1408 while (count > 0) {
1409 spin_lock_irqsave(&s->lock, flags);
1410 if (s->dma_dac2.count < 0) {
1411 s->dma_dac2.count = 0;
1412 s->dma_dac2.swptr = s->dma_dac2.hwptr;
1413 }
1414 swptr = s->dma_dac2.swptr;
1415 cnt = s->dma_dac2.dmasize-swptr;
1416 if (s->dma_dac2.count + cnt > s->dma_dac2.dmasize)
1417 cnt = s->dma_dac2.dmasize - s->dma_dac2.count;
1418 if (cnt <= 0)
1419 __set_current_state(TASK_INTERRUPTIBLE);
1420 spin_unlock_irqrestore(&s->lock, flags);
1421 if (cnt > count)
1422 cnt = count;
1423 if (cnt <= 0) {
1424 start_dac2(s);
1425 if (file->f_flags & O_NONBLOCK) {
1426 if (!ret)
1427 ret = -EAGAIN;
1428 break;
1429 }
1430 schedule();
1431 if (signal_pending(current)) {
1432 if (!ret)
1433 ret = -ERESTARTSYS;
1434 break;
1435 }
1436 continue;
1437 }
1438 if (copy_from_user(s->dma_dac2.rawbuf + swptr, buffer, cnt)) {
1439 if (!ret)
1440 ret = -EFAULT;
1441 break;
1442 }
1443 swptr = (swptr + cnt) % s->dma_dac2.dmasize;
1444 spin_lock_irqsave(&s->lock, flags);
1445 s->dma_dac2.swptr = swptr;
1446 s->dma_dac2.count += cnt;
1447 s->dma_dac2.endcleared = 0;
1448 spin_unlock_irqrestore(&s->lock, flags);
1449 count -= cnt;
1450 buffer += cnt;
1451 ret += cnt;
1452 start_dac2(s);
1453 }
1454 remove_wait_queue(&s->dma_dac2.wait, &wait);
1455 set_current_state(TASK_RUNNING);
1456 return ret;
1457 }
1458
1459 /* No kernel lock - we have our own spinlock */
1460 static unsigned int es1371_poll(struct file *file, struct poll_table_struct *wait)
1461 {
1462 struct es1371_state *s = (struct es1371_state *)file->private_data;
1463 unsigned long flags;
1464 unsigned int mask = 0;
1465
1466 VALIDATE_STATE(s);
1467 if (file->f_mode & FMODE_WRITE)
1468 poll_wait(file, &s->dma_dac2.wait, wait);
1469 if (file->f_mode & FMODE_READ)
1470 poll_wait(file, &s->dma_adc.wait, wait);
1471 spin_lock_irqsave(&s->lock, flags);
1472 es1371_update_ptr(s);
1473 if (file->f_mode & FMODE_READ) {
1474 if (s->dma_adc.count >= (signed)s->dma_adc.fragsize)
1475 mask |= POLLIN | POLLRDNORM;
1476 }
1477 if (file->f_mode & FMODE_WRITE) {
1478 if (s->dma_dac2.mapped) {
1479 if (s->dma_dac2.count >= (signed)s->dma_dac2.fragsize)
1480 mask |= POLLOUT | POLLWRNORM;
1481 } else {
1482 if ((signed)s->dma_dac2.dmasize >= s->dma_dac2.count + (signed)s->dma_dac2.fragsize)
1483 mask |= POLLOUT | POLLWRNORM;
1484 }
1485 }
1486 spin_unlock_irqrestore(&s->lock, flags);
1487 return mask;
1488 }
1489
1490 static int es1371_mmap(struct file *file, struct vm_area_struct *vma)
1491 {
1492 struct es1371_state *s = (struct es1371_state *)file->private_data;
1493 struct dmabuf *db;
1494 int ret;
1495 unsigned long size;
1496
1497 VALIDATE_STATE(s);
1498 lock_kernel();
1499 if (vma->vm_flags & VM_WRITE) {
1500 if ((ret = prog_dmabuf_dac2(s)) != 0) {
1501 unlock_kernel();
1502 return ret;
1503 }
1504 db = &s->dma_dac2;
1505 } else if (vma->vm_flags & VM_READ) {
1506 if ((ret = prog_dmabuf_adc(s)) != 0) {
1507 unlock_kernel();
1508 return ret;
1509 }
1510 db = &s->dma_adc;
1511 } else {
1512 unlock_kernel();
1513 return -EINVAL;
1514 }
1515 if (vma->vm_pgoff != 0) {
1516 unlock_kernel();
1517 return -EINVAL;
1518 }
1519 size = vma->vm_end - vma->vm_start;
1520 if (size > (PAGE_SIZE << db->buforder)) {
1521 unlock_kernel();
1522 return -EINVAL;
1523 }
1524 if (remap_page_range(vma->vm_start, virt_to_phys(db->rawbuf), size, vma->vm_page_prot)) {
1525 unlock_kernel();
1526 return -EAGAIN;
1527 }
1528 db->mapped = 1;
1529 unlock_kernel();
1530 return 0;
1531 }
1532
1533 static int es1371_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg)
1534 {
1535 struct es1371_state *s = (struct es1371_state *)file->private_data;
1536 unsigned long flags;
1537 audio_buf_info abinfo;
1538 count_info cinfo;
1539 int count;
1540 int val, mapped, ret;
1541
1542 VALIDATE_STATE(s);
1543 mapped = ((file->f_mode & FMODE_WRITE) && s->dma_dac2.mapped) ||
1544 ((file->f_mode & FMODE_READ) && s->dma_adc.mapped);
1545 switch (cmd) {
1546 case OSS_GETVERSION:
1547 return put_user(SOUND_VERSION, (int *)arg);
1548
1549 case SNDCTL_DSP_SYNC:
1550 if (file->f_mode & FMODE_WRITE)
1551 return drain_dac2(s, 0/*file->f_flags & O_NONBLOCK*/);
1552 return 0;
1553
1554 case SNDCTL_DSP_SETDUPLEX:
1555 return 0;
1556
1557 case SNDCTL_DSP_GETCAPS:
1558 return put_user(DSP_CAP_DUPLEX | DSP_CAP_REALTIME | DSP_CAP_TRIGGER | DSP_CAP_MMAP, (int *)arg);
1559
1560 case SNDCTL_DSP_RESET:
1561 if (file->f_mode & FMODE_WRITE) {
1562 stop_dac2(s);
1563 synchronize_irq();
1564 s->dma_dac2.swptr = s->dma_dac2.hwptr = s->dma_dac2.count = s->dma_dac2.total_bytes = 0;
1565 }
1566 if (file->f_mode & FMODE_READ) {
1567 stop_adc(s);
1568 synchronize_irq();
1569 s->dma_adc.swptr = s->dma_adc.hwptr = s->dma_adc.count = s->dma_adc.total_bytes = 0;
1570 }
1571 return 0;
1572
1573 case SNDCTL_DSP_SPEED:
1574 if (get_user(val, (int *)arg))
1575 return -EFAULT;
1576 if (val >= 0) {
1577 if (file->f_mode & FMODE_READ) {
1578 stop_adc(s);
1579 s->dma_adc.ready = 0;
1580 set_adc_rate(s, val);
1581 }
1582 if (file->f_mode & FMODE_WRITE) {
1583 stop_dac2(s);
1584 s->dma_dac2.ready = 0;
1585 set_dac2_rate(s, val);
1586 }
1587 }
1588 return put_user((file->f_mode & FMODE_READ) ? s->adcrate : s->dac2rate, (int *)arg);
1589
1590 case SNDCTL_DSP_STEREO:
1591 if (get_user(val, (int *)arg))
1592 return -EFAULT;
1593 if (file->f_mode & FMODE_READ) {
1594 stop_adc(s);
1595 s->dma_adc.ready = 0;
1596 spin_lock_irqsave(&s->lock, flags);
1597 if (val)
1598 s->sctrl |= SCTRL_R1SMB;
1599 else
1600 s->sctrl &= ~SCTRL_R1SMB;
1601 outl(s->sctrl, s->io+ES1371_REG_SERIAL_CONTROL);
1602 spin_unlock_irqrestore(&s->lock, flags);
1603 }
1604 if (file->f_mode & FMODE_WRITE) {
1605 stop_dac2(s);
1606 s->dma_dac2.ready = 0;
1607 spin_lock_irqsave(&s->lock, flags);
1608 if (val)
1609 s->sctrl |= SCTRL_P2SMB;
1610 else
1611 s->sctrl &= ~SCTRL_P2SMB;
1612 outl(s->sctrl, s->io+ES1371_REG_SERIAL_CONTROL);
1613 spin_unlock_irqrestore(&s->lock, flags);
1614 }
1615 return 0;
1616
1617 case SNDCTL_DSP_CHANNELS:
1618 if (get_user(val, (int *)arg))
1619 return -EFAULT;
1620 if (val != 0) {
1621 if (file->f_mode & FMODE_READ) {
1622 stop_adc(s);
1623 s->dma_adc.ready = 0;
1624 spin_lock_irqsave(&s->lock, flags);
1625 if (val >= 2)
1626 s->sctrl |= SCTRL_R1SMB;
1627 else
1628 s->sctrl &= ~SCTRL_R1SMB;
1629 outl(s->sctrl, s->io+ES1371_REG_SERIAL_CONTROL);
1630 spin_unlock_irqrestore(&s->lock, flags);
1631 }
1632 if (file->f_mode & FMODE_WRITE) {
1633 stop_dac2(s);
1634 s->dma_dac2.ready = 0;
1635 spin_lock_irqsave(&s->lock, flags);
1636 if (val >= 2)
1637 s->sctrl |= SCTRL_P2SMB;
1638 else
1639 s->sctrl &= ~SCTRL_P2SMB;
1640 outl(s->sctrl, s->io+ES1371_REG_SERIAL_CONTROL);
1641 spin_unlock_irqrestore(&s->lock, flags);
1642 }
1643 }
1644 return put_user((s->sctrl & ((file->f_mode & FMODE_READ) ? SCTRL_R1SMB : SCTRL_P2SMB)) ? 2 : 1, (int *)arg);
1645
1646 case SNDCTL_DSP_GETFMTS: /* Returns a mask */
1647 return put_user(AFMT_S16_LE|AFMT_U8, (int *)arg);
1648
1649 case SNDCTL_DSP_SETFMT: /* Selects ONE fmt*/
1650 if (get_user(val, (int *)arg))
1651 return -EFAULT;
1652 if (val != AFMT_QUERY) {
1653 if (file->f_mode & FMODE_READ) {
1654 stop_adc(s);
1655 s->dma_adc.ready = 0;
1656 spin_lock_irqsave(&s->lock, flags);
1657 if (val == AFMT_S16_LE)
1658 s->sctrl |= SCTRL_R1SEB;
1659 else
1660 s->sctrl &= ~SCTRL_R1SEB;
1661 outl(s->sctrl, s->io+ES1371_REG_SERIAL_CONTROL);
1662 spin_unlock_irqrestore(&s->lock, flags);
1663 }
1664 if (file->f_mode & FMODE_WRITE) {
1665 stop_dac2(s);
1666 s->dma_dac2.ready = 0;
1667 spin_lock_irqsave(&s->lock, flags);
1668 if (val == AFMT_S16_LE)
1669 s->sctrl |= SCTRL_P2SEB;
1670 else
1671 s->sctrl &= ~SCTRL_P2SEB;
1672 outl(s->sctrl, s->io+ES1371_REG_SERIAL_CONTROL);
1673 spin_unlock_irqrestore(&s->lock, flags);
1674 }
1675 }
1676 return put_user((s->sctrl & ((file->f_mode & FMODE_READ) ? SCTRL_R1SEB : SCTRL_P2SEB)) ?
1677 AFMT_S16_LE : AFMT_U8, (int *)arg);
1678
1679 case SNDCTL_DSP_POST:
1680 return 0;
1681
1682 case SNDCTL_DSP_GETTRIGGER:
1683 val = 0;
1684 if (file->f_mode & FMODE_READ && s->ctrl & CTRL_ADC_EN)
1685 val |= PCM_ENABLE_INPUT;
1686 if (file->f_mode & FMODE_WRITE && s->ctrl & CTRL_DAC2_EN)
1687 val |= PCM_ENABLE_OUTPUT;
1688 return put_user(val, (int *)arg);
1689
1690 case SNDCTL_DSP_SETTRIGGER:
1691 if (get_user(val, (int *)arg))
1692 return -EFAULT;
1693 if (file->f_mode & FMODE_READ) {
1694 if (val & PCM_ENABLE_INPUT) {
1695 if (!s->dma_adc.ready && (ret = prog_dmabuf_adc(s)))
1696 return ret;
1697 start_adc(s);
1698 } else
1699 stop_adc(s);
1700 }
1701 if (file->f_mode & FMODE_WRITE) {
1702 if (val & PCM_ENABLE_OUTPUT) {
1703 if (!s->dma_dac2.ready && (ret = prog_dmabuf_dac2(s)))
1704 return ret;
1705 start_dac2(s);
1706 } else
1707 stop_dac2(s);
1708 }
1709 return 0;
1710
1711 case SNDCTL_DSP_GETOSPACE:
1712 if (!(file->f_mode & FMODE_WRITE))
1713 return -EINVAL;
1714 if (!(s->ctrl & CTRL_DAC2_EN) && (val = prog_dmabuf_dac2(s)) != 0)
1715 return val;
1716 spin_lock_irqsave(&s->lock, flags);
1717 es1371_update_ptr(s);
1718 abinfo.fragsize = s->dma_dac2.fragsize;
1719 count = s->dma_dac2.count;
1720 if (count < 0)
1721 count = 0;
1722 abinfo.bytes = s->dma_dac2.dmasize - count;
1723 abinfo.fragstotal = s->dma_dac2.numfrag;
1724 abinfo.fragments = abinfo.bytes >> s->dma_dac2.fragshift;
1725 spin_unlock_irqrestore(&s->lock, flags);
1726 return copy_to_user((void *)arg, &abinfo, sizeof(abinfo)) ? -EFAULT : 0;
1727
1728 case SNDCTL_DSP_GETISPACE:
1729 if (!(file->f_mode & FMODE_READ))
1730 return -EINVAL;
1731 if (!(s->ctrl & CTRL_ADC_EN) && (val = prog_dmabuf_adc(s)) != 0)
1732 return val;
1733 spin_lock_irqsave(&s->lock, flags);
1734 es1371_update_ptr(s);
1735 abinfo.fragsize = s->dma_adc.fragsize;
1736 count = s->dma_adc.count;
1737 if (count < 0)
1738 count = 0;
1739 abinfo.bytes = count;
1740 abinfo.fragstotal = s->dma_adc.numfrag;
1741 abinfo.fragments = abinfo.bytes >> s->dma_adc.fragshift;
1742 spin_unlock_irqrestore(&s->lock, flags);
1743 return copy_to_user((void *)arg, &abinfo, sizeof(abinfo)) ? -EFAULT : 0;
1744
1745 case SNDCTL_DSP_NONBLOCK:
1746 file->f_flags |= O_NONBLOCK;
1747 return 0;
1748
1749 case SNDCTL_DSP_GETODELAY:
1750 if (!(file->f_mode & FMODE_WRITE))
1751 return -EINVAL;
1752 spin_lock_irqsave(&s->lock, flags);
1753 es1371_update_ptr(s);
1754 count = s->dma_dac2.count;
1755 spin_unlock_irqrestore(&s->lock, flags);
1756 if (count < 0)
1757 count = 0;
1758 return put_user(count, (int *)arg);
1759
1760 case SNDCTL_DSP_GETIPTR:
1761 if (!(file->f_mode & FMODE_READ))
1762 return -EINVAL;
1763 spin_lock_irqsave(&s->lock, flags);
1764 es1371_update_ptr(s);
1765 cinfo.bytes = s->dma_adc.total_bytes;
1766 count = s->dma_adc.count;
1767 if (count < 0)
1768 count = 0;
1769 cinfo.blocks = count >> s->dma_adc.fragshift;
1770 cinfo.ptr = s->dma_adc.hwptr;
1771 if (s->dma_adc.mapped)
1772 s->dma_adc.count &= s->dma_adc.fragsize-1;
1773 spin_unlock_irqrestore(&s->lock, flags);
1774 return copy_to_user((void *)arg, &cinfo, sizeof(cinfo));
1775
1776 case SNDCTL_DSP_GETOPTR:
1777 if (!(file->f_mode & FMODE_WRITE))
1778 return -EINVAL;
1779 spin_lock_irqsave(&s->lock, flags);
1780 es1371_update_ptr(s);
1781 cinfo.bytes = s->dma_dac2.total_bytes;
1782 count = s->dma_dac2.count;
1783 if (count < 0)
1784 count = 0;
1785 cinfo.blocks = count >> s->dma_dac2.fragshift;
1786 cinfo.ptr = s->dma_dac2.hwptr;
1787 if (s->dma_dac2.mapped)
1788 s->dma_dac2.count &= s->dma_dac2.fragsize-1;
1789 spin_unlock_irqrestore(&s->lock, flags);
1790 return copy_to_user((void *)arg, &cinfo, sizeof(cinfo));
1791
1792 case SNDCTL_DSP_GETBLKSIZE:
1793 if (file->f_mode & FMODE_WRITE) {
1794 if ((val = prog_dmabuf_dac2(s)))
1795 return val;
1796 return put_user(s->dma_dac2.fragsize, (int *)arg);
1797 }
1798 if ((val = prog_dmabuf_adc(s)))
1799 return val;
1800 return put_user(s->dma_adc.fragsize, (int *)arg);
1801
1802 case SNDCTL_DSP_SETFRAGMENT:
1803 if (get_user(val, (int *)arg))
1804 return -EFAULT;
1805 if (file->f_mode & FMODE_READ) {
1806 s->dma_adc.ossfragshift = val & 0xffff;
1807 s->dma_adc.ossmaxfrags = (val >> 16) & 0xffff;
1808 if (s->dma_adc.ossfragshift < 4)
1809 s->dma_adc.ossfragshift = 4;
1810 if (s->dma_adc.ossfragshift > 15)
1811 s->dma_adc.ossfragshift = 15;
1812 if (s->dma_adc.ossmaxfrags < 4)
1813 s->dma_adc.ossmaxfrags = 4;
1814 }
1815 if (file->f_mode & FMODE_WRITE) {
1816 s->dma_dac2.ossfragshift = val & 0xffff;
1817 s->dma_dac2.ossmaxfrags = (val >> 16) & 0xffff;
1818 if (s->dma_dac2.ossfragshift < 4)
1819 s->dma_dac2.ossfragshift = 4;
1820 if (s->dma_dac2.ossfragshift > 15)
1821 s->dma_dac2.ossfragshift = 15;
1822 if (s->dma_dac2.ossmaxfrags < 4)
1823 s->dma_dac2.ossmaxfrags = 4;
1824 }
1825 return 0;
1826
1827 case SNDCTL_DSP_SUBDIVIDE:
1828 if ((file->f_mode & FMODE_READ && s->dma_adc.subdivision) ||
1829 (file->f_mode & FMODE_WRITE && s->dma_dac2.subdivision))
1830 return -EINVAL;
1831 if (get_user(val, (int *)arg))
1832 return -EFAULT;
1833 if (val != 1 && val != 2 && val != 4)
1834 return -EINVAL;
1835 if (file->f_mode & FMODE_READ)
1836 s->dma_adc.subdivision = val;
1837 if (file->f_mode & FMODE_WRITE)
1838 s->dma_dac2.subdivision = val;
1839 return 0;
1840
1841 case SOUND_PCM_READ_RATE:
1842 return put_user((file->f_mode & FMODE_READ) ? s->adcrate : s->dac2rate, (int *)arg);
1843
1844 case SOUND_PCM_READ_CHANNELS:
1845 return put_user((s->sctrl & ((file->f_mode & FMODE_READ) ? SCTRL_R1SMB : SCTRL_P2SMB)) ? 2 : 1, (int *)arg);
1846
1847 case SOUND_PCM_READ_BITS:
1848 return put_user((s->sctrl & ((file->f_mode & FMODE_READ) ? SCTRL_R1SEB : SCTRL_P2SEB)) ? 16 : 8, (int *)arg);
1849
1850 case SOUND_PCM_WRITE_FILTER:
1851 case SNDCTL_DSP_SETSYNCRO:
1852 case SOUND_PCM_READ_FILTER:
1853 return -EINVAL;
1854
1855 }
1856 return mixdev_ioctl(&s->codec, cmd, arg);
1857 }
1858
1859 static int es1371_open(struct inode *inode, struct file *file)
1860 {
1861 int minor = MINOR(inode->i_rdev);
1862 DECLARE_WAITQUEUE(wait, current);
1863 unsigned long flags;
1864 struct list_head *list;
1865 struct es1371_state *s;
1866
1867 for (list = devs.next; ; list = list->next) {
1868 if (list == &devs)
1869 return -ENODEV;
1870 s = list_entry(list, struct es1371_state, devs);
1871 if (!((s->dev_audio ^ minor) & ~0xf))
1872 break;
1873 }
1874 VALIDATE_STATE(s);
1875 file->private_data = s;
1876 /* wait for device to become free */
1877 down(&s->open_sem);
1878 while (s->open_mode & file->f_mode) {
1879 if (file->f_flags & O_NONBLOCK) {
1880 up(&s->open_sem);
1881 return -EBUSY;
1882 }
1883 add_wait_queue(&s->open_wait, &wait);
1884 __set_current_state(TASK_INTERRUPTIBLE);
1885 up(&s->open_sem);
1886 schedule();
1887 remove_wait_queue(&s->open_wait, &wait);
1888 set_current_state(TASK_RUNNING);
1889 if (signal_pending(current))
1890 return -ERESTARTSYS;
1891 down(&s->open_sem);
1892 }
1893 if (file->f_mode & FMODE_READ) {
1894 s->dma_adc.ossfragshift = s->dma_adc.ossmaxfrags = s->dma_adc.subdivision = 0;
1895 set_adc_rate(s, 8000);
1896 }
1897 if (file->f_mode & FMODE_WRITE) {
1898 s->dma_dac2.ossfragshift = s->dma_dac2.ossmaxfrags = s->dma_dac2.subdivision = 0;
1899 set_dac2_rate(s, 8000);
1900 }
1901 spin_lock_irqsave(&s->lock, flags);
1902 if (file->f_mode & FMODE_READ) {
1903 s->sctrl &= ~SCTRL_R1FMT;
1904 if ((minor & 0xf) == SND_DEV_DSP16)
1905 s->sctrl |= ES1371_FMT_S16_MONO << SCTRL_SH_R1FMT;
1906 else
1907 s->sctrl |= ES1371_FMT_U8_MONO << SCTRL_SH_R1FMT;
1908 }
1909 if (file->f_mode & FMODE_WRITE) {
1910 s->sctrl &= ~SCTRL_P2FMT;
1911 if ((minor & 0xf) == SND_DEV_DSP16)
1912 s->sctrl |= ES1371_FMT_S16_MONO << SCTRL_SH_P2FMT;
1913 else
1914 s->sctrl |= ES1371_FMT_U8_MONO << SCTRL_SH_P2FMT;
1915 }
1916 outl(s->sctrl, s->io+ES1371_REG_SERIAL_CONTROL);
1917 spin_unlock_irqrestore(&s->lock, flags);
1918 s->open_mode |= file->f_mode & (FMODE_READ | FMODE_WRITE);
1919 up(&s->open_sem);
1920 return 0;
1921 }
1922
1923 static int es1371_release(struct inode *inode, struct file *file)
1924 {
1925 struct es1371_state *s = (struct es1371_state *)file->private_data;
1926
1927 VALIDATE_STATE(s);
1928 lock_kernel();
1929 if (file->f_mode & FMODE_WRITE)
1930 drain_dac2(s, file->f_flags & O_NONBLOCK);
1931 down(&s->open_sem);
1932 if (file->f_mode & FMODE_WRITE) {
1933 stop_dac2(s);
1934 dealloc_dmabuf(s, &s->dma_dac2);
1935 }
1936 if (file->f_mode & FMODE_READ) {
1937 stop_adc(s);
1938 dealloc_dmabuf(s, &s->dma_adc);
1939 }
1940 s->open_mode &= (~file->f_mode) & (FMODE_READ|FMODE_WRITE);
1941 up(&s->open_sem);
1942 wake_up(&s->open_wait);
1943 unlock_kernel();
1944 return 0;
1945 }
1946
1947 static /*const*/ struct file_operations es1371_audio_fops = {
1948 owner: THIS_MODULE,
1949 llseek: es1371_llseek,
1950 read: es1371_read,
1951 write: es1371_write,
1952 poll: es1371_poll,
1953 ioctl: es1371_ioctl,
1954 mmap: es1371_mmap,
1955 open: es1371_open,
1956 release: es1371_release,
1957 };
1958
1959 /* --------------------------------------------------------------------- */
1960
1961 static ssize_t es1371_write_dac(struct file *file, const char *buffer, size_t count, loff_t *ppos)
1962 {
1963 struct es1371_state *s = (struct es1371_state *)file->private_data;
1964 DECLARE_WAITQUEUE(wait, current);
1965 ssize_t ret = 0;
1966 unsigned long flags;
1967 unsigned swptr;
1968 int cnt;
1969
1970 VALIDATE_STATE(s);
1971 if (ppos != &file->f_pos)
1972 return -ESPIPE;
1973 if (s->dma_dac1.mapped)
1974 return -ENXIO;
1975 if (!s->dma_dac1.ready && (ret = prog_dmabuf_dac1(s)))
1976 return ret;
1977 if (!access_ok(VERIFY_READ, buffer, count))
1978 return -EFAULT;
1979 add_wait_queue(&s->dma_dac1.wait, &wait);
1980 while (count > 0) {
1981 spin_lock_irqsave(&s->lock, flags);
1982 if (s->dma_dac1.count < 0) {
1983 s->dma_dac1.count = 0;
1984 s->dma_dac1.swptr = s->dma_dac1.hwptr;
1985 }
1986 swptr = s->dma_dac1.swptr;
1987 cnt = s->dma_dac1.dmasize-swptr;
1988 if (s->dma_dac1.count + cnt > s->dma_dac1.dmasize)
1989 cnt = s->dma_dac1.dmasize - s->dma_dac1.count;
1990 if (cnt <= 0)
1991 __set_current_state(TASK_INTERRUPTIBLE);
1992 spin_unlock_irqrestore(&s->lock, flags);
1993 if (cnt > count)
1994 cnt = count;
1995 if (cnt <= 0) {
1996 start_dac1(s);
1997 if (file->f_flags & O_NONBLOCK) {
1998 if (!ret)
1999 ret = -EAGAIN;
2000 break;
2001 }
2002 schedule();
2003 if (signal_pending(current)) {
2004 if (!ret)
2005 ret = -ERESTARTSYS;
2006 break;
2007 }
2008 continue;
2009 }
2010 if (copy_from_user(s->dma_dac1.rawbuf + swptr, buffer, cnt)) {
2011 if (!ret)
2012 ret = -EFAULT;
2013 break;
2014 }
2015 swptr = (swptr + cnt) % s->dma_dac1.dmasize;
2016 spin_lock_irqsave(&s->lock, flags);
2017 s->dma_dac1.swptr = swptr;
2018 s->dma_dac1.count += cnt;
2019 s->dma_dac1.endcleared = 0;
2020 spin_unlock_irqrestore(&s->lock, flags);
2021 count -= cnt;
2022 buffer += cnt;
2023 ret += cnt;
2024 start_dac1(s);
2025 }
2026 remove_wait_queue(&s->dma_dac1.wait, &wait);
2027 set_current_state(TASK_RUNNING);
2028 return ret;
2029 }
2030
2031 /* No kernel lock - we have our own spinlock */
2032 static unsigned int es1371_poll_dac(struct file *file, struct poll_table_struct *wait)
2033 {
2034 struct es1371_state *s = (struct es1371_state *)file->private_data;
2035 unsigned long flags;
2036 unsigned int mask = 0;
2037
2038 VALIDATE_STATE(s);
2039 poll_wait(file, &s->dma_dac1.wait, wait);
2040 spin_lock_irqsave(&s->lock, flags);
2041 es1371_update_ptr(s);
2042 if (s->dma_dac1.mapped) {
2043 if (s->dma_dac1.count >= (signed)s->dma_dac1.fragsize)
2044 mask |= POLLOUT | POLLWRNORM;
2045 } else {
2046 if ((signed)s->dma_dac1.dmasize >= s->dma_dac1.count + (signed)s->dma_dac1.fragsize)
2047 mask |= POLLOUT | POLLWRNORM;
2048 }
2049 spin_unlock_irqrestore(&s->lock, flags);
2050 return mask;
2051 }
2052
2053 static int es1371_mmap_dac(struct file *file, struct vm_area_struct *vma)
2054 {
2055 struct es1371_state *s = (struct es1371_state *)file->private_data;
2056 int ret;
2057 unsigned long size;
2058
2059 VALIDATE_STATE(s);
2060 if (!(vma->vm_flags & VM_WRITE))
2061 return -EINVAL;
2062 lock_kernel();
2063 if ((ret = prog_dmabuf_dac1(s)) != 0)
2064 goto out;
2065 ret = -EINVAL;
2066 if (vma->vm_pgoff != 0)
2067 goto out;
2068 size = vma->vm_end - vma->vm_start;
2069 if (size > (PAGE_SIZE << s->dma_dac1.buforder))
2070 goto out;
2071 ret = -EAGAIN;
2072 if (remap_page_range(vma->vm_start, virt_to_phys(s->dma_dac1.rawbuf), size, vma->vm_page_prot))
2073 goto out;
2074 s->dma_dac1.mapped = 1;
2075 ret = 0;
2076 out:
2077 unlock_kernel();
2078 return ret;
2079 }
2080
2081 static int es1371_ioctl_dac(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg)
2082 {
2083 struct es1371_state *s = (struct es1371_state *)file->private_data;
2084 unsigned long flags;
2085 audio_buf_info abinfo;
2086 count_info cinfo;
2087 int count;
2088 int val, ret;
2089
2090 VALIDATE_STATE(s);
2091 switch (cmd) {
2092 case OSS_GETVERSION:
2093 return put_user(SOUND_VERSION, (int *)arg);
2094
2095 case SNDCTL_DSP_SYNC:
2096 return drain_dac1(s, 0/*file->f_flags & O_NONBLOCK*/);
2097
2098 case SNDCTL_DSP_SETDUPLEX:
2099 return -EINVAL;
2100
2101 case SNDCTL_DSP_GETCAPS:
2102 return put_user(DSP_CAP_REALTIME | DSP_CAP_TRIGGER | DSP_CAP_MMAP, (int *)arg);
2103
2104 case SNDCTL_DSP_RESET:
2105 stop_dac1(s);
2106 synchronize_irq();
2107 s->dma_dac1.swptr = s->dma_dac1.hwptr = s->dma_dac1.count = s->dma_dac1.total_bytes = 0;
2108 return 0;
2109
2110 case SNDCTL_DSP_SPEED:
2111 if (get_user(val, (int *)arg))
2112 return -EFAULT;
2113 if (val >= 0) {
2114 stop_dac1(s);
2115 s->dma_dac1.ready = 0;
2116 set_dac1_rate(s, val);
2117 }
2118 return put_user(s->dac1rate, (int *)arg);
2119
2120 case SNDCTL_DSP_STEREO:
2121 if (get_user(val, (int *)arg))
2122 return -EFAULT;
2123 stop_dac1(s);
2124 s->dma_dac1.ready = 0;
2125 spin_lock_irqsave(&s->lock, flags);
2126 if (val)
2127 s->sctrl |= SCTRL_P1SMB;
2128 else
2129 s->sctrl &= ~SCTRL_P1SMB;
2130 outl(s->sctrl, s->io+ES1371_REG_SERIAL_CONTROL);
2131 spin_unlock_irqrestore(&s->lock, flags);
2132 return 0;
2133
2134 case SNDCTL_DSP_CHANNELS:
2135 if (get_user(val, (int *)arg))
2136 return -EFAULT;
2137 if (val != 0) {
2138 stop_dac1(s);
2139 s->dma_dac1.ready = 0;
2140 spin_lock_irqsave(&s->lock, flags);
2141 if (val >= 2)
2142 s->sctrl |= SCTRL_P1SMB;
2143 else
2144 s->sctrl &= ~SCTRL_P1SMB;
2145 outl(s->sctrl, s->io+ES1371_REG_SERIAL_CONTROL);
2146 spin_unlock_irqrestore(&s->lock, flags);
2147 }
2148 return put_user((s->sctrl & SCTRL_P1SMB) ? 2 : 1, (int *)arg);
2149
2150 case SNDCTL_DSP_GETFMTS: /* Returns a mask */
2151 return put_user(AFMT_S16_LE|AFMT_U8, (int *)arg);
2152
2153 case SNDCTL_DSP_SETFMT: /* Selects ONE fmt*/
2154 if (get_user(val, (int *)arg))
2155 return -EFAULT;
2156 if (val != AFMT_QUERY) {
2157 stop_dac1(s);
2158 s->dma_dac1.ready = 0;
2159 spin_lock_irqsave(&s->lock, flags);
2160 if (val == AFMT_S16_LE)
2161 s->sctrl |= SCTRL_P1SEB;
2162 else
2163 s->sctrl &= ~SCTRL_P1SEB;
2164 outl(s->sctrl, s->io+ES1371_REG_SERIAL_CONTROL);
2165 spin_unlock_irqrestore(&s->lock, flags);
2166 }
2167 return put_user((s->sctrl & SCTRL_P1SEB) ? AFMT_S16_LE : AFMT_U8, (int *)arg);
2168
2169 case SNDCTL_DSP_POST:
2170 return 0;
2171
2172 case SNDCTL_DSP_GETTRIGGER:
2173 return put_user((s->ctrl & CTRL_DAC1_EN) ? PCM_ENABLE_OUTPUT : 0, (int *)arg);
2174
2175 case SNDCTL_DSP_SETTRIGGER:
2176 if (get_user(val, (int *)arg))
2177 return -EFAULT;
2178 if (val & PCM_ENABLE_OUTPUT) {
2179 if (!s->dma_dac1.ready && (ret = prog_dmabuf_dac1(s)))
2180 return ret;
2181 start_dac1(s);
2182 } else
2183 stop_dac1(s);
2184 return 0;
2185
2186 case SNDCTL_DSP_GETOSPACE:
2187 if (!(s->ctrl & CTRL_DAC1_EN) && (val = prog_dmabuf_dac1(s)) != 0)
2188 return val;
2189 spin_lock_irqsave(&s->lock, flags);
2190 es1371_update_ptr(s);
2191 abinfo.fragsize = s->dma_dac1.fragsize;
2192 count = s->dma_dac1.count;
2193 if (count < 0)
2194 count = 0;
2195 abinfo.bytes = s->dma_dac1.dmasize - count;
2196 abinfo.fragstotal = s->dma_dac1.numfrag;
2197 abinfo.fragments = abinfo.bytes >> s->dma_dac1.fragshift;
2198 spin_unlock_irqrestore(&s->lock, flags);
2199 return copy_to_user((void *)arg, &abinfo, sizeof(abinfo)) ? -EFAULT : 0;
2200
2201 case SNDCTL_DSP_NONBLOCK:
2202 file->f_flags |= O_NONBLOCK;
2203 return 0;
2204
2205 case SNDCTL_DSP_GETODELAY:
2206 spin_lock_irqsave(&s->lock, flags);
2207 es1371_update_ptr(s);
2208 count = s->dma_dac1.count;
2209 spin_unlock_irqrestore(&s->lock, flags);
2210 if (count < 0)
2211 count = 0;
2212 return put_user(count, (int *)arg);
2213
2214 case SNDCTL_DSP_GETOPTR:
2215 if (!(file->f_mode & FMODE_WRITE))
2216 return -EINVAL;
2217 spin_lock_irqsave(&s->lock, flags);
2218 es1371_update_ptr(s);
2219 cinfo.bytes = s->dma_dac1.total_bytes;
2220 count = s->dma_dac1.count;
2221 if (count < 0)
2222 count = 0;
2223 cinfo.blocks = count >> s->dma_dac1.fragshift;
2224 cinfo.ptr = s->dma_dac1.hwptr;
2225 if (s->dma_dac1.mapped)
2226 s->dma_dac1.count &= s->dma_dac1.fragsize-1;
2227 spin_unlock_irqrestore(&s->lock, flags);
2228 return copy_to_user((void *)arg, &cinfo, sizeof(cinfo));
2229
2230 case SNDCTL_DSP_GETBLKSIZE:
2231 if ((val = prog_dmabuf_dac1(s)))
2232 return val;
2233 return put_user(s->dma_dac1.fragsize, (int *)arg);
2234
2235 case SNDCTL_DSP_SETFRAGMENT:
2236 if (get_user(val, (int *)arg))
2237 return -EFAULT;
2238 s->dma_dac1.ossfragshift = val & 0xffff;
2239 s->dma_dac1.ossmaxfrags = (val >> 16) & 0xffff;
2240 if (s->dma_dac1.ossfragshift < 4)
2241 s->dma_dac1.ossfragshift = 4;
2242 if (s->dma_dac1.ossfragshift > 15)
2243 s->dma_dac1.ossfragshift = 15;
2244 if (s->dma_dac1.ossmaxfrags < 4)
2245 s->dma_dac1.ossmaxfrags = 4;
2246 return 0;
2247
2248 case SNDCTL_DSP_SUBDIVIDE:
2249 if (s->dma_dac1.subdivision)
2250 return -EINVAL;
2251 if (get_user(val, (int *)arg))
2252 return -EFAULT;
2253 if (val != 1 && val != 2 && val != 4)
2254 return -EINVAL;
2255 s->dma_dac1.subdivision = val;
2256 return 0;
2257
2258 case SOUND_PCM_READ_RATE:
2259 return put_user(s->dac1rate, (int *)arg);
2260
2261 case SOUND_PCM_READ_CHANNELS:
2262 return put_user((s->sctrl & SCTRL_P1SMB) ? 2 : 1, (int *)arg);
2263
2264 case SOUND_PCM_READ_BITS:
2265 return put_user((s->sctrl & SCTRL_P1SEB) ? 16 : 8, (int *)arg);
2266
2267 case SOUND_PCM_WRITE_FILTER:
2268 case SNDCTL_DSP_SETSYNCRO:
2269 case SOUND_PCM_READ_FILTER:
2270 return -EINVAL;
2271
2272 }
2273 return mixdev_ioctl(&s->codec, cmd, arg);
2274 }
2275
2276 static int es1371_open_dac(struct inode *inode, struct file *file)
2277 {
2278 int minor = MINOR(inode->i_rdev);
2279 DECLARE_WAITQUEUE(wait, current);
2280 unsigned long flags;
2281 struct list_head *list;
2282 struct es1371_state *s;
2283
2284 for (list = devs.next; ; list = list->next) {
2285 if (list == &devs)
2286 return -ENODEV;
2287 s = list_entry(list, struct es1371_state, devs);
2288 if (!((s->dev_dac ^ minor) & ~0xf))
2289 break;
2290 }
2291 VALIDATE_STATE(s);
2292 /* we allow opening with O_RDWR, most programs do it although they will only write */
2293 #if 0
2294 if (file->f_mode & FMODE_READ)
2295 return -EPERM;
2296 #endif
2297 if (!(file->f_mode & FMODE_WRITE))
2298 return -EINVAL;
2299 file->private_data = s;
2300 /* wait for device to become free */
2301 down(&s->open_sem);
2302 while (s->open_mode & FMODE_DAC) {
2303 if (file->f_flags & O_NONBLOCK) {
2304 up(&s->open_sem);
2305 return -EBUSY;
2306 }
2307 add_wait_queue(&s->open_wait, &wait);
2308 __set_current_state(TASK_INTERRUPTIBLE);
2309 up(&s->open_sem);
2310 schedule();
2311 remove_wait_queue(&s->open_wait, &wait);
2312 set_current_state(TASK_RUNNING);
2313 if (signal_pending(current))
2314 return -ERESTARTSYS;
2315 down(&s->open_sem);
2316 }
2317 s->dma_dac1.ossfragshift = s->dma_dac1.ossmaxfrags = s->dma_dac1.subdivision = 0;
2318 set_dac1_rate(s, 8000);
2319 spin_lock_irqsave(&s->lock, flags);
2320 s->sctrl &= ~SCTRL_P1FMT;
2321 if ((minor & 0xf) == SND_DEV_DSP16)
2322 s->sctrl |= ES1371_FMT_S16_MONO << SCTRL_SH_P1FMT;
2323 else
2324 s->sctrl |= ES1371_FMT_U8_MONO << SCTRL_SH_P1FMT;
2325 outl(s->sctrl, s->io+ES1371_REG_SERIAL_CONTROL);
2326 spin_unlock_irqrestore(&s->lock, flags);
2327 s->open_mode |= FMODE_DAC;
2328 up(&s->open_sem);
2329 return 0;
2330 }
2331
2332 static int es1371_release_dac(struct inode *inode, struct file *file)
2333 {
2334 struct es1371_state *s = (struct es1371_state *)file->private_data;
2335
2336 VALIDATE_STATE(s);
2337 lock_kernel();
2338 drain_dac1(s, file->f_flags & O_NONBLOCK);
2339 down(&s->open_sem);
2340 stop_dac1(s);
2341 dealloc_dmabuf(s, &s->dma_dac1);
2342 s->open_mode &= ~FMODE_DAC;
2343 up(&s->open_sem);
2344 wake_up(&s->open_wait);
2345 unlock_kernel();
2346 return 0;
2347 }
2348
2349 static /*const*/ struct file_operations es1371_dac_fops = {
2350 owner: THIS_MODULE,
2351 llseek: es1371_llseek,
2352 write: es1371_write_dac,
2353 poll: es1371_poll_dac,
2354 ioctl: es1371_ioctl_dac,
2355 mmap: es1371_mmap_dac,
2356 open: es1371_open_dac,
2357 release: es1371_release_dac,
2358 };
2359
2360 /* --------------------------------------------------------------------- */
2361
2362 static ssize_t es1371_midi_read(struct file *file, char *buffer, size_t count, loff_t *ppos)
2363 {
2364 struct es1371_state *s = (struct es1371_state *)file->private_data;
2365 DECLARE_WAITQUEUE(wait, current);
2366 ssize_t ret;
2367 unsigned long flags;
2368 unsigned ptr;
2369 int cnt;
2370
2371 VALIDATE_STATE(s);
2372 if (ppos != &file->f_pos)
2373 return -ESPIPE;
2374 if (!access_ok(VERIFY_WRITE, buffer, count))
2375 return -EFAULT;
2376 if (count == 0)
2377 return 0;
2378 ret = 0;
2379 add_wait_queue(&s->midi.iwait, &wait);
2380 while (count > 0) {
2381 spin_lock_irqsave(&s->lock, flags);
2382 ptr = s->midi.ird;
2383 cnt = MIDIINBUF - ptr;
2384 if (s->midi.icnt < cnt)
2385 cnt = s->midi.icnt;
2386 if (cnt <= 0)
2387 __set_current_state(TASK_INTERRUPTIBLE);
2388 spin_unlock_irqrestore(&s->lock, flags);
2389 if (cnt > count)
2390 cnt = count;
2391 if (cnt <= 0) {
2392 if (file->f_flags & O_NONBLOCK) {
2393 if (!ret)
2394 ret = -EAGAIN;
2395 break;
2396 }
2397 schedule();
2398 if (signal_pending(current)) {
2399 if (!ret)
2400 ret = -ERESTARTSYS;
2401 break;
2402 }
2403 continue;
2404 }
2405 if (copy_to_user(buffer, s->midi.ibuf + ptr, cnt)) {
2406 if (!ret)
2407 ret = -EFAULT;
2408 break;
2409 }
2410 ptr = (ptr + cnt) % MIDIINBUF;
2411 spin_lock_irqsave(&s->lock, flags);
2412 s->midi.ird = ptr;
2413 s->midi.icnt -= cnt;
2414 spin_unlock_irqrestore(&s->lock, flags);
2415 count -= cnt;
2416 buffer += cnt;
2417 ret += cnt;
2418 break;
2419 }
2420 __set_current_state(TASK_RUNNING);
2421 remove_wait_queue(&s->midi.iwait, &wait);
2422 return ret;
2423 }
2424
2425 static ssize_t es1371_midi_write(struct file *file, const char *buffer, size_t count, loff_t *ppos)
2426 {
2427 struct es1371_state *s = (struct es1371_state *)file->private_data;
2428 DECLARE_WAITQUEUE(wait, current);
2429 ssize_t ret;
2430 unsigned long flags;
2431 unsigned ptr;
2432 int cnt;
2433
2434 VALIDATE_STATE(s);
2435 if (ppos != &file->f_pos)
2436 return -ESPIPE;
2437 if (!access_ok(VERIFY_READ, buffer, count))
2438 return -EFAULT;
2439 if (count == 0)
2440 return 0;
2441 ret = 0;
2442 add_wait_queue(&s->midi.owait, &wait);
2443 while (count > 0) {
2444 spin_lock_irqsave(&s->lock, flags);
2445 ptr = s->midi.owr;
2446 cnt = MIDIOUTBUF - ptr;
2447 if (s->midi.ocnt + cnt > MIDIOUTBUF)
2448 cnt = MIDIOUTBUF - s->midi.ocnt;
2449 if (cnt <= 0) {
2450 __set_current_state(TASK_INTERRUPTIBLE);
2451 es1371_handle_midi(s);
2452 }
2453 spin_unlock_irqrestore(&s->lock, flags);
2454 if (cnt > count)
2455 cnt = count;
2456 if (cnt <= 0) {
2457 if (file->f_flags & O_NONBLOCK) {
2458 if (!ret)
2459 ret = -EAGAIN;
2460 break;
2461 }
2462 schedule();
2463 if (signal_pending(current)) {
2464 if (!ret)
2465 ret = -ERESTARTSYS;
2466 break;
2467 }
2468 continue;
2469 }
2470 if (copy_from_user(s->midi.obuf + ptr, buffer, cnt)) {
2471 if (!ret)
2472 ret = -EFAULT;
2473 break;
2474 }
2475 ptr = (ptr + cnt) % MIDIOUTBUF;
2476 spin_lock_irqsave(&s->lock, flags);
2477 s->midi.owr = ptr;
2478 s->midi.ocnt += cnt;
2479 spin_unlock_irqrestore(&s->lock, flags);
2480 count -= cnt;
2481 buffer += cnt;
2482 ret += cnt;
2483 spin_lock_irqsave(&s->lock, flags);
2484 es1371_handle_midi(s);
2485 spin_unlock_irqrestore(&s->lock, flags);
2486 }
2487 __set_current_state(TASK_RUNNING);
2488 remove_wait_queue(&s->midi.owait, &wait);
2489 return ret;
2490 }
2491
2492 /* No kernel lock - we have our own spinlock */
2493 static unsigned int es1371_midi_poll(struct file *file, struct poll_table_struct *wait)
2494 {
2495 struct es1371_state *s = (struct es1371_state *)file->private_data;
2496 unsigned long flags;
2497 unsigned int mask = 0;
2498
2499 VALIDATE_STATE(s);
2500 if (file->f_mode & FMODE_WRITE)
2501 poll_wait(file, &s->midi.owait, wait);
2502 if (file->f_mode & FMODE_READ)
2503 poll_wait(file, &s->midi.iwait, wait);
2504 spin_lock_irqsave(&s->lock, flags);
2505 if (file->f_mode & FMODE_READ) {
2506 if (s->midi.icnt > 0)
2507 mask |= POLLIN | POLLRDNORM;
2508 }
2509 if (file->f_mode & FMODE_WRITE) {
2510 if (s->midi.ocnt < MIDIOUTBUF)
2511 mask |= POLLOUT | POLLWRNORM;
2512 }
2513 spin_unlock_irqrestore(&s->lock, flags);
2514 return mask;
2515 }
2516
2517 static int es1371_midi_open(struct inode *inode, struct file *file)
2518 {
2519 int minor = MINOR(inode->i_rdev);
2520 DECLARE_WAITQUEUE(wait, current);
2521 unsigned long flags;
2522 struct list_head *list;
2523 struct es1371_state *s;
2524
2525 for (list = devs.next; ; list = list->next) {
2526 if (list == &devs)
2527 return -ENODEV;
2528 s = list_entry(list, struct es1371_state, devs);
2529 if (s->dev_midi == minor)
2530 break;
2531 }
2532 VALIDATE_STATE(s);
2533 file->private_data = s;
2534 /* wait for device to become free */
2535 down(&s->open_sem);
2536 while (s->open_mode & (file->f_mode << FMODE_MIDI_SHIFT)) {
2537 if (file->f_flags & O_NONBLOCK) {
2538 up(&s->open_sem);
2539 return -EBUSY;
2540 }
2541 add_wait_queue(&s->open_wait, &wait);
2542 __set_current_state(TASK_INTERRUPTIBLE);
2543 up(&s->open_sem);
2544 schedule();
2545 remove_wait_queue(&s->open_wait, &wait);
2546 set_current_state(TASK_RUNNING);
2547 if (signal_pending(current))
2548 return -ERESTARTSYS;
2549 down(&s->open_sem);
2550 }
2551 spin_lock_irqsave(&s->lock, flags);
2552 if (!(s->open_mode & (FMODE_MIDI_READ | FMODE_MIDI_WRITE))) {
2553 s->midi.ird = s->midi.iwr = s->midi.icnt = 0;
2554 s->midi.ord = s->midi.owr = s->midi.ocnt = 0;
2555 outb(UCTRL_CNTRL_SWR, s->io+ES1371_REG_UART_CONTROL);
2556 outb(0, s->io+ES1371_REG_UART_CONTROL);
2557 outb(0, s->io+ES1371_REG_UART_TEST);
2558 }
2559 if (file->f_mode & FMODE_READ) {
2560 s->midi.ird = s->midi.iwr = s->midi.icnt = 0;
2561 }
2562 if (file->f_mode & FMODE_WRITE) {
2563 s->midi.ord = s->midi.owr = s->midi.ocnt = 0;
2564 }
2565 s->ctrl |= CTRL_UART_EN;
2566 outl(s->ctrl, s->io+ES1371_REG_CONTROL);
2567 es1371_handle_midi(s);
2568 spin_unlock_irqrestore(&s->lock, flags);
2569 s->open_mode |= (file->f_mode << FMODE_MIDI_SHIFT) & (FMODE_MIDI_READ | FMODE_MIDI_WRITE);
2570 up(&s->open_sem);
2571 return 0;
2572 }
2573
2574 static int es1371_midi_release(struct inode *inode, struct file *file)
2575 {
2576 struct es1371_state *s = (struct es1371_state *)file->private_data;
2577 DECLARE_WAITQUEUE(wait, current);
2578 unsigned long flags;
2579 unsigned count, tmo;
2580
2581 VALIDATE_STATE(s);
2582 lock_kernel();
2583 if (file->f_mode & FMODE_WRITE) {
2584 add_wait_queue(&s->midi.owait, &wait);
2585 for (;;) {
2586 __set_current_state(TASK_INTERRUPTIBLE);
2587 spin_lock_irqsave(&s->lock, flags);
2588 count = s->midi.ocnt;
2589 spin_unlock_irqrestore(&s->lock, flags);
2590 if (count <= 0)
2591 break;
2592 if (signal_pending(current))
2593 break;
2594 if (file->f_flags & O_NONBLOCK) {
2595 remove_wait_queue(&s->midi.owait, &wait);
2596 set_current_state(TASK_RUNNING);
2597 return -EBUSY;
2598 }
2599 tmo = (count * HZ) / 3100;
2600 if (!schedule_timeout(tmo ? : 1) && tmo)
2601 printk(KERN_DEBUG PFX "midi timed out??\n");
2602 }
2603 remove_wait_queue(&s->midi.owait, &wait);
2604 set_current_state(TASK_RUNNING);
2605 }
2606 down(&s->open_sem);
2607 s->open_mode &= (~(file->f_mode << FMODE_MIDI_SHIFT)) & (FMODE_MIDI_READ|FMODE_MIDI_WRITE);
2608 spin_lock_irqsave(&s->lock, flags);
2609 if (!(s->open_mode & (FMODE_MIDI_READ | FMODE_MIDI_WRITE))) {
2610 s->ctrl &= ~CTRL_UART_EN;
2611 outl(s->ctrl, s->io+ES1371_REG_CONTROL);
2612 }
2613 spin_unlock_irqrestore(&s->lock, flags);
2614 up(&s->open_sem);
2615 wake_up(&s->open_wait);
2616 unlock_kernel();
2617 return 0;
2618 }
2619
2620 static /*const*/ struct file_operations es1371_midi_fops = {
2621 owner: THIS_MODULE,
2622 llseek: es1371_llseek,
2623 read: es1371_midi_read,
2624 write: es1371_midi_write,
2625 poll: es1371_midi_poll,
2626 open: es1371_midi_open,
2627 release: es1371_midi_release,
2628 };
2629
2630 /* --------------------------------------------------------------------- */
2631
2632 /*
2633 * for debugging purposes, we'll create a proc device that dumps the
2634 * CODEC chipstate
2635 */
2636
2637 #ifdef ES1371_DEBUG
2638 static int proc_es1371_dump (char *buf, char **start, off_t fpos, int length, int *eof, void *data)
2639 {
2640 struct es1371_state *s;
2641 int cnt, len = 0;
2642
2643 if (list_empty(&devs))
2644 return 0;
2645 s = list_entry(devs.next, struct es1371_state, devs);
2646 /* print out header */
2647 len += sprintf(buf + len, "\t\tCreative ES137x Debug Dump-o-matic\n");
2648
2649 /* print out CODEC state */
2650 len += sprintf (buf + len, "AC97 CODEC state\n");
2651 for (cnt=0; cnt <= 0x7e; cnt = cnt +2)
2652 len+= sprintf (buf + len, "reg:0x%02x val:0x%04x\n", cnt, rdcodec(&s->codec, cnt));
2653
2654 if (fpos >=len){
2655 *start = buf;
2656 *eof =1;
2657 return 0;
2658 }
2659 *start = buf + fpos;
2660 if ((len -= fpos) > length)
2661 return length;
2662 *eof =1;
2663 return len;
2664
2665 }
2666 #endif /* ES1371_DEBUG */
2667
2668 /* --------------------------------------------------------------------- */
2669
2670 /* maximum number of devices; only used for command line params */
2671 #define NR_DEVICE 5
2672
2673 static int joystick[NR_DEVICE] = { 0, };
2674 static int spdif[NR_DEVICE] = { 0, };
2675 static int nomix[NR_DEVICE] = { 0, };
2676
2677 static unsigned int devindex = 0;
2678
2679 MODULE_PARM(joystick, "1-" __MODULE_STRING(NR_DEVICE) "i");
2680 MODULE_PARM_DESC(joystick, "sets address and enables joystick interface (still need separate driver)");
2681 MODULE_PARM(spdif, "1-" __MODULE_STRING(NR_DEVICE) "i");
2682 MODULE_PARM_DESC(spdif, "if 1 the output is in S/PDIF digital mode");
2683 MODULE_PARM(nomix, "1-" __MODULE_STRING(NR_DEVICE) "i");
2684 MODULE_PARM_DESC(nomix, "if 1 no analog audio is mixed to the digital output");
2685
2686 MODULE_AUTHOR("Thomas M. Sailer, sailer@ife.ee.ethz.ch, hb9jnx@hb9w.che.eu");
2687 MODULE_DESCRIPTION("ES1371 AudioPCI97 Driver");
2688
2689 /* --------------------------------------------------------------------- */
2690
2691 static struct initvol {
2692 int mixch;
2693 int vol;
2694 } initvol[] __initdata = {
2695 { SOUND_MIXER_WRITE_LINE, 0x4040 },
2696 { SOUND_MIXER_WRITE_CD, 0x4040 },
2697 { MIXER_WRITE(SOUND_MIXER_VIDEO), 0x4040 },
2698 { SOUND_MIXER_WRITE_LINE1, 0x4040 },
2699 { SOUND_MIXER_WRITE_PCM, 0x4040 },
2700 { SOUND_MIXER_WRITE_VOLUME, 0x4040 },
2701 { MIXER_WRITE(SOUND_MIXER_PHONEOUT), 0x4040 },
2702 { SOUND_MIXER_WRITE_OGAIN, 0x4040 },
2703 { MIXER_WRITE(SOUND_MIXER_PHONEIN), 0x4040 },
2704 { SOUND_MIXER_WRITE_SPEAKER, 0x4040 },
2705 { SOUND_MIXER_WRITE_MIC, 0x4040 },
2706 { SOUND_MIXER_WRITE_RECLEV, 0x4040 },
2707 { SOUND_MIXER_WRITE_IGAIN, 0x4040 }
2708 };
2709
2710 #define RSRCISIOREGION(dev,num) (pci_resource_start((dev), (num)) != 0 && \
2711 (pci_resource_flags((dev), (num)) & IORESOURCE_IO))
2712
2713 static int __devinit es1371_probe(struct pci_dev *pcidev, const struct pci_device_id *pciid)
2714 {
2715 struct es1371_state *s;
2716 mm_segment_t fs;
2717 int i, val;
2718 unsigned long tmo;
2719 signed long tmo2;
2720 unsigned int cssr;
2721
2722 if (!RSRCISIOREGION(pcidev, 0))
2723 return -1;
2724 if (pcidev->irq == 0)
2725 return -1;
2726 if (!pci_dma_supported(pcidev, 0xffffffff)) {
2727 printk(KERN_WARNING "es1371: architecture does not support 32bit PCI busmaster DMA\n");
2728 return -1;
2729 }
2730 if (!(s = kmalloc(sizeof(struct es1371_state), GFP_KERNEL))) {
2731 printk(KERN_WARNING PFX "out of memory\n");
2732 return -1;
2733 }
2734 memset(s, 0, sizeof(struct es1371_state));
2735 init_waitqueue_head(&s->dma_adc.wait);
2736 init_waitqueue_head(&s->dma_dac1.wait);
2737 init_waitqueue_head(&s->dma_dac2.wait);
2738 init_waitqueue_head(&s->open_wait);
2739 init_waitqueue_head(&s->midi.iwait);
2740 init_waitqueue_head(&s->midi.owait);
2741 init_MUTEX(&s->open_sem);
2742 spin_lock_init(&s->lock);
2743 s->magic = ES1371_MAGIC;
2744 s->dev = pcidev;
2745 s->io = pci_resource_start(pcidev, 0);
2746 s->irq = pcidev->irq;
2747 s->vendor = pcidev->vendor;
2748 s->device = pcidev->device;
2749 pci_read_config_byte(pcidev, PCI_REVISION_ID, &s->rev);
2750 s->codec.private_data = s;
2751 s->codec.id = 0;
2752 s->codec.codec_read = rdcodec;
2753 s->codec.codec_write = wrcodec;
2754 printk(KERN_INFO PFX "found chip, vendor id 0x%04x device id 0x%04x revision 0x%02x\n",
2755 s->vendor, s->device, s->rev);
2756 if (!request_region(s->io, ES1371_EXTENT, "es1371")) {
2757 printk(KERN_ERR PFX "io ports %#lx-%#lx in use\n", s->io, s->io+ES1371_EXTENT-1);
2758 goto err_region;
2759 }
2760 if (pci_enable_device(pcidev))
2761 goto err_irq;
2762 if (request_irq(s->irq, es1371_interrupt, SA_SHIRQ, "es1371", s)) {
2763 printk(KERN_ERR PFX "irq %u in use\n", s->irq);
2764 goto err_irq;
2765 }
2766 printk(KERN_INFO PFX "found es1371 rev %d at io %#lx irq %u\n"
2767 KERN_INFO PFX "features: joystick 0x%x\n", s->rev, s->io, s->irq, joystick[devindex]);
2768 /* register devices */
2769 if ((s->dev_audio = register_sound_dsp(&es1371_audio_fops, -1)) < 0)
2770 goto err_dev1;
2771 if ((s->codec.dev_mixer = register_sound_mixer(&es1371_mixer_fops, -1)) < 0)
2772 goto err_dev2;
2773 if ((s->dev_dac = register_sound_dsp(&es1371_dac_fops, -1)) < 0)
2774 goto err_dev3;
2775 if ((s->dev_midi = register_sound_midi(&es1371_midi_fops, -1)) < 0)
2776 goto err_dev4;
2777 #ifdef ES1371_DEBUG
2778 /* intialize the debug proc device */
2779 s->ps = create_proc_read_entry("es1371",0,NULL,proc_es1371_dump,NULL);
2780 #endif /* ES1371_DEBUG */
2781
2782 /* initialize codec registers */
2783 s->ctrl = 0;
2784 if (pcidev->subsystem_vendor == 0x107b && pcidev->subsystem_device == 0x2150) {
2785 s->ctrl |= CTRL_GPIO_OUT0;
2786 printk(KERN_INFO PFX "Running On Gateway 2000 Solo 2510 - Amp On \n");
2787 }
2788 if ((joystick[devindex] & ~0x18) == 0x200) {
2789 if (check_region(joystick[devindex], JOY_EXTENT))
2790 printk(KERN_ERR PFX "joystick address 0x%x already in use\n", joystick[devindex]);
2791 else {
2792 s->ctrl |= CTRL_JYSTK_EN | (((joystick[devindex] >> 3) & CTRL_JOY_MASK) << CTRL_JOY_SHIFT);
2793 }
2794 }
2795 s->sctrl = 0;
2796 cssr = 0;
2797 s->spdif_volume = -1;
2798 /* check to see if s/pdif mode is being requested */
2799 if (spdif[devindex]) {
2800 if (s->rev >= 4) {
2801 printk(KERN_INFO PFX "enabling S/PDIF output\n");
2802 s->spdif_volume = 0;
2803 cssr |= STAT_EN_SPDIF;
2804 s->ctrl |= CTRL_SPDIFEN_B;
2805 if (nomix[devindex]) /* don't mix analog inputs to s/pdif output */
2806 s->ctrl |= CTRL_RECEN_B;
2807 } else {
2808 printk(KERN_ERR PFX "revision %d does not support S/PDIF\n", s->rev);
2809 }
2810 }
2811 /* initialize the chips */
2812 outl(s->ctrl, s->io+ES1371_REG_CONTROL);
2813 outl(s->sctrl, s->io+ES1371_REG_SERIAL_CONTROL);
2814 outl(0, s->io+ES1371_REG_LEGACY);
2815 pci_set_master(pcidev); /* enable bus mastering */
2816 /* if we are a 5880 turn on the AC97 */
2817 if (s->vendor == PCI_VENDOR_ID_ENSONIQ &&
2818 ((s->device == PCI_DEVICE_ID_ENSONIQ_CT5880 && s->rev == CT5880REV_CT5880_C) ||
2819 (s->device == PCI_DEVICE_ID_ENSONIQ_ES1371 && s->rev == ES1371REV_CT5880_A) ||
2820 (s->device == PCI_DEVICE_ID_ENSONIQ_ES1371 && s->rev == ES1371REV_ES1373_8))) {
2821 cssr |= CSTAT_5880_AC97_RST;
2822 outl(cssr, s->io+ES1371_REG_STATUS);
2823 /* need to delay around 20ms(bleech) to give
2824 some CODECs enough time to wakeup */
2825 tmo = jiffies + (HZ / 50) + 1;
2826 for (;;) {
2827 tmo2 = tmo - jiffies;
2828 if (tmo2 <= 0)
2829 break;
2830 schedule_timeout(tmo2);
2831 }
2832 }
2833 /* AC97 warm reset to start the bitclk */
2834 outl(s->ctrl | CTRL_SYNCRES, s->io+ES1371_REG_CONTROL);
2835 udelay(2);
2836 outl(s->ctrl, s->io+ES1371_REG_CONTROL);
2837 /* init the sample rate converter */
2838 src_init(s);
2839 /* codec init */
2840 if (!ac97_probe_codec(&s->codec))
2841 goto err_dev4;
2842 /* set default values */
2843
2844 fs = get_fs();
2845 set_fs(KERNEL_DS);
2846 val = SOUND_MASK_LINE;
2847 mixdev_ioctl(&s->codec, SOUND_MIXER_WRITE_RECSRC, (unsigned long)&val);
2848 for (i = 0; i < sizeof(initvol)/sizeof(initvol[0]); i++) {
2849 val = initvol[i].vol;
2850 mixdev_ioctl(&s->codec, initvol[i].mixch, (unsigned long)&val);
2851 }
2852 /* mute master and PCM when in S/PDIF mode */
2853 if (s->spdif_volume != -1) {
2854 val = 0x0000;
2855 s->codec.mixer_ioctl(&s->codec, SOUND_MIXER_WRITE_VOLUME, (unsigned long)&val);
2856 s->codec.mixer_ioctl(&s->codec, SOUND_MIXER_WRITE_PCM, (unsigned long)&val);
2857 }
2858 set_fs(fs);
2859 /* turn on S/PDIF output driver if requested */
2860 outl(cssr, s->io+ES1371_REG_STATUS);
2861 /* store it in the driver field */
2862 pcidev->driver_data = s;
2863 pcidev->dma_mask = 0xffffffff;
2864 /* put it into driver list */
2865 list_add_tail(&s->devs, &devs);
2866 /* increment devindex */
2867 if (devindex < NR_DEVICE-1)
2868 devindex++;
2869 return 0;
2870
2871 err_dev4:
2872 unregister_sound_dsp(s->dev_dac);
2873 err_dev3:
2874 unregister_sound_mixer(s->codec.dev_mixer);
2875 err_dev2:
2876 unregister_sound_dsp(s->dev_audio);
2877 err_dev1:
2878 printk(KERN_ERR PFX "cannot register misc device\n");
2879 free_irq(s->irq, s);
2880 err_irq:
2881 release_region(s->io, ES1371_EXTENT);
2882 err_region:
2883 kfree(s);
2884 return -1;
2885 }
2886
2887 static void __devinit es1371_remove(struct pci_dev *dev)
2888 {
2889 struct es1371_state *s = (struct es1371_state *)dev->driver_data;
2890
2891 if (!s)
2892 return;
2893 list_del(&s->devs);
2894 #ifdef ES1371_DEBUG
2895 if (s->ps)
2896 remove_proc_entry("es1371", NULL);
2897 #endif /* ES1371_DEBUG */
2898 outl(0, s->io+ES1371_REG_CONTROL); /* switch everything off */
2899 outl(0, s->io+ES1371_REG_SERIAL_CONTROL); /* clear serial interrupts */
2900 synchronize_irq();
2901 free_irq(s->irq, s);
2902 release_region(s->io, ES1371_EXTENT);
2903 unregister_sound_dsp(s->dev_audio);
2904 unregister_sound_mixer(s->codec.dev_mixer);
2905 unregister_sound_dsp(s->dev_dac);
2906 unregister_sound_midi(s->dev_midi);
2907 kfree(s);
2908 dev->driver_data = NULL;
2909 }
2910
2911 static struct pci_device_id id_table[] __devinitdata = {
2912 { PCI_VENDOR_ID_ENSONIQ, PCI_DEVICE_ID_ENSONIQ_ES1371, PCI_ANY_ID, PCI_ANY_ID, 0, 0 },
2913 { PCI_VENDOR_ID_ENSONIQ, PCI_DEVICE_ID_ENSONIQ_CT5880, PCI_ANY_ID, PCI_ANY_ID, 0, 0 },
2914 { PCI_VENDOR_ID_ECTIVA, PCI_DEVICE_ID_ECTIVA_EV1938, PCI_ANY_ID, PCI_ANY_ID, 0, 0 },
2915 { 0, }
2916 };
2917
2918 MODULE_DEVICE_TABLE(pci, id_table);
2919
2920 static struct pci_driver es1371_driver = {
2921 name: "es1371",
2922 id_table: id_table,
2923 probe: es1371_probe,
2924 remove: es1371_remove
2925 };
2926
2927 static int __init init_es1371(void)
2928 {
2929 if (!pci_present()) /* No PCI bus in this machine! */
2930 return -ENODEV;
2931 printk(KERN_INFO PFX "version v0.26 time " __TIME__ " " __DATE__ "\n");
2932 return pci_module_init(&es1371_driver);
2933 }
2934
2935 static void __exit cleanup_es1371(void)
2936 {
2937 printk(KERN_INFO PFX "unloading\n");
2938 pci_unregister_driver(&es1371_driver);
2939 }
2940
2941 module_init(init_es1371);
2942 module_exit(cleanup_es1371);
2943
2944 /* --------------------------------------------------------------------- */
2945
2946 #ifndef MODULE
2947
2948 /* format is: es1371=[joystick] */
2949
2950 static int __init es1371_setup(char *str)
2951 {
2952 static unsigned __initlocaldata nr_dev = 0;
2953
2954 if (nr_dev >= NR_DEVICE)
2955 return 0;
2956 if (get_option(&str, &joystick[nr_dev]) == 2)
2957 (void)get_option(&str, &spdif[nr_dev]);
2958 nr_dev++;
2959 return 1;
2960 }
2961
2962 __setup("es1371=", es1371_setup);
2963
2964 #endif /* MODULE */
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