arch/alpha/kernel/core_irongate.c

   1 /*
   2  *      linux/arch/alpha/kernel/core_irongate.c
   3  *
   4  * Based on code written by David A. Rusling (david.rusling@reo.mts.dec.com).
   5  *
   6  *      Copyright (C) 1999 Alpha Processor, Inc.,
   7  *              (David Daniel, Stig Telfer, Soohoon Lee)
   8  *
   9  * Code common to all IRONGATE core logic chips.
  10  */
  11
  12 #include <linux/kernel.h>
  13 #include <linux/types.h>
  14 #include <linux/pci.h>
  15 #include <linux/sched.h>
  16 #include <linux/init.h>
  17
  18 #include <asm/ptrace.h>
  19 #include <asm/system.h>
  20 #include <asm/pci.h>
  21 #include <asm/hwrpb.h>
  22
  23 #define __EXTERN_INLINE inline
  24 #include <asm/io.h>
  25 #include <asm/core_irongate.h>
  26 #undef __EXTERN_INLINE
  27
  28 #include "proto.h"
  29 #include "pci_impl.h"
  30
  31 #undef DEBUG_IRONGATE           /* define to enable verbose Irongate debug */
  32
  33 /*
  34  * BIOS32-style PCI interface:
  35  */
  36
  37 #define DEBUG_CONFIG 0
  38
  39 #if DEBUG_CONFIG
  40 # define DBG_CFG(args)  printk args
  41 #else
  42 # define DBG_CFG(args)
  43 #endif
  44
  45
  46 /*
  47  * Given a bus, device, and function number, compute resulting
  48  * configuration space address accordingly.  It is therefore not safe
  49  * to have concurrent invocations to configuration space access
  50  * routines, but there really shouldn't be any need for this.
  51  *
  52  *      addr[31:24]             reserved
  53  *      addr[23:16]             bus number (8 bits = 128 possible buses)
  54  *      addr[15:11]             Device number (5 bits)
  55  *      addr[10: 8]             function number
  56  *      addr[ 7: 2]             register number
  57  *
  58  * For IRONGATE:
  59  *    if (bus = addr[23:16]) == 0
  60  *    then
  61  *        type 0 config cycle:
  62  *            addr_on_pci[31:11] = id selection for device = addr[15:11]
  63  *            addr_on_pci[10: 2] = addr[10: 2] ???
  64  *            addr_on_pci[ 1: 0] = 00
  65  *    else
  66  *        type 1 config cycle (pass on with no decoding):
  67  *            addr_on_pci[31:24] = 0
  68  *            addr_on_pci[23: 2] = addr[23: 2]
  69  *            addr_on_pci[ 1: 0] = 01
  70  *    fi
  71  *
  72  * Notes:
  73  *      The function number selects which function of a multi-function device
  74  *      (e.g., SCSI and Ethernet).
  75  *
  76  *      The register selects a DWORD (32 bit) register offset.  Hence it
  77  *      doesn't get shifted by 2 bits as we want to "drop" the bottom two
  78  *      bits.
  79  */
  80
  81 static int
  82 mk_conf_addr(struct pci_dev *dev, int where, unsigned long *pci_addr,
  83              unsigned char *type1)
  84 {
  85         unsigned long addr;
  86         u8 bus = dev->bus->number;
  87         u8 device_fn = dev->devfn;
  88
  89         DBG_CFG(("mk_conf_addr(bus=%d ,device_fn=0x%x, where=0x%x, "
  90                  "pci_addr=0x%p, type1=0x%p)\n",
  91                  bus, device_fn, where, pci_addr, type1));
  92
  93         *type1 = (bus != 0);
  94
  95         addr = (bus << 16) | (device_fn << 8) | where;
  96         addr |= IRONGATE_CONF;
  97
  98         *pci_addr = addr;
  99         DBG_CFG(("mk_conf_addr: returning pci_addr 0x%lx\n", addr));
 100         return 0;
 101 }
 102
 103 static int
 104 irongate_read_config_byte(struct pci_dev *dev, int where, u8 *value)
 105 {
 106         unsigned long addr;
 107         unsigned char type1;
 108
 109         if (mk_conf_addr(dev, where, &addr, &type1))
 110                 return PCIBIOS_DEVICE_NOT_FOUND;
 111
 112         *value = __kernel_ldbu(*(vucp)addr);
 113         return PCIBIOS_SUCCESSFUL;
 114 }
 115
 116 static int
 117 irongate_read_config_word(struct pci_dev *dev, int where, u16 *value)
 118 {
 119         unsigned long addr;
 120         unsigned char type1;
 121
 122         if (mk_conf_addr(dev, where, &addr, &type1))
 123                 return PCIBIOS_DEVICE_NOT_FOUND;
 124
 125         *value = __kernel_ldwu(*(vusp)addr);
 126         return PCIBIOS_SUCCESSFUL;
 127 }
 128
 129 static int
 130 irongate_read_config_dword(struct pci_dev *dev, int where, u32 *value)
 131 {
 132         unsigned long addr;
 133         unsigned char type1;
 134
 135         if (mk_conf_addr(dev, where, &addr, &type1))
 136                 return PCIBIOS_DEVICE_NOT_FOUND;
 137
 138         *value = *(vuip)addr;
 139         return PCIBIOS_SUCCESSFUL;
 140 }
 141
 142 static int
 143 irongate_write_config_byte(struct pci_dev *dev, int where, u8 value)
 144 {
 145         unsigned long addr;
 146         unsigned char type1;
 147
 148         if (mk_conf_addr(dev, where, &addr, &type1))
 149                 return PCIBIOS_DEVICE_NOT_FOUND;
 150
 151         __kernel_stb(value, *(vucp)addr);
 152         mb();
 153         __kernel_ldbu(*(vucp)addr);
 154         return PCIBIOS_SUCCESSFUL;
 155 }
 156
 157 static int
 158 irongate_write_config_word(struct pci_dev *dev, int where, u16 value)
 159 {
 160         unsigned long addr;
 161         unsigned char type1;
 162
 163         if (mk_conf_addr(dev, where, &addr, &type1))
 164                 return PCIBIOS_DEVICE_NOT_FOUND;
 165
 166         __kernel_stw(value, *(vusp)addr);
 167         mb();
 168         __kernel_ldwu(*(vusp)addr);
 169         return PCIBIOS_SUCCESSFUL;
 170 }
 171
 172 static int
 173 irongate_write_config_dword(struct pci_dev *dev, int where, u32 value)
 174 {
 175         unsigned long addr;
 176         unsigned char type1;
 177
 178         if (mk_conf_addr(dev, where, &addr, &type1))
 179                 return PCIBIOS_DEVICE_NOT_FOUND;
 180
 181         *(vuip)addr = value;
 182         mb();
 183         *(vuip)addr;
 184         return PCIBIOS_SUCCESSFUL;
 185 }
 186
 187
 188 struct pci_ops irongate_pci_ops =
 189 {
 190         read_byte:      irongate_read_config_byte,
 191         read_word:      irongate_read_config_word,
 192         read_dword:     irongate_read_config_dword,
 193         write_byte:     irongate_write_config_byte,
 194         write_word:     irongate_write_config_word,
 195         write_dword:    irongate_write_config_dword
 196 };
 197 \f
 198 #ifdef DEBUG_IRONGATE
 199 static void
 200 irongate_register_dump(const char *function_name)
 201 {
 202         printk("%s: Irongate registers:\n"
 203                "\tFunction 0:\n"
 204                "\tdev_vendor\t0x%08x\n"
 205                "\tstat_cmd\t0x%08x\n"
 206                "\tclass\t\t0x%08x\n"
 207                "\tlatency\t\t0x%08x\n"
 208                "\tbar0\t\t0x%08x\n"
 209                "\tbar1\t\t0x%08x\n"
 210                "\tbar2\t\t0x%08x\n"
 211                "\trsrvd0[0]\t0x%08x\n"
 212                "\trsrvd0[1]\t0x%08x\n"
 213                "\trsrvd0[2]\t0x%08x\n"
 214                "\trsrvd0[3]\t0x%08x\n"
 215                "\trsrvd0[4]\t0x%08x\n"
 216                "\trsrvd0[5]\t0x%08x\n"
 217                "\tcapptr\t\t0x%08x\n"
 218                "\trsrvd1[0]\t0x%08x\n"
 219                "\trsrvd1[1]\t0x%08x\n"
 220                "\tbacsr10\t\t0x%08x\n"
 221                "\tbacsr32\t\t0x%08x\n"
 222                "\tbacsr54\t\t0x%08x\n"
 223                "\trsrvd2[0]\t0x%08x\n"
 224                "\tdrammap\t\t0x%08x\n"
 225                "\tdramtm\t\t0x%08x\n"
 226                "\tdramms\t\t0x%08x\n"
 227                "\trsrvd3[0]\t0x%08x\n"
 228                "\tbiu0\t\t0x%08x\n"
 229                "\tbiusip\t\t0x%08x\n"
 230                "\trsrvd4[0]\t0x%08x\n"
 231                "\trsrvd4[1]\t0x%08x\n"
 232                "\tmro\t\t0x%08x\n"
 233                "\trsrvd5[0]\t0x%08x\n"
 234                "\trsrvd5[1]\t0x%08x\n"
 235                "\trsrvd5[2]\t0x%08x\n"
 236                "\twhami\t\t0x%08x\n"
 237                "\tpciarb\t\t0x%08x\n"
 238                "\tpcicfg\t\t0x%08x\n"
 239                "\trsrvd6[0]\t0x%08x\n"
 240                "\trsrvd6[1]\t0x%08x\n"
 241                "\trsrvd6[2]\t0x%08x\n"
 242                "\trsrvd6[3]\t0x%08x\n"
 243                "\trsrvd6[4]\t0x%08x\n"
 244                "\tagpcap\t\t0x%08x\n"
 245                "\tagpstat\t\t0x%08x\n"
 246                "\tagpcmd\t\t0x%08x\n"
 247                "\tagpva\t\t0x%08x\n"
 248                "\tagpmode\t\t0x%08x\n"
 249
 250                "\n\tFunction 1:\n"
 251                "\tdev_vendor:\t0x%08x\n"
 252                "\tcmd_status:\t0x%08x\n"
 253                "\trevid_etc :\t0x%08x\n"
 254                "\thtype_etc :\t0x%08x\n"
 255                "\trsrvd0[0] :\t0x%08x\n"
 256                "\trsrvd0[1] :\t0x%08x\n"
 257                "\tbus_nmbers:\t0x%08x\n"
 258                "\tio_baselim:\t0x%08x\n"
 259                "\tmem_bselim:\t0x%08x\n"
 260                "\tpf_baselib:\t0x%08x\n"
 261                "\trsrvd1[0] :\t0x%08x\n"
 262                "\trsrvd1[1] :\t0x%08x\n"
 263                "\tio_baselim:\t0x%08x\n"
 264                "\trsrvd2[0] :\t0x%08x\n"
 265                "\trsrvd2[1] :\t0x%08x\n"
 266                "\tinterrupt :\t0x%08x\n",
 267
 268                function_name,
 269                IRONGATE0->dev_vendor,
 270                IRONGATE0->stat_cmd,
 271                IRONGATE0->class,
 272                IRONGATE0->latency,
 273                IRONGATE0->bar0,
 274                IRONGATE0->bar1,
 275                IRONGATE0->bar2,
 276                IRONGATE0->rsrvd0[0],
 277                IRONGATE0->rsrvd0[1],
 278                IRONGATE0->rsrvd0[2],
 279                IRONGATE0->rsrvd0[3],
 280                IRONGATE0->rsrvd0[4],
 281                IRONGATE0->rsrvd0[5],
 282                IRONGATE0->capptr,
 283                IRONGATE0->rsrvd1[0],
 284                IRONGATE0->rsrvd1[1],
 285                IRONGATE0->bacsr10,
 286                IRONGATE0->bacsr32,
 287                IRONGATE0->bacsr54,
 288                IRONGATE0->rsrvd2[0],
 289                IRONGATE0->drammap,
 290                IRONGATE0->dramtm,
 291                IRONGATE0->dramms,
 292                IRONGATE0->rsrvd3[0],
 293                IRONGATE0->biu0,
 294                IRONGATE0->biusip,
 295                IRONGATE0->rsrvd4[0],
 296                IRONGATE0->rsrvd4[1],
 297                IRONGATE0->mro,
 298                IRONGATE0->rsrvd5[0],
 299                IRONGATE0->rsrvd5[1],
 300                IRONGATE0->rsrvd5[2],
 301                IRONGATE0->whami,
 302                IRONGATE0->pciarb,
 303                IRONGATE0->pcicfg,
 304                IRONGATE0->rsrvd6[0],
 305                IRONGATE0->rsrvd6[1],
 306                IRONGATE0->rsrvd6[2],
 307                IRONGATE0->rsrvd6[3],
 308                IRONGATE0->rsrvd6[4],
 309                IRONGATE0->agpcap,
 310                IRONGATE0->agpstat,
 311                IRONGATE0->agpcmd,
 312                IRONGATE0->agpva,
 313                IRONGATE0->agpmode,
 314                IRONGATE1->dev_vendor,
 315                IRONGATE1->stat_cmd,
 316                IRONGATE1->class,
 317                IRONGATE1->htype,
 318                IRONGATE1->rsrvd0[0],
 319                IRONGATE1->rsrvd0[1],
 320                IRONGATE1->busnos,
 321                IRONGATE1->io_baselim_regs,
 322                IRONGATE1->mem_baselim,
 323                IRONGATE1->pfmem_baselim,
 324                IRONGATE1->rsrvd1[0],
 325                IRONGATE1->rsrvd1[1],
 326                IRONGATE1->io_baselim,
 327                IRONGATE1->rsrvd2[0],
 328                IRONGATE1->rsrvd2[1],
 329                IRONGATE1->interrupt );
 330 }
 331 #else
 332 #define irongate_register_dump(x)
 333 #endif
 334
 335 int
 336 irongate_pci_clr_err(void)
 337 {
 338         unsigned int nmi_ctl=0;
 339         unsigned int IRONGATE_jd;
 340
 341 again:
 342         IRONGATE_jd = IRONGATE0->stat_cmd;
 343         printk("Iron stat_cmd %x\n", IRONGATE_jd);
 344         IRONGATE0->stat_cmd = IRONGATE_jd; /* write again clears error bits */
 345         mb();
 346         IRONGATE_jd = IRONGATE0->stat_cmd;  /* re-read to force write */
 347
 348         IRONGATE_jd = IRONGATE0->dramms;
 349         printk("Iron dramms %x\n", IRONGATE_jd);
 350         IRONGATE0->dramms = IRONGATE_jd; /* write again clears error bits */
 351         mb();
 352         IRONGATE_jd = IRONGATE0->dramms;  /* re-read to force write */
 353
 354         /* Clear ALI NMI */
 355         nmi_ctl = inb(0x61);
 356         nmi_ctl |= 0x0c;
 357         outb(nmi_ctl, 0x61);
 358         nmi_ctl &= ~0x0c;
 359         outb(nmi_ctl, 0x61);
 360
 361         IRONGATE_jd = IRONGATE0->dramms;
 362         if (IRONGATE_jd & 0x300) goto again;
 363
 364         return 0;
 365 }
 366
 367 void __init
 368 irongate_init_arch(void)
 369 {
 370         struct pci_controler *hose;
 371
 372         IRONGATE0->stat_cmd = IRONGATE0->stat_cmd & ~0x100;
 373         irongate_pci_clr_err();
 374         irongate_register_dump(__FUNCTION__);
 375
 376         /*
 377          * Create our single hose.
 378          */
 379
 380         pci_isa_hose = hose = alloc_pci_controler();
 381         hose->io_space = &ioport_resource;
 382         hose->mem_space = &iomem_resource;
 383         hose->index = 0;
 384
 385         /* This is for userland consumption.  For some reason, the 40-bit
 386            PIO bias that we use in the kernel through KSEG didn't work for
 387            the page table based user mappings.  So make sure we get the
 388            43-bit PIO bias.  */
 389         hose->sparse_mem_base = 0;
 390         hose->sparse_io_base = 0;
 391         hose->dense_mem_base
 392           = (IRONGATE_MEM & 0xffffffffff) | 0x80000000000;
 393         hose->dense_io_base
 394           = (IRONGATE_IO & 0xffffffffff) | 0x80000000000;
 395
 396         hose->sg_isa = hose->sg_pci = NULL;
 397         __direct_map_base = 0;
 398         __direct_map_size = 0xffffffff;
 399 }