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[davej-history.git] / drivers / net / defxx.h
blob10e159c922521194efb915a56ce678a4481efc75
1 /*
2 * File Name:
3 * defxx.h
4 *
5 * Copyright Information:
6 * Copyright Digital Equipment Corporation 1996.
7 *
8 * This software may be used and distributed according to the terms of
9 * the GNU Public License, incorporated herein by reference.
10 *
11 * Abstract:
12 * Contains all definitions specified by port specification and required
13 * by the defxx.c driver.
14 *
15 * Maintainers:
16 * LVS Lawrence V. Stefani
17 *
18 * Contact:
19 * The author may be reached at:
20 *
21 * Inet: stefani@lkg.dec.com
22 * Mail: Digital Equipment Corporation
23 * 550 King Street
24 * M/S: LKG1-3/M07
25 * Littleton, MA 01460
26 *
27 * Modification History:
28 * Date Name Description
29 * 16-Aug-96 LVS Created.
30 * 09-Sep-96 LVS Added group_prom field. Moved read/write I/O
31 * macros to DEFXX.C.
32 * 12-Sep-96 LVS Removed packet request header pointers.
33 */
34
35 #ifndef _DEFXX_H_
36 #define _DEFXX_H_
37
38 /* Define basic types for unsigned chars, shorts, longs */
39
40 typedef u8 PI_UINT8;
41 typedef u16 PI_UINT16;
42 typedef u32 PI_UINT32;
43
44 /* Define general structures */
45
46 typedef struct /* 64-bit counter */
47 {
48 PI_UINT32 ms;
49 PI_UINT32 ls;
50 } PI_CNTR;
51
52 typedef struct /* LAN address */
53 {
54 PI_UINT32 lwrd_0;
55 PI_UINT32 lwrd_1;
56 } PI_LAN_ADDR;
57
58 typedef struct /* Station ID address */
59 {
60 PI_UINT32 octet_7_4;
61 PI_UINT32 octet_3_0;
62 } PI_STATION_ID;
63
64
65 /* Define general constants */
66
67 #define PI_ALIGN_K_DESC_BLK 8192 /* Descriptor block boundary */
68 #define PI_ALIGN_K_CONS_BLK 64 /* Consumer block boundary */
69 #define PI_ALIGN_K_CMD_REQ_BUFF 128 /* Xmt Command que buffer alignment */
70 #define PI_ALIGN_K_CMD_RSP_BUFF 128 /* Rcv Command que buffer alignment */
71 #define PI_ALIGN_K_UNSOL_BUFF 128 /* Unsol que buffer alignment */
72 #define PI_ALIGN_K_XMT_DATA_BUFF 0 /* Xmt data que buffer alignment */
73 #define PI_ALIGN_K_RCV_DATA_BUFF 128 /* Rcv que buffer alignment */
74
75 /* Define PHY index values */
76
77 #define PI_PHY_K_S 0 /* Index to S phy */
78 #define PI_PHY_K_A 0 /* Index to A phy */
79 #define PI_PHY_K_B 1 /* Index to B phy */
80 #define PI_PHY_K_MAX 2 /* Max number of phys */
81
82 /* Define FMC descriptor fields */
83
84 #define PI_FMC_DESCR_V_SOP 31
85 #define PI_FMC_DESCR_V_EOP 30
86 #define PI_FMC_DESCR_V_FSC 27
87 #define PI_FMC_DESCR_V_FSB_ERROR 26
88 #define PI_FMC_DESCR_V_FSB_ADDR_RECOG 25
89 #define PI_FMC_DESCR_V_FSB_ADDR_COPIED 24
90 #define PI_FMC_DESCR_V_FSB 22
91 #define PI_FMC_DESCR_V_RCC_FLUSH 21
92 #define PI_FMC_DESCR_V_RCC_CRC 20
93 #define PI_FMC_DESCR_V_RCC_RRR 17
94 #define PI_FMC_DESCR_V_RCC_DD 15
95 #define PI_FMC_DESCR_V_RCC_SS 13
96 #define PI_FMC_DESCR_V_RCC 13
97 #define PI_FMC_DESCR_V_LEN 0
98
99 #define PI_FMC_DESCR_M_SOP 0x80000000
100 #define PI_FMC_DESCR_M_EOP 0x40000000
101 #define PI_FMC_DESCR_M_FSC 0x38000000
102 #define PI_FMC_DESCR_M_FSB_ERROR 0x04000000
103 #define PI_FMC_DESCR_M_FSB_ADDR_RECOG 0x02000000
104 #define PI_FMC_DESCR_M_FSB_ADDR_COPIED 0x01000000
105 #define PI_FMC_DESCR_M_FSB 0x07C00000
106 #define PI_FMC_DESCR_M_RCC_FLUSH 0x00200000
107 #define PI_FMC_DESCR_M_RCC_CRC 0x00100000
108 #define PI_FMC_DESCR_M_RCC_RRR 0x000E0000
109 #define PI_FMC_DESCR_M_RCC_DD 0x00018000
110 #define PI_FMC_DESCR_M_RCC_SS 0x00006000
111 #define PI_FMC_DESCR_M_RCC 0x003FE000
112 #define PI_FMC_DESCR_M_LEN 0x00001FFF
113
114 #define PI_FMC_DESCR_K_RCC_FMC_INT_ERR 0x01AA
115
116 #define PI_FMC_DESCR_K_RRR_SUCCESS 0x00
117 #define PI_FMC_DESCR_K_RRR_SA_MATCH 0x01
118 #define PI_FMC_DESCR_K_RRR_DA_MATCH 0x02
119 #define PI_FMC_DESCR_K_RRR_FMC_ABORT 0x03
120 #define PI_FMC_DESCR_K_RRR_LENGTH_BAD 0x04
121 #define PI_FMC_DESCR_K_RRR_FRAGMENT 0x05
122 #define PI_FMC_DESCR_K_RRR_FORMAT_ERR 0x06
123 #define PI_FMC_DESCR_K_RRR_MAC_RESET 0x07
124
125 #define PI_FMC_DESCR_K_DD_NO_MATCH 0x0
126 #define PI_FMC_DESCR_K_DD_PROMISCUOUS 0x1
127 #define PI_FMC_DESCR_K_DD_CAM_MATCH 0x2
128 #define PI_FMC_DESCR_K_DD_LOCAL_MATCH 0x3
129
130 #define PI_FMC_DESCR_K_SS_NO_MATCH 0x0
131 #define PI_FMC_DESCR_K_SS_BRIDGE_MATCH 0x1
132 #define PI_FMC_DESCR_K_SS_NOT_POSSIBLE 0x2
133 #define PI_FMC_DESCR_K_SS_LOCAL_MATCH 0x3
134
135 /* Define some max buffer sizes */
136
137 #define PI_CMD_REQ_K_SIZE_MAX 512
138 #define PI_CMD_RSP_K_SIZE_MAX 512
139 #define PI_UNSOL_K_SIZE_MAX 512
140 #define PI_SMT_HOST_K_SIZE_MAX 4608 /* 4 1/2 K */
141 #define PI_RCV_DATA_K_SIZE_MAX 4608 /* 4 1/2 K */
142 #define PI_XMT_DATA_K_SIZE_MAX 4608 /* 4 1/2 K */
143
144 /* Define adapter states */
145
146 #define PI_STATE_K_RESET 0
147 #define PI_STATE_K_UPGRADE 1
148 #define PI_STATE_K_DMA_UNAVAIL 2
149 #define PI_STATE_K_DMA_AVAIL 3
150 #define PI_STATE_K_LINK_AVAIL 4
151 #define PI_STATE_K_LINK_UNAVAIL 5
152 #define PI_STATE_K_HALTED 6
153 #define PI_STATE_K_RING_MEMBER 7
154 #define PI_STATE_K_NUMBER 8
155
156 /* Define codes for command type */
157
158 #define PI_CMD_K_START 0x00
159 #define PI_CMD_K_FILTERS_SET 0x01
160 #define PI_CMD_K_FILTERS_GET 0x02
161 #define PI_CMD_K_CHARS_SET 0x03
162 #define PI_CMD_K_STATUS_CHARS_GET 0x04
163 #define PI_CMD_K_CNTRS_GET 0x05
164 #define PI_CMD_K_CNTRS_SET 0x06
165 #define PI_CMD_K_ADDR_FILTER_SET 0x07
166 #define PI_CMD_K_ADDR_FILTER_GET 0x08
167 #define PI_CMD_K_ERROR_LOG_CLEAR 0x09
168 #define PI_CMD_K_ERROR_LOG_GET 0x0A
169 #define PI_CMD_K_FDDI_MIB_GET 0x0B
170 #define PI_CMD_K_DEC_EXT_MIB_GET 0x0C
171 #define PI_CMD_K_DEVICE_SPECIFIC_GET 0x0D
172 #define PI_CMD_K_SNMP_SET 0x0E
173 #define PI_CMD_K_UNSOL_TEST 0x0F
174 #define PI_CMD_K_SMT_MIB_GET 0x10
175 #define PI_CMD_K_SMT_MIB_SET 0x11
176 #define PI_CMD_K_MAX 0x11 /* Must match last */
177
178 /* Define item codes for Chars_Set and Filters_Set commands */
179
180 #define PI_ITEM_K_EOL 0x00 /* End-of-Item list */
181 #define PI_ITEM_K_T_REQ 0x01 /* DECnet T_REQ */
182 #define PI_ITEM_K_TVX 0x02 /* DECnet TVX */
183 #define PI_ITEM_K_RESTRICTED_TOKEN 0x03 /* DECnet Restricted Token */
184 #define PI_ITEM_K_LEM_THRESHOLD 0x04 /* DECnet LEM Threshold */
185 #define PI_ITEM_K_RING_PURGER 0x05 /* DECnet Ring Purger Enable */
186 #define PI_ITEM_K_CNTR_INTERVAL 0x06 /* Chars_Set */
187 #define PI_ITEM_K_IND_GROUP_PROM 0x07 /* Filters_Set */
188 #define PI_ITEM_K_GROUP_PROM 0x08 /* Filters_Set */
189 #define PI_ITEM_K_BROADCAST 0x09 /* Filters_Set */
190 #define PI_ITEM_K_SMT_PROM 0x0A /* Filters_Set */
191 #define PI_ITEM_K_SMT_USER 0x0B /* Filters_Set */
192 #define PI_ITEM_K_RESERVED 0x0C /* Filters_Set */
193 #define PI_ITEM_K_IMPLEMENTOR 0x0D /* Filters_Set */
194 #define PI_ITEM_K_LOOPBACK_MODE 0x0E /* Chars_Set */
195 #define PI_ITEM_K_CONFIG_POLICY 0x10 /* SMTConfigPolicy */
196 #define PI_ITEM_K_CON_POLICY 0x11 /* SMTConnectionPolicy */
197 #define PI_ITEM_K_T_NOTIFY 0x12 /* SMTTNotify */
198 #define PI_ITEM_K_STATION_ACTION 0x13 /* SMTStationAction */
199 #define PI_ITEM_K_MAC_PATHS_REQ 0x15 /* MACPathsRequested */
200 #define PI_ITEM_K_MAC_ACTION 0x17 /* MACAction */
201 #define PI_ITEM_K_CON_POLICIES 0x18 /* PORTConnectionPolicies */
202 #define PI_ITEM_K_PORT_PATHS_REQ 0x19 /* PORTPathsRequested */
203 #define PI_ITEM_K_MAC_LOOP_TIME 0x1A /* PORTMACLoopTime */
204 #define PI_ITEM_K_TB_MAX 0x1B /* PORTTBMax */
205 #define PI_ITEM_K_LER_CUTOFF 0x1C /* PORTLerCutoff */
206 #define PI_ITEM_K_LER_ALARM 0x1D /* PORTLerAlarm */
207 #define PI_ITEM_K_PORT_ACTION 0x1E /* PORTAction */
208 #define PI_ITEM_K_FLUSH_TIME 0x20 /* Chars_Set */
209 #define PI_ITEM_K_MAC_T_REQ 0x29 /* MACTReq */
210 #define PI_ITEM_K_EMAC_RING_PURGER 0x2A /* eMACRingPurgerEnable */
211 #define PI_ITEM_K_EMAC_RTOKEN_TIMEOUT 0x2B /* eMACRestrictedTokenTimeout */
212 #define PI_ITEM_K_FDX_ENB_DIS 0x2C /* eFDXEnable */
213 #define PI_ITEM_K_MAX 0x2C /* Must equal high item */
214
215 /* Values for some of the items */
216
217 #define PI_K_FALSE 0 /* Generic false */
218 #define PI_K_TRUE 1 /* Generic true */
219
220 #define PI_SNMP_K_TRUE 1 /* SNMP true/false values */
221 #define PI_SNMP_K_FALSE 2
222
223 #define PI_FSTATE_K_BLOCK 0 /* Filter State */
224 #define PI_FSTATE_K_PASS 1
225
226 /* Define command return codes */
227
228 #define PI_RSP_K_SUCCESS 0x00
229 #define PI_RSP_K_FAILURE 0x01
230 #define PI_RSP_K_WARNING 0x02
231 #define PI_RSP_K_LOOP_MODE_BAD 0x03
232 #define PI_RSP_K_ITEM_CODE_BAD 0x04
233 #define PI_RSP_K_TVX_BAD 0x05
234 #define PI_RSP_K_TREQ_BAD 0x06
235 #define PI_RSP_K_TOKEN_BAD 0x07
236 #define PI_RSP_K_NO_EOL 0x0C
237 #define PI_RSP_K_FILTER_STATE_BAD 0x0D
238 #define PI_RSP_K_CMD_TYPE_BAD 0x0E
239 #define PI_RSP_K_ADAPTER_STATE_BAD 0x0F
240 #define PI_RSP_K_RING_PURGER_BAD 0x10
241 #define PI_RSP_K_LEM_THRESHOLD_BAD 0x11
242 #define PI_RSP_K_LOOP_NOT_SUPPORTED 0x12
243 #define PI_RSP_K_FLUSH_TIME_BAD 0x13
244 #define PI_RSP_K_NOT_IMPLEMENTED 0x14
245 #define PI_RSP_K_CONFIG_POLICY_BAD 0x15
246 #define PI_RSP_K_STATION_ACTION_BAD 0x16
247 #define PI_RSP_K_MAC_ACTION_BAD 0x17
248 #define PI_RSP_K_CON_POLICIES_BAD 0x18
249 #define PI_RSP_K_MAC_LOOP_TIME_BAD 0x19
250 #define PI_RSP_K_TB_MAX_BAD 0x1A
251 #define PI_RSP_K_LER_CUTOFF_BAD 0x1B
252 #define PI_RSP_K_LER_ALARM_BAD 0x1C
253 #define PI_RSP_K_MAC_PATHS_REQ_BAD 0x1D
254 #define PI_RSP_K_MAC_T_REQ_BAD 0x1E
255 #define PI_RSP_K_EMAC_RING_PURGER_BAD 0x1F
256 #define PI_RSP_K_EMAC_RTOKEN_TIME_BAD 0x20
257 #define PI_RSP_K_NO_SUCH_ENTRY 0x21
258 #define PI_RSP_K_T_NOTIFY_BAD 0x22
259 #define PI_RSP_K_TR_MAX_EXP_BAD 0x23
260 #define PI_RSP_K_MAC_FRM_ERR_THR_BAD 0x24
261 #define PI_RSP_K_MAX_T_REQ_BAD 0x25
262 #define PI_RSP_K_FDX_ENB_DIS_BAD 0x26
263 #define PI_RSP_K_ITEM_INDEX_BAD 0x27
264 #define PI_RSP_K_PORT_ACTION_BAD 0x28
265
266 /* Commonly used structures */
267
268 typedef struct /* Item list */
269 {
270 PI_UINT32 item_code;
271 PI_UINT32 value;
272 } PI_ITEM_LIST;
273
274 typedef struct /* Response header */
275 {
276 PI_UINT32 reserved;
277 PI_UINT32 cmd_type;
278 PI_UINT32 status;
279 } PI_RSP_HEADER;
280
281
282 /* Start Command */
283
284 typedef struct
285 {
286 PI_UINT32 cmd_type;
287 } PI_CMD_START_REQ;
288
289 /* Start Response */
290
291 typedef struct
292 {
293 PI_RSP_HEADER header;
294 } PI_CMD_START_RSP;
295
296 /* Filters_Set Request */
297
298 #define PI_CMD_FILTERS_SET_K_ITEMS_MAX 63 /* Fits in a 512 byte buffer */
299
300 typedef struct
301 {
302 PI_UINT32 cmd_type;
303 PI_ITEM_LIST item[PI_CMD_FILTERS_SET_K_ITEMS_MAX];
304 } PI_CMD_FILTERS_SET_REQ;
305
306 /* Filters_Set Response */
307
308 typedef struct
309 {
310 PI_RSP_HEADER header;
311 } PI_CMD_FILTERS_SET_RSP;
312
313 /* Filters_Get Request */
314
315 typedef struct
316 {
317 PI_UINT32 cmd_type;
318 } PI_CMD_FILTERS_GET_REQ;
319
320 /* Filters_Get Response */
321
322 typedef struct
323 {
324 PI_RSP_HEADER header;
325 PI_UINT32 ind_group_prom;
326 PI_UINT32 group_prom;
327 PI_UINT32 broadcast_all;
328 PI_UINT32 smt_all;
329 PI_UINT32 smt_user;
330 PI_UINT32 reserved_all;
331 PI_UINT32 implementor_all;
332 } PI_CMD_FILTERS_GET_RSP;
333
334
335 /* Chars_Set Request */
336
337 #define PI_CMD_CHARS_SET_K_ITEMS_MAX 42 /* Fits in a 512 byte buffer */
338
339 typedef struct
340 {
341 PI_UINT32 cmd_type;
342 struct /* Item list */
343 {
344 PI_UINT32 item_code;
345 PI_UINT32 value;
346 PI_UINT32 item_index;
347 } item[PI_CMD_CHARS_SET_K_ITEMS_MAX];
348 } PI_CMD_CHARS_SET_REQ;
349
350 /* Chars_Set Response */
351
352 typedef struct
353 {
354 PI_RSP_HEADER header;
355 } PI_CMD_CHARS_SET_RSP;
356
357
358 /* SNMP_Set Request */
359
360 #define PI_CMD_SNMP_SET_K_ITEMS_MAX 42 /* Fits in a 512 byte buffer */
361
362 typedef struct
363 {
364 PI_UINT32 cmd_type;
365 struct /* Item list */
366 {
367 PI_UINT32 item_code;
368 PI_UINT32 value;
369 PI_UINT32 item_index;
370 } item[PI_CMD_SNMP_SET_K_ITEMS_MAX];
371 } PI_CMD_SNMP_SET_REQ;
372
373 /* SNMP_Set Response */
374
375 typedef struct
376 {
377 PI_RSP_HEADER header;
378 } PI_CMD_SNMP_SET_RSP;
379
380
381 /* SMT_MIB_Set Request */
382
383 #define PI_CMD_SMT_MIB_SET_K_ITEMS_MAX 42 /* Max number of items */
384
385 typedef struct
386 {
387 PI_UINT32 cmd_type;
388 struct
389 {
390 PI_UINT32 item_code;
391 PI_UINT32 value;
392 PI_UINT32 item_index;
393 } item[PI_CMD_SMT_MIB_SET_K_ITEMS_MAX];
394 } PI_CMD_SMT_MIB_SET_REQ;
395
396 /* SMT_MIB_Set Response */
397
398 typedef struct
399 {
400 PI_RSP_HEADER header;
401 } PI_CMD_SMT_MIB_SET_RSP;
402
403 /* SMT_MIB_Get Request */
404
405 typedef struct
406 {
407 PI_UINT32 cmd_type;
408 } PI_CMD_SMT_MIB_GET_REQ;
409
410 /* SMT_MIB_Get Response */
411
412 typedef struct /* Refer to ANSI FDDI SMT Rev. 7.3 */
413 {
414 PI_RSP_HEADER header;
415
416 /* SMT GROUP */
417
418 PI_STATION_ID smt_station_id;
419 PI_UINT32 smt_op_version_id;
420 PI_UINT32 smt_hi_version_id;
421 PI_UINT32 smt_lo_version_id;
422 PI_UINT32 smt_user_data[8];
423 PI_UINT32 smt_mib_version_id;
424 PI_UINT32 smt_mac_ct;
425 PI_UINT32 smt_non_master_ct;
426 PI_UINT32 smt_master_ct;
427 PI_UINT32 smt_available_paths;
428 PI_UINT32 smt_config_capabilities;
429 PI_UINT32 smt_config_policy;
430 PI_UINT32 smt_connection_policy;
431 PI_UINT32 smt_t_notify;
432 PI_UINT32 smt_stat_rpt_policy;
433 PI_UINT32 smt_trace_max_expiration;
434 PI_UINT32 smt_bypass_present;
435 PI_UINT32 smt_ecm_state;
436 PI_UINT32 smt_cf_state;
437 PI_UINT32 smt_remote_disconnect_flag;
438 PI_UINT32 smt_station_status;
439 PI_UINT32 smt_peer_wrap_flag;
440 PI_CNTR smt_msg_time_stamp;
441 PI_CNTR smt_transition_time_stamp;
442
443 /* MAC GROUP */
444
445 PI_UINT32 mac_frame_status_functions;
446 PI_UINT32 mac_t_max_capability;
447 PI_UINT32 mac_tvx_capability;
448 PI_UINT32 mac_available_paths;
449 PI_UINT32 mac_current_path;
450 PI_LAN_ADDR mac_upstream_nbr;
451 PI_LAN_ADDR mac_downstream_nbr;
452 PI_LAN_ADDR mac_old_upstream_nbr;
453 PI_LAN_ADDR mac_old_downstream_nbr;
454 PI_UINT32 mac_dup_address_test;
455 PI_UINT32 mac_requested_paths;
456 PI_UINT32 mac_downstream_port_type;
457 PI_LAN_ADDR mac_smt_address;
458 PI_UINT32 mac_t_req;
459 PI_UINT32 mac_t_neg;
460 PI_UINT32 mac_t_max;
461 PI_UINT32 mac_tvx_value;
462 PI_UINT32 mac_frame_error_threshold;
463 PI_UINT32 mac_frame_error_ratio;
464 PI_UINT32 mac_rmt_state;
465 PI_UINT32 mac_da_flag;
466 PI_UINT32 mac_unda_flag;
467 PI_UINT32 mac_frame_error_flag;
468 PI_UINT32 mac_ma_unitdata_available;
469 PI_UINT32 mac_hardware_present;
470 PI_UINT32 mac_ma_unitdata_enable;
471
472 /* PATH GROUP */
473
474 PI_UINT32 path_configuration[8];
475 PI_UINT32 path_tvx_lower_bound;
476 PI_UINT32 path_t_max_lower_bound;
477 PI_UINT32 path_max_t_req;
478
479 /* PORT GROUP */
480
481 PI_UINT32 port_my_type[PI_PHY_K_MAX];
482 PI_UINT32 port_neighbor_type[PI_PHY_K_MAX];
483 PI_UINT32 port_connection_policies[PI_PHY_K_MAX];
484 PI_UINT32 port_mac_indicated[PI_PHY_K_MAX];
485 PI_UINT32 port_current_path[PI_PHY_K_MAX];
486 PI_UINT32 port_requested_paths[PI_PHY_K_MAX];
487 PI_UINT32 port_mac_placement[PI_PHY_K_MAX];
488 PI_UINT32 port_available_paths[PI_PHY_K_MAX];
489 PI_UINT32 port_pmd_class[PI_PHY_K_MAX];
490 PI_UINT32 port_connection_capabilities[PI_PHY_K_MAX];
491 PI_UINT32 port_bs_flag[PI_PHY_K_MAX];
492 PI_UINT32 port_ler_estimate[PI_PHY_K_MAX];
493 PI_UINT32 port_ler_cutoff[PI_PHY_K_MAX];
494 PI_UINT32 port_ler_alarm[PI_PHY_K_MAX];
495 PI_UINT32 port_connect_state[PI_PHY_K_MAX];
496 PI_UINT32 port_pcm_state[PI_PHY_K_MAX];
497 PI_UINT32 port_pc_withhold[PI_PHY_K_MAX];
498 PI_UINT32 port_ler_flag[PI_PHY_K_MAX];
499 PI_UINT32 port_hardware_present[PI_PHY_K_MAX];
500
501 /* GROUP for things that were added later, so must be at the end. */
502
503 PI_CNTR path_ring_latency;
504
505 } PI_CMD_SMT_MIB_GET_RSP;
506
507
508 /*
509 * Item and group code definitions for SMT 7.3 mandatory objects. These
510 * definitions are to be used as appropriate in SMT_MIB_SET commands and
511 * certain host-sent SMT frames such as PMF Get and Set requests. The
512 * codes have been taken from the MIB summary section of ANSI SMT 7.3.
513 */
514
515 #define PI_GRP_K_SMT_STATION_ID 0x100A
516 #define PI_ITEM_K_SMT_STATION_ID 0x100B
517 #define PI_ITEM_K_SMT_OP_VERS_ID 0x100D
518 #define PI_ITEM_K_SMT_HI_VERS_ID 0x100E
519 #define PI_ITEM_K_SMT_LO_VERS_ID 0x100F
520 #define PI_ITEM_K_SMT_USER_DATA 0x1011
521 #define PI_ITEM_K_SMT_MIB_VERS_ID 0x1012
522
523 #define PI_GRP_K_SMT_STATION_CONFIG 0x1014
524 #define PI_ITEM_K_SMT_MAC_CT 0x1015
525 #define PI_ITEM_K_SMT_NON_MASTER_CT 0x1016
526 #define PI_ITEM_K_SMT_MASTER_CT 0x1017
527 #define PI_ITEM_K_SMT_AVAIL_PATHS 0x1018
528 #define PI_ITEM_K_SMT_CONFIG_CAPS 0x1019
529 #define PI_ITEM_K_SMT_CONFIG_POL 0x101A
530 #define PI_ITEM_K_SMT_CONN_POL 0x101B
531 #define PI_ITEM_K_SMT_T_NOTIFY 0x101D
532 #define PI_ITEM_K_SMT_STAT_POL 0x101E
533 #define PI_ITEM_K_SMT_TR_MAX_EXP 0x101F
534 #define PI_ITEM_K_SMT_PORT_INDEXES 0x1020
535 #define PI_ITEM_K_SMT_MAC_INDEXES 0x1021
536 #define PI_ITEM_K_SMT_BYPASS_PRESENT 0x1022
537
538 #define PI_GRP_K_SMT_STATUS 0x1028
539 #define PI_ITEM_K_SMT_ECM_STATE 0x1029
540 #define PI_ITEM_K_SMT_CF_STATE 0x102A
541 #define PI_ITEM_K_SMT_REM_DISC_FLAG 0x102C
542 #define PI_ITEM_K_SMT_STATION_STATUS 0x102D
543 #define PI_ITEM_K_SMT_PEER_WRAP_FLAG 0x102E
544
545 #define PI_GRP_K_SMT_MIB_OPERATION 0x1032
546 #define PI_ITEM_K_SMT_MSG_TIME_STAMP 0x1033
547 #define PI_ITEM_K_SMT_TRN_TIME_STAMP 0x1034
548
549 #define PI_ITEM_K_SMT_STATION_ACT 0x103C
550
551 #define PI_GRP_K_MAC_CAPABILITIES 0x200A
552 #define PI_ITEM_K_MAC_FRM_STAT_FUNC 0x200B
553 #define PI_ITEM_K_MAC_T_MAX_CAP 0x200D
554 #define PI_ITEM_K_MAC_TVX_CAP 0x200E
555
556 #define PI_GRP_K_MAC_CONFIG 0x2014
557 #define PI_ITEM_K_MAC_AVAIL_PATHS 0x2016
558 #define PI_ITEM_K_MAC_CURRENT_PATH 0x2017
559 #define PI_ITEM_K_MAC_UP_NBR 0x2018
560 #define PI_ITEM_K_MAC_DOWN_NBR 0x2019
561 #define PI_ITEM_K_MAC_OLD_UP_NBR 0x201A
562 #define PI_ITEM_K_MAC_OLD_DOWN_NBR 0x201B
563 #define PI_ITEM_K_MAC_DUP_ADDR_TEST 0x201D
564 #define PI_ITEM_K_MAC_REQ_PATHS 0x2020
565 #define PI_ITEM_K_MAC_DOWN_PORT_TYPE 0x2021
566 #define PI_ITEM_K_MAC_INDEX 0x2022
567
568 #define PI_GRP_K_MAC_ADDRESS 0x2028
569 #define PI_ITEM_K_MAC_SMT_ADDRESS 0x2029
570
571 #define PI_GRP_K_MAC_OPERATION 0x2032
572 #define PI_ITEM_K_MAC_TREQ 0x2033
573 #define PI_ITEM_K_MAC_TNEG 0x2034
574 #define PI_ITEM_K_MAC_TMAX 0x2035
575 #define PI_ITEM_K_MAC_TVX_VALUE 0x2036
576
577 #define PI_GRP_K_MAC_COUNTERS 0x2046
578 #define PI_ITEM_K_MAC_FRAME_CT 0x2047
579 #define PI_ITEM_K_MAC_COPIED_CT 0x2048
580 #define PI_ITEM_K_MAC_TRANSMIT_CT 0x2049
581 #define PI_ITEM_K_MAC_ERROR_CT 0x2051
582 #define PI_ITEM_K_MAC_LOST_CT 0x2052
583
584 #define PI_GRP_K_MAC_FRM_ERR_COND 0x205A
585 #define PI_ITEM_K_MAC_FRM_ERR_THR 0x205F
586 #define PI_ITEM_K_MAC_FRM_ERR_RAT 0x2060
587
588 #define PI_GRP_K_MAC_STATUS 0x206E
589 #define PI_ITEM_K_MAC_RMT_STATE 0x206F
590 #define PI_ITEM_K_MAC_DA_FLAG 0x2070
591 #define PI_ITEM_K_MAC_UNDA_FLAG 0x2071
592 #define PI_ITEM_K_MAC_FRM_ERR_FLAG 0x2072
593 #define PI_ITEM_K_MAC_MA_UNIT_AVAIL 0x2074
594 #define PI_ITEM_K_MAC_HW_PRESENT 0x2075
595 #define PI_ITEM_K_MAC_MA_UNIT_ENAB 0x2076
596
597 #define PI_GRP_K_PATH_CONFIG 0x320A
598 #define PI_ITEM_K_PATH_INDEX 0x320B
599 #define PI_ITEM_K_PATH_CONFIGURATION 0x3212
600 #define PI_ITEM_K_PATH_TVX_LB 0x3215
601 #define PI_ITEM_K_PATH_T_MAX_LB 0x3216
602 #define PI_ITEM_K_PATH_MAX_T_REQ 0x3217
603
604 #define PI_GRP_K_PORT_CONFIG 0x400A
605 #define PI_ITEM_K_PORT_MY_TYPE 0x400C
606 #define PI_ITEM_K_PORT_NBR_TYPE 0x400D
607 #define PI_ITEM_K_PORT_CONN_POLS 0x400E
608 #define PI_ITEM_K_PORT_MAC_INDICATED 0x400F
609 #define PI_ITEM_K_PORT_CURRENT_PATH 0x4010
610 #define PI_ITEM_K_PORT_REQ_PATHS 0x4011
611 #define PI_ITEM_K_PORT_MAC_PLACEMENT 0x4012
612 #define PI_ITEM_K_PORT_AVAIL_PATHS 0x4013
613 #define PI_ITEM_K_PORT_PMD_CLASS 0x4016
614 #define PI_ITEM_K_PORT_CONN_CAPS 0x4017
615 #define PI_ITEM_K_PORT_INDEX 0x401D
616
617 #define PI_GRP_K_PORT_OPERATION 0x401E
618 #define PI_ITEM_K_PORT_BS_FLAG 0x4021
619
620 #define PI_GRP_K_PORT_ERR_CNTRS 0x4028
621 #define PI_ITEM_K_PORT_LCT_FAIL_CT 0x402A
622
623 #define PI_GRP_K_PORT_LER 0x4032
624 #define PI_ITEM_K_PORT_LER_ESTIMATE 0x4033
625 #define PI_ITEM_K_PORT_LEM_REJ_CT 0x4034
626 #define PI_ITEM_K_PORT_LEM_CT 0x4035
627 #define PI_ITEM_K_PORT_LER_CUTOFF 0x403A
628 #define PI_ITEM_K_PORT_LER_ALARM 0x403B
629
630 #define PI_GRP_K_PORT_STATUS 0x403C
631 #define PI_ITEM_K_PORT_CONNECT_STATE 0x403D
632 #define PI_ITEM_K_PORT_PCM_STATE 0x403E
633 #define PI_ITEM_K_PORT_PC_WITHHOLD 0x403F
634 #define PI_ITEM_K_PORT_LER_FLAG 0x4040
635 #define PI_ITEM_K_PORT_HW_PRESENT 0x4041
636
637 #define PI_ITEM_K_PORT_ACT 0x4046
638
639 /* Addr_Filter_Set Request */
640
641 #define PI_CMD_ADDR_FILTER_K_SIZE 62
642
643 typedef struct
644 {
645 PI_UINT32 cmd_type;
646 PI_LAN_ADDR entry[PI_CMD_ADDR_FILTER_K_SIZE];
647 } PI_CMD_ADDR_FILTER_SET_REQ;
648
649 /* Addr_Filter_Set Response */
650
651 typedef struct
652 {
653 PI_RSP_HEADER header;
654 } PI_CMD_ADDR_FILTER_SET_RSP;
655
656 /* Addr_Filter_Get Request */
657
658 typedef struct
659 {
660 PI_UINT32 cmd_type;
661 } PI_CMD_ADDR_FILTER_GET_REQ;
662
663 /* Addr_Filter_Get Response */
664
665 typedef struct
666 {
667 PI_RSP_HEADER header;
668 PI_LAN_ADDR entry[PI_CMD_ADDR_FILTER_K_SIZE];
669 } PI_CMD_ADDR_FILTER_GET_RSP;
670
671 /* Status_Chars_Get Request */
672
673 typedef struct
674 {
675 PI_UINT32 cmd_type;
676 } PI_CMD_STATUS_CHARS_GET_REQ;
677
678 /* Status_Chars_Get Response */
679
680 typedef struct
681 {
682 PI_RSP_HEADER header;
683 PI_STATION_ID station_id; /* Station */
684 PI_UINT32 station_type;
685 PI_UINT32 smt_ver_id;
686 PI_UINT32 smt_ver_id_max;
687 PI_UINT32 smt_ver_id_min;
688 PI_UINT32 station_state;
689 PI_LAN_ADDR link_addr; /* Link */
690 PI_UINT32 t_req;
691 PI_UINT32 tvx;
692 PI_UINT32 token_timeout;
693 PI_UINT32 purger_enb;
694 PI_UINT32 link_state;
695 PI_UINT32 tneg;
696 PI_UINT32 dup_addr_flag;
697 PI_LAN_ADDR una;
698 PI_LAN_ADDR una_old;
699 PI_UINT32 un_dup_addr_flag;
700 PI_LAN_ADDR dna;
701 PI_LAN_ADDR dna_old;
702 PI_UINT32 purger_state;
703 PI_UINT32 fci_mode;
704 PI_UINT32 error_reason;
705 PI_UINT32 loopback;
706 PI_UINT32 ring_latency;
707 PI_LAN_ADDR last_dir_beacon_sa;
708 PI_LAN_ADDR last_dir_beacon_una;
709 PI_UINT32 phy_type[PI_PHY_K_MAX]; /* Phy */
710 PI_UINT32 pmd_type[PI_PHY_K_MAX];
711 PI_UINT32 lem_threshold[PI_PHY_K_MAX];
712 PI_UINT32 phy_state[PI_PHY_K_MAX];
713 PI_UINT32 nbor_phy_type[PI_PHY_K_MAX];
714 PI_UINT32 link_error_est[PI_PHY_K_MAX];
715 PI_UINT32 broken_reason[PI_PHY_K_MAX];
716 PI_UINT32 reject_reason[PI_PHY_K_MAX];
717 PI_UINT32 cntr_interval; /* Miscellaneous */
718 PI_UINT32 module_rev;
719 PI_UINT32 firmware_rev;
720 PI_UINT32 mop_device_type;
721 PI_UINT32 phy_led[PI_PHY_K_MAX];
722 PI_UINT32 flush_time;
723 } PI_CMD_STATUS_CHARS_GET_RSP;
724
725 /* FDDI_MIB_Get Request */
726
727 typedef struct
728 {
729 PI_UINT32 cmd_type;
730 } PI_CMD_FDDI_MIB_GET_REQ;
731
732 /* FDDI_MIB_Get Response */
733
734 typedef struct
735 {
736 PI_RSP_HEADER header;
737
738 /* SMT GROUP */
739
740 PI_STATION_ID smt_station_id;
741 PI_UINT32 smt_op_version_id;
742 PI_UINT32 smt_hi_version_id;
743 PI_UINT32 smt_lo_version_id;
744 PI_UINT32 smt_mac_ct;
745 PI_UINT32 smt_non_master_ct;
746 PI_UINT32 smt_master_ct;
747 PI_UINT32 smt_paths_available;
748 PI_UINT32 smt_config_capabilities;
749 PI_UINT32 smt_config_policy;
750 PI_UINT32 smt_connection_policy;
751 PI_UINT32 smt_t_notify;
752 PI_UINT32 smt_status_reporting;
753 PI_UINT32 smt_ecm_state;
754 PI_UINT32 smt_cf_state;
755 PI_UINT32 smt_hold_state;
756 PI_UINT32 smt_remote_disconnect_flag;
757 PI_UINT32 smt_station_action;
758
759 /* MAC GROUP */
760
761 PI_UINT32 mac_frame_status_capabilities;
762 PI_UINT32 mac_t_max_greatest_lower_bound;
763 PI_UINT32 mac_tvx_greatest_lower_bound;
764 PI_UINT32 mac_paths_available;
765 PI_UINT32 mac_current_path;
766 PI_LAN_ADDR mac_upstream_nbr;
767 PI_LAN_ADDR mac_old_upstream_nbr;
768 PI_UINT32 mac_dup_addr_test;
769 PI_UINT32 mac_paths_requested;
770 PI_UINT32 mac_downstream_port_type;
771 PI_LAN_ADDR mac_smt_address;
772 PI_UINT32 mac_t_req;
773 PI_UINT32 mac_t_neg;
774 PI_UINT32 mac_t_max;
775 PI_UINT32 mac_tvx_value;
776 PI_UINT32 mac_t_min;
777 PI_UINT32 mac_current_frame_status;
778 /* mac_frame_cts */
779 /* mac_error_cts */
780 /* mac_lost_cts */
781 PI_UINT32 mac_frame_error_threshold;
782 PI_UINT32 mac_frame_error_ratio;
783 PI_UINT32 mac_rmt_state;
784 PI_UINT32 mac_da_flag;
785 PI_UINT32 mac_una_da_flag;
786 PI_UINT32 mac_frame_condition;
787 PI_UINT32 mac_chip_set;
788 PI_UINT32 mac_action;
789
790 /* PATH GROUP => Does not need to be implemented */
791
792 /* PORT GROUP */
793
794 PI_UINT32 port_pc_type[PI_PHY_K_MAX];
795 PI_UINT32 port_pc_neighbor[PI_PHY_K_MAX];
796 PI_UINT32 port_connection_policies[PI_PHY_K_MAX];
797 PI_UINT32 port_remote_mac_indicated[PI_PHY_K_MAX];
798 PI_UINT32 port_ce_state[PI_PHY_K_MAX];
799 PI_UINT32 port_paths_requested[PI_PHY_K_MAX];
800 PI_UINT32 port_mac_placement[PI_PHY_K_MAX];
801 PI_UINT32 port_available_paths[PI_PHY_K_MAX];
802 PI_UINT32 port_mac_loop_time[PI_PHY_K_MAX];
803 PI_UINT32 port_tb_max[PI_PHY_K_MAX];
804 PI_UINT32 port_bs_flag[PI_PHY_K_MAX];
805 /* port_lct_fail_cts[PI_PHY_K_MAX]; */
806 PI_UINT32 port_ler_estimate[PI_PHY_K_MAX];
807 /* port_lem_reject_cts[PI_PHY_K_MAX]; */
808 /* port_lem_cts[PI_PHY_K_MAX]; */
809 PI_UINT32 port_ler_cutoff[PI_PHY_K_MAX];
810 PI_UINT32 port_ler_alarm[PI_PHY_K_MAX];
811 PI_UINT32 port_connect_state[PI_PHY_K_MAX];
812 PI_UINT32 port_pcm_state[PI_PHY_K_MAX];
813 PI_UINT32 port_pc_withhold[PI_PHY_K_MAX];
814 PI_UINT32 port_ler_condition[PI_PHY_K_MAX];
815 PI_UINT32 port_chip_set[PI_PHY_K_MAX];
816 PI_UINT32 port_action[PI_PHY_K_MAX];
817
818 /* ATTACHMENT GROUP */
819
820 PI_UINT32 attachment_class;
821 PI_UINT32 attachment_ob_present;
822 PI_UINT32 attachment_imax_expiration;
823 PI_UINT32 attachment_inserted_status;
824 PI_UINT32 attachment_insert_policy;
825
826 /* CHIP SET GROUP => Does not need to be implemented */
827
828 } PI_CMD_FDDI_MIB_GET_RSP;
829
830 /* DEC_Ext_MIB_Get Request */
831
832 typedef struct
833 {
834 PI_UINT32 cmd_type;
835 } PI_CMD_DEC_EXT_MIB_GET_REQ;
836
837 /* DEC_Ext_MIB_Get (efddi and efdx groups only) Response */
838
839 typedef struct
840 {
841 PI_RSP_HEADER header;
842
843 /* SMT GROUP */
844
845 PI_UINT32 esmt_station_type;
846
847 /* MAC GROUP */
848
849 PI_UINT32 emac_link_state;
850 PI_UINT32 emac_ring_purger_state;
851 PI_UINT32 emac_ring_purger_enable;
852 PI_UINT32 emac_frame_strip_mode;
853 PI_UINT32 emac_ring_error_reason;
854 PI_UINT32 emac_up_nbr_dup_addr_flag;
855 PI_UINT32 emac_restricted_token_timeout;
856
857 /* PORT GROUP */
858
859 PI_UINT32 eport_pmd_type[PI_PHY_K_MAX];
860 PI_UINT32 eport_phy_state[PI_PHY_K_MAX];
861 PI_UINT32 eport_reject_reason[PI_PHY_K_MAX];
862
863 /* FDX (Full-Duplex) GROUP */
864
865 PI_UINT32 efdx_enable; /* Valid only in SMT 7.3 */
866 PI_UINT32 efdx_op; /* Valid only in SMT 7.3 */
867 PI_UINT32 efdx_state; /* Valid only in SMT 7.3 */
868
869 } PI_CMD_DEC_EXT_MIB_GET_RSP;
870
871 typedef struct
872 {
873 PI_CNTR traces_rcvd; /* Station */
874 PI_CNTR frame_cnt; /* Link */
875 PI_CNTR error_cnt;
876 PI_CNTR lost_cnt;
877 PI_CNTR octets_rcvd;
878 PI_CNTR octets_sent;
879 PI_CNTR pdus_rcvd;
880 PI_CNTR pdus_sent;
881 PI_CNTR mcast_octets_rcvd;
882 PI_CNTR mcast_octets_sent;
883 PI_CNTR mcast_pdus_rcvd;
884 PI_CNTR mcast_pdus_sent;
885 PI_CNTR xmt_underruns;
886 PI_CNTR xmt_failures;
887 PI_CNTR block_check_errors;
888 PI_CNTR frame_status_errors;
889 PI_CNTR pdu_length_errors;
890 PI_CNTR rcv_overruns;
891 PI_CNTR user_buff_unavailable;
892 PI_CNTR inits_initiated;
893 PI_CNTR inits_rcvd;
894 PI_CNTR beacons_initiated;
895 PI_CNTR dup_addrs;
896 PI_CNTR dup_tokens;
897 PI_CNTR purge_errors;
898 PI_CNTR fci_strip_errors;
899 PI_CNTR traces_initiated;
900 PI_CNTR directed_beacons_rcvd;
901 PI_CNTR emac_frame_alignment_errors;
902 PI_CNTR ebuff_errors[PI_PHY_K_MAX]; /* Phy */
903 PI_CNTR lct_rejects[PI_PHY_K_MAX];
904 PI_CNTR lem_rejects[PI_PHY_K_MAX];
905 PI_CNTR link_errors[PI_PHY_K_MAX];
906 PI_CNTR connections[PI_PHY_K_MAX];
907 PI_CNTR copied_cnt; /* Valid only if using SMT 7.3 */
908 PI_CNTR transmit_cnt; /* Valid only if using SMT 7.3 */
909 PI_CNTR tokens;
910 } PI_CNTR_BLK;
911
912 /* Counters_Get Request */
913
914 typedef struct
915 {
916 PI_UINT32 cmd_type;
917 } PI_CMD_CNTRS_GET_REQ;
918
919 /* Counters_Get Response */
920
921 typedef struct
922 {
923 PI_RSP_HEADER header;
924 PI_CNTR time_since_reset;
925 PI_CNTR_BLK cntrs;
926 } PI_CMD_CNTRS_GET_RSP;
927
928 /* Counters_Set Request */
929
930 typedef struct
931 {
932 PI_UINT32 cmd_type;
933 PI_CNTR_BLK cntrs;
934 } PI_CMD_CNTRS_SET_REQ;
935
936 /* Counters_Set Response */
937
938 typedef struct
939 {
940 PI_RSP_HEADER header;
941 } PI_CMD_CNTRS_SET_RSP;
942
943 /* Error_Log_Clear Request */
944
945 typedef struct
946 {
947 PI_UINT32 cmd_type;
948 } PI_CMD_ERROR_LOG_CLEAR_REQ;
949
950 /* Error_Log_Clear Response */
951
952 typedef struct
953 {
954 PI_RSP_HEADER header;
955 } PI_CMD_ERROR_LOG_CLEAR_RSP;
956
957 /* Error_Log_Get Request */
958
959 #define PI_LOG_ENTRY_K_INDEX_MIN 0 /* Minimum index for entry */
960
961 typedef struct
962 {
963 PI_UINT32 cmd_type;
964 PI_UINT32 entry_index;
965 } PI_CMD_ERROR_LOG_GET_REQ;
966
967 /* Error_Log_Get Response */
968
969 #define PI_K_LOG_FW_SIZE 111 /* Max number of fw longwords */
970 #define PI_K_LOG_DIAG_SIZE 6 /* Max number of diag longwords */
971
972 typedef struct
973 {
974 struct
975 {
976 PI_UINT32 fru_imp_mask;
977 PI_UINT32 test_id;
978 PI_UINT32 reserved[PI_K_LOG_DIAG_SIZE];
979 } diag;
980 PI_UINT32 fw[PI_K_LOG_FW_SIZE];
981 } PI_LOG_ENTRY;
982
983 typedef struct
984 {
985 PI_RSP_HEADER header;
986 PI_UINT32 event_status;
987 PI_UINT32 caller_id;
988 PI_UINT32 timestamp_l;
989 PI_UINT32 timestamp_h;
990 PI_UINT32 write_count;
991 PI_LOG_ENTRY entry_info;
992 } PI_CMD_ERROR_LOG_GET_RSP;
993
994 /* Define error log related constants and types. */
995 /* Not all of the caller id's can occur. The only ones currently */
996 /* implemented are: none, selftest, mfg, fw, console */
997
998 #define PI_LOG_EVENT_STATUS_K_VALID 0 /* Valid Event Status */
999 #define PI_LOG_EVENT_STATUS_K_INVALID 1 /* Invalid Event Status */
1000 #define PI_LOG_CALLER_ID_K_NONE 0 /* No caller */
1001 #define PI_LOG_CALLER_ID_K_SELFTEST 1 /* Normal power-up selftest */
1002 #define PI_LOG_CALLER_ID_K_MFG 2 /* Mfg power-up selftest */
1003 #define PI_LOG_CALLER_ID_K_ONLINE 3 /* On-line diagnostics */
1004 #define PI_LOG_CALLER_ID_K_HW 4 /* Hardware */
1005 #define PI_LOG_CALLER_ID_K_FW 5 /* Firmware */
1006 #define PI_LOG_CALLER_ID_K_CNS_HW 6 /* CNS firmware */
1007 #define PI_LOG_CALLER_ID_K_CNS_FW 7 /* CNS hardware */
1008 #define PI_LOG_CALLER_ID_K_CONSOLE 8 /* Console Caller Id */
1009
1010 /*
1011 * Place all DMA commands in the following request and response structures
1012 * to simplify code.
1013 */
1014
1015 typedef union
1016 {
1017 PI_UINT32 cmd_type;
1018 PI_CMD_START_REQ start;
1019 PI_CMD_FILTERS_SET_REQ filter_set;
1020 PI_CMD_FILTERS_GET_REQ filter_get;
1021 PI_CMD_CHARS_SET_REQ char_set;
1022 PI_CMD_ADDR_FILTER_SET_REQ addr_filter_set;
1023 PI_CMD_ADDR_FILTER_GET_REQ addr_filter_get;
1024 PI_CMD_STATUS_CHARS_GET_REQ stat_char_get;
1025 PI_CMD_CNTRS_GET_REQ cntrs_get;
1026 PI_CMD_CNTRS_SET_REQ cntrs_set;
1027 PI_CMD_ERROR_LOG_CLEAR_REQ error_log_clear;
1028 PI_CMD_ERROR_LOG_GET_REQ error_log_read;
1029 PI_CMD_SNMP_SET_REQ snmp_set;
1030 PI_CMD_FDDI_MIB_GET_REQ fddi_mib_get;
1031 PI_CMD_DEC_EXT_MIB_GET_REQ dec_mib_get;
1032 PI_CMD_SMT_MIB_SET_REQ smt_mib_set;
1033 PI_CMD_SMT_MIB_GET_REQ smt_mib_get;
1034 char pad[PI_CMD_REQ_K_SIZE_MAX];
1035 } PI_DMA_CMD_REQ;
1036
1037 typedef union
1038 {
1039 PI_RSP_HEADER header;
1040 PI_CMD_START_RSP start;
1041 PI_CMD_FILTERS_SET_RSP filter_set;
1042 PI_CMD_FILTERS_GET_RSP filter_get;
1043 PI_CMD_CHARS_SET_RSP char_set;
1044 PI_CMD_ADDR_FILTER_SET_RSP addr_filter_set;
1045 PI_CMD_ADDR_FILTER_GET_RSP addr_filter_get;
1046 PI_CMD_STATUS_CHARS_GET_RSP stat_char_get;
1047 PI_CMD_CNTRS_GET_RSP cntrs_get;
1048 PI_CMD_CNTRS_SET_RSP cntrs_set;
1049 PI_CMD_ERROR_LOG_CLEAR_RSP error_log_clear;
1050 PI_CMD_ERROR_LOG_GET_RSP error_log_get;
1051 PI_CMD_SNMP_SET_RSP snmp_set;
1052 PI_CMD_FDDI_MIB_GET_RSP fddi_mib_get;
1053 PI_CMD_DEC_EXT_MIB_GET_RSP dec_mib_get;
1054 PI_CMD_SMT_MIB_SET_RSP smt_mib_set;
1055 PI_CMD_SMT_MIB_GET_RSP smt_mib_get;
1056 char pad[PI_CMD_RSP_K_SIZE_MAX];
1057 } PI_DMA_CMD_RSP;
1058
1059 typedef union
1060 {
1061 PI_DMA_CMD_REQ request;
1062 PI_DMA_CMD_RSP response;
1063 } PI_DMA_CMD_BUFFER;
1064
1065
1066 /* Define format of Consumer Block (resident in host memory) */
1067
1068 typedef struct
1069 {
1070 volatile PI_UINT32 xmt_rcv_data;
1071 volatile PI_UINT32 reserved_1;
1072 volatile PI_UINT32 smt_host;
1073 volatile PI_UINT32 reserved_2;
1074 volatile PI_UINT32 unsol;
1075 volatile PI_UINT32 reserved_3;
1076 volatile PI_UINT32 cmd_rsp;
1077 volatile PI_UINT32 reserved_4;
1078 volatile PI_UINT32 cmd_req;
1079 volatile PI_UINT32 reserved_5;
1080 } PI_CONSUMER_BLOCK;
1081
1082 #define PI_CONS_M_RCV_INDEX 0x000000FF
1083 #define PI_CONS_M_XMT_INDEX 0x00FF0000
1084 #define PI_CONS_V_RCV_INDEX 0
1085 #define PI_CONS_V_XMT_INDEX 16
1086
1087 /* Offsets into consumer block */
1088
1089 #define PI_CONS_BLK_K_XMT_RCV 0x00
1090 #define PI_CONS_BLK_K_SMT_HOST 0x08
1091 #define PI_CONS_BLK_K_UNSOL 0x10
1092 #define PI_CONS_BLK_K_CMD_RSP 0x18
1093 #define PI_CONS_BLK_K_CMD_REQ 0x20
1094
1095 /* Offsets into descriptor block */
1096
1097 #define PI_DESCR_BLK_K_RCV_DATA 0x0000
1098 #define PI_DESCR_BLK_K_XMT_DATA 0x0800
1099 #define PI_DESCR_BLK_K_SMT_HOST 0x1000
1100 #define PI_DESCR_BLK_K_UNSOL 0x1200
1101 #define PI_DESCR_BLK_K_CMD_RSP 0x1280
1102 #define PI_DESCR_BLK_K_CMD_REQ 0x1300
1103
1104 /* Define format of a rcv descr (Rcv Data, Cmd Rsp, Unsolicited, SMT Host) */
1105 /* Note a field has been added for later versions of the PDQ to allow for */
1106 /* finer granularity of the rcv buffer alignment. For backwards */
1107 /* compatibility, the two bits (which allow the rcv buffer to be longword */
1108 /* aligned) have been added at the MBZ bits. To support previous drivers, */
1109 /* the MBZ definition is left intact. */
1110
1111 typedef struct
1112 {
1113 PI_UINT32 long_0;
1114 PI_UINT32 long_1;
1115 } PI_RCV_DESCR;
1116
1117 #define PI_RCV_DESCR_M_SOP 0x80000000
1118 #define PI_RCV_DESCR_M_SEG_LEN_LO 0x60000000
1119 #define PI_RCV_DESCR_M_MBZ 0x60000000
1120 #define PI_RCV_DESCR_M_SEG_LEN 0x1F800000
1121 #define PI_RCV_DESCR_M_SEG_LEN_HI 0x1FF00000
1122 #define PI_RCV_DESCR_M_SEG_CNT 0x000F0000
1123 #define PI_RCV_DESCR_M_BUFF_HI 0x0000FFFF
1124
1125 #define PI_RCV_DESCR_V_SOP 31
1126 #define PI_RCV_DESCR_V_SEG_LEN_LO 29
1127 #define PI_RCV_DESCR_V_MBZ 29
1128 #define PI_RCV_DESCR_V_SEG_LEN 23
1129 #define PI_RCV_DESCR_V_SEG_LEN_HI 20
1130 #define PI_RCV_DESCR_V_SEG_CNT 16
1131 #define PI_RCV_DESCR_V_BUFF_HI 0
1132
1133 /* Define the format of a transmit descriptor (Xmt Data, Cmd Req) */
1134
1135 typedef struct
1136 {
1137 PI_UINT32 long_0;
1138 PI_UINT32 long_1;
1139 } PI_XMT_DESCR;
1140
1141 #define PI_XMT_DESCR_M_SOP 0x80000000
1142 #define PI_XMT_DESCR_M_EOP 0x40000000
1143 #define PI_XMT_DESCR_M_MBZ 0x20000000
1144 #define PI_XMT_DESCR_M_SEG_LEN 0x1FFF0000
1145 #define PI_XMT_DESCR_M_BUFF_HI 0x0000FFFF
1146
1147 #define PI_XMT_DESCR_V_SOP 31
1148 #define PI_XMT_DESCR_V_EOP 30
1149 #define PI_XMT_DESCR_V_MBZ 29
1150 #define PI_XMT_DESCR_V_SEG_LEN 16
1151 #define PI_XMT_DESCR_V_BUFF_HI 0
1152
1153 /* Define format of the Descriptor Block (resident in host memory) */
1154
1155 #define PI_RCV_DATA_K_NUM_ENTRIES 256
1156 #define PI_XMT_DATA_K_NUM_ENTRIES 256
1157 #define PI_SMT_HOST_K_NUM_ENTRIES 64
1158 #define PI_UNSOL_K_NUM_ENTRIES 16
1159 #define PI_CMD_RSP_K_NUM_ENTRIES 16
1160 #define PI_CMD_REQ_K_NUM_ENTRIES 16
1161
1162 typedef struct
1163 {
1164 PI_RCV_DESCR rcv_data[PI_RCV_DATA_K_NUM_ENTRIES];
1165 PI_XMT_DESCR xmt_data[PI_XMT_DATA_K_NUM_ENTRIES];
1166 PI_RCV_DESCR smt_host[PI_SMT_HOST_K_NUM_ENTRIES];
1167 PI_RCV_DESCR unsol[PI_UNSOL_K_NUM_ENTRIES];
1168 PI_RCV_DESCR cmd_rsp[PI_CMD_RSP_K_NUM_ENTRIES];
1169 PI_XMT_DESCR cmd_req[PI_CMD_REQ_K_NUM_ENTRIES];
1170 } PI_DESCR_BLOCK;
1171
1172 /* Define Port Registers - offsets from PDQ Base address */
1173
1174 #define PI_PDQ_K_REG_PORT_RESET 0x00000000
1175 #define PI_PDQ_K_REG_HOST_DATA 0x00000004
1176 #define PI_PDQ_K_REG_PORT_CTRL 0x00000008
1177 #define PI_PDQ_K_REG_PORT_DATA_A 0x0000000C
1178 #define PI_PDQ_K_REG_PORT_DATA_B 0x00000010
1179 #define PI_PDQ_K_REG_PORT_STATUS 0x00000014
1180 #define PI_PDQ_K_REG_TYPE_0_STATUS 0x00000018
1181 #define PI_PDQ_K_REG_HOST_INT_ENB 0x0000001C
1182 #define PI_PDQ_K_REG_TYPE_2_PROD_NOINT 0x00000020
1183 #define PI_PDQ_K_REG_TYPE_2_PROD 0x00000024
1184 #define PI_PDQ_K_REG_CMD_RSP_PROD 0x00000028
1185 #define PI_PDQ_K_REG_CMD_REQ_PROD 0x0000002C
1186 #define PI_PDQ_K_REG_SMT_HOST_PROD 0x00000030
1187 #define PI_PDQ_K_REG_UNSOL_PROD 0x00000034
1188
1189 /* Port Control Register - Command codes for primary commands */
1190
1191 #define PI_PCTRL_M_CMD_ERROR 0x8000
1192 #define PI_PCTRL_M_BLAST_FLASH 0x4000
1193 #define PI_PCTRL_M_HALT 0x2000
1194 #define PI_PCTRL_M_COPY_DATA 0x1000
1195 #define PI_PCTRL_M_ERROR_LOG_START 0x0800
1196 #define PI_PCTRL_M_ERROR_LOG_READ 0x0400
1197 #define PI_PCTRL_M_XMT_DATA_FLUSH_DONE 0x0200
1198 #define PI_PCTRL_M_INIT 0x0100
1199 #define PI_PCTRL_M_INIT_START 0x0080
1200 #define PI_PCTRL_M_CONS_BLOCK 0x0040
1201 #define PI_PCTRL_M_UNINIT 0x0020
1202 #define PI_PCTRL_M_RING_MEMBER 0x0010
1203 #define PI_PCTRL_M_MLA 0x0008
1204 #define PI_PCTRL_M_FW_REV_READ 0x0004
1205 #define PI_PCTRL_M_DEV_SPECIFIC 0x0002
1206 #define PI_PCTRL_M_SUB_CMD 0x0001
1207
1208 /* Define sub-commands accessed via the PI_PCTRL_M_SUB_CMD command */
1209
1210 #define PI_SUB_CMD_K_LINK_UNINIT 0x0001
1211 #define PI_SUB_CMD_K_BURST_SIZE_SET 0x0002
1212 #define PI_SUB_CMD_K_PDQ_REV_GET 0x0004
1213 #define PI_SUB_CMD_K_HW_REV_GET 0x0008
1214
1215 /* Define some Port Data B values */
1216
1217 #define PI_PDATA_B_DMA_BURST_SIZE_4 0 /* valid values for command */
1218 #define PI_PDATA_B_DMA_BURST_SIZE_8 1
1219 #define PI_PDATA_B_DMA_BURST_SIZE_16 2
1220 #define PI_PDATA_B_DMA_BURST_SIZE_32 3 /* not supported on PCI */
1221 #define PI_PDATA_B_DMA_BURST_SIZE_DEF PI_PDATA_B_DMA_BURST_SIZE_16
1222
1223 /* Port Data A Reset state */
1224
1225 #define PI_PDATA_A_RESET_M_UPGRADE 0x00000001
1226 #define PI_PDATA_A_RESET_M_SOFT_RESET 0x00000002
1227 #define PI_PDATA_A_RESET_M_SKIP_ST 0x00000004
1228
1229 /* Read adapter MLA address port control command constants */
1230
1231 #define PI_PDATA_A_MLA_K_LO 0
1232 #define PI_PDATA_A_MLA_K_HI 1
1233
1234 /* Byte Swap values for init command */
1235
1236 #define PI_PDATA_A_INIT_M_DESC_BLK_ADDR 0x0FFFFE000
1237 #define PI_PDATA_A_INIT_M_RESERVED 0x000001FFC
1238 #define PI_PDATA_A_INIT_M_BSWAP_DATA 0x000000002
1239 #define PI_PDATA_A_INIT_M_BSWAP_LITERAL 0x000000001
1240
1241 #define PI_PDATA_A_INIT_V_DESC_BLK_ADDR 13
1242 #define PI_PDATA_A_INIT_V_RESERVED 3
1243 #define PI_PDATA_A_INIT_V_BSWAP_DATA 1
1244 #define PI_PDATA_A_INIT_V_BSWAP_LITERAL 0
1245
1246 /* Port Reset Register */
1247
1248 #define PI_RESET_M_ASSERT_RESET 1
1249
1250 /* Port Status register */
1251
1252 #define PI_PSTATUS_V_RCV_DATA_PENDING 31
1253 #define PI_PSTATUS_V_XMT_DATA_PENDING 30
1254 #define PI_PSTATUS_V_SMT_HOST_PENDING 29
1255 #define PI_PSTATUS_V_UNSOL_PENDING 28
1256 #define PI_PSTATUS_V_CMD_RSP_PENDING 27
1257 #define PI_PSTATUS_V_CMD_REQ_PENDING 26
1258 #define PI_PSTATUS_V_TYPE_0_PENDING 25
1259 #define PI_PSTATUS_V_RESERVED_1 16
1260 #define PI_PSTATUS_V_RESERVED_2 11
1261 #define PI_PSTATUS_V_STATE 8
1262 #define PI_PSTATUS_V_HALT_ID 0
1263
1264 #define PI_PSTATUS_M_RCV_DATA_PENDING 0x80000000
1265 #define PI_PSTATUS_M_XMT_DATA_PENDING 0x40000000
1266 #define PI_PSTATUS_M_SMT_HOST_PENDING 0x20000000
1267 #define PI_PSTATUS_M_UNSOL_PENDING 0x10000000
1268 #define PI_PSTATUS_M_CMD_RSP_PENDING 0x08000000
1269 #define PI_PSTATUS_M_CMD_REQ_PENDING 0x04000000
1270 #define PI_PSTATUS_M_TYPE_0_PENDING 0x02000000
1271 #define PI_PSTATUS_M_RESERVED_1 0x01FF0000
1272 #define PI_PSTATUS_M_RESERVED_2 0x0000F800
1273 #define PI_PSTATUS_M_STATE 0x00000700
1274 #define PI_PSTATUS_M_HALT_ID 0x000000FF
1275
1276 /* Define Halt Id's */
1277 /* Do not insert into this list, only append. */
1278
1279 #define PI_HALT_ID_K_SELFTEST_TIMEOUT 0
1280 #define PI_HALT_ID_K_PARITY_ERROR 1
1281 #define PI_HALT_ID_K_HOST_DIR_HALT 2
1282 #define PI_HALT_ID_K_SW_FAULT 3
1283 #define PI_HALT_ID_K_HW_FAULT 4
1284 #define PI_HALT_ID_K_PC_TRACE 5
1285 #define PI_HALT_ID_K_DMA_ERROR 6 /* Host Data has error reg */
1286 #define PI_HALT_ID_K_IMAGE_CRC_ERROR 7 /* Image is bad, update it */
1287 #define PI_HALT_ID_K_BUS_EXCEPTION 8 /* 68K bus exception */
1288
1289 /* Host Interrupt Enable Register as seen by host */
1290
1291 #define PI_HOST_INT_M_XMT_DATA_ENB 0x80000000 /* Type 2 Enables */
1292 #define PI_HOST_INT_M_RCV_DATA_ENB 0x40000000
1293 #define PI_HOST_INT_M_SMT_HOST_ENB 0x10000000 /* Type 1 Enables */
1294 #define PI_HOST_INT_M_UNSOL_ENB 0x20000000
1295 #define PI_HOST_INT_M_CMD_RSP_ENB 0x08000000
1296 #define PI_HOST_INT_M_CMD_REQ_ENB 0x04000000
1297 #define PI_HOST_INT_M_TYPE_1_RESERVED 0x00FF0000
1298 #define PI_HOST_INT_M_TYPE_0_RESERVED 0x0000FF00 /* Type 0 Enables */
1299 #define PI_HOST_INT_M_1MS 0x00000080
1300 #define PI_HOST_INT_M_20MS 0x00000040
1301 #define PI_HOST_INT_M_CSR_CMD_DONE 0x00000020
1302 #define PI_HOST_INT_M_STATE_CHANGE 0x00000010
1303 #define PI_HOST_INT_M_XMT_FLUSH 0x00000008
1304 #define PI_HOST_INT_M_NXM 0x00000004
1305 #define PI_HOST_INT_M_PM_PAR_ERR 0x00000002
1306 #define PI_HOST_INT_M_BUS_PAR_ERR 0x00000001
1307
1308 #define PI_HOST_INT_V_XMT_DATA_ENB 31 /* Type 2 Enables */
1309 #define PI_HOST_INT_V_RCV_DATA_ENB 30
1310 #define PI_HOST_INT_V_SMT_HOST_ENB 29 /* Type 1 Enables */
1311 #define PI_HOST_INT_V_UNSOL_ENB 28
1312 #define PI_HOST_INT_V_CMD_RSP_ENB 27
1313 #define PI_HOST_INT_V_CMD_REQ_ENB 26
1314 #define PI_HOST_INT_V_TYPE_1_RESERVED 16
1315 #define PI_HOST_INT_V_TYPE_0_RESERVED 8 /* Type 0 Enables */
1316 #define PI_HOST_INT_V_1MS_ENB 7
1317 #define PI_HOST_INT_V_20MS_ENB 6
1318 #define PI_HOST_INT_V_CSR_CMD_DONE_ENB 5
1319 #define PI_HOST_INT_V_STATE_CHANGE_ENB 4
1320 #define PI_HOST_INT_V_XMT_FLUSH_ENB 3
1321 #define PI_HOST_INT_V_NXM_ENB 2
1322 #define PI_HOST_INT_V_PM_PAR_ERR_ENB 1
1323 #define PI_HOST_INT_V_BUS_PAR_ERR_ENB 0
1324
1325 #define PI_HOST_INT_K_ACK_ALL_TYPE_0 0x000000FF
1326 #define PI_HOST_INT_K_DISABLE_ALL_INTS 0x00000000
1327 #define PI_HOST_INT_K_ENABLE_ALL_INTS 0xFFFFFFFF
1328 #define PI_HOST_INT_K_ENABLE_DEF_INTS 0xC000001F
1329
1330 /* Type 0 Interrupt Status Register */
1331
1332 #define PI_TYPE_0_STAT_M_1MS 0x00000080
1333 #define PI_TYPE_0_STAT_M_20MS 0x00000040
1334 #define PI_TYPE_0_STAT_M_CSR_CMD_DONE 0x00000020
1335 #define PI_TYPE_0_STAT_M_STATE_CHANGE 0x00000010
1336 #define PI_TYPE_0_STAT_M_XMT_FLUSH 0x00000008
1337 #define PI_TYPE_0_STAT_M_NXM 0x00000004
1338 #define PI_TYPE_0_STAT_M_PM_PAR_ERR 0x00000002
1339 #define PI_TYPE_0_STAT_M_BUS_PAR_ERR 0x00000001
1340
1341 #define PI_TYPE_0_STAT_V_1MS 7
1342 #define PI_TYPE_0_STAT_V_20MS 6
1343 #define PI_TYPE_0_STAT_V_CSR_CMD_DONE 5
1344 #define PI_TYPE_0_STAT_V_STATE_CHANGE 4
1345 #define PI_TYPE_0_STAT_V_XMT_FLUSH 3
1346 #define PI_TYPE_0_STAT_V_NXM 2
1347 #define PI_TYPE_0_STAT_V_PM_PAR_ERR 1
1348 #define PI_TYPE_0_STAT_V_BUS_PAR_ERR 0
1349
1350 /* Register definition structures are defined for both big and little endian systems */
1351
1352 #ifndef BIG_ENDIAN
1353
1354 /* Little endian format of Type 1 Producer register */
1355
1356 typedef union
1357 {
1358 PI_UINT32 lword;
1359 struct
1360 {
1361 PI_UINT8 prod;
1362 PI_UINT8 comp;
1363 PI_UINT8 mbz_1;
1364 PI_UINT8 mbz_2;
1365 } index;
1366 } PI_TYPE_1_PROD_REG;
1367
1368 /* Little endian format of Type 2 Producer register */
1369
1370 typedef union
1371 {
1372 PI_UINT32 lword;
1373 struct
1374 {
1375 PI_UINT8 rcv_prod;
1376 PI_UINT8 xmt_prod;
1377 PI_UINT8 rcv_comp;
1378 PI_UINT8 xmt_comp;
1379 } index;
1380 } PI_TYPE_2_PROD_REG;
1381
1382 /* Little endian format of Type 1 Consumer Block longword */
1383
1384 typedef union
1385 {
1386 PI_UINT32 lword;
1387 struct
1388 {
1389 PI_UINT8 cons;
1390 PI_UINT8 res0;
1391 PI_UINT8 res1;
1392 PI_UINT8 res2;
1393 } index;
1394 } PI_TYPE_1_CONSUMER;
1395
1396 /* Little endian format of Type 2 Consumer Block longword */
1397
1398 typedef union
1399 {
1400 PI_UINT32 lword;
1401 struct
1402 {
1403 PI_UINT8 rcv_cons;
1404 PI_UINT8 res0;
1405 PI_UINT8 xmt_cons;
1406 PI_UINT8 res1;
1407 } index;
1408 } PI_TYPE_2_CONSUMER;
1409
1410 #else
1411
1412 /* Big endian format of Type 1 Producer register */
1413
1414 typedef union
1415 {
1416 PI_UINT32 lword;
1417 struct
1418 {
1419 PI_UINT8 mbz_2;
1420 PI_UINT8 mbz_1;
1421 PI_UINT8 comp;
1422 PI_UINT8 prod;
1423 } index;
1424 } PI_TYPE_1_PROD_REG;
1425
1426 /* Big endian format of Type 2 Producer register */
1427
1428 typedef union
1429 {
1430 PI_UINT32 lword;
1431 struct
1432 {
1433 PI_UINT8 xmt_comp;
1434 PI_UINT8 rcv_comp;
1435 PI_UINT8 xmt_prod;
1436 PI_UINT8 rcv_prod;
1437 } index;
1438 } PI_TYPE_2_PROD_REG;
1439
1440 /* Big endian format of Type 1 Consumer Block longword */
1441
1442 typedef union
1443 {
1444 PI_UINT32 lword;
1445 struct
1446 {
1447 PI_UINT8 res2;
1448 PI_UINT8 res1;
1449 PI_UINT8 res0;
1450 PI_UINT8 cons;
1451 } index;
1452 } PI_TYPE_1_CONSUMER;
1453
1454 /* Big endian format of Type 2 Consumer Block longword */
1455
1456 typedef union
1457 {
1458 PI_UINT32 lword;
1459 struct
1460 {
1461 PI_UINT8 res1;
1462 PI_UINT8 xmt_cons;
1463 PI_UINT8 res0;
1464 PI_UINT8 rcv_cons;
1465 } index;
1466 } PI_TYPE_2_CONSUMER;
1467
1468 #endif /* #ifndef BIG_ENDIAN */
1469
1470 /* Define EISA controller register offsets */
1471
1472 #define PI_ESIC_K_BURST_HOLDOFF 0x040
1473 #define PI_ESIC_K_SLOT_ID 0xC80
1474 #define PI_ESIC_K_SLOT_CNTRL 0xC84
1475 #define PI_ESIC_K_MEM_ADD_CMP_0 0xC85
1476 #define PI_ESIC_K_MEM_ADD_CMP_1 0xC86
1477 #define PI_ESIC_K_MEM_ADD_CMP_2 0xC87
1478 #define PI_ESIC_K_MEM_ADD_HI_CMP_0 0xC88
1479 #define PI_ESIC_K_MEM_ADD_HI_CMP_1 0xC89
1480 #define PI_ESIC_K_MEM_ADD_HI_CMP_2 0xC8A
1481 #define PI_ESIC_K_MEM_ADD_MASK_0 0xC8B
1482 #define PI_ESIC_K_MEM_ADD_MASK_1 0xC8C
1483 #define PI_ESIC_K_MEM_ADD_MASK_2 0xC8D
1484 #define PI_ESIC_K_MEM_ADD_LO_CMP_0 0xC8E
1485 #define PI_ESIC_K_MEM_ADD_LO_CMP_1 0xC8F
1486 #define PI_ESIC_K_MEM_ADD_LO_CMP_2 0xC90
1487 #define PI_ESIC_K_IO_CMP_0_0 0xC91
1488 #define PI_ESIC_K_IO_CMP_0_1 0xC92
1489 #define PI_ESIC_K_IO_CMP_1_0 0xC93
1490 #define PI_ESIC_K_IO_CMP_1_1 0xC94
1491 #define PI_ESIC_K_IO_CMP_2_0 0xC95
1492 #define PI_ESIC_K_IO_CMP_2_1 0xC96
1493 #define PI_ESIC_K_IO_CMP_3_0 0xC97
1494 #define PI_ESIC_K_IO_CMP_3_1 0xC98
1495 #define PI_ESIC_K_IO_ADD_MASK_0_0 0xC99
1496 #define PI_ESIC_K_IO_ADD_MASK_0_1 0xC9A
1497 #define PI_ESIC_K_IO_ADD_MASK_1_0 0xC9B
1498 #define PI_ESIC_K_IO_ADD_MASK_1_1 0xC9C
1499 #define PI_ESIC_K_IO_ADD_MASK_2_0 0xC9D
1500 #define PI_ESIC_K_IO_ADD_MASK_2_1 0xC9E
1501 #define PI_ESIC_K_IO_ADD_MASK_3_0 0xC9F
1502 #define PI_ESIC_K_IO_ADD_MASK_3_1 0xCA0
1503 #define PI_ESIC_K_MOD_CONFIG_1 0xCA1
1504 #define PI_ESIC_K_MOD_CONFIG_2 0xCA2
1505 #define PI_ESIC_K_MOD_CONFIG_3 0xCA3
1506 #define PI_ESIC_K_MOD_CONFIG_4 0xCA4
1507 #define PI_ESIC_K_MOD_CONFIG_5 0xCA5
1508 #define PI_ESIC_K_MOD_CONFIG_6 0xCA6
1509 #define PI_ESIC_K_MOD_CONFIG_7 0xCA7
1510 #define PI_ESIC_K_DIP_SWITCH 0xCA8
1511 #define PI_ESIC_K_IO_CONFIG_STAT_0 0xCA9
1512 #define PI_ESIC_K_IO_CONFIG_STAT_1 0xCAA
1513 #define PI_ESIC_K_DMA_CONFIG 0xCAB
1514 #define PI_ESIC_K_INPUT_PORT 0xCAC
1515 #define PI_ESIC_K_OUTPUT_PORT 0xCAD
1516 #define PI_ESIC_K_FUNCTION_CNTRL 0xCAE
1517 #define PI_ESIC_K_CSR_IO_LEN PI_ESIC_K_FUNCTION_CNTRL+1 /* always last reg + 1 */
1518
1519 /* Define the value all drivers must write to the function control register. */
1520
1521 #define PI_ESIC_K_FUNCTION_CNTRL_IO_ENB 0x03
1522
1523 /* Define the bits in the slot control register. */
1524
1525 #define PI_SLOT_CNTRL_M_RESET 0x04 /* Don't use. */
1526 #define PI_SLOT_CNTRL_M_ERROR 0x02 /* Not implemented. */
1527 #define PI_SLOT_CNTRL_M_ENB 0x01 /* Must be set. */
1528
1529 /* Define the bits in the burst holdoff register. */
1530
1531 #define PI_BURST_HOLDOFF_M_HOLDOFF 0xFC
1532 #define PI_BURST_HOLDOFF_M_RESERVED 0x02
1533 #define PI_BURST_HOLDOFF_M_MEM_MAP 0x01
1534
1535 #define PI_BURST_HOLDOFF_V_HOLDOFF 2
1536 #define PI_BURST_HOLDOFF_V_RESERVED 1
1537 #define PI_BURST_HOLDOFF_V_MEM_MAP 0
1538
1539 /*
1540 * Define the fields in the IO Compare registers.
1541 * The driver must initialize the slot field with the slot ID shifted by the
1542 * amount shown below.
1543 */
1544
1545 #define PI_IO_CMP_V_SLOT 4
1546
1547 /* Define the fields in the Interrupt Channel Configuration and Status reg */
1548
1549 #define PI_CONFIG_STAT_0_M_PEND 0x80
1550 #define PI_CONFIG_STAT_0_M_RES_1 0x40
1551 #define PI_CONFIG_STAT_0_M_IREQ_OUT 0x20
1552 #define PI_CONFIG_STAT_0_M_IREQ_IN 0x10
1553 #define PI_CONFIG_STAT_0_M_INT_ENB 0x08
1554 #define PI_CONFIG_STAT_0_M_RES_0 0x04
1555 #define PI_CONFIG_STAT_0_M_IRQ 0x03
1556
1557 #define PI_CONFIG_STAT_0_V_PEND 7
1558 #define PI_CONFIG_STAT_0_V_RES_1 6
1559 #define PI_CONFIG_STAT_0_V_IREQ_OUT 5
1560 #define PI_CONFIG_STAT_0_V_IREQ_IN 4
1561 #define PI_CONFIG_STAT_0_V_INT_ENB 3
1562 #define PI_CONFIG_STAT_0_V_RES_0 2
1563 #define PI_CONFIG_STAT_0_V_IRQ 0
1564
1565 #define PI_CONFIG_STAT_0_IRQ_K_9 0
1566 #define PI_CONFIG_STAT_0_IRQ_K_10 1
1567 #define PI_CONFIG_STAT_0_IRQ_K_11 2
1568 #define PI_CONFIG_STAT_0_IRQ_K_15 3
1569
1570 /* Define DEC FDDIcontroller/EISA (DEFEA) EISA hardware ID's */
1571
1572 #define DEFEA_PRODUCT_ID 0x0030A310 /* DEC product 300 (no rev) */
1573 #define DEFEA_PROD_ID_1 0x0130A310 /* DEC product 300, rev 1 */
1574 #define DEFEA_PROD_ID_2 0x0230A310 /* DEC product 300, rev 2 */
1575 #define DEFEA_PROD_ID_3 0x0330A310 /* DEC product 300, rev 3 */
1576
1577 /**********************************************/
1578 /* Digital PFI Specification v1.0 Definitions */
1579 /**********************************************/
1580
1581 /* PCI Configuration Space Constants */
1582
1583 #define PFI_K_LAT_TIMER_DEF 0x88 /* def max master latency timer */
1584 #define PFI_K_LAT_TIMER_MIN 0x20 /* min max master latency timer */
1585 #define PFI_K_CSR_MEM_LEN 0x80 /* 128 bytes */
1586 #define PFI_K_CSR_IO_LEN 0x80 /* 128 bytes */
1587 #define PFI_K_PKT_MEM_LEN 0x10000 /* 64K bytes */
1588
1589 /* PFI Register Offsets (starting at PDQ Register Base Address) */
1590
1591 #define PFI_K_REG_RESERVED_0 0X00000038
1592 #define PFI_K_REG_RESERVED_1 0X0000003C
1593 #define PFI_K_REG_MODE_CTRL 0X00000040
1594 #define PFI_K_REG_STATUS 0X00000044
1595 #define PFI_K_REG_FIFO_WRITE 0X00000048
1596 #define PFI_K_REG_FIFO_READ 0X0000004C
1597
1598 /* PFI Mode Control Register Constants */
1599
1600 #define PFI_MODE_M_RESERVED 0XFFFFFFF0
1601 #define PFI_MODE_M_TGT_ABORT_ENB 0X00000008
1602 #define PFI_MODE_M_PDQ_INT_ENB 0X00000004
1603 #define PFI_MODE_M_PFI_INT_ENB 0X00000002
1604 #define PFI_MODE_M_DMA_ENB 0X00000001
1605
1606 #define PFI_MODE_V_RESERVED 4
1607 #define PFI_MODE_V_TGT_ABORT_ENB 3
1608 #define PFI_MODE_V_PDQ_INT_ENB 2
1609 #define PFI_MODE_V_PFI_INT_ENB 1
1610 #define PFI_MODE_V_DMA_ENB 0
1611
1612 #define PFI_MODE_K_ALL_DISABLE 0X00000000
1613
1614 /* PFI Status Register Constants */
1615
1616 #define PFI_STATUS_M_RESERVED 0XFFFFFFC0
1617 #define PFI_STATUS_M_PFI_ERROR 0X00000020 /* only valid in rev 1 or later PFI */
1618 #define PFI_STATUS_M_PDQ_INT 0X00000010
1619 #define PFI_STATUS_M_PDQ_DMA_ABORT 0X00000008
1620 #define PFI_STATUS_M_FIFO_FULL 0X00000004
1621 #define PFI_STATUS_M_FIFO_EMPTY 0X00000002
1622 #define PFI_STATUS_M_DMA_IN_PROGRESS 0X00000001
1623
1624 #define PFI_STATUS_V_RESERVED 6
1625 #define PFI_STATUS_V_PFI_ERROR 5 /* only valid in rev 1 or later PFI */
1626 #define PFI_STATUS_V_PDQ_INT 4
1627 #define PFI_STATUS_V_PDQ_DMA_ABORT 3
1628 #define PFI_STATUS_V_FIFO_FULL 2
1629 #define PFI_STATUS_V_FIFO_EMPTY 1
1630 #define PFI_STATUS_V_DMA_IN_PROGRESS 0
1631
1632 #define DFX_MAX_EISA_SLOTS 16 /* maximum number of EISA slots to scan */
1633 #define DFX_MAX_NUM_BOARDS 8 /* maximum number of adapters supported */
1634
1635 #define DFX_BUS_TYPE_PCI 0 /* type code for DEC FDDIcontroller/PCI */
1636 #define DFX_BUS_TYPE_EISA 1 /* type code for DEC FDDIcontroller/EISA */
1637
1638 #define DFX_FC_PRH2_PRH1_PRH0 0x54003820 /* Packet Request Header bytes + FC */
1639 #define DFX_PRH0_BYTE 0x20 /* Packet Request Header byte 0 */
1640 #define DFX_PRH1_BYTE 0x38 /* Packet Request Header byte 1 */
1641 #define DFX_PRH2_BYTE 0x00 /* Packet Request Header byte 2 */
1642
1643 /* Driver routine status (return) codes */
1644
1645 #define DFX_K_SUCCESS 0 /* routine succeeded */
1646 #define DFX_K_FAILURE 1 /* routine failed */
1647 #define DFX_K_OUTSTATE 2 /* bad state for command */
1648 #define DFX_K_HW_TIMEOUT 3 /* command timed out */
1649
1650 /* Define LLC host receive buffer min/max/default values */
1651
1652 #define RCV_BUFS_MIN 2 /* minimum pre-allocated receive buffers */
1653 #define RCV_BUFS_MAX 32 /* maximum pre-allocated receive buffers */
1654 #define RCV_BUFS_DEF 8 /* default pre-allocated receive buffers */
1655
1656 /* Define offsets into FDDI LLC or SMT receive frame buffers - used when indicating frames */
1657
1658 #define RCV_BUFF_K_DESCR 0 /* four byte FMC descriptor */
1659 #define RCV_BUFF_K_PADDING 4 /* three null bytes */
1660 #define RCV_BUFF_K_FC 7 /* one byte frame control */
1661 #define RCV_BUFF_K_DA 8 /* six byte destination address */
1662 #define RCV_BUFF_K_SA 14 /* six byte source address */
1663 #define RCV_BUFF_K_DATA 20 /* offset to start of packet data */
1664
1665 /* Define offsets into FDDI LLC transmit frame buffers - used when sending frames */
1666
1667 #define XMT_BUFF_K_FC 0 /* one byte frame control */
1668 #define XMT_BUFF_K_DA 1 /* six byte destination address */
1669 #define XMT_BUFF_K_SA 7 /* six byte source address */
1670 #define XMT_BUFF_K_DATA 13 /* offset to start of packet data */
1671
1672 /*
1673 * Macro evaluates to "value" aligned to "size" bytes. Make sure that
1674 * "size" is greater than 0 bytes.
1675 */
1676
1677 #define ALIGN(value,size) ((value + (size - 1)) & ~(size - 1))
1678
1679 /* Macro for checking a "value" is within a specific range */
1680
1681 #define IN_RANGE(value,low,high) ((value >= low) && (value <= high))
1682
1683 /* Only execute special print call when debug driver was built */
1684
1685 #ifdef DEFXX_DEBUG
1686 #define DBG_printk(args...) printk(## args)
1687 #else
1688 #define DBG_printk(args...)
1689 #endif
1690
1691 /* Define constants for masking/unmasking interrupts */
1692
1693 #define DFX_MASK_INTERRUPTS 1
1694 #define DFX_UNMASK_INTERRUPTS 0
1695
1696 /* Define structure for driver transmit descriptor block */
1697
1698 typedef struct
1699 {
1700 struct sk_buff *p_skb; /* ptr to skb */
1701 } XMT_DRIVER_DESCR;
1702
1703 typedef struct DFX_board_tag
1704 {
1705 /* Keep virtual and physical pointers to locked, physically contiguous memory */
1706
1707 char *kmalloced; /* kfree this on unload */
1708 PI_DESCR_BLOCK *descr_block_virt; /* PDQ descriptor block virt address */
1709 u32 descr_block_phys; /* PDQ descriptor block phys address */
1710 PI_DMA_CMD_REQ *cmd_req_virt; /* Command request buffer virt address */
1711 u32 cmd_req_phys; /* Command request buffer phys address */
1712 PI_DMA_CMD_RSP *cmd_rsp_virt; /* Command response buffer virt address */
1713 u32 cmd_rsp_phys; /* Command response buffer phys address */
1714 char *rcv_block_virt; /* LLC host receive queue buf blk virt */
1715 u32 rcv_block_phys; /* LLC host receive queue buf blk phys */
1716 PI_CONSUMER_BLOCK *cons_block_virt; /* PDQ consumer block virt address */
1717 u32 cons_block_phys; /* PDQ consumer block phys address */
1718
1719 /* Keep local copies of Type 1 and Type 2 register data */
1720
1721 PI_TYPE_1_PROD_REG cmd_req_reg; /* Command Request register */
1722 PI_TYPE_1_PROD_REG cmd_rsp_reg; /* Command Response register */
1723 PI_TYPE_2_PROD_REG rcv_xmt_reg; /* Type 2 (RCV/XMT) register */
1724
1725 /* Storage for unicast and multicast address entries in adapter CAM */
1726
1727 u8 uc_table[1*FDDI_K_ALEN];
1728 u32 uc_count; /* number of unicast addresses */
1729 u8 mc_table[PI_CMD_ADDR_FILTER_K_SIZE*FDDI_K_ALEN];
1730 u32 mc_count; /* number of multicast addresses */
1731
1732 /* Current packet filter settings */
1733
1734 u32 ind_group_prom; /* LLC individual & group frame prom mode */
1735 u32 group_prom; /* LLC group (multicast) frame prom mode */
1736
1737 /* Link available flag needed to determine whether to drop outgoing packet requests */
1738
1739 u32 link_available; /* is link available? */
1740
1741 /* Resources to indicate reset type when resetting adapter */
1742
1743 u32 reset_type; /* skip or rerun diagnostics */
1744
1745 /* Store pointers to receive buffers for queue processing code */
1746
1747 char *p_rcv_buff_va[PI_RCV_DATA_K_NUM_ENTRIES];
1748
1749 /* Store pointers to transmit buffers for transmit completion code */
1750
1751 XMT_DRIVER_DESCR xmt_drv_descr_blk[PI_XMT_DATA_K_NUM_ENTRIES];
1752
1753 /* Transmit spinlocks */
1754
1755 spinlock_t lock;
1756
1757 /* Store device, bus-specific, and parameter information for this adapter */
1758
1759 struct net_device *dev; /* pointer to device structure */
1760 struct net_device *next;
1761 u32 bus_type; /* bus type (0 == PCI, 1 == EISA) */
1762 u16 base_addr; /* base I/O address (same as dev->base_addr) */
1763 struct pci_dev * pci_dev;
1764 u32 full_duplex_enb; /* FDDI Full Duplex enable (1 == on, 2 == off) */
1765 u32 req_ttrt; /* requested TTRT value (in 80ns units) */
1766 u32 burst_size; /* adapter burst size (enumerated) */
1767 u32 rcv_bufs_to_post; /* receive buffers to post for LLC host queue */
1768 u8 factory_mac_addr[FDDI_K_ALEN]; /* factory (on-board) MAC address */
1769
1770 /* Common FDDI statistics structure and private counters */
1771
1772 struct fddi_statistics stats;
1773
1774 u32 rcv_discards;
1775 u32 rcv_crc_errors;
1776 u32 rcv_frame_status_errors;
1777 u32 rcv_length_errors;
1778 u32 rcv_total_frames;
1779 u32 rcv_multicast_frames;
1780 u32 rcv_total_bytes;
1781
1782 u32 xmt_discards;
1783 u32 xmt_length_errors;
1784 u32 xmt_total_frames;
1785 u32 xmt_total_bytes;
1786 } DFX_board_t;
1787
1788 #endif /* #ifndef _DEFXX_H_ */
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