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[davej-history.git] / drivers / ide / sis5513.c
blobc00f3305a23a0b79823ea04d78bbd8e1122530ca
1 /*
2 * linux/drivers/ide/sis5513.c Version 0.11 June 9, 2000
3 *
4 * Copyright (C) 1999-2000 Andre Hedrick <andre@linux-ide.org>
5 * May be copied or modified under the terms of the GNU General Public License
6 *
7 * Thanks to SIS Taiwan for direct support and hardware.
8 * Tested and designed on the SiS620/5513 chipset.
9 */
10
11 #include <linux/config.h>
12 #include <linux/types.h>
13 #include <linux/kernel.h>
14 #include <linux/delay.h>
15 #include <linux/timer.h>
16 #include <linux/mm.h>
17 #include <linux/ioport.h>
18 #include <linux/blkdev.h>
19 #include <linux/hdreg.h>
20
21 #include <linux/interrupt.h>
22 #include <linux/pci.h>
23 #include <linux/init.h>
24 #include <linux/ide.h>
25
26 #include <asm/io.h>
27 #include <asm/irq.h>
28
29 #include "ide_modes.h"
30
31 #define DISPLAY_SIS_TIMINGS
32 #define SIS5513_DEBUG_DRIVE_INFO 0
33
34 static struct pci_dev *host_dev = NULL;
35
36 #define arraysize(x) (sizeof(x)/sizeof(*(x)))
37
38 #define SIS5513_FLAG_ATA_00 0x00000000
39 #define SIS5513_FLAG_ATA_16 0x00000001
40 #define SIS5513_FLAG_ATA_33 0x00000002
41 #define SIS5513_FLAG_ATA_66 0x00000004
42 #define SIS5513_FLAG_LATENCY 0x00000010
43
44 static const struct {
45 const char *name;
46 unsigned short host_id;
47 unsigned int flags;
48 } SiSHostChipInfo[] = {
49 { "SiS530", PCI_DEVICE_ID_SI_530, SIS5513_FLAG_ATA_66, },
50 { "SiS540", PCI_DEVICE_ID_SI_540, SIS5513_FLAG_ATA_66, },
51 { "SiS620", PCI_DEVICE_ID_SI_620, SIS5513_FLAG_ATA_66|SIS5513_FLAG_LATENCY, },
52 { "SiS630", PCI_DEVICE_ID_SI_630, SIS5513_FLAG_ATA_66|SIS5513_FLAG_LATENCY, },
53 { "SiS5591", PCI_DEVICE_ID_SI_5591, SIS5513_FLAG_ATA_33, },
54 { "SiS5597", PCI_DEVICE_ID_SI_5597, SIS5513_FLAG_ATA_33, },
55 { "SiS5600", PCI_DEVICE_ID_SI_5600, SIS5513_FLAG_ATA_33, },
56 { "SiS5511", PCI_DEVICE_ID_SI_5511, SIS5513_FLAG_ATA_16, },
57 };
58
59 #if 0
60
61 static struct _pio_mode_mapping {
62 byte data_active;
63 byte recovery;
64 byte pio_mode;
65 } pio_mode_mapping[] = {
66 { 8, 12, 0 },
67 { 6, 7, 1 },
68 { 4, 4, 2 },
69 { 3, 3, 3 },
70 { 3, 1, 4 }
71 };
72
73 static struct _dma_mode_mapping {
74 byte data_active;
75 byte recovery;
76 byte dma_mode;
77 } dma_mode_mapping[] = {
78 { 8, 8, 0 },
79 { 3, 2, 1 },
80 { 3, 1, 2 }
81 };
82
83 static struct _udma_mode_mapping {
84 byte cycle_time;
85 char * udma_mode;
86 } udma_mode_mapping[] = {
87 { 8, "Mode 0" },
88 { 6, "Mode 1" },
89 { 4, "Mode 2" },
90 { 3, "Mode 3" },
91 { 2, "Mode 4" },
92 { 0, "Undefined" }
93 };
94
95 static __inline__ char * find_udma_mode (byte cycle_time)
96 {
97 int n;
98
99 for (n = 0; n <= 4; n++)
100 if (udma_mode_mapping[n].cycle_time <= cycle_time)
101 return udma_mode_mapping[n].udma_mode;
102 return udma_mode_mapping[4].udma_mode;
103 }
104 #endif
105
106 #if defined(DISPLAY_SIS_TIMINGS) && defined(CONFIG_PROC_FS)
107 #include <linux/stat.h>
108 #include <linux/proc_fs.h>
109
110 static int sis_get_info(char *, char **, off_t, int);
111 extern int (*sis_display_info)(char *, char **, off_t, int); /* ide-proc.c */
112 static struct pci_dev *bmide_dev;
113
114 static char *cable_type[] = {
115 "80 pins",
116 "40 pins"
117 };
118
119 static char *recovery_time [] ={
120 "12 PCICLK", "1 PCICLK",
121 "2 PCICLK", "3 PCICLK",
122 "4 PCICLK", "5 PCICLCK",
123 "6 PCICLK", "7 PCICLCK",
124 "8 PCICLK", "9 PCICLCK",
125 "10 PCICLK", "11 PCICLK",
126 "13 PCICLK", "14 PCICLK",
127 "15 PCICLK", "15 PCICLK"
128 };
129
130 static char * cycle_time [] = {
131 "Undefined", "2 CLCK",
132 "3 CLK", "4 CLK",
133 "5 CLK", "6 CLK",
134 "7 CLK", "8 CLK"
135 };
136
137 static char * active_time [] = {
138 "8 PCICLK", "1 PCICLCK",
139 "2 PCICLK", "2 PCICLK",
140 "4 PCICLK", "5 PCICLK",
141 "6 PCICLK", "12 PCICLK"
142 };
143
144 static int sis_get_info (char *buffer, char **addr, off_t offset, int count)
145 {
146 int rc;
147 char *p = buffer;
148 byte reg,reg1;
149 u16 reg2, reg3;
150
151 p += sprintf(p, "--------------- Primary Channel ---------------- Secondary Channel -------------\n");
152 rc = pci_read_config_byte(bmide_dev, 0x4a, &reg);
153 p += sprintf(p, "Channel Status: %s \t \t \t \t %s \n",
154 (reg & 0x02) ? "On" : "Off",
155 (reg & 0x04) ? "On" : "Off");
156
157 rc = pci_read_config_byte(bmide_dev, 0x09, &reg);
158 p += sprintf(p, "Operation Mode: %s \t \t \t %s \n",
159 (reg & 0x01) ? "Native" : "Compatible",
160 (reg & 0x04) ? "Native" : "Compatible");
161
162 rc = pci_read_config_byte(bmide_dev, 0x48, &reg);
163 p += sprintf(p, "Cable Type: %s \t \t \t %s\n",
164 (reg & 0x10) ? cable_type[1] : cable_type[0],
165 (reg & 0x20) ? cable_type[1] : cable_type[0]);
166
167 rc = pci_read_config_word(bmide_dev, 0x4c, &reg2);
168 rc = pci_read_config_word(bmide_dev, 0x4e, &reg3);
169 p += sprintf(p, "Prefetch Count: %d \t \t \t \t %d\n",
170 reg2, reg3);
171
172 rc = pci_read_config_byte(bmide_dev, 0x4b, &reg);
173 p += sprintf(p, "Drive 0: Postwrite %s \t \t Postwrite %s\n",
174 (reg & 0x10) ? "Enabled" : "Disabled",
175 (reg & 0x40) ? "Enabled" : "Disabled");
176 p += sprintf(p, " Prefetch %s \t \t Prefetch %s\n",
177 (reg & 0x01) ? "Enabled" : "Disabled",
178 (reg & 0x04) ? "Enabled" : "Disabled");
179
180 rc = pci_read_config_byte(bmide_dev, 0x41, &reg);
181 rc = pci_read_config_byte(bmide_dev, 0x45, &reg1);
182 p += sprintf(p, " UDMA %s \t \t \t UDMA %s\n",
183 (reg & 0x80) ? "Enabled" : "Disabled",
184 (reg1 & 0x80) ? "Enabled" : "Disabled");
185 p += sprintf(p, " UDMA Cycle Time %s \t UDMA Cycle Time %s\n",
186 cycle_time[(reg & 0x70) >> 4], cycle_time[(reg1 & 0x70) >> 4]);
187 p += sprintf(p, " Data Active Time %s \t Data Active Time %s\n",
188 active_time[(reg & 0x07)], active_time[(reg1 &0x07)] );
189
190 rc = pci_read_config_byte(bmide_dev, 0x40, &reg);
191 rc = pci_read_config_byte(bmide_dev, 0x44, &reg1);
192 p += sprintf(p, " Data Recovery Time %s \t Data Recovery Time %s\n",
193 recovery_time[(reg & 0x0f)], recovery_time[(reg1 & 0x0f)]);
194
195
196 rc = pci_read_config_byte(bmide_dev, 0x4b, &reg);
197 p += sprintf(p, "Drive 1: Postwrite %s \t \t Postwrite %s\n",
198 (reg & 0x20) ? "Enabled" : "Disabled",
199 (reg & 0x80) ? "Enabled" : "Disabled");
200 p += sprintf(p, " Prefetch %s \t \t Prefetch %s\n",
201 (reg & 0x02) ? "Enabled" : "Disabled",
202 (reg & 0x08) ? "Enabled" : "Disabled");
203
204 rc = pci_read_config_byte(bmide_dev, 0x43, &reg);
205 rc = pci_read_config_byte(bmide_dev, 0x47, &reg1);
206 p += sprintf(p, " UDMA %s \t \t \t UDMA %s\n",
207 (reg & 0x80) ? "Enabled" : "Disabled",
208 (reg1 & 0x80) ? "Enabled" : "Disabled");
209 p += sprintf(p, " UDMA Cycle Time %s \t UDMA Cycle Time %s\n",
210 cycle_time[(reg & 0x70) >> 4], cycle_time[(reg1 & 0x70) >> 4]);
211 p += sprintf(p, " Data Active Time %s \t Data Active Time %s\n",
212 active_time[(reg & 0x07)], active_time[(reg1 &0x07)] );
213
214 rc = pci_read_config_byte(bmide_dev, 0x42, &reg);
215 rc = pci_read_config_byte(bmide_dev, 0x46, &reg1);
216 p += sprintf(p, " Data Recovery Time %s \t Data Recovery Time %s\n",
217 recovery_time[(reg & 0x0f)], recovery_time[(reg1 & 0x0f)]);
218 return p-buffer;
219 }
220 #endif /* defined(DISPLAY_SIS_TIMINGS) && defined(CONFIG_PROC_FS) */
221
222 byte sis_proc = 0;
223 extern char *ide_xfer_verbose (byte xfer_rate);
224
225 static void config_drive_art_rwp (ide_drive_t *drive)
226 {
227 ide_hwif_t *hwif = HWIF(drive);
228 struct pci_dev *dev = hwif->pci_dev;
229
230 byte reg4bh = 0;
231 byte rw_prefetch = (0x11 << drive->dn);
232
233 pci_read_config_byte(dev, 0x4b, &reg4bh);
234 if (drive->media != ide_disk)
235 return;
236
237 if ((reg4bh & rw_prefetch) != rw_prefetch)
238 pci_write_config_byte(dev, 0x4b, reg4bh|rw_prefetch);
239 }
240
241 static void config_art_rwp_pio (ide_drive_t *drive, byte pio)
242 {
243 ide_hwif_t *hwif = HWIF(drive);
244 struct pci_dev *dev = hwif->pci_dev;
245
246 byte timing, drive_pci, test1, test2;
247
248 unsigned short eide_pio_timing[6] = {600, 390, 240, 180, 120, 90};
249 unsigned short xfer_pio = drive->id->eide_pio_modes;
250
251 config_drive_art_rwp(drive);
252 pio = ide_get_best_pio_mode(drive, 255, pio, NULL);
253
254 if (xfer_pio> 4)
255 xfer_pio = 0;
256
257 if (drive->id->eide_pio_iordy > 0) {
258 for (xfer_pio = 5;
259 xfer_pio>0 &&
260 drive->id->eide_pio_iordy>eide_pio_timing[xfer_pio];
261 xfer_pio--);
262 } else {
263 xfer_pio = (drive->id->eide_pio_modes & 4) ? 0x05 :
264 (drive->id->eide_pio_modes & 2) ? 0x04 :
265 (drive->id->eide_pio_modes & 1) ? 0x03 : xfer_pio;
266 }
267
268 timing = (xfer_pio >= pio) ? xfer_pio : pio;
269
270 /*
271 * Mode 0 Mode 1 Mode 2 Mode 3 Mode 4
272 * Active time 8T (240ns) 6T (180ns) 4T (120ns) 3T (90ns) 3T (90ns)
273 * 0x41 2:0 bits 000 110 100 011 011
274 * Recovery time 12T (360ns) 7T (210ns) 4T (120ns) 3T (90ns) 1T (30ns)
275 * 0x40 3:0 bits 0000 0111 0100 0011 0001
276 * Cycle time 20T (600ns) 13T (390ns) 8T (240ns) 6T (180ns) 4T (120ns)
277 */
278
279 switch(drive->dn) {
280 case 0: drive_pci = 0x40; break;
281 case 1: drive_pci = 0x42; break;
282 case 2: drive_pci = 0x44; break;
283 case 3: drive_pci = 0x46; break;
284 default: return;
285 }
286
287 pci_read_config_byte(dev, drive_pci, &test1);
288 pci_read_config_byte(dev, drive_pci|0x01, &test2);
289
290 /*
291 * Do a blanket clear of active and recovery timings.
292 */
293
294 test1 &= ~0x07;
295 test2 &= ~0x0F;
296
297 switch(timing) {
298 case 4: test1 |= 0x01; test2 |= 0x03; break;
299 case 3: test1 |= 0x03; test2 |= 0x03; break;
300 case 2: test1 |= 0x04; test2 |= 0x04; break;
301 case 1: test1 |= 0x07; test2 |= 0x06; break;
302 default: break;
303 }
304
305 pci_write_config_byte(dev, drive_pci, test1);
306 pci_write_config_byte(dev, drive_pci|0x01, test2);
307 }
308
309 static int config_chipset_for_pio (ide_drive_t *drive, byte pio)
310 {
311 int err;
312 byte speed;
313
314 switch(pio) {
315 case 4: speed = XFER_PIO_4; break;
316 case 3: speed = XFER_PIO_3; break;
317 case 2: speed = XFER_PIO_2; break;
318 case 1: speed = XFER_PIO_1; break;
319 default: speed = XFER_PIO_0; break;
320 }
321
322 config_art_rwp_pio(drive, pio);
323 drive->current_speed = speed;
324 err = ide_config_drive_speed(drive, speed);
325 return err;
326 }
327
328 static int sis5513_tune_chipset (ide_drive_t *drive, byte speed)
329 {
330 ide_hwif_t *hwif = HWIF(drive);
331 struct pci_dev *dev = hwif->pci_dev;
332
333 byte drive_pci, test1, test2;
334 byte unmask, four_two, mask = 0;
335
336 if (host_dev) {
337 switch(host_dev->device) {
338 case PCI_DEVICE_ID_SI_530:
339 case PCI_DEVICE_ID_SI_540:
340 case PCI_DEVICE_ID_SI_620:
341 case PCI_DEVICE_ID_SI_630:
342 unmask = 0xF0;
343 four_two = 0x01;
344 break;
345 default:
346 unmask = 0xE0;
347 four_two = 0x00;
348 break;
349 }
350 } else {
351 unmask = 0xE0;
352 four_two = 0x00;
353 }
354
355 switch(drive->dn) {
356 case 0: drive_pci = 0x40;break;
357 case 1: drive_pci = 0x42;break;
358 case 2: drive_pci = 0x44;break;
359 case 3: drive_pci = 0x46;break;
360 default: return ide_dma_off;
361 }
362
363 pci_read_config_byte(dev, drive_pci, &test1);
364 pci_read_config_byte(dev, drive_pci|0x01, &test2);
365
366 if ((speed <= XFER_MW_DMA_2) && (test2 & 0x80)) {
367 pci_write_config_byte(dev, drive_pci|0x01, test2 & ~0x80);
368 pci_read_config_byte(dev, drive_pci|0x01, &test2);
369 } else {
370 pci_write_config_byte(dev, drive_pci|0x01, test2 & ~unmask);
371 }
372
373 switch(speed) {
374 #ifdef CONFIG_BLK_DEV_IDEDMA
375 case XFER_UDMA_5: /* can not do ultra mode 5 yet */
376 case XFER_UDMA_4: mask = 0x90; break;
377 case XFER_UDMA_3: mask = 0xA0; break;
378 case XFER_UDMA_2: mask = (four_two) ? 0xB0 : 0xA0; break;
379 case XFER_UDMA_1: mask = (four_two) ? 0xD0 : 0xC0; break;
380 case XFER_UDMA_0: mask = unmask; break;
381 case XFER_MW_DMA_2:
382 case XFER_MW_DMA_1:
383 case XFER_MW_DMA_0:
384 case XFER_SW_DMA_2:
385 case XFER_SW_DMA_1:
386 case XFER_SW_DMA_0: break;
387 #endif /* CONFIG_BLK_DEV_IDEDMA */
388 case XFER_PIO_4: return((int) config_chipset_for_pio(drive, 4));
389 case XFER_PIO_3: return((int) config_chipset_for_pio(drive, 3));
390 case XFER_PIO_2: return((int) config_chipset_for_pio(drive, 2));
391 case XFER_PIO_1: return((int) config_chipset_for_pio(drive, 1));
392 case XFER_PIO_0:
393 default: return((int) config_chipset_for_pio(drive, 0));
394 }
395
396 if (speed > XFER_MW_DMA_2)
397 pci_write_config_byte(dev, drive_pci|0x01, test2|mask);
398
399 drive->current_speed = speed;
400 return ((int) ide_config_drive_speed(drive, speed));
401 }
402
403 static void sis5513_tune_drive (ide_drive_t *drive, byte pio)
404 {
405 (void) config_chipset_for_pio(drive, pio);
406 }
407
408 #ifdef CONFIG_BLK_DEV_IDEDMA
409 /*
410 * ((id->hw_config & 0x4000|0x2000) && (HWIF(drive)->udma_four))
411 */
412 static int config_chipset_for_dma (ide_drive_t *drive, byte ultra)
413 {
414 struct hd_driveid *id = drive->id;
415 ide_hwif_t *hwif = HWIF(drive);
416
417 byte four_two = 0, speed = 0;
418 int err;
419
420 byte unit = (drive->select.b.unit & 0x01);
421 byte udma_66 = eighty_ninty_three(drive);
422
423 if (host_dev) {
424 switch(host_dev->device) {
425 case PCI_DEVICE_ID_SI_530:
426 case PCI_DEVICE_ID_SI_540:
427 case PCI_DEVICE_ID_SI_620:
428 case PCI_DEVICE_ID_SI_630:
429 four_two = 0x01; break;
430 default:
431 four_two = 0x00; break;
432 }
433 }
434
435 if ((id->dma_ultra & 0x0010) && (ultra) && (udma_66) && (four_two))
436 speed = XFER_UDMA_4;
437 else if ((id->dma_ultra & 0x0008) && (ultra) && (udma_66) && (four_two))
438 speed = XFER_UDMA_3;
439 else if ((id->dma_ultra & 0x0004) && (ultra))
440 speed = XFER_UDMA_2;
441 else if ((id->dma_ultra & 0x0002) && (ultra))
442 speed = XFER_UDMA_1;
443 else if ((id->dma_ultra & 0x0001) && (ultra))
444 speed = XFER_UDMA_0;
445 else if (id->dma_mword & 0x0004)
446 speed = XFER_MW_DMA_2;
447 else if (id->dma_mword & 0x0002)
448 speed = XFER_MW_DMA_1;
449 else if (id->dma_mword & 0x0001)
450 speed = XFER_MW_DMA_0;
451 else if (id->dma_1word & 0x0004)
452 speed = XFER_SW_DMA_2;
453 else if (id->dma_1word & 0x0002)
454 speed = XFER_SW_DMA_1;
455 else if (id->dma_1word & 0x0001)
456 speed = XFER_SW_DMA_0;
457 else
458 return ((int) ide_dma_off_quietly);
459
460 outb(inb(hwif->dma_base+2)|(1<<(5+unit)), hwif->dma_base+2);
461
462 err = sis5513_tune_chipset(drive, speed);
463
464 #if SIS5513_DEBUG_DRIVE_INFO
465 printk("%s: %s drive%d\n", drive->name, ide_xfer_verbose(speed), drive->dn);
466 #endif /* SIS5513_DEBUG_DRIVE_INFO */
467
468 return ((int) ((id->dma_ultra >> 11) & 3) ? ide_dma_on :
469 ((id->dma_ultra >> 8) & 7) ? ide_dma_on :
470 ((id->dma_mword >> 8) & 7) ? ide_dma_on :
471 ((id->dma_1word >> 8) & 7) ? ide_dma_on :
472 ide_dma_off_quietly);
473 }
474
475 static int config_drive_xfer_rate (ide_drive_t *drive)
476 {
477 struct hd_driveid *id = drive->id;
478 ide_dma_action_t dma_func = ide_dma_off_quietly;
479
480 if (id && (id->capability & 1) && HWIF(drive)->autodma) {
481 /* Consult the list of known "bad" drives */
482 if (ide_dmaproc(ide_dma_bad_drive, drive)) {
483 dma_func = ide_dma_off;
484 goto fast_ata_pio;
485 }
486 dma_func = ide_dma_off_quietly;
487 if (id->field_valid & 4) {
488 if (id->dma_ultra & 0x001F) {
489 /* Force if Capable UltraDMA */
490 dma_func = config_chipset_for_dma(drive, 1);
491 if ((id->field_valid & 2) &&
492 (dma_func != ide_dma_on))
493 goto try_dma_modes;
494 }
495 } else if (id->field_valid & 2) {
496 try_dma_modes:
497 if ((id->dma_mword & 0x0007) ||
498 (id->dma_1word & 0x0007)) {
499 /* Force if Capable regular DMA modes */
500 dma_func = config_chipset_for_dma(drive, 0);
501 if (dma_func != ide_dma_on)
502 goto no_dma_set;
503 }
504 } else if ((ide_dmaproc(ide_dma_good_drive, drive)) &&
505 (id->eide_dma_time > 150)) {
506 /* Consult the list of known "good" drives */
507 dma_func = config_chipset_for_dma(drive, 0);
508 if (dma_func != ide_dma_on)
509 goto no_dma_set;
510 } else {
511 goto fast_ata_pio;
512 }
513 } else if ((id->capability & 8) || (id->field_valid & 2)) {
514 fast_ata_pio:
515 dma_func = ide_dma_off_quietly;
516 no_dma_set:
517 (void) config_chipset_for_pio(drive, 5);
518 }
519
520 return HWIF(drive)->dmaproc(dma_func, drive);
521 }
522
523 /*
524 * sis5513_dmaproc() initiates/aborts (U)DMA read/write operations on a drive.
525 */
526 int sis5513_dmaproc (ide_dma_action_t func, ide_drive_t *drive)
527 {
528 switch (func) {
529 case ide_dma_check:
530 config_drive_art_rwp(drive);
531 config_art_rwp_pio(drive, 5);
532 return config_drive_xfer_rate(drive);
533 default:
534 break;
535 }
536 return ide_dmaproc(func, drive); /* use standard DMA stuff */
537 }
538 #endif /* CONFIG_BLK_DEV_IDEDMA */
539
540 unsigned int __init pci_init_sis5513 (struct pci_dev *dev, const char *name)
541 {
542 struct pci_dev *host;
543 int i = 0;
544 byte latency = 0;
545
546 pci_read_config_byte(dev, PCI_LATENCY_TIMER, &latency);
547
548 for (i = 0; i < arraysize (SiSHostChipInfo) && !host_dev; i++) {
549 host = pci_find_device (PCI_VENDOR_ID_SI,
550 SiSHostChipInfo[i].host_id,
551 NULL);
552 if (!host)
553 continue;
554
555 host_dev = host;
556 printk(SiSHostChipInfo[i].name);
557 printk("\n");
558 if (SiSHostChipInfo[i].flags & SIS5513_FLAG_LATENCY) {
559 if (latency != 0x10)
560 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x10);
561 }
562 }
563
564 if (host_dev) {
565 byte reg52h = 0;
566
567 pci_read_config_byte(dev, 0x52, &reg52h);
568 if (!(reg52h & 0x04)) {
569 /* set IDE controller to operate in Compabitility mode only */
570 pci_write_config_byte(dev, 0x52, reg52h|0x04);
571 }
572 #if defined(DISPLAY_SIS_TIMINGS) && defined(CONFIG_PROC_FS)
573 if (!sis_proc) {
574 sis_proc = 1;
575 bmide_dev = dev;
576 sis_display_info = &sis_get_info;
577 }
578 #endif /* defined(DISPLAY_SIS_TIMINGS) && defined(CONFIG_PROC_FS) */
579 }
580 return 0;
581 }
582
583 unsigned int __init ata66_sis5513 (ide_hwif_t *hwif)
584 {
585 byte reg48h = 0, ata66 = 0;
586 byte mask = hwif->channel ? 0x20 : 0x10;
587 pci_read_config_byte(hwif->pci_dev, 0x48, &reg48h);
588
589 if (host_dev) {
590 switch(host_dev->device) {
591 case PCI_DEVICE_ID_SI_530:
592 case PCI_DEVICE_ID_SI_540:
593 case PCI_DEVICE_ID_SI_620:
594 case PCI_DEVICE_ID_SI_630:
595 ata66 = (reg48h & mask) ? 0 : 1;
596 default:
597 break;
598 }
599 }
600 return (ata66);
601 }
602
603 void __init ide_init_sis5513 (ide_hwif_t *hwif)
604 {
605
606 hwif->irq = hwif->channel ? 15 : 14;
607
608 hwif->tuneproc = &sis5513_tune_drive;
609 hwif->speedproc = &sis5513_tune_chipset;
610
611 if (!(hwif->dma_base))
612 return;
613
614 if (host_dev) {
615 switch(host_dev->device) {
616 #ifdef CONFIG_BLK_DEV_IDEDMA
617 case PCI_DEVICE_ID_SI_530:
618 case PCI_DEVICE_ID_SI_540:
619 case PCI_DEVICE_ID_SI_620:
620 case PCI_DEVICE_ID_SI_630:
621 case PCI_DEVICE_ID_SI_5600:
622 case PCI_DEVICE_ID_SI_5597:
623 case PCI_DEVICE_ID_SI_5591:
624 hwif->autodma = 1;
625 hwif->dmaproc = &sis5513_dmaproc;
626 break;
627 #endif /* CONFIG_BLK_DEV_IDEDMA */
628 default:
629 hwif->autodma = 0;
630 break;
631 }
632 }
633 return;
634 }
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