1 /* $Id: r2300_misc.S,v 1.1.1.1 1997/06/01 03:16:42 ralf Exp $
2 * r2300_misc.S: Misc. exception handling code for R3000/R2000.
4 * Copyright (C) 1994, 1995, 1996 by Ralf Baechle and Andreas Busse
6 * Multi-cpu abstraction reworking:
7 * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
9 #include <linux/config.h>
12 #include <asm/bootinfo.h>
13 #include <asm/cachectl.h>
14 #include <asm/fpregdef.h>
15 #include <asm/mipsconfig.h>
16 #include <asm/mipsregs.h>
18 #include <asm/pgtable.h>
19 #include <asm/processor.h>
20 #include <asm/regdef.h>
21 #include <asm/stackframe.h>
28 NESTED(r2300_handle_tlbl, PT_SIZE, sp)
30 /* Check whether this is a refill or an invalid exception */
33 ori k0,0xfff # clear ASID...
34 xori k0,0xfff # in BadVAddr
35 andi k1,0xfc0 # get current ASID
36 or k0,k1 # make new entryhi
47 bgez k0,invalid_tlbl # bad addr in c0_badvaddr
50 /* Damn... The next nop is required on the R4400PC V5.0, but
51 * I don't know why - at least there is no documented
52 * reason as for the others :-(
53 * And I haven't tested it as being necessary on R3000 - PMA.
54 * (The R3000 pipeline has only 5 stages, so it's probably not
60 /* OK, this is a double fault. Let's see whether this is
61 * due to an invalid entry in the page_table.
63 /* used to be dmfc0 */
65 /* FIXME: This srl/sll sequence is as it is for the R4xx0,
66 * and I suspect that it should be different for
68 * (No, it's the assembler way to do
69 * k0 = k0 / PAGE_SIZE;
70 * k0 = k0 * sizeof(pte_t)
71 * Acutally the R4xx0 code will have to change when
72 * switching to 64 bit ... -- Ralf)
79 andi k1,(_PAGE_PRESENT|_PAGE_ACCESSED)
80 bnez k1,reload_pgd_entries
86 PRINT("Double fault caused by invalid entries in pgd:\n")
88 PRINT("Double fault address : %08lx\n")
90 PRINT("c0_epc : %08lx\n")
100 jal dump_list_current
106 PANIC("Corrupted pagedir")
110 #endif /* CONF_DEBUG_TLB */
112 /* Load missing pair of entries from the pgd and return. */
114 lw k0,(k1) # Never causes nested exception
115 mfc0 k1,CP0_EPC # get the return PC
116 srl k0,12 # Convert to EntryLo format
123 /* We don't know whether the original access was read or
124 * write, so return and see what happens...
129 /* Handle invalid exception
131 * There are two possible causes for an invalid (tlbl)
133 * 1) pages with present bit set but the valid bit clear
134 * 2) nonexistant pages
135 * Case one needs fast handling, therefore don't save
138 * k0 contains c0_index.
141 #ifdef CONFIG_TLB_SHUTDOWN
142 /* Remove entry so we don't need to care later
143 * For sake of the pipeline the tlbwi insn has been moved down.
144 * Moving it around is juggling with explosives...
146 /* FIXME: Why is Ralf setting bit 3 of k1? This may need to
147 * be changed for R[236]000! PMA
148 * (The new ENTRYHI value will then point represent a
149 * inique virtual address outside the 32 bit address
150 * limit. This is just paranoia to avoid a tlb
151 * shutdown. This whole part of the routine is probably
152 * no longer required and can be removed -- Ralf)
156 sll k0,12 # make it EntryHi format
158 mtc0 zero,CP0_ENTRYLO0
160 /* Test present bit in entry */
162 /* FIXME: This srl/sll sequence is as it is for the R4xx0,
163 * and I suspect that it should be different for
165 * (No, it's the assembler way to do
166 * k0 = k0 / PAGE_SIZE;
167 * k0 = k0 * sizeof(pte_t)
168 * Acutally the R4xx0 code will have to change when
169 * switching to 64 bit ... -- Ralf)
173 #ifdef CONFIG_TLB_SHUTDOWN
179 andi k1,(_PAGE_PRESENT|_PAGE_READ)
180 xori k1,(_PAGE_PRESENT|_PAGE_READ)
185 /* Present and read bits are set -> set valid and accessed bits */
186 ori k1,(_PAGE_VALID|_PAGE_ACCESSED)
194 /* Page doesn't exist. Lots of work which is less important
195 * for speed needs to be done, so hand it all over to the
196 * kernel memory management routines.
203 /* a0 (struct pt_regs *) regs
204 * a1 (unsigned long) 0 for read access
205 * a2 (unsigned long) faulting virtual address
213 END(r2300_handle_tlbl)
218 NESTED(r2300_handle_tlbs, PT_SIZE, sp)
220 /* It is impossible that is a nested reload exception.
221 * Therefore this must be a invalid exception.
222 * Two possible cases:
223 * 1) Page exists but not dirty.
224 * 2) Page doesn't exist yet. Hand over to the kernel.
226 * Test whether present bit in entry is set
228 /* used to be dmfc0 */
230 /* FIXME: This srl/sll sequence is as it is for the R4xx0,
231 * and I suspect that it should be different for
239 tlbp # find faulting entry
240 andi k1,(_PAGE_PRESENT|_PAGE_WRITE)
241 xori k1,(_PAGE_PRESENT|_PAGE_WRITE)
246 /* Present and writable bits set: set accessed and dirty bits. */
247 ori k1,k1,(_PAGE_ACCESSED|_PAGE_MODIFIED| \
248 _PAGE_VALID|_PAGE_DIRTY)
250 /* Now reload the entry into the TLB */
251 /* FIXME: Why has Ralf set bit 2? Should it be different for
253 * (The ori/xori combination actually _clears_ bit 2.
254 * This is required for the R4xx0 these CPUs always
255 * map page pairs; a page pair of 4k pages therfore
256 * has always an address with bit 2 set to zero. -- Ralf)
273 /* Page doesn't exist. Lots of work which is less important
274 * for speed needs to be done, so hand it all over to the
275 * kernel memory management routines.
279 #ifdef CONFIG_TLB_SHUTDOWN
280 /* Remove entry so we don't need to care later */
282 #ifdef CONF_DEBUG_TLB
285 /* We got a tlbs exception but found no matching entry in
286 * the tlb. This should never happen. Paranoia makes us
294 PRINT("c0_badvaddr == %08lx\n")
296 PRINT("c0_index == %08x\n")
298 PRINT("c0_entryhi == %08x\n")
302 PANIC("Tlbs or tlbm exception with no matching entry in tlb")
307 #endif /* CONF_DEBUG_TLB */
308 /* FIXME: Why is Ralf setting bit 3 of k1? This may need to
309 * be changed for R[236]000! PMA
310 * (The new ENTRYHI value will then point represent a
311 * inique virtual address outside the 32 bit address
312 * limit. This is just paranoia to avoid a tlb
313 * shutdown. This whole part of the routine is probably
314 * no longer required and can be removed -- Ralf)
320 mtc0 zero,CP0_ENTRYLO0
322 nop # R4000 V2.2 requires 4 NOPs
326 #endif /* CONFIG_TLB_SHUTDOWN */
332 /* a0 (struct pt_regs *) regs
333 * a1 (unsigned long) 1 for write access
334 * a2 (unsigned long) faulting virtual address
342 END(r2300_handle_tlbs)
346 NESTED(r2300_handle_mod, PT_SIZE, sp)
348 /* Two possible cases:
349 * 1) Page is writable but not dirty -> set dirty and return
350 * 2) Page is not writable -> call C handler
352 /* used to be dmfc0 */
354 /* FIXME: This srl/sll sequence is as it is for the R4xx0,
355 * and I suspect that it should be different for
363 tlbp # find faulting entry
369 /* Present and writable bits set: set accessed and dirty bits. */
370 ori k1,(_PAGE_ACCESSED|_PAGE_DIRTY)
372 /* Now reload the entry into the tlb */
373 /* FIXME: Why has Ralf set bit 2? Should it be different for
375 * (The ori/xori combination actually _clears_ bit 2.
376 * This is required for the R4xx0 these CPUs always
377 * map page pairs; a page pair of 4k pages therfore
378 * has always an address with bit 2 set to zero. -- Ralf)
396 END(r2300_handle_mod)