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Import 2.4.0-test2pre7
[davej-history.git] / drivers / net / dmfe.c
blobb425513b04cd8d44086d0fd2a4320eb8eba942e1
1 /*
2 dmfe.c: Version 1.30 06/11/2000
3
4 A Davicom DM9102(A)/DM9132/DM9801 fast ethernet driver for Linux.
5 Copyright (C) 1997 Sten Wang
6 (C)Copyright 1997-1998 DAVICOM Semiconductor,Inc. All Rights Reserved.
7
8 This program is free software; you can redistribute it and/or
9 modify it under the terms of the GNU General Public License
10 as published by the Free Software Foundation; either version 2
11 of the License, or (at your option) any later version.
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18
19 Compiler command:
20 "gcc -DMODULE -D__KERNEL__ -I/usr/src/linux/net/inet -Wall
21 -Wstrict-prototypes -O6 -c dmfe.c"
22 OR
23 "gcc -DMODULE -D__KERNEL__ -I/usr/src/linux/net -Wall
24 -Wstrict-prototypes -O6 -c dmfe.c"
25
26 The following steps teach you how to active DM9102 board:
27 1. Used the upper compiler command to compile dmfe.c
28 2. insert dmfe module into kernel
29 "insmod dmfe" ;;Auto Detection Mode
30 "insmod dmfe mode=0" ;;Force 10M Half Duplex
31 "insmod dmfe mode=1" ;;Force 100M Half Duplex
32 "insmod dmfe mode=4" ;;Force 10M Full Duplex
33 "insmod dmfe mode=5" ;;Force 100M Full Duplex
34 3. config a dm9102 network interface
35 "ifconfig eth0 172.22.3.18"
36 4. active the IP routing table
37 "route add -net 172.22.3.0 eth0"
38 5. Well done. Your DM9102 adapter actived now.
39
40 Author: Sten Wang, 886-3-5798797-8517, E-mail: sten_wang@davicom.com.tw
41
42 Date: 10/28,1998
43
44 (C)Copyright 1997-1998 DAVICOM Semiconductor, Inc. All Rights Reserved.
45
46 Marcelo Tosatti <marcelo@conectiva.com.br> :
47 Made it compile in 2.3 (device to net_device)
48
49 Alan Cox <alan@redhat.com> :
50 Cleaned up for kernel merge.
51 Removed the back compatibility support
52 Reformatted, fixing spelling etc as I went
53 Removed IRQ 0-15 assumption
54
55 Jeff Garzik <jgarzik@mandrakesoft.com> :
56 Updated to use new PCI driver API.
57 Resource usage cleanups.
58 Report driver version to user.
59
60 TODO
61
62 Implement pci_driver::suspend() and pci_driver::resume()
63 power management methods.
64
65 Check and fix on 64bit and big endian boxes.
66
67 Test and make sure PCI latency is now correct for all cases.
68
69 */
70
71 #define DMFE_VERSION "1.30 (June 11, 2000)"
72
73 #include <linux/module.h>
74
75 #include <linux/kernel.h>
76 #include <linux/sched.h>
77 #include <linux/string.h>
78 #include <linux/timer.h>
79 #include <linux/ptrace.h>
80 #include <linux/errno.h>
81 #include <linux/ioport.h>
82 #include <linux/malloc.h>
83 #include <linux/interrupt.h>
84 #include <linux/pci.h>
85 #include <linux/init.h>
86 #include <linux/version.h>
87 #include <linux/netdevice.h>
88 #include <linux/etherdevice.h>
89 #include <linux/skbuff.h>
90 #include <linux/delay.h>
91
92 #include <asm/processor.h>
93 #include <asm/bitops.h>
94 #include <asm/io.h>
95 #include <asm/dma.h>
96
97
98
99 /* Board/System/Debug information/definition ---------------- */
100 #define PCI_DM9132_ID 0x91321282 /* Davicom DM9132 ID */
101 #define PCI_DM9102_ID 0x91021282 /* Davicom DM9102 ID */
102 #define PCI_DM9100_ID 0x91001282 /* Davicom DM9100 ID */
103
104 #define DMFE_SUCC 0
105 #define DM9102_IO_SIZE 0x80
106 #define DM9102A_IO_SIZE 0x100
107 #define TX_FREE_DESC_CNT 0xc /* Tx packet count */
108 #define TX_MAX_SEND_CNT 0x1 /* Maximum tx packet per time */
109 #define TX_DESC_CNT 0x10 /* Allocated Tx descriptors */
110 #define RX_DESC_CNT 0x10 /* Allocated Rx descriptors */
111 #define DESC_ALL_CNT TX_DESC_CNT+RX_DESC_CNT
112 #define TX_BUF_ALLOC 0x600
113 #define RX_ALLOC_SIZE 0x620
114 #define DM910X_RESET 1
115 #define CR6_DEFAULT 0x00280000 /* SF, HD */
116 #define CR7_DEFAULT 0x1a2cd
117 #define CR15_DEFAULT 0x06 /* TxJabber RxWatchdog */
118 #define TDES0_ERR_MASK 0x4302 /* TXJT, LC, EC, FUE */
119 #define MAX_PACKET_SIZE 1514
120 #define DMFE_MAX_MULTICAST 14
121 #define RX_MAX_TRAFFIC 0x14000
122 #define MAX_CHECK_PACKET 0x8000
123
124 #define DMFE_10MHF 0
125 #define DMFE_100MHF 1
126 #define DMFE_10MFD 4
127 #define DMFE_100MFD 5
128 #define DMFE_AUTO 8
129
130 #define DMFE_TIMER_WUT jiffies+(HZ*2)/2 /* timer wakeup time : 1 second */
131 #define DMFE_TX_TIMEOUT ((HZ*3)/2) /* tx packet time-out time 1.5 s" */
132
133 #define DMFE_DBUG(dbug_now, msg, vaule) if (dmfe_debug || dbug_now) printk("DBUG: %s %x\n", msg, vaule)
134
135 #define DELAY_5US udelay(5) /* udelay scale 1 usec */
136
137 #define DELAY_1US udelay(1) /* udelay scale 1 usec */
138
139 #define SHOW_MEDIA_TYPE(mode) printk(KERN_WARNING "dmfe: Change Speed to %sMhz %s duplex\n",mode & 1 ?"100":"10", mode & 4 ? "full":"half");
140
141
142 /* CR9 definition: SROM/MII */
143 #define CR9_SROM_READ 0x4800
144 #define CR9_SRCS 0x1
145 #define CR9_SRCLK 0x2
146 #define CR9_CRDOUT 0x8
147 #define SROM_DATA_0 0x0
148 #define SROM_DATA_1 0x4
149 #define PHY_DATA_1 0x20000
150 #define PHY_DATA_0 0x00000
151 #define MDCLKH 0x10000
152
153 #define SROM_CLK_WRITE(data, ioaddr) outl(data|CR9_SROM_READ|CR9_SRCS,ioaddr);DELAY_5US;outl(data|CR9_SROM_READ|CR9_SRCS|CR9_SRCLK,ioaddr);DELAY_5US;outl(data|CR9_SROM_READ|CR9_SRCS,ioaddr);DELAY_5US;
154
155 #define __CHK_IO_SIZE(pci_id, dev_rev) ( ((pci_id)==PCI_DM9132_ID) || ((dev_rev) >= 0x02000030) ) ? DM9102A_IO_SIZE: DM9102_IO_SIZE
156 #define CHK_IO_SIZE(pci_dev, dev_rev) \
157 __CHK_IO_SIZE(((pci_dev)->device << 16) | (pci_dev)->vendor, dev_rev)
158
159
160 /* Structure/enum declaration ------------------------------- */
161 struct tx_desc {
162 u32 tdes0, tdes1, tdes2, tdes3;
163 u32 tx_skb_ptr;
164 u32 tx_buf_ptr;
165 u32 next_tx_desc;
166 u32 reserved;
167 };
168
169 struct rx_desc {
170 u32 rdes0, rdes1, rdes2, rdes3;
171 u32 rx_skb_ptr;
172 u32 rx_buf_ptr;
173 u32 next_rx_desc;
174 u32 reserved;
175 };
176
177 struct dmfe_board_info {
178 u32 chip_id; /* Chip vendor/Device ID */
179 u32 chip_revision; /* Chip revision */
180 struct net_device *next_dev; /* next device */
181
182 struct pci_dev *net_dev; /* PCI device */
183
184 unsigned long ioaddr; /* I/O base address */
185 u32 cr0_data;
186 u32 cr5_data;
187 u32 cr6_data;
188 u32 cr7_data;
189 u32 cr15_data;
190
191 /* descriptor pointer */
192 unsigned char *buf_pool_ptr; /* Tx buffer pool memory */
193 unsigned char *buf_pool_start; /* Tx buffer pool align dword */
194 unsigned char *desc_pool_ptr; /* descriptor pool memory */
195 struct tx_desc *first_tx_desc;
196 struct tx_desc *tx_insert_ptr;
197 struct tx_desc *tx_remove_ptr;
198 struct rx_desc *first_rx_desc;
199 struct rx_desc *rx_insert_ptr;
200 struct rx_desc *rx_ready_ptr; /* packet come pointer */
201 u32 tx_packet_cnt; /* transmitted packet count */
202 u32 tx_queue_cnt; /* wait to send packet count */
203 u32 rx_avail_cnt; /* available rx descriptor count */
204 u32 interval_rx_cnt; /* rx packet count a callback time */
205
206 u16 phy_id2; /* Phyxcer ID2 */
207
208 u8 media_mode; /* user specify media mode */
209 u8 op_mode; /* real work media mode */
210 u8 phy_addr;
211 u8 link_failed; /* Ever link failed */
212 u8 wait_reset; /* Hardware failed, need to reset */
213 u8 in_reset_state; /* Now driver in reset routine */
214 u8 rx_error_cnt; /* recievd abnormal case count */
215 u8 dm910x_chk_mode; /* Operating mode check */
216 struct timer_list timer;
217 struct enet_statistics stats; /* statistic counter */
218 unsigned char srom[128];
219 };
220
221 enum dmfe_offsets {
222 DCR0 = 0, DCR1 = 0x08, DCR2 = 0x10, DCR3 = 0x18, DCR4 = 0x20, DCR5 = 0x28,
223 DCR6 = 0x30, DCR7 = 0x38, DCR8 = 0x40, DCR9 = 0x48, DCR10 = 0x50, DCR11 = 0x58,
224 DCR12 = 0x60, DCR13 = 0x68, DCR14 = 0x70, DCR15 = 0x78
225 };
226
227 enum dmfe_CR6_bits {
228 CR6_RXSC = 0x2, CR6_PBF = 0x8, CR6_PM = 0x40, CR6_PAM = 0x80, CR6_FDM = 0x200,
229 CR6_TXSC = 0x2000, CR6_STI = 0x100000, CR6_SFT = 0x200000, CR6_RXA = 0x40000000,
230 CR6_NO_PURGE = 0x20000000
231 };
232
233 /* Global variable declaration ----------------------------- */
234 static int dmfe_debug = 0;
235 static unsigned char dmfe_media_mode = 8;
236 static u32 dmfe_cr6_user_set = 0;
237
238 /* For module input parameter */
239 static int debug = 0;
240 static u32 cr6set = 0;
241 static unsigned char mode = 8;
242 static u8 chkmode = 1;
243
244 static unsigned long CrcTable[256] =
245 {
246 0x00000000L, 0x77073096L, 0xEE0E612CL, 0x990951BAL,
247 0x076DC419L, 0x706AF48FL, 0xE963A535L, 0x9E6495A3L,
248 0x0EDB8832L, 0x79DCB8A4L, 0xE0D5E91EL, 0x97D2D988L,
249 0x09B64C2BL, 0x7EB17CBDL, 0xE7B82D07L, 0x90BF1D91L,
250 0x1DB71064L, 0x6AB020F2L, 0xF3B97148L, 0x84BE41DEL,
251 0x1ADAD47DL, 0x6DDDE4EBL, 0xF4D4B551L, 0x83D385C7L,
252 0x136C9856L, 0x646BA8C0L, 0xFD62F97AL, 0x8A65C9ECL,
253 0x14015C4FL, 0x63066CD9L, 0xFA0F3D63L, 0x8D080DF5L,
254 0x3B6E20C8L, 0x4C69105EL, 0xD56041E4L, 0xA2677172L,
255 0x3C03E4D1L, 0x4B04D447L, 0xD20D85FDL, 0xA50AB56BL,
256 0x35B5A8FAL, 0x42B2986CL, 0xDBBBC9D6L, 0xACBCF940L,
257 0x32D86CE3L, 0x45DF5C75L, 0xDCD60DCFL, 0xABD13D59L,
258 0x26D930ACL, 0x51DE003AL, 0xC8D75180L, 0xBFD06116L,
259 0x21B4F4B5L, 0x56B3C423L, 0xCFBA9599L, 0xB8BDA50FL,
260 0x2802B89EL, 0x5F058808L, 0xC60CD9B2L, 0xB10BE924L,
261 0x2F6F7C87L, 0x58684C11L, 0xC1611DABL, 0xB6662D3DL,
262 0x76DC4190L, 0x01DB7106L, 0x98D220BCL, 0xEFD5102AL,
263 0x71B18589L, 0x06B6B51FL, 0x9FBFE4A5L, 0xE8B8D433L,
264 0x7807C9A2L, 0x0F00F934L, 0x9609A88EL, 0xE10E9818L,
265 0x7F6A0DBBL, 0x086D3D2DL, 0x91646C97L, 0xE6635C01L,
266 0x6B6B51F4L, 0x1C6C6162L, 0x856530D8L, 0xF262004EL,
267 0x6C0695EDL, 0x1B01A57BL, 0x8208F4C1L, 0xF50FC457L,
268 0x65B0D9C6L, 0x12B7E950L, 0x8BBEB8EAL, 0xFCB9887CL,
269 0x62DD1DDFL, 0x15DA2D49L, 0x8CD37CF3L, 0xFBD44C65L,
270 0x4DB26158L, 0x3AB551CEL, 0xA3BC0074L, 0xD4BB30E2L,
271 0x4ADFA541L, 0x3DD895D7L, 0xA4D1C46DL, 0xD3D6F4FBL,
272 0x4369E96AL, 0x346ED9FCL, 0xAD678846L, 0xDA60B8D0L,
273 0x44042D73L, 0x33031DE5L, 0xAA0A4C5FL, 0xDD0D7CC9L,
274 0x5005713CL, 0x270241AAL, 0xBE0B1010L, 0xC90C2086L,
275 0x5768B525L, 0x206F85B3L, 0xB966D409L, 0xCE61E49FL,
276 0x5EDEF90EL, 0x29D9C998L, 0xB0D09822L, 0xC7D7A8B4L,
277 0x59B33D17L, 0x2EB40D81L, 0xB7BD5C3BL, 0xC0BA6CADL,
278 0xEDB88320L, 0x9ABFB3B6L, 0x03B6E20CL, 0x74B1D29AL,
279 0xEAD54739L, 0x9DD277AFL, 0x04DB2615L, 0x73DC1683L,
280 0xE3630B12L, 0x94643B84L, 0x0D6D6A3EL, 0x7A6A5AA8L,
281 0xE40ECF0BL, 0x9309FF9DL, 0x0A00AE27L, 0x7D079EB1L,
282 0xF00F9344L, 0x8708A3D2L, 0x1E01F268L, 0x6906C2FEL,
283 0xF762575DL, 0x806567CBL, 0x196C3671L, 0x6E6B06E7L,
284 0xFED41B76L, 0x89D32BE0L, 0x10DA7A5AL, 0x67DD4ACCL,
285 0xF9B9DF6FL, 0x8EBEEFF9L, 0x17B7BE43L, 0x60B08ED5L,
286 0xD6D6A3E8L, 0xA1D1937EL, 0x38D8C2C4L, 0x4FDFF252L,
287 0xD1BB67F1L, 0xA6BC5767L, 0x3FB506DDL, 0x48B2364BL,
288 0xD80D2BDAL, 0xAF0A1B4CL, 0x36034AF6L, 0x41047A60L,
289 0xDF60EFC3L, 0xA867DF55L, 0x316E8EEFL, 0x4669BE79L,
290 0xCB61B38CL, 0xBC66831AL, 0x256FD2A0L, 0x5268E236L,
291 0xCC0C7795L, 0xBB0B4703L, 0x220216B9L, 0x5505262FL,
292 0xC5BA3BBEL, 0xB2BD0B28L, 0x2BB45A92L, 0x5CB36A04L,
293 0xC2D7FFA7L, 0xB5D0CF31L, 0x2CD99E8BL, 0x5BDEAE1DL,
294 0x9B64C2B0L, 0xEC63F226L, 0x756AA39CL, 0x026D930AL,
295 0x9C0906A9L, 0xEB0E363FL, 0x72076785L, 0x05005713L,
296 0x95BF4A82L, 0xE2B87A14L, 0x7BB12BAEL, 0x0CB61B38L,
297 0x92D28E9BL, 0xE5D5BE0DL, 0x7CDCEFB7L, 0x0BDBDF21L,
298 0x86D3D2D4L, 0xF1D4E242L, 0x68DDB3F8L, 0x1FDA836EL,
299 0x81BE16CDL, 0xF6B9265BL, 0x6FB077E1L, 0x18B74777L,
300 0x88085AE6L, 0xFF0F6A70L, 0x66063BCAL, 0x11010B5CL,
301 0x8F659EFFL, 0xF862AE69L, 0x616BFFD3L, 0x166CCF45L,
302 0xA00AE278L, 0xD70DD2EEL, 0x4E048354L, 0x3903B3C2L,
303 0xA7672661L, 0xD06016F7L, 0x4969474DL, 0x3E6E77DBL,
304 0xAED16A4AL, 0xD9D65ADCL, 0x40DF0B66L, 0x37D83BF0L,
305 0xA9BCAE53L, 0xDEBB9EC5L, 0x47B2CF7FL, 0x30B5FFE9L,
306 0xBDBDF21CL, 0xCABAC28AL, 0x53B39330L, 0x24B4A3A6L,
307 0xBAD03605L, 0xCDD70693L, 0x54DE5729L, 0x23D967BFL,
308 0xB3667A2EL, 0xC4614AB8L, 0x5D681B02L, 0x2A6F2B94L,
309 0xB40BBE37L, 0xC30C8EA1L, 0x5A05DF1BL, 0x2D02EF8DL
310 };
311
312 /* function declaration ------------------------------------- */
313 static int dmfe_open(struct net_device *);
314 static int dmfe_start_xmit(struct sk_buff *, struct net_device *);
315 static int dmfe_stop(struct net_device *);
316 static struct enet_statistics *dmfe_get_stats(struct net_device *);
317 static void dmfe_set_filter_mode(struct net_device *);
318 static int dmfe_do_ioctl(struct net_device *, struct ifreq *, int);
319 static u16 read_srom_word(long, int);
320 static void dmfe_interrupt(int, void *, struct pt_regs *);
321 static void dmfe_descriptor_init(struct dmfe_board_info *, u32);
322 static void allocated_rx_buffer(struct dmfe_board_info *);
323 static void update_cr6(u32, u32);
324 static void send_filter_frame(struct net_device *, int);
325 static void dm9132_id_table(struct net_device *, int);
326 static u16 phy_read(u32, u8, u8, u32);
327 static void phy_write(u32, u8, u8, u16, u32);
328 static void phy_write_1bit(u32, u32);
329 static u16 phy_read_1bit(u32);
330 static void dmfe_sense_speed(struct dmfe_board_info *);
331 static void dmfe_process_mode(struct dmfe_board_info *);
332 static void dmfe_timer(unsigned long);
333 static void dmfe_rx_packet(struct net_device *, struct dmfe_board_info *);
334 static void dmfe_reused_skb(struct dmfe_board_info *, struct sk_buff *);
335 static void dmfe_dynamic_reset(struct net_device *);
336 static void dmfe_free_rxbuffer(struct dmfe_board_info *);
337 static void dmfe_init_dm910x(struct net_device *);
338 static unsigned long cal_CRC(unsigned char *, unsigned int, u8);
339
340 /* DM910X network board routine ---------------------------- */
341
342 /*
343 * Search DM910X board, allocate space and register it
344 */
345
346
347 static int __init dmfe_init_one (struct pci_dev *pdev,
348 const struct pci_device_id *ent)
349 {
350 unsigned long pci_iobase;
351 u8 pci_irqline;
352 struct dmfe_board_info *db; /* Point a board information structure */
353 int i;
354 struct net_device *dev;
355 u32 dev_rev;
356
357 DMFE_DBUG(0, "dmfe_probe()", 0);
358
359 pci_iobase = pci_resource_start(pdev, 0);
360 pci_irqline = pdev->irq;
361
362 /* Interrupt check */
363 if (pci_irqline == 0) {
364 printk(KERN_ERR "dmfe: Interrupt wrong : IRQ=%d\n",
365 pci_irqline);
366 goto err_out;
367 }
368
369 /* iobase check */
370 if (pci_iobase == 0) {
371 printk(KERN_ERR "dmfe: I/O base is zero\n");
372 goto err_out;
373 }
374
375 /* Enable Master/IO access, Disable memory access */
376 if (pci_enable_device(pdev))
377 goto err_out;
378 pci_set_master(pdev);
379
380 #if 0 /* pci_{enable_device,set_master} sets minimum latency for us now */
381
382 /* Set Latency Timer 80h */
383 /* FIXME: setting values > 32 breaks some SiS 559x stuff.
384 Need a PCI quirk.. */
385
386 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x80);
387 #endif
388
389 /* Read Chip revision */
390 pci_read_config_dword(pdev, PCI_REVISION_ID, &dev_rev);
391
392 /* Init network device */
393 dev = init_etherdev(NULL, sizeof(*db));
394 if (dev == NULL)
395 goto err_out;
396
397 /* IO range check */
398 if (!request_region(pci_iobase, CHK_IO_SIZE(pdev, dev_rev), dev->name)) {
399 printk(KERN_ERR "dmfe: I/O conflict : IO=%lx Range=%x\n",
400 pci_iobase, CHK_IO_SIZE(pdev, dev_rev));
401 goto err_out_netdev;
402 }
403
404 db = dev->priv;
405 pdev->driver_data = dev;
406
407 db->chip_id = ent->driver_data;
408 db->ioaddr = pci_iobase;
409 db->chip_revision = dev_rev;
410
411 db->net_dev = pdev;
412
413 dev->base_addr = pci_iobase;
414 dev->irq = pci_irqline;
415 dev->open = &dmfe_open;
416 dev->hard_start_xmit = &dmfe_start_xmit;
417 dev->stop = &dmfe_stop;
418 dev->get_stats = &dmfe_get_stats;
419 dev->set_multicast_list = &dmfe_set_filter_mode;
420 dev->do_ioctl = &dmfe_do_ioctl;
421
422 /* read 64 word srom data */
423 for (i = 0; i < 64; i++)
424 ((u16 *) db->srom)[i] = read_srom_word(pci_iobase, i);
425
426 /* Set Node address */
427 for (i = 0; i < 6; i++)
428 dev->dev_addr[i] = db->srom[20 + i];
429
430 return 0;
431
432 err_out_netdev:
433 unregister_netdev(dev);
434 kfree(dev);
435 err_out:
436 return -ENODEV;
437 }
438
439
440 static void __exit dmfe_remove_one (struct pci_dev *pdev)
441 {
442 struct net_device *dev = pdev->driver_data;
443 struct dmfe_board_info *db;
444
445 DMFE_DBUG(0, "dmfe_remove_one()", 0);
446
447 db = dev->priv;
448
449 unregister_netdev(dev);
450 release_region(dev->base_addr, CHK_IO_SIZE(pdev, db->chip_revision));
451 kfree(dev); /* free board information */
452
453 DMFE_DBUG(0, "dmfe_remove_one() exit", 0);
454 }
455
456
457 /*
458 * Open the interface.
459 * The interface is opened whenever "ifconfig" actives it.
460 */
461
462 static int dmfe_open(struct net_device *dev)
463 {
464 struct dmfe_board_info *db = dev->priv;
465
466 DMFE_DBUG(0, "dmfe_open", 0);
467
468 if (request_irq(dev->irq, &dmfe_interrupt, SA_SHIRQ, dev->name, dev))
469 return -EAGAIN;
470
471 /* Allocated Tx/Rx descriptor memory */
472 db->desc_pool_ptr = kmalloc(sizeof(struct tx_desc) * DESC_ALL_CNT + 0x20, GFP_KERNEL | GFP_DMA);
473 if (db->desc_pool_ptr == NULL)
474 return -ENOMEM;
475 if ((u32) db->desc_pool_ptr & 0x1f)
476 db->first_tx_desc = (struct tx_desc *) (((u32) db->desc_pool_ptr & ~0x1f) + 0x20);
477 else
478 db->first_tx_desc = (struct tx_desc *) db->desc_pool_ptr;
479
480 /* Allocated Tx buffer memory */
481 db->buf_pool_ptr = kmalloc(TX_BUF_ALLOC * TX_DESC_CNT + 4, GFP_KERNEL | GFP_DMA);
482 if (db->buf_pool_ptr == NULL) {
483 kfree(db->desc_pool_ptr);
484 return -ENOMEM;
485 }
486 if ((u32) db->buf_pool_ptr & 0x3)
487 db->buf_pool_start = (char *) (((u32) db->buf_pool_ptr & ~0x3) + 0x4);
488 else
489 db->buf_pool_start = db->buf_pool_ptr;
490
491 /* system variable init */
492 db->cr6_data = CR6_DEFAULT | dmfe_cr6_user_set;
493 db->tx_packet_cnt = 0;
494 db->tx_queue_cnt = 0;
495 db->rx_avail_cnt = 0;
496 db->link_failed = 0;
497 db->wait_reset = 0;
498 db->in_reset_state = 0;
499 db->rx_error_cnt = 0;
500
501 if (!chkmode || (db->chip_id == PCI_DM9132_ID) || (db->chip_revision >= 0x02000030)) {
502 //db->cr6_data &= ~CR6_SFT; /* Used Tx threshold */
503 //db->cr6_data |= CR6_NO_PURGE; /* No purge if rx unavailable */
504 db->cr0_data = 0xc00000; /* TX/RX desc burst mode */
505 db->dm910x_chk_mode = 4; /* Enter the normal mode */
506 } else {
507 db->cr0_data = 0;
508 db->dm910x_chk_mode = 1; /* Enter the check mode */
509 }
510
511 /* Initilize DM910X board */
512 dmfe_init_dm910x(dev);
513
514 /* Active System Interface */
515 MOD_INC_USE_COUNT;
516
517 /* set and active a timer process */
518 init_timer(&db->timer);
519 db->timer.expires = DMFE_TIMER_WUT;
520 db->timer.data = (unsigned long) dev;
521 db->timer.function = &dmfe_timer;
522 add_timer(&db->timer);
523
524 netif_wake_queue(dev);
525
526 return 0;
527 }
528
529 /* Initilize DM910X board
530 Reset DM910X board
531 Initilize TX/Rx descriptor chain structure
532 Send the set-up frame
533 Enable Tx/Rx machine
534 */
535 static void dmfe_init_dm910x(struct net_device *dev)
536 {
537 struct dmfe_board_info *db = dev->priv;
538 u32 ioaddr = db->ioaddr;
539
540 DMFE_DBUG(0, "dmfe_init_dm910x()", 0);
541
542 /* Reset DM910x board : need 32 PCI clock to complete */
543 outl(DM910X_RESET, ioaddr + DCR0); /* RESET MAC */
544 DELAY_5US;
545 outl(db->cr0_data, ioaddr + DCR0);
546
547 outl(0x180, ioaddr + DCR12); /* Let bit 7 output port */
548 outl(0x80, ioaddr + DCR12); /* RESET DM9102 phyxcer */
549 outl(0x0, ioaddr + DCR12); /* Clear RESET signal */
550
551 /* Phy addr : DM910(A)2/DM9132/9801, phy address = 1 */
552 db->phy_addr = 1;
553
554 /* Media Mode Check */
555 db->media_mode = dmfe_media_mode;
556 if (db->media_mode & DMFE_AUTO)
557 dmfe_sense_speed(db);
558 else
559 db->op_mode = db->media_mode;
560 dmfe_process_mode(db);
561
562 /* Initiliaze Transmit/Receive decriptor and CR3/4 */
563 dmfe_descriptor_init(db, ioaddr);
564
565 /* Init CR6 to program DM910x operation */
566 update_cr6(db->cr6_data, ioaddr);
567
568 /* Send setup frame */
569 if (db->chip_id == PCI_DM9132_ID)
570 dm9132_id_table(dev, dev->mc_count); /* DM9132 */
571 else
572 send_filter_frame(dev, dev->mc_count); /* DM9102/DM9102A */
573
574 /* Init CR5/CR7, interrupt active bit */
575 outl(0xffffffff, ioaddr + DCR5); /* clear all CR5 status */
576 db->cr7_data = CR7_DEFAULT;
577 outl(db->cr7_data, ioaddr + DCR7);
578
579 /* Init CR15, Tx jabber and Rx watchdog timer */
580 db->cr15_data = CR15_DEFAULT;
581 outl(db->cr15_data, ioaddr + DCR15);
582
583 /* Enable DM910X Tx/Rx function */
584 db->cr6_data |= CR6_RXSC | CR6_TXSC;
585 update_cr6(db->cr6_data, ioaddr);
586
587 }
588
589
590 /*
591 Hardware start transmission.
592 Send a packet to media from the upper layer.
593 */
594 static int dmfe_start_xmit(struct sk_buff *skb, struct net_device *dev)
595 {
596 struct dmfe_board_info *db = dev->priv;
597 struct tx_desc *txptr;
598
599 DMFE_DBUG(0, "dmfe_start_xmit", 0);
600
601 netif_stop_queue(dev);
602
603 /* Too large packet check */
604 if (skb->len > MAX_PACKET_SIZE) {
605 printk(KERN_ERR "%s: oversized frame (%d bytes) for transmit.\n", dev->name, (u16) skb->len);
606 dev_kfree_skb(skb);
607 return 0;
608 }
609 /* No Tx resource check, it never happen nromally */
610 if (db->tx_packet_cnt >= TX_FREE_DESC_CNT) {
611 return 1;
612 }
613
614 /* transmit this packet */
615 txptr = db->tx_insert_ptr;
616 memcpy((char *) txptr->tx_buf_ptr, (char *) skb->data, skb->len);
617 txptr->tdes1 = 0xe1000000 | skb->len;
618
619 /* Point to next transmit free descriptor */
620 db->tx_insert_ptr = (struct tx_desc *) txptr->next_tx_desc;
621
622 /* Transmit Packet Process */
623 if (db->tx_packet_cnt < TX_MAX_SEND_CNT) {
624 txptr->tdes0 = 0x80000000; /* set owner bit to DM910X */
625 db->tx_packet_cnt++; /* Ready to send count */
626 outl(0x1, dev->base_addr + DCR1); /* Issue Tx polling comand */
627 } else {
628 db->tx_queue_cnt++; /* queue the tx packet */
629 outl(0x1, dev->base_addr + DCR1); /* Issue Tx polling comand */
630 }
631
632 /* Tx resource check */
633 if (db->tx_packet_cnt < TX_FREE_DESC_CNT)
634 netif_wake_queue(dev);
635
636 /* free this SKB */
637 dev_kfree_skb(skb);
638 return 0;
639 }
640
641 /*
642 * Stop the interface.
643 * The interface is stopped when it is brought.
644 */
645
646 static int dmfe_stop(struct net_device *dev)
647 {
648 struct dmfe_board_info *db = dev->priv;
649 u32 ioaddr = dev->base_addr;
650
651 DMFE_DBUG(0, "dmfe_stop", 0);
652
653 netif_stop_queue(dev);
654
655 /* Reset & stop DM910X board */
656 outl(DM910X_RESET, ioaddr + DCR0);
657 DELAY_5US;
658
659 /* deleted timer */
660 del_timer(&db->timer);
661
662 /* free interrupt */
663 free_irq(dev->irq, dev);
664
665 /* free allocated rx buffer */
666 dmfe_free_rxbuffer(db);
667
668 /* free all descriptor memory and buffer memory */
669 kfree(db->desc_pool_ptr);
670 kfree(db->buf_pool_ptr);
671
672 MOD_DEC_USE_COUNT;
673
674 return 0;
675 }
676
677 /*
678 DM9102 insterrupt handler
679 receive the packet to upper layer, free the transmitted packet
680 */
681
682 static void dmfe_interrupt(int irq, void *dev_id, struct pt_regs *regs)
683 {
684 struct net_device *dev = dev_id;
685 struct tx_desc *txptr;
686 struct dmfe_board_info *db;
687 u32 ioaddr;
688
689 if (!dev) {
690 DMFE_DBUG(1, "dmfe_interrupt() without device arg", 0);
691 return;
692 }
693 /* A real interrupt coming */
694 db = (struct dmfe_board_info *) dev->priv;
695 ioaddr = dev->base_addr;
696
697 DMFE_DBUG(0, "dmfe_interrupt()", 0);
698
699 /* Disable all interrupt in CR7 to solve the interrupt edge problem */
700 outl(0, ioaddr + DCR7);
701
702 /* Got DM910X status */
703 db->cr5_data = inl(ioaddr + DCR5);
704 outl(db->cr5_data, ioaddr + DCR5);
705 /* printk("CR5=%x\n", db->cr5_data); */
706
707 /* Check system status */
708 if (db->cr5_data & 0x2000) {
709 /* A system bus error occurred */
710 DMFE_DBUG(1, "A system bus error occurred. CR5=", db->cr5_data);
711 netif_stop_queue(dev);
712 db->wait_reset = 1; /* Need to RESET */
713 outl(0, ioaddr + DCR7); /* disable all interrupt */
714 return;
715 }
716 /* Free the transmitted descriptor */
717 txptr = db->tx_remove_ptr;
718 while (db->tx_packet_cnt) {
719 /* printk("tdes0=%x\n", txptr->tdes0); */
720 if (txptr->tdes0 & 0x80000000)
721 break;
722 db->stats.tx_packets++;
723
724 if ((txptr->tdes0 & TDES0_ERR_MASK) && (txptr->tdes0 != 0x7fffffff)) {
725 /* printk("tdes0=%x\n", txptr->tdes0); */
726 db->stats.tx_errors++;
727 }
728 /* Transmit statistic counter */
729 if (txptr->tdes0 != 0x7fffffff) {
730 /* printk("tdes0=%x\n", txptr->tdes0); */
731 db->stats.collisions += (txptr->tdes0 >> 3) & 0xf;
732 db->stats.tx_bytes += txptr->tdes1 & 0x7ff;
733 if (txptr->tdes0 & TDES0_ERR_MASK)
734 db->stats.tx_errors++;
735 }
736 txptr = (struct tx_desc *) txptr->next_tx_desc;
737 db->tx_packet_cnt--;
738 }
739 /* Update TX remove pointer to next */
740 db->tx_remove_ptr = (struct tx_desc *) txptr;
741
742 /* Send the Tx packet in queue */
743 if ((db->tx_packet_cnt < TX_MAX_SEND_CNT) && db->tx_queue_cnt) {
744 txptr->tdes0 = 0x80000000; /* set owner bit to DM910X */
745 db->tx_packet_cnt++; /* Ready to send count */
746 outl(0x1, ioaddr + DCR1); /* Issue Tx polling command */
747 dev->trans_start = jiffies; /* saved the time stamp */
748 db->tx_queue_cnt--;
749 }
750 /* Resource available check */
751 if (db->tx_packet_cnt < TX_FREE_DESC_CNT)
752 netif_wake_queue(dev);
753
754 /* Received the coming packet */
755 if (db->rx_avail_cnt)
756 dmfe_rx_packet(dev, db);
757
758 /* reallocated rx descriptor buffer */
759 if (db->rx_avail_cnt < RX_DESC_CNT)
760 allocated_rx_buffer(db);
761
762 /* Mode Check */
763 if (db->dm910x_chk_mode & 0x2) {
764 db->dm910x_chk_mode = 0x4;
765 db->cr6_data |= 0x100;
766 update_cr6(db->cr6_data, db->ioaddr);
767 }
768
769 /* Restore CR7 to enable interrupt mask */
770 if (db->interval_rx_cnt > RX_MAX_TRAFFIC)
771 db->cr7_data = 0x1a28d;
772 else
773 db->cr7_data = 0x1a2cd;
774 outl(db->cr7_data, ioaddr + DCR7);
775 }
776
777 /*
778 Receive the come packet and pass to upper layer
779 */
780 static void dmfe_rx_packet(struct net_device *dev, struct dmfe_board_info *db)
781 {
782 struct rx_desc *rxptr;
783 struct sk_buff *skb;
784 int rxlen;
785
786 rxptr = db->rx_ready_ptr;
787
788 while (db->rx_avail_cnt) {
789 if (rxptr->rdes0 & 0x80000000) /* packet owner check */
790 break;
791
792 db->rx_avail_cnt--;
793 db->interval_rx_cnt++;
794
795 if ((rxptr->rdes0 & 0x300) != 0x300) {
796 /* A packet without First/Last flag */
797 /* reused this SKB */
798 DMFE_DBUG(0, "Reused SK buffer, rdes0", rxptr->rdes0);
799 dmfe_reused_skb(db, (struct sk_buff *) rxptr->rx_skb_ptr);
800 /* db->rx_error_cnt++; */
801 } else {
802 /* A packet with First/Last flag */
803 rxlen = ((rxptr->rdes0 >> 16) & 0x3fff) - 4; /* skip CRC */
804
805 if (rxptr->rdes0 & 0x8000) { /* error summary bit check */
806 /* This is a error packet */
807 /* printk("rdes0 error : %x \n", rxptr->rdes0); */
808 db->stats.rx_errors++;
809 if (rxptr->rdes0 & 1)
810 db->stats.rx_fifo_errors++;
811 if (rxptr->rdes0 & 2)
812 db->stats.rx_crc_errors++;
813 if (rxptr->rdes0 & 0x80)
814 db->stats.rx_length_errors++;
815 }
816 if (!(rxptr->rdes0 & 0x8000) ||
817 ((db->cr6_data & CR6_PM) && (rxlen > 6))) {
818 skb = (struct sk_buff *) rxptr->rx_skb_ptr;
819
820 /* Received Packet CRC check need or not */
821 if ((db->dm910x_chk_mode & 1) && (cal_CRC(skb->tail, rxlen, 1) != (*(unsigned long *) (skb->tail + rxlen)))) {
822 /* Found a error received packet */
823 dmfe_reused_skb(db, (struct sk_buff *) rxptr->rx_skb_ptr);
824 db->dm910x_chk_mode = 3;
825 } else {
826 /* A good packet coming, send to upper layer */
827 skb->dev = dev;
828 skb_put(skb, rxlen);
829 skb->protocol = eth_type_trans(skb, dev);
830 netif_rx(skb); /* Send to upper layer */
831 dev->last_rx = jiffies;
832 db->stats.rx_packets++;
833 db->stats.rx_bytes += rxlen;
834 }
835 } else {
836 /* Reuse SKB buffer when the packet is error */
837 DMFE_DBUG(0, "Reused SK buffer, rdes0", rxptr->rdes0);
838 dmfe_reused_skb(db, (struct sk_buff *) rxptr->rx_skb_ptr);
839 }
840 }
841
842 rxptr = (struct rx_desc *) rxptr->next_rx_desc;
843 }
844
845 db->rx_ready_ptr = rxptr;
846
847 }
848
849 /*
850 Get statistics from driver.
851 */
852 static struct enet_statistics *dmfe_get_stats(struct net_device *dev)
853 {
854 struct dmfe_board_info *db = (struct dmfe_board_info *) dev->priv;
855
856 DMFE_DBUG(0, "dmfe_get_stats", 0);
857 return &db->stats;
858 }
859
860 /*
861 Set DM910X multicast address
862 */
863 static void dmfe_set_filter_mode(struct net_device *dev)
864 {
865 struct dmfe_board_info *db = dev->priv;
866
867 DMFE_DBUG(0, "dmfe_set_filter_mode()", 0);
868
869 if (dev->flags & IFF_PROMISC) {
870 DMFE_DBUG(0, "Enable PROM Mode", 0);
871 db->cr6_data |= CR6_PM | CR6_PBF;
872 update_cr6(db->cr6_data, db->ioaddr);
873 return;
874 }
875 if (dev->flags & IFF_ALLMULTI || dev->mc_count > DMFE_MAX_MULTICAST) {
876 DMFE_DBUG(0, "Pass all multicast address", dev->mc_count);
877 db->cr6_data &= ~(CR6_PM | CR6_PBF);
878 db->cr6_data |= CR6_PAM;
879 return;
880 }
881 DMFE_DBUG(0, "Set multicast address", dev->mc_count);
882 if (db->chip_id == PCI_DM9132_ID)
883 dm9132_id_table(dev, dev->mc_count); /* DM9132 */
884 else
885 send_filter_frame(dev, dev->mc_count); /* DM9102/DM9102A */
886 }
887
888 /*
889 Process the upper socket ioctl command
890 */
891 static int dmfe_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
892 {
893 DMFE_DBUG(0, "dmfe_do_ioctl()", 0);
894 return 0;
895 }
896
897 /*
898 A periodic timer routine
899 Dynamic media sense, allocated Rx buffer...
900 */
901 static void dmfe_timer(unsigned long data)
902 {
903 u32 tmp_cr8;
904 unsigned char tmp_cr12;
905 struct net_device *dev = (struct net_device *) data;
906 struct dmfe_board_info *db = (struct dmfe_board_info *) dev->priv;
907
908 DMFE_DBUG(0, "dmfe_timer()", 0);
909
910 /* Do reset now */
911 if (db->in_reset_state)
912 return;
913
914 /* Operating Mode Check */
915 if ((db->dm910x_chk_mode & 0x1) && (db->stats.rx_packets > MAX_CHECK_PACKET)) {
916 db->dm910x_chk_mode = 0x4;
917 }
918 /* Dynamic reset DM910X : system error or transmit time-out */
919 tmp_cr8 = inl(db->ioaddr + DCR8);
920 if ((db->interval_rx_cnt == 0) && (tmp_cr8)) {
921 db->wait_reset = 1;
922 /* printk("CR8 %x, Interval Rx %x\n", tmp_cr8, db->interval_rx_cnt); */
923 }
924 /* Receiving Traffic check */
925 if (db->interval_rx_cnt > RX_MAX_TRAFFIC)
926 db->cr7_data = 0x1a28d;
927 else
928 db->cr7_data = 0x1a2cd;
929 outl(db->cr7_data, db->ioaddr + DCR7);
930
931 db->interval_rx_cnt = 0;
932
933 if (db->wait_reset | (db->tx_packet_cnt &&
934 ((jiffies - dev->trans_start) > DMFE_TX_TIMEOUT)) | (db->rx_error_cnt > 3)) {
935 /*
936 printk("wait_reset %x, tx cnt %x, rx err %x, time %x\n", db->wait_reset, db->tx_packet_cnt, db->rx_error_cnt, jiffies-dev->trans_start);
937 */
938 DMFE_DBUG(0, "Warn!! Warn!! Tx/Rx moniotr step1", db->tx_packet_cnt);
939 dmfe_dynamic_reset(dev);
940 db->timer.expires = DMFE_TIMER_WUT;
941 add_timer(&db->timer);
942 return;
943 }
944 db->rx_error_cnt = 0; /* Clear previos counter */
945
946 /* Link status check, Dynamic media type change */
947 if (db->chip_id == PCI_DM9132_ID)
948 tmp_cr12 = inb(db->ioaddr + DCR9 + 3); /* DM9132 */
949 else
950 tmp_cr12 = inb(db->ioaddr + DCR12); /* DM9102/DM9102A */
951
952 if (((db->chip_id == PCI_DM9102_ID) && (db->chip_revision == 0x02000030)) ||
953 ((db->chip_id == PCI_DM9132_ID) && (db->chip_revision == 0x02000010))) {
954 /* DM9102A Chip */
955 if (tmp_cr12 & 2)
956 tmp_cr12 = 0x0; /* Link failed */
957 else
958 tmp_cr12 = 0x3; /* Link OK */
959 }
960 if (!(tmp_cr12 & 0x3) && !db->link_failed) {
961 /* Link Failed */
962 DMFE_DBUG(0, "Link Failed", tmp_cr12);
963 db->link_failed = 1;
964 phy_write(db->ioaddr, db->phy_addr, 0, 0x8000, db->chip_id); /* reset Phy */
965
966 /* 10/100M link failed, used 1M Home-Net */
967 db->cr6_data |= 0x00040000; /* CR6 bit18 = 1, select Home-Net */
968 db->cr6_data &= ~0x00000200; /* CR6 bit9 =0, half duplex mode */
969 update_cr6(db->cr6_data, db->ioaddr);
970
971 /* For DM9801 : PHY ID1 0181h, PHY ID2 B900h */
972 db->phy_id2 = phy_read(db->ioaddr, db->phy_addr, 3, db->chip_id);
973 if (db->phy_id2 == 0xb900)
974 phy_write(db->ioaddr, db->phy_addr, 25, 0x7e08, db->chip_id);
975 } else if ((tmp_cr12 & 0x3) && db->link_failed) {
976 DMFE_DBUG(0, "Link link OK", tmp_cr12);
977 db->link_failed = 0;
978
979 /* CR6 bit18=0, select 10/100M */
980 db->cr6_data &= ~0x00040000;
981 update_cr6(db->cr6_data, db->ioaddr);
982
983 /* Auto Sense Speed */
984 if (db->media_mode & DMFE_AUTO)
985 dmfe_sense_speed(db);
986 dmfe_process_mode(db);
987 update_cr6(db->cr6_data, db->ioaddr);
988 /* SHOW_MEDIA_TYPE(db->op_mode); */
989 }
990 /* reallocated rx descriptor buffer */
991 if (db->rx_avail_cnt < RX_DESC_CNT)
992 allocated_rx_buffer(db);
993
994 /* Timer active again */
995 db->timer.expires = DMFE_TIMER_WUT;
996 add_timer(&db->timer);
997 }
998
999 /*
1000 Dynamic reset the DM910X board
1001 Stop DM910X board
1002 Free Tx/Rx allocated memory
1003 Reset DM910X board
1004 Re-initilize DM910X board
1005 */
1006 static void dmfe_dynamic_reset(struct net_device *dev)
1007 {
1008 struct dmfe_board_info *db = dev->priv;
1009
1010 DMFE_DBUG(0, "dmfe_dynamic_reset()", 0);
1011
1012 /* Enter dynamic reset route */
1013 db->in_reset_state = 1;
1014
1015 /* Disable upper layer interface */
1016 netif_stop_queue(dev);
1017
1018 db->cr6_data &= ~(CR6_RXSC | CR6_TXSC); /* Disable Tx/Rx */
1019 update_cr6(db->cr6_data, dev->base_addr);
1020
1021 /* Free Rx Allocate buffer */
1022 dmfe_free_rxbuffer(db);
1023
1024 /* system variable init */
1025 db->tx_packet_cnt = 0;
1026 db->tx_queue_cnt = 0;
1027 db->rx_avail_cnt = 0;
1028 db->link_failed = 0;
1029 db->wait_reset = 0;
1030 db->rx_error_cnt = 0;
1031
1032 /* Re-initilize DM910X board */
1033 dmfe_init_dm910x(dev);
1034
1035 /* Leave dynamic reser route */
1036 db->in_reset_state = 0;
1037
1038 /* Restart upper layer interface */
1039 netif_wake_queue(dev);
1040 }
1041
1042 /*
1043 free all allocated rx buffer
1044 */
1045 static void dmfe_free_rxbuffer(struct dmfe_board_info *db)
1046 {
1047 DMFE_DBUG(0, "dmfe_free_rxbuffer()", 0);
1048
1049 /* free allocated rx buffer */
1050 while (db->rx_avail_cnt) {
1051 dev_kfree_skb((void *) (db->rx_ready_ptr->rx_skb_ptr));
1052 db->rx_ready_ptr = (struct rx_desc *) db->rx_ready_ptr->next_rx_desc;
1053 db->rx_avail_cnt--;
1054 }
1055 }
1056
1057 /*
1058 Reused the SK buffer
1059 */
1060 static void dmfe_reused_skb(struct dmfe_board_info *db, struct sk_buff *skb)
1061 {
1062 struct rx_desc *rxptr = db->rx_insert_ptr;
1063
1064 if (!(rxptr->rdes0 & 0x80000000)) {
1065 rxptr->rx_skb_ptr = (u32) skb;
1066 rxptr->rdes2 = virt_to_bus(skb->tail);
1067 rxptr->rdes0 = 0x80000000;
1068 db->rx_avail_cnt++;
1069 db->rx_insert_ptr = (struct rx_desc *) rxptr->next_rx_desc;
1070 } else
1071 DMFE_DBUG(0, "SK Buffer reused method error", db->rx_avail_cnt);
1072 }
1073
1074 /*
1075 Initialize transmit/Receive descriptor
1076 Using Chain structure, and allocated Tx/Rx buffer
1077 */
1078 static void dmfe_descriptor_init(struct dmfe_board_info *db, u32 ioaddr)
1079 {
1080 struct tx_desc *tmp_tx;
1081 struct rx_desc *tmp_rx;
1082 unsigned char *tmp_buf;
1083 int i;
1084
1085 DMFE_DBUG(0, "dmfe_descriptor_init()", 0);
1086
1087 /* tx descriptor start pointer */
1088 db->tx_insert_ptr = db->first_tx_desc;
1089 db->tx_remove_ptr = db->first_tx_desc;
1090 outl(virt_to_bus(db->first_tx_desc), ioaddr + DCR4); /* Init CR4 */
1091
1092 /* rx descriptor start pointer */
1093 db->first_rx_desc = (struct rx_desc *)
1094 ((u32) db->first_tx_desc + sizeof(struct rx_desc) * TX_DESC_CNT);
1095 db->rx_insert_ptr = db->first_rx_desc;
1096 db->rx_ready_ptr = db->first_rx_desc;
1097 outl(virt_to_bus(db->first_rx_desc), ioaddr + DCR3); /* Init CR3 */
1098
1099 /* Init Transmit chain */
1100 tmp_buf = db->buf_pool_start;
1101 for (tmp_tx = db->first_tx_desc, i = 0; i < TX_DESC_CNT; i++, tmp_tx++) {
1102 tmp_tx->tx_buf_ptr = (u32) tmp_buf;
1103 tmp_tx->tdes0 = 0;
1104 tmp_tx->tdes1 = 0x81000000; /* IC, chain */
1105 tmp_tx->tdes2 = (u32) virt_to_bus(tmp_buf);
1106 tmp_tx->tdes3 = (u32) virt_to_bus(tmp_tx) + sizeof(struct tx_desc);
1107 tmp_tx->next_tx_desc = (u32) ((u32) tmp_tx + sizeof(struct tx_desc));
1108 tmp_buf = (unsigned char *) ((u32) tmp_buf + TX_BUF_ALLOC);
1109 }
1110 (--tmp_tx)->tdes3 = (u32) virt_to_bus(db->first_tx_desc);
1111 tmp_tx->next_tx_desc = (u32) db->first_tx_desc;
1112
1113 /* Init Receive descriptor chain */
1114 for (tmp_rx = db->first_rx_desc, i = 0; i < RX_DESC_CNT; i++, tmp_rx++) {
1115 tmp_rx->rdes0 = 0;
1116 tmp_rx->rdes1 = 0x01000600;
1117 tmp_rx->rdes3 = (u32) virt_to_bus(tmp_rx) + sizeof(struct rx_desc);
1118 tmp_rx->next_rx_desc = (u32) ((u32) tmp_rx + sizeof(struct rx_desc));
1119 }
1120 (--tmp_rx)->rdes3 = (u32) virt_to_bus(db->first_rx_desc);
1121 tmp_rx->next_rx_desc = (u32) db->first_rx_desc;
1122
1123 /* pre-allocated Rx buffer */
1124 allocated_rx_buffer(db);
1125 }
1126
1127 /*
1128 Update CR6 vaule
1129 Firstly stop DM910X , then written value and start
1130 */
1131 static void update_cr6(u32 cr6_data, u32 ioaddr)
1132 {
1133 u32 cr6_tmp;
1134
1135 cr6_tmp = cr6_data & ~0x2002; /* stop Tx/Rx */
1136 outl(cr6_tmp, ioaddr + DCR6);
1137 DELAY_5US;
1138 outl(cr6_data, ioaddr + DCR6);
1139 cr6_tmp = inl(ioaddr + DCR6);
1140 /* printk("CR6 update %x ", cr6_tmp); */
1141 }
1142
1143 /* Send a setup frame for DM9132
1144 This setup frame initilize DM910X addres filter mode
1145 */
1146 static void dm9132_id_table(struct net_device *dev, int mc_cnt)
1147 {
1148 struct dev_mc_list *mcptr;
1149 u16 *addrptr;
1150 u32 ioaddr = dev->base_addr + 0xc0; /* ID Table */
1151 u32 hash_val;
1152 u16 i, hash_table[4];
1153
1154 DMFE_DBUG(0, "dm9132_id_table()", 0);
1155
1156 /* Node address */
1157 addrptr = (u16 *) dev->dev_addr;
1158 outw(addrptr[0], ioaddr);
1159 ioaddr += 4;
1160 outw(addrptr[1], ioaddr);
1161 ioaddr += 4;
1162 outw(addrptr[2], ioaddr);
1163 ioaddr += 4;
1164
1165 /* Clear Hash Table */
1166 for (i = 0; i < 4; i++)
1167 hash_table[i] = 0x0;
1168
1169 /* broadcast address */
1170 hash_table[3] = 0x8000;
1171
1172 /* the multicast address in Hash Table : 64 bits */
1173 for (mcptr = dev->mc_list, i = 0; i < mc_cnt; i++, mcptr = mcptr->next) {
1174 hash_val = cal_CRC((char *) mcptr->dmi_addr, 6, 0) & 0x3f;
1175 hash_table[hash_val / 16] |= (u16) 1 << (hash_val % 16);
1176 }
1177
1178 /* Write the hash table to MAC MD table */
1179 for (i = 0; i < 4; i++, ioaddr += 4) {
1180 outw(hash_table[i], ioaddr);
1181 }
1182 }
1183
1184 /* Send a setup frame for DM9102/DM9102A
1185 This setup frame initilize DM910X addres filter mode
1186 */
1187 static void send_filter_frame(struct net_device *dev, int mc_cnt)
1188 {
1189 struct dmfe_board_info *db = dev->priv;
1190 struct dev_mc_list *mcptr;
1191 struct tx_desc *txptr;
1192 u16 *addrptr;
1193 u32 *suptr;
1194 int i;
1195
1196 DMFE_DBUG(0, "send_filetr_frame()", 0);
1197
1198 txptr = db->tx_insert_ptr;
1199 suptr = (u32 *) txptr->tx_buf_ptr;
1200
1201 /* Node address */
1202 addrptr = (u16 *) dev->dev_addr;
1203 *suptr++ = addrptr[0];
1204 *suptr++ = addrptr[1];
1205 *suptr++ = addrptr[2];
1206
1207 /* broadcast address */
1208 *suptr++ = 0xffff;
1209 *suptr++ = 0xffff;
1210 *suptr++ = 0xffff;
1211
1212 /* fit the multicast address */
1213 for (mcptr = dev->mc_list, i = 0; i < mc_cnt; i++, mcptr = mcptr->next) {
1214 addrptr = (u16 *) mcptr->dmi_addr;
1215 *suptr++ = addrptr[0];
1216 *suptr++ = addrptr[1];
1217 *suptr++ = addrptr[2];
1218 }
1219
1220 for (; i < 14; i++) {
1221 *suptr++ = 0xffff;
1222 *suptr++ = 0xffff;
1223 *suptr++ = 0xffff;
1224 }
1225 /* prepare the setup frame */
1226 db->tx_insert_ptr = (struct tx_desc *) txptr->next_tx_desc;
1227 txptr->tdes1 = 0x890000c0;
1228 /* Resource Check and Send the setup packet */
1229 if (!db->tx_packet_cnt) {
1230 /* Resource Empty */
1231 db->tx_packet_cnt++;
1232 txptr->tdes0 = 0x80000000;
1233 update_cr6(db->cr6_data | 0x2000, dev->base_addr);
1234 outl(0x1, dev->base_addr + DCR1); /* Issue Tx polling command */
1235 update_cr6(db->cr6_data, dev->base_addr);
1236 } else {
1237 /* Put into TX queue */
1238 db->tx_queue_cnt++;
1239 }
1240 }
1241
1242 /*
1243 * Allocate rx buffer,
1244 * Allocate as many Rx buffers as possible.
1245 */
1246 static void allocated_rx_buffer(struct dmfe_board_info *db)
1247 {
1248 struct rx_desc *rxptr;
1249 struct sk_buff *skb;
1250
1251 rxptr = db->rx_insert_ptr;
1252
1253 while (db->rx_avail_cnt < RX_DESC_CNT) {
1254 if ((skb = alloc_skb(RX_ALLOC_SIZE, GFP_ATOMIC)) == NULL)
1255 break;
1256 rxptr->rx_skb_ptr = (u32) skb;
1257 rxptr->rdes2 = virt_to_bus(skb->tail);
1258 rxptr->rdes0 = 0x80000000;
1259 rxptr = (struct rx_desc *) rxptr->next_rx_desc;
1260 db->rx_avail_cnt++;
1261 }
1262
1263 db->rx_insert_ptr = rxptr;
1264 }
1265
1266 /*
1267 Read one word data from the serial ROM
1268 */
1269 static u16 read_srom_word(long ioaddr, int offset)
1270 {
1271 int i;
1272 u16 srom_data = 0;
1273 long cr9_ioaddr = ioaddr + DCR9;
1274
1275 outl(CR9_SROM_READ, cr9_ioaddr);
1276 outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr);
1277
1278 /* Send the Read Command 110b */
1279 SROM_CLK_WRITE(SROM_DATA_1, cr9_ioaddr);
1280 SROM_CLK_WRITE(SROM_DATA_1, cr9_ioaddr);
1281 SROM_CLK_WRITE(SROM_DATA_0, cr9_ioaddr);
1282
1283 /* Send the offset */
1284 for (i = 5; i >= 0; i--) {
1285 srom_data = (offset & (1 << i)) ? SROM_DATA_1 : SROM_DATA_0;
1286 SROM_CLK_WRITE(srom_data, cr9_ioaddr);
1287 }
1288
1289 outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr);
1290
1291 for (i = 16; i > 0; i--) {
1292 outl(CR9_SROM_READ | CR9_SRCS | CR9_SRCLK, cr9_ioaddr);
1293 DELAY_5US;
1294 srom_data = (srom_data << 1) | ((inl(cr9_ioaddr) & CR9_CRDOUT) ? 1 : 0);
1295 outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr);
1296 DELAY_5US;
1297 }
1298
1299 outl(CR9_SROM_READ, cr9_ioaddr);
1300 return srom_data;
1301 }
1302
1303 /*
1304 * Auto sense the media mode
1305 */
1306
1307 static void dmfe_sense_speed(struct dmfe_board_info *db)
1308 {
1309 int i;
1310 u16 phy_mode;
1311
1312 for (i = 1000; i; i--) {
1313 DELAY_5US;
1314 phy_mode = phy_read(db->ioaddr, db->phy_addr, 1, db->chip_id);
1315 if ((phy_mode & 0x24) == 0x24)
1316 break;
1317 }
1318
1319 if (i) {
1320 if (db->chip_id == PCI_DM9132_ID) /* DM9132 */
1321 phy_mode = phy_read(db->ioaddr, db->phy_addr, 7, db->chip_id) & 0xf000;
1322 else /* DM9102/DM9102A */
1323 phy_mode = phy_read(db->ioaddr, db->phy_addr, 17, db->chip_id) & 0xf000;
1324 /* printk("Phy_mode %x ",phy_mode); */
1325 switch (phy_mode) {
1326 case 0x1000:
1327 db->op_mode = DMFE_10MHF;
1328 break;
1329 case 0x2000:
1330 db->op_mode = DMFE_10MFD;
1331 break;
1332 case 0x4000:
1333 db->op_mode = DMFE_100MHF;
1334 break;
1335 case 0x8000:
1336 db->op_mode = DMFE_100MFD;
1337 break;
1338 default:
1339 db->op_mode = DMFE_10MHF;
1340 DMFE_DBUG(0, "Media Type error, phy reg17", phy_mode);
1341 break;
1342 }
1343 } else {
1344 db->op_mode = DMFE_10MHF;
1345 DMFE_DBUG(0, "Link Failed :", phy_mode);
1346 }
1347 }
1348
1349 /*
1350 Process op-mode
1351 AUTO mode : PHY controller in Auto-negotiation Mode
1352 Force mode: PHY controller in force mode with HUB
1353 N-way force capability with SWITCH
1354 */
1355 static void dmfe_process_mode(struct dmfe_board_info *db)
1356 {
1357 u16 phy_reg;
1358
1359 /* Full Duplex Mode Check */
1360 db->cr6_data &= ~CR6_FDM; /* Clear Full Duplex Bit */
1361 if (db->op_mode & 0x4)
1362 db->cr6_data |= CR6_FDM;
1363
1364 if (!(db->media_mode & DMFE_AUTO)) { /* Force Mode Check */
1365 /* User force the media type */
1366 phy_reg = phy_read(db->ioaddr, db->phy_addr, 5, db->chip_id);
1367 /* printk("Nway phy_reg5 %x ",phy_reg); */
1368 if (phy_reg & 0x1) {
1369 /* parter own the N-Way capability */
1370 phy_reg = phy_read(db->ioaddr, db->phy_addr, 4, db->chip_id) & ~0x1e0;
1371 switch (db->op_mode) {
1372 case DMFE_10MHF:
1373 phy_reg |= 0x20;
1374 break;
1375 case DMFE_10MFD:
1376 phy_reg |= 0x40;
1377 break;
1378 case DMFE_100MHF:
1379 phy_reg |= 0x80;
1380 break;
1381 case DMFE_100MFD:
1382 phy_reg |= 0x100;
1383 break;
1384 }
1385 phy_write(db->ioaddr, db->phy_addr, 4, phy_reg, db->chip_id);
1386 } else {
1387 /* parter without the N-Way capability */
1388 switch (db->op_mode) {
1389 case DMFE_10MHF:
1390 phy_reg = 0x0;
1391 break;
1392 case DMFE_10MFD:
1393 phy_reg = 0x100;
1394 break;
1395 case DMFE_100MHF:
1396 phy_reg = 0x2000;
1397 break;
1398 case DMFE_100MFD:
1399 phy_reg = 0x2100;
1400 break;
1401 }
1402 phy_write(db->ioaddr, db->phy_addr, 0, phy_reg, db->chip_id);
1403 }
1404 }
1405 }
1406
1407 /*
1408 Write a word to Phy register
1409 */
1410 static void phy_write(u32 iobase, u8 phy_addr, u8 offset, u16 phy_data, u32 chip_id)
1411 {
1412 u16 i;
1413 u32 ioaddr;
1414
1415 if (chip_id == PCI_DM9132_ID) {
1416 ioaddr = iobase + 0x80 + offset * 4;
1417 outw(phy_data, ioaddr);
1418 } else {
1419 /* DM9102/DM9102A Chip */
1420 ioaddr = iobase + DCR9;
1421
1422 /* Send 33 synchronization clock to Phy controller */
1423 for (i = 0; i < 35; i++)
1424 phy_write_1bit(ioaddr, PHY_DATA_1);
1425
1426 /* Send start command(01) to Phy */
1427 phy_write_1bit(ioaddr, PHY_DATA_0);
1428 phy_write_1bit(ioaddr, PHY_DATA_1);
1429
1430 /* Send write command(01) to Phy */
1431 phy_write_1bit(ioaddr, PHY_DATA_0);
1432 phy_write_1bit(ioaddr, PHY_DATA_1);
1433
1434 /* Send Phy addres */
1435 for (i = 0x10; i > 0; i = i >> 1)
1436 phy_write_1bit(ioaddr, phy_addr & i ? PHY_DATA_1 : PHY_DATA_0);
1437
1438 /* Send register addres */
1439 for (i = 0x10; i > 0; i = i >> 1)
1440 phy_write_1bit(ioaddr, offset & i ? PHY_DATA_1 : PHY_DATA_0);
1441
1442 /* written trasnition */
1443 phy_write_1bit(ioaddr, PHY_DATA_1);
1444 phy_write_1bit(ioaddr, PHY_DATA_0);
1445
1446 /* Write a word data to PHY controller */
1447 for (i = 0x8000; i > 0; i >>= 1)
1448 phy_write_1bit(ioaddr, phy_data & i ? PHY_DATA_1 : PHY_DATA_0);
1449 }
1450 }
1451
1452 /*
1453 Read a word data from phy register
1454 */
1455 static u16 phy_read(u32 iobase, u8 phy_addr, u8 offset, u32 chip_id)
1456 {
1457 int i;
1458 u16 phy_data;
1459 u32 ioaddr;
1460
1461 if (chip_id == PCI_DM9132_ID) {
1462 /* DM9132 Chip */
1463 ioaddr = iobase + 0x80 + offset * 4;
1464 phy_data = inw(ioaddr);
1465 } else {
1466 /* DM9102/DM9102A Chip */
1467
1468 ioaddr = iobase + DCR9;
1469 /* Send 33 synchronization clock to Phy controller */
1470 for (i = 0; i < 35; i++)
1471 phy_write_1bit(ioaddr, PHY_DATA_1);
1472
1473 /* Send start command(01) to Phy */
1474 phy_write_1bit(ioaddr, PHY_DATA_0);
1475 phy_write_1bit(ioaddr, PHY_DATA_1);
1476
1477 /* Send read command(10) to Phy */
1478 phy_write_1bit(ioaddr, PHY_DATA_1);
1479 phy_write_1bit(ioaddr, PHY_DATA_0);
1480
1481 /* Send Phy addres */
1482 for (i = 0x10; i > 0; i = i >> 1)
1483 phy_write_1bit(ioaddr, phy_addr & i ? PHY_DATA_1 : PHY_DATA_0);
1484
1485 /* Send register addres */
1486 for (i = 0x10; i > 0; i = i >> 1)
1487 phy_write_1bit(ioaddr, offset & i ? PHY_DATA_1 : PHY_DATA_0);
1488
1489 /* Skip transition state */
1490 phy_read_1bit(ioaddr);
1491
1492 /* read 16bit data */
1493 for (phy_data = 0, i = 0; i < 16; i++) {
1494 phy_data <<= 1;
1495 phy_data |= phy_read_1bit(ioaddr);
1496 }
1497 }
1498
1499 return phy_data;
1500 }
1501
1502 /*
1503 Write one bit data to Phy Controller
1504 */
1505 static void phy_write_1bit(u32 ioaddr, u32 phy_data)
1506 {
1507 outl(phy_data, ioaddr); /* MII Clock Low */
1508 DELAY_1US;
1509 outl(phy_data | MDCLKH, ioaddr); /* MII Clock High */
1510 DELAY_1US;
1511 outl(phy_data, ioaddr); /* MII Clock Low */
1512 DELAY_1US;
1513 }
1514
1515 /*
1516 Read one bit phy data from PHY controller
1517 */
1518 static u16 phy_read_1bit(u32 ioaddr)
1519 {
1520 u16 phy_data;
1521
1522 outl(0x50000, ioaddr);
1523 DELAY_1US;
1524 phy_data = (inl(ioaddr) >> 19) & 0x1;
1525 outl(0x40000, ioaddr);
1526 DELAY_1US;
1527
1528 return phy_data;
1529 }
1530
1531 /*
1532 Calculate the CRC valude of the Rx packet
1533 flag = 1 : return the reverse CRC (for the received packet CRC)
1534 0 : return the normal CRC (for Hash Table index)
1535 */
1536 unsigned long cal_CRC(unsigned char *Data, unsigned int Len, u8 flag)
1537 {
1538 unsigned long Crc = 0xffffffff;
1539
1540 while (Len--) {
1541 Crc = CrcTable[(Crc ^ *Data++) & 0xFF] ^ (Crc >> 8);
1542 }
1543
1544 if (flag)
1545 return ~Crc;
1546 else
1547 return Crc;
1548 }
1549
1550
1551 static struct pci_device_id dmfe_pci_tbl[] __initdata = {
1552 { 0x1282, 0x9132, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PCI_DM9132_ID },
1553 { 0x1282, 0x9102, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PCI_DM9102_ID },
1554 { 0x1282, 0x9100, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PCI_DM9100_ID },
1555 { 0, }
1556 };
1557 MODULE_DEVICE_TABLE(pci, dmfe_pci_tbl);
1558
1559 static struct pci_driver dmfe_driver = {
1560 name: "dmfe",
1561 id_table: dmfe_pci_tbl,
1562 probe: dmfe_init_one,
1563 remove: dmfe_remove_one,
1564 };
1565
1566 MODULE_AUTHOR("Sten Wang, sten_wang@davicom.com.tw");
1567 MODULE_DESCRIPTION("Davicom DM910X fast ethernet driver");
1568 MODULE_PARM(debug, "i");
1569 MODULE_PARM(mode, "i");
1570 MODULE_PARM(cr6set, "i");
1571 MODULE_PARM(chkmode, "i");
1572
1573 /* Description:
1574 * when user used insmod to add module, system invoked init_module()
1575 * to initilize and register.
1576 */
1577
1578 static int __init dmfe_init_module(void)
1579 {
1580 int rc;
1581
1582 DMFE_DBUG(0, "init_module() ", debug);
1583
1584 if (debug)
1585 dmfe_debug = debug; /* set debug flag */
1586 if (cr6set)
1587 dmfe_cr6_user_set = cr6set;
1588
1589 switch (mode) {
1590 case 0:
1591 case 1:
1592 case 4:
1593 case 5:
1594 dmfe_media_mode = mode;
1595 break;
1596 default:
1597 dmfe_media_mode = 8;
1598 break;
1599 }
1600
1601 rc = pci_register_driver(&dmfe_driver);
1602 if (rc < 0)
1603 return rc;
1604 if (rc > 0) {
1605 printk (KERN_INFO "Davicom DM91xx net driver loaded, version "
1606 DMFE_VERSION "\n");
1607 return 0;
1608 }
1609 return -ENODEV;
1610 }
1611
1612 /*
1613 * Description:
1614 * when user used rmmod to delete module, system invoked clean_module()
1615 * to un-register all registered services.
1616 */
1617
1618 static void __exit dmfe_cleanup_module(void)
1619 {
1620 pci_unregister_driver(&dmfe_driver);
1621 }
1622
1623 module_init(dmfe_init_module);
1624 module_exit(dmfe_cleanup_module);
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