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Import 2.4.0-test4
[davej-history.git] / drivers / net / sunqe.c
blobf4ea45189e396d9315cdccdac255ef026c318432
1 /* $Id: sunqe.c,v 1.46 2000/06/19 06:24:46 davem Exp $
2 * sunqe.c: Sparc QuadEthernet 10baseT SBUS card driver.
3 * Once again I am out to prove that every ethernet
4 * controller out there can be most efficiently programmed
5 * if you make it look like a LANCE.
6 *
7 * Copyright (C) 1996, 1999 David S. Miller (davem@redhat.com)
8 */
9
10 static char *version =
11 "sunqe.c:v2.9 9/11/99 David S. Miller (davem@redhat.com)\n";
12
13 #include <linux/module.h>
14
15 #include <linux/kernel.h>
16 #include <linux/sched.h>
17 #include <linux/types.h>
18 #include <linux/fcntl.h>
19 #include <linux/interrupt.h>
20 #include <linux/ptrace.h>
21 #include <linux/ioport.h>
22 #include <linux/in.h>
23 #include <linux/malloc.h>
24 #include <linux/string.h>
25 #include <linux/delay.h>
26 #include <linux/init.h>
27
28 #include <asm/system.h>
29 #include <asm/bitops.h>
30 #include <asm/io.h>
31 #include <asm/dma.h>
32 #include <linux/errno.h>
33 #include <asm/byteorder.h>
34
35 #include <asm/idprom.h>
36 #include <asm/sbus.h>
37 #include <asm/openprom.h>
38 #include <asm/oplib.h>
39 #include <asm/auxio.h>
40 #include <asm/pgtable.h>
41 #include <asm/irq.h>
42
43 #include <linux/netdevice.h>
44 #include <linux/etherdevice.h>
45 #include <linux/skbuff.h>
46
47 #include "sunqe.h"
48
49 #ifdef MODULE
50 static struct sunqec *root_qec_dev = NULL;
51 #endif
52
53 static void qe_set_multicast(struct net_device *dev);
54
55 #define QEC_RESET_TRIES 200
56
57 static inline int qec_global_reset(unsigned long gregs)
58 {
59 int tries = QEC_RESET_TRIES;
60
61 sbus_writel(GLOB_CTRL_RESET, gregs + GLOB_CTRL);
62 while (--tries) {
63 u32 tmp = sbus_readl(gregs + GLOB_CTRL);
64 if (tmp & GLOB_CTRL_RESET) {
65 udelay(20);
66 continue;
67 }
68 break;
69 }
70 if (tries)
71 return 0;
72 printk(KERN_ERR "QuadEther: AIEEE cannot reset the QEC!\n");
73 return -1;
74 }
75
76 #define MACE_RESET_RETRIES 200
77 #define QE_RESET_RETRIES 200
78
79 static inline int qe_stop(struct sunqe *qep)
80 {
81 unsigned long cregs = qep->qcregs;
82 unsigned long mregs = qep->mregs;
83 int tries;
84
85 /* Reset the MACE, then the QEC channel. */
86 sbus_writeb(MREGS_BCONFIG_RESET, mregs + MREGS_BCONFIG);
87 tries = MACE_RESET_RETRIES;
88 while (--tries) {
89 u8 tmp = sbus_readb(mregs + MREGS_BCONFIG);
90 if (tmp & MREGS_BCONFIG_RESET) {
91 udelay(20);
92 continue;
93 }
94 break;
95 }
96 if (!tries) {
97 printk(KERN_ERR "QuadEther: AIEEE cannot reset the MACE!\n");
98 return -1;
99 }
100
101 sbus_writel(CREG_CTRL_RESET, cregs + CREG_CTRL);
102 tries = QE_RESET_RETRIES;
103 while (--tries) {
104 u32 tmp = sbus_readl(cregs + CREG_CTRL);
105 if (tmp & CREG_CTRL_RESET) {
106 udelay(20);
107 continue;
108 }
109 break;
110 }
111 if (!tries) {
112 printk(KERN_ERR "QuadEther: Cannot reset QE channel!\n");
113 return -1;
114 }
115 return 0;
116 }
117
118 static void qe_init_rings(struct sunqe *qep)
119 {
120 struct qe_init_block *qb = qep->qe_block;
121 struct sunqe_buffers *qbufs = qep->buffers;
122 __u32 qbufs_dvma = qep->buffers_dvma;
123 int i;
124
125 qep->rx_new = qep->rx_old = qep->tx_new = qep->tx_old = 0;
126 memset(qb, 0, sizeof(struct qe_init_block));
127 memset(qbufs, 0, sizeof(struct sunqe_buffers));
128 for (i = 0; i < RX_RING_SIZE; i++) {
129 qb->qe_rxd[i].rx_addr = qbufs_dvma + qebuf_offset(rx_buf, i);
130 qb->qe_rxd[i].rx_flags =
131 (RXD_OWN | ((RXD_PKT_SZ) & RXD_LENGTH));
132 }
133 }
134
135 static int qe_init(struct sunqe *qep, int from_irq)
136 {
137 struct sunqec *qecp = qep->parent;
138 unsigned long cregs = qep->qcregs;
139 unsigned long mregs = qep->mregs;
140 unsigned long gregs = qecp->gregs;
141 unsigned char *e = &qep->dev->dev_addr[0];
142 u32 tmp;
143 int i;
144
145 /* Shut it up. */
146 if (qe_stop(qep))
147 return -EAGAIN;
148
149 /* Setup initial rx/tx init block pointers. */
150 sbus_writel(qep->qblock_dvma + qib_offset(qe_rxd, 0), cregs + CREG_RXDS);
151 sbus_writel(qep->qblock_dvma + qib_offset(qe_txd, 0), cregs + CREG_TXDS);
152
153 /* Enable/mask the various irq's. */
154 sbus_writel(0, cregs + CREG_RIMASK);
155 sbus_writel(1, cregs + CREG_TIMASK);
156
157 sbus_writel(0, cregs + CREG_QMASK);
158 sbus_writel(CREG_MMASK_RXCOLL, cregs + CREG_MMASK);
159
160 /* Setup the FIFO pointers into QEC local memory. */
161 tmp = qep->channel * sbus_readl(gregs + GLOB_MSIZE);
162 sbus_writel(tmp, cregs + CREG_RXRBUFPTR);
163 sbus_writel(tmp, cregs + CREG_RXWBUFPTR);
164
165 tmp = sbus_readl(cregs + CREG_RXRBUFPTR) +
166 sbus_readl(gregs + GLOB_RSIZE);
167 sbus_writel(tmp, cregs + CREG_TXRBUFPTR);
168 sbus_writel(tmp, cregs + CREG_TXWBUFPTR);
169
170 /* Clear the channel collision counter. */
171 sbus_writel(0, cregs + CREG_CCNT);
172
173 /* For 10baseT, inter frame space nor throttle seems to be necessary. */
174 sbus_writel(0, cregs + CREG_PIPG);
175
176 /* Now dork with the AMD MACE. */
177 sbus_writeb(MREGS_PHYCONFIG_AUTO, mregs + MREGS_PHYCONFIG);
178 sbus_writeb(MREGS_TXFCNTL_AUTOPAD, mregs + MREGS_TXFCNTL);
179 sbus_writeb(0, mregs + MREGS_RXFCNTL);
180
181 /* The QEC dma's the rx'd packets from local memory out to main memory,
182 * and therefore it interrupts when the packet reception is "complete".
183 * So don't listen for the MACE talking about it.
184 */
185 sbus_writeb(MREGS_IMASK_COLL | MREGS_IMASK_RXIRQ, mregs + MREGS_IMASK);
186 sbus_writeb(MREGS_BCONFIG_BSWAP | MREGS_BCONFIG_64TS, mregs + MREGS_BCONFIG);
187 sbus_writeb((MREGS_FCONFIG_TXF16 | MREGS_FCONFIG_RXF32 |
188 MREGS_FCONFIG_RFWU | MREGS_FCONFIG_TFWU),
189 mregs + MREGS_FCONFIG);
190
191 /* Only usable interface on QuadEther is twisted pair. */
192 sbus_writeb(MREGS_PLSCONFIG_TP, mregs + MREGS_PLSCONFIG);
193
194 /* Tell MACE we are changing the ether address. */
195 sbus_writeb(MREGS_IACONFIG_ACHNGE | MREGS_IACONFIG_PARESET,
196 mregs + MREGS_IACONFIG);
197 while ((sbus_readb(mregs + MREGS_IACONFIG) & MREGS_IACONFIG_ACHNGE) != 0)
198 barrier();
199 sbus_writeb(e[0], mregs + MREGS_ETHADDR);
200 sbus_writeb(e[1], mregs + MREGS_ETHADDR);
201 sbus_writeb(e[2], mregs + MREGS_ETHADDR);
202 sbus_writeb(e[3], mregs + MREGS_ETHADDR);
203 sbus_writeb(e[4], mregs + MREGS_ETHADDR);
204 sbus_writeb(e[5], mregs + MREGS_ETHADDR);
205
206 /* Clear out the address filter. */
207 sbus_writeb(MREGS_IACONFIG_ACHNGE | MREGS_IACONFIG_LARESET,
208 mregs + MREGS_IACONFIG);
209 while ((sbus_readb(mregs + MREGS_IACONFIG) & MREGS_IACONFIG_ACHNGE) != 0)
210 barrier();
211 for (i = 0; i < 8; i++)
212 sbus_writeb(0, mregs + MREGS_FILTER);
213
214 /* Address changes are now complete. */
215 sbus_writeb(0, mregs + MREGS_IACONFIG);
216
217 qe_init_rings(qep);
218
219 /* Wait a little bit for the link to come up... */
220 mdelay(5);
221 if (!(sbus_readb(mregs + MREGS_PHYCONFIG) & MREGS_PHYCONFIG_LTESTDIS)) {
222 int tries = 50;
223
224 while (tries--) {
225 u8 tmp;
226
227 mdelay(5);
228 barrier();
229 tmp = sbus_readb(mregs + MREGS_PHYCONFIG);
230 if ((tmp & MREGS_PHYCONFIG_LSTAT) != 0)
231 break;
232 }
233 if (tries == 0)
234 printk(KERN_NOTICE "%s: Warning, link state is down.\n", qep->dev->name);
235 }
236
237 /* Missed packet counter is cleared on a read. */
238 sbus_readb(mregs + MREGS_MPCNT);
239
240 /* Reload multicast information, this will enable the receiver
241 * and transmitter.
242 */
243 qe_set_multicast(qep->dev);
244
245 /* QEC should now start to show interrupts. */
246 return 0;
247 }
248
249 /* Grrr, certain error conditions completely lock up the AMD MACE,
250 * so when we get these we _must_ reset the chip.
251 */
252 static int qe_is_bolixed(struct sunqe *qep, u32 qe_status)
253 {
254 struct net_device *dev = qep->dev;
255 int mace_hwbug_workaround = 0;
256
257 if (qe_status & CREG_STAT_EDEFER) {
258 printk(KERN_ERR "%s: Excessive transmit defers.\n", dev->name);
259 qep->net_stats.tx_errors++;
260 }
261
262 if (qe_status & CREG_STAT_CLOSS) {
263 printk(KERN_ERR "%s: Carrier lost, link down?\n", dev->name);
264 qep->net_stats.tx_errors++;
265 qep->net_stats.tx_carrier_errors++;
266 }
267
268 if (qe_status & CREG_STAT_ERETRIES) {
269 printk(KERN_ERR "%s: Excessive transmit retries (more than 16).\n", dev->name);
270 qep->net_stats.tx_errors++;
271 mace_hwbug_workaround = 1;
272 }
273
274 if (qe_status & CREG_STAT_LCOLL) {
275 printk(KERN_ERR "%s: Late transmit collision.\n", dev->name);
276 qep->net_stats.tx_errors++;
277 qep->net_stats.collisions++;
278 mace_hwbug_workaround = 1;
279 }
280
281 if (qe_status & CREG_STAT_FUFLOW) {
282 printk(KERN_ERR "%s: Transmit fifo underflow, driver bug.\n", dev->name);
283 qep->net_stats.tx_errors++;
284 mace_hwbug_workaround = 1;
285 }
286
287 if (qe_status & CREG_STAT_JERROR) {
288 printk(KERN_ERR "%s: Jabber error.\n", dev->name);
289 }
290
291 if (qe_status & CREG_STAT_BERROR) {
292 printk(KERN_ERR "%s: Babble error.\n", dev->name);
293 }
294
295 if (qe_status & CREG_STAT_CCOFLOW) {
296 qep->net_stats.tx_errors += 256;
297 qep->net_stats.collisions += 256;
298 }
299
300 if (qe_status & CREG_STAT_TXDERROR) {
301 printk(KERN_ERR "%s: Transmit descriptor is bogus, driver bug.\n", dev->name);
302 qep->net_stats.tx_errors++;
303 qep->net_stats.tx_aborted_errors++;
304 mace_hwbug_workaround = 1;
305 }
306
307 if (qe_status & CREG_STAT_TXLERR) {
308 printk(KERN_ERR "%s: Transmit late error.\n", dev->name);
309 qep->net_stats.tx_errors++;
310 mace_hwbug_workaround = 1;
311 }
312
313 if (qe_status & CREG_STAT_TXPERR) {
314 printk(KERN_ERR "%s: Transmit DMA parity error.\n", dev->name);
315 qep->net_stats.tx_errors++;
316 qep->net_stats.tx_aborted_errors++;
317 mace_hwbug_workaround = 1;
318 }
319
320 if (qe_status & CREG_STAT_TXSERR) {
321 printk(KERN_ERR "%s: Transmit DMA sbus error ack.\n", dev->name);
322 qep->net_stats.tx_errors++;
323 qep->net_stats.tx_aborted_errors++;
324 mace_hwbug_workaround = 1;
325 }
326
327 if (qe_status & CREG_STAT_RCCOFLOW) {
328 qep->net_stats.rx_errors += 256;
329 qep->net_stats.collisions += 256;
330 }
331
332 if (qe_status & CREG_STAT_RUOFLOW) {
333 qep->net_stats.rx_errors += 256;
334 qep->net_stats.rx_over_errors += 256;
335 }
336
337 if (qe_status & CREG_STAT_MCOFLOW) {
338 qep->net_stats.rx_errors += 256;
339 qep->net_stats.rx_missed_errors += 256;
340 }
341
342 if (qe_status & CREG_STAT_RXFOFLOW) {
343 printk(KERN_ERR "%s: Receive fifo overflow.\n", dev->name);
344 qep->net_stats.rx_errors++;
345 qep->net_stats.rx_over_errors++;
346 }
347
348 if (qe_status & CREG_STAT_RLCOLL) {
349 printk(KERN_ERR "%s: Late receive collision.\n", dev->name);
350 qep->net_stats.rx_errors++;
351 qep->net_stats.collisions++;
352 }
353
354 if (qe_status & CREG_STAT_FCOFLOW) {
355 qep->net_stats.rx_errors += 256;
356 qep->net_stats.rx_frame_errors += 256;
357 }
358
359 if (qe_status & CREG_STAT_CECOFLOW) {
360 qep->net_stats.rx_errors += 256;
361 qep->net_stats.rx_crc_errors += 256;
362 }
363
364 if (qe_status & CREG_STAT_RXDROP) {
365 printk(KERN_ERR "%s: Receive packet dropped.\n", dev->name);
366 qep->net_stats.rx_errors++;
367 qep->net_stats.rx_dropped++;
368 qep->net_stats.rx_missed_errors++;
369 }
370
371 if (qe_status & CREG_STAT_RXSMALL) {
372 printk(KERN_ERR "%s: Receive buffer too small, driver bug.\n", dev->name);
373 qep->net_stats.rx_errors++;
374 qep->net_stats.rx_length_errors++;
375 }
376
377 if (qe_status & CREG_STAT_RXLERR) {
378 printk(KERN_ERR "%s: Receive late error.\n", dev->name);
379 qep->net_stats.rx_errors++;
380 mace_hwbug_workaround = 1;
381 }
382
383 if (qe_status & CREG_STAT_RXPERR) {
384 printk(KERN_ERR "%s: Receive DMA parity error.\n", dev->name);
385 qep->net_stats.rx_errors++;
386 qep->net_stats.rx_missed_errors++;
387 mace_hwbug_workaround = 1;
388 }
389
390 if (qe_status & CREG_STAT_RXSERR) {
391 printk(KERN_ERR "%s: Receive DMA sbus error ack.\n", dev->name);
392 qep->net_stats.rx_errors++;
393 qep->net_stats.rx_missed_errors++;
394 mace_hwbug_workaround = 1;
395 }
396
397 if (mace_hwbug_workaround)
398 qe_init(qep, 1);
399 return mace_hwbug_workaround;
400 }
401
402 /* Per-QE receive interrupt service routine. Just like on the happy meal
403 * we receive directly into skb's with a small packet copy water mark.
404 */
405 static void qe_rx(struct sunqe *qep)
406 {
407 struct qe_rxd *rxbase = &qep->qe_block->qe_rxd[0];
408 struct qe_rxd *this;
409 struct sunqe_buffers *qbufs = qep->buffers;
410 __u32 qbufs_dvma = qep->buffers_dvma;
411 int elem = qep->rx_new, drops = 0;
412 u32 flags;
413
414 this = &rxbase[elem];
415 while (!((flags = this->rx_flags) & RXD_OWN)) {
416 struct sk_buff *skb;
417 unsigned char *this_qbuf =
418 &qbufs->rx_buf[elem & (RX_RING_SIZE - 1)][0];
419 __u32 this_qbuf_dvma = qbufs_dvma +
420 qebuf_offset(rx_buf, (elem & (RX_RING_SIZE - 1)));
421 struct qe_rxd *end_rxd =
422 &rxbase[(elem+RX_RING_SIZE)&(RX_RING_MAXSIZE-1)];
423 int len = (flags & RXD_LENGTH) - 4; /* QE adds ether FCS size to len */
424
425 /* Check for errors. */
426 if (len < ETH_ZLEN) {
427 qep->net_stats.rx_errors++;
428 qep->net_stats.rx_length_errors++;
429 qep->net_stats.rx_dropped++;
430 } else {
431 skb = dev_alloc_skb(len + 2);
432 if (skb == NULL) {
433 drops++;
434 qep->net_stats.rx_dropped++;
435 } else {
436 skb->dev = qep->dev;
437 skb_reserve(skb, 2);
438 skb_put(skb, len);
439 eth_copy_and_sum(skb, (unsigned char *) this_qbuf,
440 len, 0);
441 skb->protocol = eth_type_trans(skb, qep->dev);
442 netif_rx(skb);
443 qep->net_stats.rx_packets++;
444 qep->net_stats.rx_bytes += len;
445 }
446 }
447 end_rxd->rx_addr = this_qbuf_dvma;
448 end_rxd->rx_flags = (RXD_OWN | ((RXD_PKT_SZ) & RXD_LENGTH));
449
450 elem = NEXT_RX(elem);
451 this = &rxbase[elem];
452 }
453 qep->rx_new = elem;
454 if (drops)
455 printk(KERN_NOTICE "%s: Memory squeeze, deferring packet.\n", qep->dev->name);
456 }
457
458 static void qe_tx_reclaim(struct sunqe *qep);
459
460 /* Interrupts for all QE's get filtered out via the QEC master controller,
461 * so we just run through each qe and check to see who is signaling
462 * and thus needs to be serviced.
463 */
464 static void qec_interrupt(int irq, void *dev_id, struct pt_regs *regs)
465 {
466 struct sunqec *qecp = (struct sunqec *) dev_id;
467 u32 qec_status;
468 int channel = 0;
469
470 /* Latch the status now. */
471 qec_status = sbus_readl(qecp->gregs + GLOB_STAT);
472 while (channel < 4) {
473 if (qec_status & 0xf) {
474 struct sunqe *qep = qecp->qes[channel];
475 u32 qe_status;
476
477 qe_status = sbus_readl(qep->qcregs + CREG_STAT);
478 if (qe_status & CREG_STAT_ERRORS) {
479 if (qe_is_bolixed(qep, qe_status))
480 goto next;
481 }
482 if (qe_status & CREG_STAT_RXIRQ)
483 qe_rx(qep);
484 if (netif_queue_stopped(qep->dev) &&
485 (qe_status & CREG_STAT_TXIRQ)) {
486 spin_lock(&qep->lock);
487 qe_tx_reclaim(qep);
488 if (TX_BUFFS_AVAIL(qep) > 0) {
489 /* Wake net queue and return to
490 * lazy tx reclaim.
491 */
492 netif_wake_queue(qep->dev);
493 sbus_writel(1, qep->qcregs + CREG_TIMASK);
494 }
495 spin_unlock(&qep->lock);
496 }
497 next:
498 }
499 qec_status >>= 4;
500 channel++;
501 }
502 }
503
504 static int qe_open(struct net_device *dev)
505 {
506 struct sunqe *qep = (struct sunqe *) dev->priv;
507 int res;
508
509 qep->mconfig = (MREGS_MCONFIG_TXENAB |
510 MREGS_MCONFIG_RXENAB |
511 MREGS_MCONFIG_MBAENAB);
512 res = qe_init(qep, 0);
513 if (!res)
514 MOD_INC_USE_COUNT;
515
516 return res;
517 }
518
519 static int qe_close(struct net_device *dev)
520 {
521 struct sunqe *qep = (struct sunqe *) dev->priv;
522
523 qe_stop(qep);
524 MOD_DEC_USE_COUNT;
525 return 0;
526 }
527
528 /* Reclaim TX'd frames from the ring. This must always run under
529 * the IRQ protected qep->lock.
530 */
531 static void qe_tx_reclaim(struct sunqe *qep)
532 {
533 struct qe_txd *txbase = &qep->qe_block->qe_txd[0];
534 int elem = qep->tx_old;
535
536 while (elem != qep->tx_new) {
537 u32 flags = txbase[elem].tx_flags;
538
539 if (flags & TXD_OWN)
540 break;
541 elem = NEXT_TX(elem);
542 }
543 qep->tx_old = elem;
544 }
545
546 static void qe_tx_timeout(struct net_device *dev)
547 {
548 struct sunqe *qep = (struct sunqe *) dev->priv;
549 int tx_full;
550
551 spin_lock_irq(&qep->lock);
552
553 /* Try to reclaim, if that frees up some tx
554 * entries, we're fine.
555 */
556 qe_tx_reclaim(qep);
557 tx_full = TX_BUFFS_AVAIL(qep) <= 0;
558
559 spin_unlock_irq(&qep->lock);
560
561 if (! tx_full)
562 goto out;
563
564 printk(KERN_ERR "%s: transmit timed out, resetting\n", dev->name);
565 qe_init(qep, 1);
566
567 out:
568 netif_wake_queue(dev);
569 }
570
571 /* Get a packet queued to go onto the wire. */
572 static int qe_start_xmit(struct sk_buff *skb, struct net_device *dev)
573 {
574 struct sunqe *qep = (struct sunqe *) dev->priv;
575 struct sunqe_buffers *qbufs = qep->buffers;
576 __u32 txbuf_dvma, qbufs_dvma = qep->buffers_dvma;
577 unsigned char *txbuf;
578 int len, entry;
579
580 spin_lock_irq(&qep->lock);
581
582 qe_tx_reclaim(qep);
583
584 len = skb->len;
585 entry = qep->tx_new;
586
587 txbuf = &qbufs->tx_buf[entry & (TX_RING_SIZE - 1)][0];
588 txbuf_dvma = qbufs_dvma +
589 qebuf_offset(tx_buf, (entry & (TX_RING_SIZE - 1)));
590
591 /* Avoid a race... */
592 qep->qe_block->qe_txd[entry].tx_flags = TXD_UPDATE;
593
594 memcpy(txbuf, skb->data, len);
595
596 qep->qe_block->qe_txd[entry].tx_addr = txbuf_dvma;
597 qep->qe_block->qe_txd[entry].tx_flags =
598 (TXD_OWN | TXD_SOP | TXD_EOP | (len & TXD_LENGTH));
599 qep->tx_new = NEXT_TX(entry);
600
601 /* Get it going. */
602 dev->trans_start = jiffies;
603 sbus_writel(CREG_CTRL_TWAKEUP, qep->qcregs + CREG_CTRL);
604
605 qep->net_stats.tx_packets++;
606 qep->net_stats.tx_bytes += len;
607
608 if (TX_BUFFS_AVAIL(qep) <= 0) {
609 /* Halt the net queue and enable tx interrupts.
610 * When the tx queue empties the tx irq handler
611 * will wake up the queue and return us back to
612 * the lazy tx reclaim scheme.
613 */
614 netif_stop_queue(dev);
615 sbus_writel(0, qep->qcregs + CREG_TIMASK);
616 }
617 spin_unlock_irq(&qep->lock);
618
619 dev_kfree_skb(skb);
620
621 return 0;
622 }
623
624 static struct net_device_stats *qe_get_stats(struct net_device *dev)
625 {
626 struct sunqe *qep = (struct sunqe *) dev->priv;
627
628 return &qep->net_stats;
629 }
630
631 #define CRC_POLYNOMIAL_BE 0x04c11db7UL /* Ethernet CRC, big endian */
632 #define CRC_POLYNOMIAL_LE 0xedb88320UL /* Ethernet CRC, little endian */
633
634 static void qe_set_multicast(struct net_device *dev)
635 {
636 struct sunqe *qep = (struct sunqe *) dev->priv;
637 struct dev_mc_list *dmi = dev->mc_list;
638 u8 new_mconfig = qep->mconfig;
639 char *addrs;
640 int i, j, bit, byte;
641 u32 crc, poly = CRC_POLYNOMIAL_LE;
642
643 /* Lock out others. */
644 netif_stop_queue(dev);
645
646 if ((dev->flags & IFF_ALLMULTI) || (dev->mc_count > 64)) {
647 sbus_writeb(MREGS_IACONFIG_ACHNGE | MREGS_IACONFIG_LARESET,
648 qep->mregs + MREGS_IACONFIG);
649 while ((sbus_readb(qep->mregs + MREGS_IACONFIG) & MREGS_IACONFIG_ACHNGE) != 0)
650 barrier();
651 for (i = 0; i < 8; i++)
652 sbus_writeb(0xff, qep->mregs + MREGS_FILTER);
653 sbus_writeb(0, qep->mregs + MREGS_IACONFIG);
654 } else if (dev->flags & IFF_PROMISC) {
655 new_mconfig |= MREGS_MCONFIG_PROMISC;
656 } else {
657 u16 hash_table[4];
658 u8 *hbytes = (unsigned char *) &hash_table[0];
659
660 for (i = 0; i < 4; i++)
661 hash_table[i] = 0;
662
663 for (i = 0; i < dev->mc_count; i++) {
664 addrs = dmi->dmi_addr;
665 dmi = dmi->next;
666
667 if (!(*addrs & 1))
668 continue;
669
670 crc = 0xffffffffU;
671 for (byte = 0; byte < 6; byte++) {
672 for (bit = *addrs++, j = 0; j < 8; j++, bit >>= 1) {
673 int test;
674
675 test = ((bit ^ crc) & 0x01);
676 crc >>= 1;
677 if (test)
678 crc = crc ^ poly;
679 }
680 }
681 crc >>= 26;
682 hash_table[crc >> 4] |= 1 << (crc & 0xf);
683 }
684 /* Program the qe with the new filter value. */
685 sbus_writeb(MREGS_IACONFIG_ACHNGE | MREGS_IACONFIG_LARESET,
686 qep->mregs + MREGS_IACONFIG);
687 while ((sbus_readb(qep->mregs + MREGS_IACONFIG) & MREGS_IACONFIG_ACHNGE) != 0)
688 barrier();
689 for (i = 0; i < 8; i++) {
690 u8 tmp = *hbytes++;
691 sbus_writeb(tmp, qep->mregs + MREGS_FILTER);
692 }
693 sbus_writeb(0, qep->mregs + MREGS_IACONFIG);
694 }
695
696 /* Any change of the logical address filter, the physical address,
697 * or enabling/disabling promiscuous mode causes the MACE to disable
698 * the receiver. So we must re-enable them here or else the MACE
699 * refuses to listen to anything on the network. Sheesh, took
700 * me a day or two to find this bug.
701 */
702 qep->mconfig = new_mconfig;
703 sbus_writeb(qep->mconfig, qep->mregs + MREGS_MCONFIG);
704
705 /* Let us get going again. */
706 netif_wake_queue(dev);
707 }
708
709 /* This is only called once at boot time for each card probed. */
710 static inline void qec_init_once(struct sunqec *qecp, struct sbus_dev *qsdev)
711 {
712 u8 bsizes = qecp->qec_bursts;
713
714 if (sbus_can_burst64(qsdev) && (bsizes & DMA_BURST64)) {
715 sbus_writel(GLOB_CTRL_B64, qecp->gregs + GLOB_CTRL);
716 } else if (bsizes & DMA_BURST32) {
717 sbus_writel(GLOB_CTRL_B32, qecp->gregs + GLOB_CTRL);
718 } else {
719 sbus_writel(GLOB_CTRL_B16, qecp->gregs + GLOB_CTRL);
720 }
721
722 /* Packetsize only used in 100baseT BigMAC configurations,
723 * set it to zero just to be on the safe side.
724 */
725 sbus_writel(GLOB_PSIZE_2048, qecp->gregs + GLOB_PSIZE);
726
727 /* Set the local memsize register, divided up to one piece per QE channel. */
728 sbus_writel((qsdev->reg_addrs[1].reg_size >> 2),
729 qecp->gregs + GLOB_MSIZE);
730
731 /* Divide up the local QEC memory amongst the 4 QE receiver and
732 * transmitter FIFOs. Basically it is (total / 2 / num_channels).
733 */
734 sbus_writel((qsdev->reg_addrs[1].reg_size >> 2) >> 1,
735 qecp->gregs + GLOB_TSIZE);
736 sbus_writel((qsdev->reg_addrs[1].reg_size >> 2) >> 1,
737 qecp->gregs + GLOB_RSIZE);
738 }
739
740 /* Four QE's per QEC card. */
741 static int __init qec_ether_init(struct net_device *dev, struct sbus_dev *sdev)
742 {
743 static unsigned version_printed = 0;
744 struct net_device *qe_devs[4];
745 struct sunqe *qeps[4];
746 struct sbus_dev *qesdevs[4];
747 struct sunqec *qecp = NULL;
748 u8 bsizes, bsizes_more;
749 int i, j, res = ENOMEM;
750
751 dev = init_etherdev(0, sizeof(struct sunqe));
752 qe_devs[0] = dev;
753 qeps[0] = (struct sunqe *) dev->priv;
754 qeps[0]->channel = 0;
755 spin_lock_init(&qeps[0]->lock);
756 for (j = 0; j < 6; j++)
757 qe_devs[0]->dev_addr[j] = idprom->id_ethaddr[j];
758
759 if (version_printed++ == 0)
760 printk(KERN_INFO "%s", version);
761
762 qe_devs[1] = qe_devs[2] = qe_devs[3] = NULL;
763 for (i = 1; i < 4; i++) {
764 qe_devs[i] = init_etherdev(0, sizeof(struct sunqe));
765 if (qe_devs[i] == NULL || qe_devs[i]->priv == NULL)
766 goto qec_free_devs;
767 qeps[i] = (struct sunqe *) qe_devs[i]->priv;
768 for (j = 0; j < 6; j++)
769 qe_devs[i]->dev_addr[j] = idprom->id_ethaddr[j];
770 qeps[i]->channel = i;
771 }
772 qecp = kmalloc(sizeof(struct sunqec), GFP_KERNEL);
773 if (qecp == NULL)
774 goto qec_free_devs;
775 qecp->qec_sdev = sdev;
776
777 for (i = 0; i < 4; i++) {
778 qecp->qes[i] = qeps[i];
779 qeps[i]->dev = qe_devs[i];
780 qeps[i]->parent = qecp;
781 }
782
783 /* Link in channel 0. */
784 i = prom_getintdefault(sdev->child->prom_node, "channel#", -1);
785 if (i == -1) { res=ENODEV; goto qec_free_devs; }
786 qesdevs[i] = sdev->child;
787
788 /* Link in channel 1. */
789 i = prom_getintdefault(sdev->child->next->prom_node, "channel#", -1);
790 if (i == -1) { res=ENODEV; goto qec_free_devs; }
791 qesdevs[i] = sdev->child->next;
792
793 /* Link in channel 2. */
794 i = prom_getintdefault(sdev->child->next->next->prom_node, "channel#", -1);
795 if (i == -1) { res=ENODEV; goto qec_free_devs; }
796 qesdevs[i] = sdev->child->next->next;
797
798 /* Link in channel 3. */
799 i = prom_getintdefault(sdev->child->next->next->next->prom_node, "channel#", -1);
800 if (i == -1) { res=ENODEV; goto qec_free_devs; }
801 qesdevs[i] = sdev->child->next->next->next;
802
803 for (i = 0; i < 4; i++)
804 qeps[i]->qe_sdev = qesdevs[i];
805
806 /* Now map in the registers, QEC globals first. */
807 qecp->gregs = sbus_ioremap(&sdev->resource[0], 0,
808 GLOB_REG_SIZE, "QEC Global Registers");
809 if (!qecp->gregs) {
810 printk(KERN_ERR "QuadEther: Cannot map QEC global registers.\n");
811 res = ENODEV;
812 goto qec_free_devs;
813 }
814
815 /* Make sure the QEC is in MACE mode. */
816 if ((sbus_readl(qecp->gregs + GLOB_CTRL) & 0xf0000000) != GLOB_CTRL_MMODE) {
817 printk(KERN_ERR "QuadEther: AIEEE, QEC is not in MACE mode!\n");
818 res = ENODEV;
819 goto qec_free_devs;
820 }
821
822 /* Reset the QEC. */
823 if (qec_global_reset(qecp->gregs)) {
824 res = ENODEV;
825 goto qec_free_devs;
826 }
827
828 /* Find and set the burst sizes for the QEC, since it does
829 * the actual dma for all 4 channels.
830 */
831 bsizes = prom_getintdefault(sdev->prom_node, "burst-sizes", 0xff);
832 bsizes &= 0xff;
833 bsizes_more = prom_getintdefault(sdev->bus->prom_node, "burst-sizes", 0xff);
834
835 if (bsizes_more != 0xff)
836 bsizes &= bsizes_more;
837 if (bsizes == 0xff || (bsizes & DMA_BURST16) == 0 ||
838 (bsizes & DMA_BURST32)==0)
839 bsizes = (DMA_BURST32 - 1);
840
841 qecp->qec_bursts = bsizes;
842
843 /* Perform one time QEC initialization, we never touch the QEC
844 * globals again after this.
845 */
846 qec_init_once(qecp, sdev);
847
848 for (i = 0; i < 4; i++) {
849 /* Map in QEC per-channel control registers. */
850 qeps[i]->qcregs = sbus_ioremap(&qesdevs[i]->resource[0], 0,
851 CREG_REG_SIZE, "QEC Channel Registers");
852 if (!qeps[i]->qcregs) {
853 printk(KERN_ERR "QuadEther: Cannot map QE %d's channel registers.\n", i);
854 res = ENODEV;
855 goto qec_free_devs;
856 }
857
858 /* Map in per-channel AMD MACE registers. */
859 qeps[i]->mregs = sbus_ioremap(&qesdevs[i]->resource[1], 0,
860 MREGS_REG_SIZE, "QE MACE Registers");
861 if (!qeps[i]->mregs) {
862 printk(KERN_ERR "QuadEther: Cannot map QE %d's MACE registers.\n", i);
863 res = ENODEV;
864 goto qec_free_devs;
865 }
866
867 qeps[i]->qe_block = sbus_alloc_consistent(qesdevs[i],
868 PAGE_SIZE,
869 &qeps[i]->qblock_dvma);
870 qeps[i]->buffers = sbus_alloc_consistent(qesdevs[i],
871 sizeof(struct sunqe_buffers),
872 &qeps[i]->buffers_dvma);
873 if (qeps[i]->qe_block == NULL ||
874 qeps[i]->qblock_dvma == 0 ||
875 qeps[i]->buffers == NULL ||
876 qeps[i]->buffers_dvma == 0) {
877 res = ENODEV;
878 goto qec_free_devs;
879 }
880
881 /* Stop this QE. */
882 qe_stop(qeps[i]);
883 }
884
885 for (i = 0; i < 4; i++) {
886 qe_devs[i]->open = qe_open;
887 qe_devs[i]->stop = qe_close;
888 qe_devs[i]->hard_start_xmit = qe_start_xmit;
889 qe_devs[i]->get_stats = qe_get_stats;
890 qe_devs[i]->set_multicast_list = qe_set_multicast;
891 qe_devs[i]->tx_timeout = qe_tx_timeout;
892 qe_devs[i]->watchdog_timeo = 5*HZ;
893 qe_devs[i]->irq = sdev->irqs[0];
894 qe_devs[i]->dma = 0;
895 ether_setup(qe_devs[i]);
896 }
897
898 /* QEC receives interrupts from each QE, then it sends the actual
899 * IRQ to the cpu itself. Since QEC is the single point of
900 * interrupt for all QE channels we register the IRQ handler
901 * for it now.
902 */
903 if (request_irq(sdev->irqs[0], &qec_interrupt,
904 SA_SHIRQ, "QuadEther", (void *) qecp)) {
905 printk(KERN_ERR "QuadEther: Can't register QEC master irq handler.\n");
906 res = EAGAIN;
907 goto qec_free_devs;
908 }
909
910 /* Report the QE channels. */
911 for (i = 0; i < 4; i++) {
912 printk(KERN_INFO "%s: QuadEthernet channel[%d] ", qe_devs[i]->name, i);
913 for (j = 0; j < 6; j++)
914 printk ("%2.2x%c",
915 qe_devs[i]->dev_addr[j],
916 j == 5 ? ' ': ':');
917 printk("\n");
918 }
919
920 #ifdef MODULE
921 /* We are home free at this point, link the qe's into
922 * the master list for later module unloading.
923 */
924 for (i = 0; i < 4; i++)
925 qe_devs[i]->ifindex = dev_new_index();
926 qecp->next_module = root_qec_dev;
927 root_qec_dev = qecp;
928 #endif
929
930 return 0;
931
932 qec_free_devs:
933 for (i = 0; i < 4; i++) {
934 if (qe_devs[i] != NULL) {
935 if (qe_devs[i]->priv) {
936 struct sunqe *qe = (struct sunqe *)qe_devs[i]->priv;
937
938 if (qe->qcregs)
939 sbus_iounmap(qe->qcregs, CREG_REG_SIZE);
940 if (qe->mregs)
941 sbus_iounmap(qe->mregs, MREGS_REG_SIZE);
942 if (qe->qe_block != NULL)
943 sbus_free_consistent(qe->qe_sdev,
944 PAGE_SIZE,
945 qe->qe_block,
946 qe->qblock_dvma);
947 if (qe->buffers != NULL)
948 sbus_free_consistent(qe->qe_sdev,
949 sizeof(struct sunqe_buffers),
950 qe->buffers,
951 qe->buffers_dvma);
952 kfree(qe_devs[i]->priv);
953 }
954 kfree(qe_devs[i]);
955 }
956 }
957 if (qecp != NULL) {
958 if (qecp->gregs)
959 sbus_iounmap(qecp->gregs, GLOB_REG_SIZE);
960 kfree(qecp);
961 }
962 return res;
963 }
964
965 static int __init qec_match(struct sbus_dev *sdev)
966 {
967 struct sbus_dev *sibling;
968 int i;
969
970 if (strcmp(sdev->prom_name, "qec") != 0)
971 return 0;
972
973 /* QEC can be parent of either QuadEthernet or BigMAC
974 * children. Do not confuse this with qfe/SUNW,qfe
975 * which is a quad-happymeal card and handled by
976 * a different driver.
977 */
978 sibling = sdev->child;
979 for (i = 0; i < 4; i++) {
980 if (sibling == NULL)
981 return 0;
982 if (strcmp(sibling->prom_name, "qe") != 0)
983 return 0;
984 sibling = sibling->next;
985 }
986 return 1;
987 }
988
989 static int __init qec_probe(void)
990 {
991 struct net_device *dev = NULL;
992 struct sbus_bus *bus;
993 struct sbus_dev *sdev = 0;
994 static int called = 0;
995 int cards = 0, v;
996
997 #ifdef MODULE
998 root_qec_dev = NULL;
999 #endif
1000
1001 if (called)
1002 return -ENODEV;
1003 called++;
1004
1005 for_each_sbus(bus) {
1006 for_each_sbusdev(sdev, bus) {
1007 if (cards)
1008 dev = NULL;
1009
1010 if (qec_match(sdev)) {
1011 cards++;
1012 if ((v = qec_ether_init(dev, sdev)))
1013 return v;
1014 }
1015 }
1016 }
1017 if (!cards)
1018 return -ENODEV;
1019 return 0;
1020 }
1021
1022 static void __exit qec_cleanup(void)
1023 {
1024 #ifdef MODULE
1025 struct sunqec *next_qec;
1026 int i;
1027
1028 /* No need to check MOD_IN_USE, as sys_delete_module() checks. */
1029 while (root_qec_dev) {
1030 next_qec = root_qec_dev->next_module;
1031
1032 /* Release all four QE channels, then the QEC itself. */
1033 for (i = 0; i < 4; i++) {
1034 unregister_netdev(root_qec_dev->qes[i]->dev);
1035 sbus_iounmap(root_qec_dev->qes[i]->qcregs, CREG_REG_SIZE);
1036 sbus_iounmap(root_qec_dev->qes[i]->mregs, MREGS_REG_SIZE);
1037 sbus_free_consistent(root_qec_dev->qes[i]->qe_sdev,
1038 PAGE_SIZE,
1039 root_qec_dev->qes[i]->qe_block,
1040 root_qec_dev->qes[i]->qblock_dvma);
1041 sbus_free_consistent(root_qec_dev->qes[i]->qe_sdev,
1042 sizeof(struct sunqe_buffers),
1043 root_qec_dev->qes[i]->buffers,
1044 root_qec_dev->qes[i]->buffers_dvma);
1045 kfree(root_qec_dev->qes[i]->dev);
1046 }
1047 free_irq(root_qec_dev->qec_sdev->irqs[0], (void *)root_qec_dev);
1048 sbus_iounmap(root_qec_dev->gregs, GLOB_REG_SIZE);
1049 kfree(root_qec_dev);
1050 root_qec_dev = next_qec;
1051 }
1052 #endif /* MODULE */
1053 }
1054
1055 module_init(qec_probe);
1056 module_exit(qec_cleanup);
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