1 /* sis900.h Definitions for SiS ethernet controllers including 7014/7016 and 900
2 * Copyright 1999 Silicon Integrated System Corporation
4 * SiS 7016 Fast Ethernet PCI Bus 10/100 Mbps LAN Controller with OnNow Support,
5 * preliminary Rev. 1.0 Jan. 14, 1998
6 * SiS 900 Fast Ethernet PCI Bus 10/100 Mbps LAN Single Chip with OnNow Support,
7 * preliminary Rev. 1.0 Nov. 10, 1998
8 * SiS 7014 Single Chip 100BASE-TX/10BASE-T Physical Layer Solution,
9 * preliminary Rev. 1.0 Jan. 18, 1998
10 * http://www.sis.com.tw/support/databook.htm
13 /* MAC operationl registers of SiS 7016 and SiS 900 ehternet controller */
14 /* The I/O extent, SiS 900 needs 256 bytes of io address */
15 #define SIS900_TOTAL_SIZE 0x100
17 /* Symbolic offsets to registers. */
18 enum sis900_registers
{
19 cr
=0x0, //Command Register
20 cfg
=0x4, //Configuration Register
21 mear
=0x8, //EEPROM Access Register
22 ptscr
=0xc, //PCI Test Control Register
23 isr
=0x10, //Interrupt Status Register
24 imr
=0x14, //Interrupt Mask Register
25 ier
=0x18, //Interrupt Enable Register
26 epar
=0x18, //Enhanced PHY Access Register
27 txdp
=0x20, //Transmit Descriptor Pointer Register
28 txcfg
=0x24, //Transmit Configuration Register
29 rxdp
=0x30, //Receive Descriptor Pointer Register
30 rxcfg
=0x34, //Receive Configuration Register
31 flctrl
=0x38, //Flow Control Register
32 rxlen
=0x3c, //Receive Packet Length Register
33 rfcr
=0x48, //Receive Filter Control Register
34 rfdr
=0x4C, //Receive Filter Data Register
35 pmctrl
=0xB0, //Power Management Control Register
36 pmer
=0xB4 //Power Management Wake-up Event Register
39 /* Symbolic names for bits in various registers */
40 enum sis900_command_register_bits
{
41 RESET
= 0x00000100, SWI
= 0x00000080, RxRESET
= 0x00000020,
42 TxRESET
= 0x00000010, RxDIS
= 0x00000008, RxENA
= 0x00000004,
43 TxDIS
= 0x00000002, TxENA
= 0x00000001
46 enum sis900_configuration_register_bits
{
47 DESCRFMT
= 0x00000100 /* 7016 specific */, REQALG
= 0x00000080,
48 SB
= 0x00000040, POW
= 0x00000020, EXD
= 0x00000010,
49 PESEL
= 0x00000008, LPM
= 0x00000004, BEM
= 0x00000001
52 enum sis900_eeprom_access_reigster_bits
{
53 MDC
= 0x00000040, MDDIR
= 0x00000020, MDIO
= 0x00000010, /* 7016 specific */
54 EECS
= 0x00000008, EECLK
= 0x00000004, EEDO
= 0x00000002,
58 enum sis900_interrupt_register_bits
{
59 WKEVT
= 0x10000000, TxPAUSEEND
= 0x08000000, TxPAUSE
= 0x04000000,
60 TxRCMP
= 0x02000000, RxRCMP
= 0x01000000, DPERR
= 0x00800000,
61 SSERR
= 0x00400000, RMABT
= 0x00200000, RTABT
= 0x00100000,
62 RxSOVR
= 0x00010000, HIBERR
= 0x00008000, SWINT
= 0x00001000,
63 MIBINT
= 0x00000800, TxURN
= 0x00000400, TxIDLE
= 0x00000200,
64 TxERR
= 0x00000100, TxDESC
= 0x00000080, TxOK
= 0x00000040,
65 RxORN
= 0x00000020, RxIDLE
= 0x00000010, RxEARLY
= 0x00000008,
66 RxERR
= 0x00000004, RxDESC
= 0x00000002, RxOK
= 0x00000001
69 enum sis900_interrupt_enable_reigster_bits
{
73 /* maximum dma burst fro transmission and receive*/
74 #define MAX_DMA_RANGE 7 /* actually 0 means MAXIMUM !! */
75 #define TxMXDMA_shift 20
76 #define RxMXDMA_shift 20
77 #define TX_DMA_BURST 0
78 #define RX_DMA_BURST 0
80 /* transmit FIFO threshholds */
81 #define TX_FILL_THRESH 16 /* 1/4 FIFO size */
82 #define TxFILLT_shift 8
83 #define TxDRNT_shift 0
84 #define TxDRNT_100 48 /* 3/4 FIFO size */
85 #define TxDRNT_10 16 /* 1/2 FIFO size */
87 enum sis900_transmit_config_register_bits
{
88 TxCSI
= 0x80000000, TxHBI
= 0x40000000, TxMLB
= 0x20000000,
89 TxATP
= 0x10000000, TxIFG
= 0x0C000000, TxFILLT
= 0x00003F00,
93 /* recevie FIFO thresholds */
94 #define RxDRNT_shift 1
95 #define RxDRNT_100 16 /* 1/2 FIFO size */
96 #define RxDRNT_10 24 /* 3/4 FIFO size */
98 enum sis900_reveive_config_register_bits
{
99 RxAEP
= 0x80000000, RxARP
= 0x40000000, RxATX
= 0x10000000,
100 RxAJAB
= 0x08000000, RxDRNT
= 0x0000007F
103 #define RFAA_shift 28
104 #define RFADDR_shift 16
106 enum sis900_receive_filter_control_register_bits
{
107 RFEN
= 0x80000000, RFAAB
= 0x40000000, RFAAM
= 0x20000000,
108 RFAAP
= 0x10000000, RFPromiscuous
= (RFAAB
|RFAAM
|RFAAP
)
111 enum sis900_reveive_filter_data_mask
{
115 /* EEPROM Addresses */
116 enum sis900_eeprom_address
{
117 EEPROMSignature
= 0x00, EEPROMVendorID
= 0x02, EEPROMDeviceID
= 0x03,
118 EEPROMMACAddr
= 0x08, EEPROMChecksum
= 0x0b
121 /* The EEPROM commands include the alway-set leading bit. Refer to NM93Cxx datasheet */
122 enum sis900_eeprom_command
{
123 EEread
= 0x0180, EEwrite
= 0x0140, EEerase
= 0x01C0,
124 EEwriteEnable
= 0x0130, EEwriteDisable
= 0x0100,
125 EEeraseAll
= 0x0120, EEwriteAll
= 0x0110,
126 EEaddrMask
= 0x013F, EEcmdShift
= 16
129 /* Manamgement Data I/O (mdio) frame */
130 #define MIIread 0x6000
131 #define MIIwrite 0x5002
132 #define MIIpmdShift 7
133 #define MIIregShift 2
135 #define MIIcmdShift 16
137 /* Buffer Descriptor Status*/
138 enum sis900_buffer_status
{
139 OWN
= 0x80000000, MORE
= 0x40000000, INTR
= 0x20000000,
140 SUPCRC
= 0x10000000, INCCRC
= 0x10000000,
141 OK
= 0x08000000, DSIZE
= 0x00000FFF
143 /* Status for TX Buffers */
144 enum sis900_tx_buffer_status
{
145 ABORT
= 0x04000000, UNDERRUN
= 0x02000000, NOCARRIER
= 0x01000000,
146 DEFERD
= 0x00800000, EXCDEFER
= 0x00400000, OWCOLL
= 0x00200000,
147 EXCCOLL
= 0x00100000, COLCNT
= 0x000F0000
150 enum sis900_rx_bufer_status
{
151 OVERRUN
= 0x02000000, DEST
= 0x00800000, BCAST
= 0x01800000,
152 MCAST
= 0x01000000, UNIMATCH
= 0x00800000, TOOLONG
= 0x00400000,
153 RUNT
= 0x00200000, RXISERR
= 0x00100000, CRCERR
= 0x00080000,
154 FAERR
= 0x00040000, LOOPBK
= 0x00020000, RXCOL
= 0x00010000
157 /* MII register offsets */
159 MII_CONTROL
= 0x0000, MII_STATUS
= 0x0001, MII_PHY_ID0
= 0x0002,
160 MII_PHY_ID1
= 0x0003, MII_ANADV
= 0x0004, MII_ANLPAR
= 0x0005,
164 /* mii registers specific to SiS 900 */
165 enum sis_mii_registers
{
166 MII_CONFIG1
= 0x0010, MII_CONFIG2
= 0x0011, MII_STSOUT
= 0x0012,
170 /* mii registers specific to AMD 79C901 */
171 enum amd_mii_registers
{
172 MII_STATUS_SUMMARY
= 0x0018
175 /* MII Control register bit definitions. */
176 enum mii_control_register_bits
{
177 MII_CNTL_FDX
= 0x0100, MII_CNTL_RST_AUTO
= 0x0200,
178 MII_CNTL_ISOLATE
= 0x0400, MII_CNTL_PWRDWN
= 0x0800,
179 MII_CNTL_AUTO
= 0x1000, MII_CNTL_SPEED
= 0x2000,
180 MII_CNTL_LPBK
= 0x4000, MII_CNTL_RESET
= 0x8000
183 /* MII Status register bit */
184 enum mii_status_register_bits
{
185 MII_STAT_EXT
= 0x0001, MII_STAT_JAB
= 0x0002,
186 MII_STAT_LINK
= 0x0004, MII_STAT_CAN_AUTO
= 0x0008,
187 MII_STAT_FAULT
= 0x0010, MII_STAT_AUTO_DONE
= 0x0020,
188 MII_STAT_CAN_T
= 0x0800, MII_STAT_CAN_T_FDX
= 0x1000,
189 MII_STAT_CAN_TX
= 0x2000, MII_STAT_CAN_TX_FDX
= 0x4000,
190 MII_STAT_CAN_T4
= 0x8000
193 #define MII_ID1_OUI_LO 0xFC00 /* low bits of OUI mask */
194 #define MII_ID1_MODEL 0x03F0 /* model number */
195 #define MII_ID1_REV 0x000F /* model number */
197 /* MII NWAY Register Bits ...
198 valid for the ANAR (Auto-Negotiation Advertisement) and
199 ANLPAR (Auto-Negotiation Link Partner) registers */
200 enum mii_nway_register_bits
{
201 MII_NWAY_NODE_SEL
= 0x001f, MII_NWAY_CSMA_CD
= 0x0001,
202 MII_NWAY_T
= 0x0020, MII_NWAY_T_FDX
= 0x0040,
203 MII_NWAY_TX
= 0x0080, MII_NWAY_TX_FDX
= 0x0100,
204 MII_NWAY_T4
= 0x0200, MII_NWAY_PAUSE
= 0x0400,
205 MII_NWAY_RF
= 0x2000, MII_NWAY_ACK
= 0x4000,
209 enum mii_stsout_register_bits
{
210 MII_STSOUT_LINK_FAIL
= 0x4000,
211 MII_STSOUT_SPD
= 0x0080, MII_STSOUT_DPLX
= 0x0040
214 enum mii_stssum_register_bits
{
215 MII_STSSUM_LINK
= 0x0008, MII_STSSUM_DPLX
= 0x0004,
216 MII_STSSUM_AUTO
= 0x0002, MII_STSSUM_SPD
= 0x0001
219 #define FDX_CAPABLE_DUPLEX_UNKNOWN 0
220 #define FDX_CAPABLE_HALF_SELECTED 1
221 #define FDX_CAPABLE_FULL_SELECTED 2
223 #define HW_SPEED_UNCONFIG 0
224 #define HW_SPEED_HOME 1
225 #define HW_SPEED_10_MBPS 10
226 #define HW_SPEED_100_MBPS 100
227 #define HW_SPEED_DEFAULT (HW_SPEED_100_MBPS)
230 #define MAC_HEADER_SIZE 14
232 #define TX_BUF_SIZE 1536
233 #define RX_BUF_SIZE 1536
235 #define NUM_TX_DESC 16 /* Number of Tx descriptor registers. */
236 #define NUM_RX_DESC 16 /* Number of Rx descriptor registers. */
241 /* PCI stuff, should be move to pic.h */
242 #define PCI_DEVICE_ID_SI_900 0x900
243 #define PCI_DEVICE_ID_SI_7016 0x7016
245 /* ioctl for accessing MII transveiver */
246 #define SIOCGMIIPHY (SIOCDEVPRIVATE) /* Get the PHY in use. */
247 #define SIOCGMIIREG (SIOCDEVPRIVATE+1) /* Read a PHY register. */
248 #define SIOCSMIIREG (SIOCDEVPRIVATE+2) /* Write a PHY register */