3 * pt.c: Linux device driver for the Gracilis PackeTwin.
4 * Copyright (c) 1995 Craig Small VK2XLZ (vk2xlz@vk2xlz.ampr.org.)
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2, as
8 * published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software Foundation,
17 * Inc., 675 Mass Ave, Cambridge MA 02139, USA.
19 * This driver is largely based upon the PI driver by David Perry.
22 * 23/02/95 cs Started again on driver, last one scrapped
23 * 27/02/95 cs Program works, we have chan A only. Tx stays on
24 * 28/02/95 cs Fix Tx problem (& TxUIE instead of | )
25 * Fix Chan B Tx timer problem, used TMR2 instead of TMR1
26 * 03/03/95 cs Painfully found out (after 3 days) SERIAL_CFG is write only
27 * created image of it and DMA_CFG
28 * 21/06/95 cs Upgraded to suit PI driver 0.8 ALPHA
29 * 22/08/95 cs Changed it all around to make it like pi driver
30 * 23/08/95 cs It now works, got caught again by TMR2 and we must have
31 * auto-enables for daughter boards.
32 * 07/10/95 cs Fixed for 1.3.30 (hopefully)
33 * 26/11/95 cs Fixed for 1.3.43, ala 29/10 for pi2.c by ac
34 * 21/12/95 cs Got rid of those nasty warnings when compiling, for 1.3.48
35 * 08/08/96 jsn Convert to use as a module. Removed send_kiss, empty_scc and
36 * pt_loopback functions - they were unused.
37 * 13/12/96 jsn Fixed to match Linux networking changes.
41 * default configuration of the PackeTwin,
42 * ie What Craig uses his PT for.
46 #define DEF_A_SPEED 4800 /* 4800 baud */
47 #define DEF_A_TXDELAY 350 /* 350 mS */
48 #define DEF_A_PERSIST 64 /* 25% persistence */
49 #define DEF_A_SLOTIME 10 /* 10 mS */
50 #define DEF_A_SQUELDELAY 30 /* 30 mS */
51 #define DEF_A_CLOCKMODE 0 /* Normal clock mode */
52 #define DEF_A_NRZI 1 /* NRZI mode */
54 #define DEF_B_SPEED 0 /* 0 means external clock */
55 #define DEF_B_TXDELAY 250 /* 250 mS */
56 #define DEF_B_PERSIST 64 /* 25% */
57 #define DEF_B_SLOTIME 10 /* 10 mS */
58 #define DEF_B_SQUELDELAY 30 /* 30 mS */
59 #define DEF_B_CLOCKMODE 0 /* Normal clock mode ?!? */
60 #define DEF_B_NRZI 1 /* NRZI mode */
63 #define PARAM_TXDELAY 1
64 #define PARAM_PERSIST 2
65 #define PARAM_SLOTTIME 3
66 #define PARAM_FULLDUP 5
67 #define PARAM_HARDWARE 6
68 #define PARAM_RETURN 255
70 #include <linux/config.h>
71 #include <linux/kernel.h>
72 #include <linux/module.h>
73 #include <linux/sched.h>
74 #include <linux/types.h>
75 #include <linux/fcntl.h>
76 #include <linux/interrupt.h>
77 #include <linux/ptrace.h>
78 #include <linux/ioport.h>
80 #include <linux/malloc.h>
81 #include <linux/string.h>
82 #include <linux/errno.h>
83 #include <asm/system.h>
84 #include <asm/bitops.h>
87 #include <asm/uaccess.h>
88 #include <linux/inet.h>
89 #include <linux/netdevice.h>
90 #include <linux/etherdevice.h>
91 #include <linux/skbuff.h>
92 #include <linux/timer.h>
93 #include <linux/if_arp.h>
95 #include <linux/init.h>
106 * The actual PT devices we will use
108 static int pt0_preprobe(struct device
*dev
) {return 0;} /* Dummy probe function */
109 static struct device pt0a
= { "pt0a", 0, 0, 0, 0, 0, 0, 0, 0, 0, NULL
, pt0_preprobe
};
110 static struct device pt0b
= { "pt0b", 0, 0, 0, 0, 0, 0, 0, 0, 0, NULL
, pt0_preprobe
};
112 /* Ok, they shouldn't be here, but both channels share them */
113 /* The Images of the Serial and DMA config registers */
114 static unsigned char pt_sercfg
= 0;
115 static unsigned char pt_dmacfg
= 0;
117 /* The number of IO ports used by the card */
118 #define PT_TOTAL_SIZE 16
120 /* Index to functions, as function prototypes. */
122 static int pt_probe(struct device
*dev
);
123 static int pt_open(struct device
*dev
);
124 static int pt_send_packet(struct sk_buff
*skb
, struct device
*dev
);
125 static void pt_interrupt(int irq
, void *dev_id
, struct pt_regs
*regs
);
126 static int pt_close(struct device
*dev
);
127 static int pt_ioctl(struct device
*dev
, struct ifreq
*ifr
, int cmd
);
128 static struct net_device_stats
*pt_get_stats(struct device
*dev
);
129 static void pt_rts(struct pt_local
*lp
, int x
);
130 static void pt_rxisr(struct device
*dev
);
131 static void pt_txisr(struct pt_local
*lp
);
132 static void pt_exisr(struct pt_local
*lp
);
133 static void pt_tmrisr(struct pt_local
*lp
);
134 static char *get_dma_buffer(unsigned long *mem_ptr
);
135 static int valid_dma_page(unsigned long addr
, unsigned long dev_buffsize
);
136 static int hw_probe(int ioaddr
);
137 static void tdelay(struct pt_local
*lp
, int time
);
138 static void chipset_init(struct device
*dev
);
140 static char ax25_bcast
[7] =
141 {'Q' << 1, 'S' << 1, 'T' << 1, ' ' << 1, ' ' << 1, ' ' << 1, '0' << 1};
142 static char ax25_test
[7] =
143 {'L' << 1, 'I' << 1, 'N' << 1, 'U' << 1, 'X' << 1, ' ' << 1, '1' << 1};
147 static int ext2_secrm_seed
= 152;
149 static inline unsigned char random(void)
151 return (unsigned char) (ext2_secrm_seed
= ext2_secrm_seed
* 60691 + 1);
154 static inline void wrtscc(int cbase
, int ctl
, int sccreg
, unsigned char val
)
156 outb_p(sccreg
, ctl
); /* Select register */
157 outb_p(val
, ctl
); /* Output value */
160 static inline unsigned char rdscc(int cbase
, int ctl
, int sccreg
)
162 unsigned char retval
;
164 outb_p(sccreg
, ctl
); /* Select register */
169 static void switchbuffers(struct pt_local
*lp
)
171 if (lp
->rcvbuf
== lp
->rxdmabuf1
)
172 lp
->rcvbuf
= lp
->rxdmabuf2
;
174 lp
->rcvbuf
= lp
->rxdmabuf1
;
177 static void hardware_send_packet(struct pt_local
*lp
, struct sk_buff
*skb
)
184 /* First, let's see if this packet is actually a KISS packet */
186 if (ptr
[0] != 0 && skb
->len
>= 2)
189 printk(KERN_DEBUG
"PT: Rx KISS... Control = %d, value = %d.\n", ptr
[0], (skb
->len
> 1? ptr
[1] : -1));
191 /* Kludge to get device */
192 if ((struct pt_local
*)(&pt0b
.priv
) == lp
)
200 /*TxDelay is in 10mS increments */
201 lp
->txdelay
= ptr
[1] * 10;
204 lp
->persist
= ptr
[1];
207 lp
->slotime
= ptr
[1];
210 /* Yeah right, you wish! Fullduplex is a little while to
211 * go folks, but this is how you fire it up
214 /* Perhaps we should have txtail here?? */
219 lp
->stats
.tx_packets
++;
220 lp
->stats
.tx_bytes
+=skb
->len
;
223 kickflag
= (skb_peek(&lp
->sndq
) == NULL
) && (lp
->sndbuf
== NULL
);
224 restore_flags(flags
);
227 printk(KERN_DEBUG
"PT: hardware_send_packet(): kickflag = %d (%d).\n", kickflag
, lp
->base
& CHANA
);
229 skb_queue_tail(&lp
->sndq
, skb
);
232 /* Simulate interrupt to transmit */
239 if (lp
->tstate
== IDLE
)
241 restore_flags(flags
);
244 } /* hardware_send_packet() */
246 static void setup_rx_dma(struct pt_local
*lp
)
250 unsigned long dma_abs
;
251 unsigned char dmachan
;
256 dma_abs
= (unsigned long) (lp
->rcvbuf
->data
);
257 dmachan
= lp
->dmachan
;
258 cmd
= lp
->base
+ CTL
;
260 if(!valid_dma_page(dma_abs
, DMA_BUFF_SIZE
+ sizeof(struct mbuf
)))
261 panic("PI: RX buffer violates DMA boundary!");
263 /* Get ready for RX DMA */
264 wrtscc(lp
->cardbase
, cmd
, R1
, WT_FN_RDYFN
| WT_RDY_RT
| INT_ERR_Rx
| EXT_INT_ENAB
);
266 disable_dma(dmachan
);
267 clear_dma_ff(dmachan
);
270 * Set DMA mode register to single transfers, incrementing address,
274 set_dma_mode(dmachan
, DMA_MODE_READ
| 0x10);
275 set_dma_addr(dmachan
, dma_abs
);
276 set_dma_count(dmachan
, lp
->bufsiz
);
280 * If a packet is already coming in, this line is supposed to
281 * avoid receiving a partial packet.
284 wrtscc(lp
->cardbase
, cmd
, R0
, RES_Rx_CRC
);
287 wrtscc(lp
->cardbase
, cmd
, R1
,
288 WT_RDY_ENAB
| WT_FN_RDYFN
| WT_RDY_RT
| INT_ERR_Rx
| EXT_INT_ENAB
);
290 restore_flags(flags
);
293 static void setup_tx_dma(struct pt_local
*lp
, int length
)
295 unsigned long dma_abs
;
297 unsigned long dmachan
;
302 dmachan
= lp
->dmachan
;
303 dma_abs
= (unsigned long) (lp
->txdmabuf
);
305 if(!valid_dma_page(dma_abs
, DMA_BUFF_SIZE
+ sizeof(struct mbuf
)))
306 panic("PT: TX buffer violates DMA boundary!");
308 disable_dma(dmachan
);
309 /* Set DMA mode register to single transfers, incrementing address,
310 * no auto init, reads
312 set_dma_mode(dmachan
, DMA_MODE_WRITE
);
313 clear_dma_ff(dmachan
);
314 set_dma_addr(dmachan
, dma_abs
);
315 /* output byte count */
316 set_dma_count(dmachan
, length
);
318 restore_flags(flags
);
322 * This sets up all the registers in the SCC for the given channel
323 * based upon tsync_hwint()
325 static void scc_init(struct device
*dev
)
328 struct pt_local
*lp
= (struct pt_local
*) dev
->priv
;
329 register int cmd
= lp
->base
+ CTL
;
333 printk(KERN_DEBUG
"PT: scc_init(): (%d).\n", lp
->base
& CHANA
);
338 /* We may put something here to enable_escc */
342 wrtscc(lp
->cardbase
, cmd
, R9
, CHRA
); /* Reset channel A */
343 wrtscc(lp
->cardbase
, cmd
, R2
, 0xff); /* Initialise interrupt vector */
346 wrtscc(lp
->cardbase
, cmd
, R9
, CHRB
); /* Reset channel B */
348 /* Deselect all Rx and Tx interrupts */
349 wrtscc(lp
->cardbase
, cmd
, R1
, 0);
351 /* Turn off external interrupts (like CTS/CD) */
352 wrtscc(lp
->cardbase
, cmd
, R15
, 0);
354 /* X1 clock, SDLC mode */
355 wrtscc(lp
->cardbase
, cmd
, R4
, SDLC
| X1CLK
);
357 /* Preset CRC and set mode */
359 /* Preset Tx CRC, put into NRZI mode */
360 wrtscc(lp
->cardbase
, cmd
, R10
, CRCPS
| NRZI
);
362 /* Preset Tx CRC, put into NRZ mode */
363 wrtscc(lp
->cardbase
, cmd
, R10
, CRCPS
);
365 /* Tx/Rx parameters */
366 if (lp
->speed
) /* Use internal clocking */
367 /* Tx Clk from BRG. Rx Clk form DPLL, TRxC pin outputs DPLL */
368 wrtscc(lp
->cardbase
, cmd
, R11
, TCBR
| RCDPLL
| TRxCDP
| TRxCOI
);
369 else /* Use external clocking */
371 /* Tx Clk from TRxCL. Rx Clk from RTxCL, TRxC pin if input */
372 wrtscc(lp
->cardbase
, cmd
, R11
, TCTRxCP
| RCRTxCP
| TRxCBR
);
373 wrtscc(lp
->cardbase
,cmd
, R14
, 0); /* wiz1 */
376 /* Null out SDLC start address */
377 wrtscc(lp
->cardbase
, cmd
, R6
, 0);
380 wrtscc(lp
->cardbase
, cmd
, R7
, FLAG
);
382 /* Setup Tx but don't enable it */
383 wrtscc(lp
->cardbase
, cmd
, R5
, Tx8
| DTR
);
386 wrtscc(lp
->cardbase
, cmd
, R3
, AUTO_ENAB
| Rx8
);
388 /* Setup the BRG, turn it off first */
389 wrtscc(lp
->cardbase
, cmd
, R14
, BRSRC
);
391 /* set the 32x time constant for the BRG in Rx mode */
395 tc
= ((lp
->xtal
/ 32) / (br
* 2)) - 2;
396 wrtscc(lp
->cardbase
, cmd
, R12
, tc
& 0xff); /* lower byte */
397 wrtscc(lp
->cardbase
, cmd
, R13
, (tc
>> 8) & 0xff); /* upper byte */
400 /* Turn transmitter off, to setup stuff */
403 /* External clocking */
406 /* DPLL frm BRG, BRG src PCLK */
407 wrtscc(lp
->cardbase
, cmd
, R14
, BRSRC
| SSBR
);
408 wrtscc(lp
->cardbase
, cmd
, R14
, BRSRC
| SEARCH
); /* SEARCH mode, keep BRG src */
409 wrtscc(lp
->cardbase
, cmd
, R14
, BRSRC
| BRENABL
); /* Enable the BRG */
411 /* Turn off external clock port */
412 if (lp
->base
& CHANA
)
413 outb_p( (pt_sercfg
&= ~PT_EXTCLKA
), (lp
->cardbase
+ SERIAL_CFG
) );
415 outb_p( (pt_sercfg
&= ~PT_EXTCLKB
), (lp
->cardbase
+ SERIAL_CFG
) );
419 /* DPLL frm rtxc,BRG src PCLK */
420 /* Turn on external clock port */
421 if (lp
->base
& CHANA
)
422 outb_p( (pt_sercfg
|= PT_EXTCLKA
), (lp
->cardbase
+ SERIAL_CFG
) );
424 outb_p( (pt_sercfg
|= PT_EXTCLKB
), (lp
->cardbase
+ SERIAL_CFG
) );
428 wrtscc(lp
->cardbase
, cmd
, R1
, (INT_ALL_Rx
| EXT_INT_ENAB
));
430 wrtscc(lp
->cardbase
, cmd
, R15
, BRKIE
); /* ABORT int */
432 /* Turn on the DTR to tell modem we're alive */
433 if (lp
->base
& CHANA
)
434 outb_p( (pt_sercfg
|= PT_DTRA_ON
), (lp
->cardbase
+ SERIAL_CFG
) );
436 outb_p( (pt_sercfg
|= PT_DTRB_ON
), (lp
->cardbase
+ SERIAL_CFG
) );
438 /* Now, turn on the receiver and hunt for a flag */
439 wrtscc(lp
->cardbase
, cmd
, R3
, RxENABLE
| RxCRC_ENAB
| AUTO_ENAB
| Rx8
);
441 restore_flags(flags
);
445 /* Resets the given channel and whole SCC if both channels off */
446 static void chipset_init(struct device
*dev
)
449 struct pt_local
*lp
= (struct pt_local
*) dev
->priv
;
451 printk(KERN_DEBUG
"PT: chipset_init(): pt0a tstate = %d.\n", ((struct pt_local
*)pt0a
.priv
)->tstate
);
452 printk(KERN_DEBUG
"PT: chipset_init(): pt0b tstate = %d.\n", ((struct pt_local
*)pt0b
.priv
)->tstate
);
454 /* Reset SCC if both channels are to be canned */
455 if ( ((lp
->base
& CHANA
) && !(pt_sercfg
& PT_DTRB_ON
)) ||
456 (!(lp
->base
& CHANA
) && !(pt_sercfg
& PT_DTRA_ON
)) )
458 wrtscc(lp
->cardbase
, lp
->base
+ CTL
, R9
, FHWRES
);
459 /* Reset int and dma registers */
460 outb_p((pt_sercfg
= 0), lp
->cardbase
+ SERIAL_CFG
);
461 outb_p((pt_dmacfg
= 0), lp
->cardbase
+ DMA_CFG
);
463 printk(KERN_DEBUG
"PT: chipset_init() Resetting SCC, called by ch (%d).\n", lp
->base
& CHANA
);
466 /* Reset individual channel */
467 if (lp
->base
& CHANA
) {
468 wrtscc(lp
->cardbase
, lp
->base
+ CTL
, R9
, MIE
| DLC
| NV
| CHRA
);
469 outb_p( (pt_sercfg
&= ~PT_DTRA_ON
), lp
->cardbase
+ SERIAL_CFG
);
471 wrtscc(lp
->cardbase
, lp
->base
+ CTL
, R9
, MIE
| DLC
| NV
| CHRB
);
472 outb_p( (pt_sercfg
&= ~PT_DTRB_ON
), lp
->cardbase
+ SERIAL_CFG
);
474 } /* chipset_init() */
477 int __init
pt_init(void)
483 { 0x230, 0x240, 0x250, 0x260, 0x270, 0x280, 0x290, 0x2a0,
484 0x2b0, 0x300, 0x330, 0x3f0, 0};
486 printk(KERN_INFO
"PT: 0.41 ALPHA 07 October 1995 Craig Small (csmall@small.dropbear.id.au)\n");
488 for (port
= &ports
[0]; *port
&& !card_type
; port
++) {
491 if (check_region(ioaddr
, PT_TOTAL_SIZE
) == 0) {
492 printk(KERN_INFO
"PT: Probing for card at address %#3x\n", ioaddr
);
493 card_type
= hw_probe(ioaddr
);
497 printk(KERN_INFO
"PT: Found a PT at address %#3x\n",ioaddr
);
499 printk(KERN_ERR
"PT: ERROR: No card found.\n");
504 * Link a couple of device structures into the chain
507 * Allocate space for 4 buffers even though we only need 3,
508 * because one of them may cross a DMA page boundary and
509 * be rejected by get_dma_buffer().
511 register_netdev(&pt0a
);
513 pt0a
.priv
= kmalloc(sizeof(struct pt_local
) + (DMA_BUFF_SIZE
+ sizeof(struct mbuf
)) * 4, GFP_KERNEL
| GFP_DMA
);
515 pt0a
.dma
= 0; /* wizzer - no dma yet */
516 pt0a
.base_addr
= ioaddr
+ CHANA
;
520 register_netdev(&pt0b
);
522 pt0b
.priv
= kmalloc(sizeof(struct pt_local
) + (DMA_BUFF_SIZE
+ sizeof(struct mbuf
)) * 4, GFP_KERNEL
| GFP_DMA
);
524 pt0b
.base_addr
= ioaddr
+ CHANB
;
527 /* Now initialise them */
531 pt0b
.irq
= pt0a
.irq
; /* IRQ is shared */
537 * Probe for PT card. Also initialises the timers
539 static int __init
hw_probe(int ioaddr
)
541 int time
= 1000; /* Number of milliseconds to test */
544 unsigned long start_time
, end_time
;
546 inb_p(ioaddr
+ TMR1CLR
);
547 inb_p(ioaddr
+ TMR2CLR
);
549 /* Timer counter channel 0, 1mS period */
550 outb_p(SC0
| LSB_MSB
| MODE3
, ioaddr
+ TMRCMD
);
551 outb_p(0x00, ioaddr
+ TMR0
);
552 outb_p(0x18, ioaddr
+ TMR0
);
554 /* Setup timer control word for timer 1 */
555 outb_p(SC1
| LSB_MSB
| MODE0
, ioaddr
+ TMRCMD
);
556 outb_p((time
<< 1) & 0xff, ioaddr
+ TMR1
);
557 outb_p((time
>> 7) & 0xff, ioaddr
+ TMR1
);
559 /* wait until counter reg is loaded */
561 /* Latch count for reading */
562 outb_p(SC1
, ioaddr
+ TMRCMD
);
563 a
= inb_p(ioaddr
+ TMR1
);
564 b
= inb_p(ioaddr
+ TMR1
);
566 start_time
= jiffies
;
569 /* Latch count for reading */
570 outb_p(SC1
, ioaddr
+ TMRCMD
);
571 a
= inb_p(ioaddr
+ TMR1
);
572 b
= inb_p(ioaddr
+ TMR1
);
574 /* Don't wait forever - there may be no card here */
575 if ((end_time
- start_time
) > 200)
577 inb_p(ioaddr
+ TMR1CLR
);
582 /* Now fix the timers up for general operation */
584 /* Clear the timers */
585 inb_p(ioaddr
+ TMR1CLR
);
586 inb_p(ioaddr
+ TMR2CLR
);
588 outb_p(SC1
| LSB_MSB
| MODE0
, ioaddr
+ TMRCMD
);
589 inb_p(ioaddr
+ TMR1CLR
);
591 outb_p(SC2
| LSB_MSB
| MODE0
, ioaddr
+ TMRCMD
);
592 /* Should this be tmr1 or tmr2? wiz3*/
593 inb_p(ioaddr
+ TMR1CLR
);
599 static void pt_rts(struct pt_local
*lp
, int x
)
603 int cmd
= lp
->base
+ CTL
;
605 printk(KERN_DEBUG
"PT: pt_rts(): Transmitter status will be %d (%d).\n", x
, lp
->base
& CHANA
);
608 /* Ex ints off to avoid int */
609 wrtscc(lp
->cardbase
, cmd
, R15
, 0);
610 wrtscc(lp
->cardbase
, cmd
, R3
, AUTO_ENAB
| Rx8
); /* Rx off */
615 /* Setup for Tx DMA */
616 wrtscc(lp
->cardbase
, cmd
, R1
, WT_FN_RDYFN
| EXT_INT_ENAB
);
619 wrtscc(lp
->cardbase
, cmd
, R1
, 0);
627 tc
= (lp
->xtal
/ (br
* 2)) - 2;
628 wrtscc(lp
->cardbase
, cmd
, R12
, tc
& 0xff);
629 wrtscc(lp
->cardbase
, cmd
, R13
, (tc
>> 8) & 0xff);
632 /* Turn on Tx by raising RTS */
633 wrtscc(lp
->cardbase
, cmd
, R5
, TxCRC_ENAB
| RTS
| TxENAB
| Tx8
| DTR
);
634 /* Transmitter on now */
635 } else { /* turning off Tx */
638 /* Turn off Tx by dropping RTS */
639 wrtscc(lp
->cardbase
, cmd
, R5
, Tx8
| DTR
);
642 if (lp
->speed
) /* internally clocked */
644 /* Reprogram BRG from 32x clock for Rx DPLL */
645 /* BRG off, keep PClk source */
646 wrtscc(lp
->cardbase
, cmd
, R14
, BRSRC
);
648 tc
= ((lp
->xtal
/ 32) / (br
* 2)) - 2;
649 wrtscc(lp
->cardbase
, cmd
, R12
, tc
& 0xff);
650 wrtscc(lp
->cardbase
, cmd
, R13
, (tc
>> 8) & 0xff);
652 /* SEARCH mode, BRG source */
653 wrtscc(lp
->cardbase
, cmd
, R14
, BRSRC
| SEARCH
);
655 wrtscc(lp
->cardbase
, cmd
, R14
, BRSRC
| BRENABL
);
660 wrtscc(lp
->cardbase
, cmd
, R3
, AUTO_ENAB
| Rx8
);
662 /* Reset error latch */
663 wrtscc(lp
->cardbase
, cmd
, R0
, ERR_RES
);
665 /* get status byte from R1 */
666 (void) rdscc(lp
->cardbase
, cmd
, R1
);
668 /* Read and dump data in queue */
669 (void) rdscc(lp
->cardbase
, cmd
, R8
);
670 (void) rdscc(lp
->cardbase
, cmd
, R8
);
671 (void) rdscc(lp
->cardbase
, cmd
, R8
);
673 /* Now, turn on Rx and hunt for a flag */
674 wrtscc(lp
->cardbase
, cmd
, R3
, RxENABLE
| AUTO_ENAB
| Rx8
);
682 /* Reset buffer pointers */
683 lp
->rcp
= lp
->rcvbuf
->data
;
685 /* Allow aborts to interrupt us */
686 wrtscc(lp
->cardbase
, cmd
, R1
, INT_ALL_Rx
| EXT_INT_ENAB
);
689 wrtscc(lp
->cardbase
, cmd
, R15
, BRKIE
);
694 static int valid_dma_page(unsigned long addr
, unsigned long dev_bufsize
)
696 if (((addr
& 0xffff) + dev_bufsize
) <= 0x10000)
702 static int pt_set_mac_address(struct device
*dev
, void *addr
)
704 struct sockaddr
*sa
= (struct sockaddr
*)addr
;
705 memcpy(dev
->dev_addr
, sa
->sa_data
, dev
->addr_len
); /* addr is an AX.25 shifted ASCII */
706 return 0; /* mac address */
710 /* Allocate a buffer which does not cross a DMA page boundary */
711 static char * get_dma_buffer(unsigned long *mem_ptr
)
715 ret
= (char *) *mem_ptr
;
717 if (!valid_dma_page(*mem_ptr
, DMA_BUFF_SIZE
+ sizeof(struct mbuf
))) {
718 *mem_ptr
+= (DMA_BUFF_SIZE
+ sizeof(struct mbuf
));
719 ret
= (char *) *mem_ptr
;
721 *mem_ptr
+= (DMA_BUFF_SIZE
+ sizeof(struct mbuf
));
723 } /* get_dma_buffer() */
727 * Sets up all the structures for the PT device
729 static int pt_probe(struct device
*dev
)
734 unsigned long mem_ptr
;
736 ioaddr
= dev
->base_addr
;
739 * Initialise the device structure.
740 * Must be done before chipset_init()
741 * Make sure data structures used by the PT are aligned
743 dev
->priv
= (void *) (((int) dev
->priv
+ 7) & ~7);
744 lp
= (struct pt_local
*) dev
->priv
;
746 memset(dev
->priv
, 0, sizeof(struct pt_local
));
748 /* Allocate some buffers which do not cross DMA boundaries */
749 mem_ptr
= (unsigned long) dev
->priv
+ sizeof(struct pt_local
);
750 lp
->txdmabuf
= get_dma_buffer(&mem_ptr
);
751 lp
->rxdmabuf1
= (struct mbuf
*) get_dma_buffer(&mem_ptr
);
752 lp
->rxdmabuf2
= (struct mbuf
*) get_dma_buffer(&mem_ptr
);
754 /* Initialise the Rx buffer */
755 lp
->rcvbuf
= lp
->rxdmabuf1
;
756 lp
->rcp
= lp
->rcvbuf
->data
;
759 /* Initialise the transmit queue head structure */
760 skb_queue_head_init(&lp
->sndq
);
762 lp
->base
= dev
->base_addr
;
763 lp
->cardbase
= dev
->base_addr
& 0x3f0;
765 /* These need to be initialised before scc_init() is called.
769 if (dev
->base_addr
& CHANA
) {
770 lp
->speed
= DEF_A_SPEED
;
771 lp
->txdelay
= DEF_A_TXDELAY
;
772 lp
->persist
= DEF_A_PERSIST
;
773 lp
->slotime
= DEF_A_SLOTIME
;
774 lp
->squeldelay
= DEF_A_SQUELDELAY
;
775 lp
->clockmode
= DEF_A_CLOCKMODE
;
776 lp
->nrzi
= DEF_A_NRZI
;
778 lp
->speed
= DEF_B_SPEED
;
779 lp
->txdelay
= DEF_B_TXDELAY
;
780 lp
->persist
= DEF_B_PERSIST
;
781 lp
->slotime
= DEF_B_SLOTIME
;
782 lp
->squeldelay
= DEF_B_SQUELDELAY
;
783 lp
->clockmode
= DEF_B_CLOCKMODE
;
784 lp
->nrzi
= DEF_B_NRZI
;
786 lp
->bufsiz
= DMA_BUFF_SIZE
;
791 if (dev
->base_addr
& CHANA
) {
792 /* Note that a single IRQ services 2 devices (A and B channels)
796 * We disable the dma for a while, we have to get ints working
804 /* Turn on PT interrupts */
807 outb_p( pt_sercfg
|= PT_EI
, lp
->cardbase
+ INT_CFG
);
808 restore_flags(flags
);
810 /* Set a timer interrupt */
812 dev
->irq
= autoirq_report(20);
814 /* Turn off PT interrupts */
817 outb_p( (pt_sercfg
&= ~ PT_EI
), lp
->cardbase
+ INT_CFG
);
818 restore_flags(flags
);
821 printk(KERN_ERR
"PT: ERROR: Failed to detect IRQ line, assuming IRQ7.\n");
825 printk(KERN_INFO
"PT: Autodetected IRQ %d, assuming DMA %d\n", dev
->irq
, dev
->dma
);
827 /* This board has jumpered interrupts. Snarf the interrupt vector
828 * now. There is no point in waiting since no other device can use
829 * the interrupt, and this marks the 'irqaction' as busy.
832 int irqval
= request_irq(dev
->irq
, &pt_interrupt
,0, "pt", dev
);
834 printk(KERN_ERR
"PT: ERROR: Unable to get IRQ %d (irqval = %d).\n",
840 /* Grab the region */
841 request_region(ioaddr
& 0x3f0, PT_TOTAL_SIZE
, "pt" );
844 dev
->stop
= pt_close
;
845 dev
->do_ioctl
= pt_ioctl
;
846 dev
->hard_start_xmit
= pt_send_packet
;
847 dev
->get_stats
= pt_get_stats
;
849 /* Fill in the fields of the device structure */
850 dev_init_buffers(dev
);
852 #if defined(CONFIG_AX25) || defined(CONFIG_AX25_MODULE)
853 dev
->hard_header
= ax25_encapsulate
;
854 dev
->rebuild_header
= ax25_rebuild_header
;
857 dev
->set_mac_address
= pt_set_mac_address
;
859 dev
->type
= ARPHRD_AX25
; /* AF_AX25 device */
860 dev
->hard_header_len
= 73; /* We do digipeaters now */
861 dev
->mtu
= 1500; /* eth_mtu is default */
862 dev
->addr_len
= 7; /* sizeof an ax.25 address */
863 memcpy(dev
->broadcast
, ax25_bcast
, 7);
864 memcpy(dev
->dev_addr
, ax25_test
, 7);
866 /* New style flags */
873 /* Open/initialise the board. This is called (in the current kernel)
874 * sometime after booting when the 'ifconfig' program is run.
876 * This routine should set everything up anew at each open, even
877 * registers that 'should' only be set once at boot, so that there is
878 * a non-reboot way to recover if something goes wrong.
879 * derived from last half of tsync_attach()
881 static int pt_open(struct device
*dev
)
884 struct pt_local
*lp
= dev
->priv
;
885 static first_time
= 1;
887 if (dev
->base_addr
& CHANA
)
891 if (request_dma(dev
->dma
, "pt"))
893 free_irq(dev
->irq
, dev
);
903 if (dev
->base_addr
& CHANA
)
908 /* Save a copy of register RR0 for comparing with later on */
909 /* We always put 0 in zero count */
910 lp
->saved_RR0
= rdscc(lp
->cardbase
, lp
->base
+ CTL
, R0
) & ~ZCOUNT
;
912 /* master interrupt enable */
915 wrtscc(lp
->cardbase
, lp
->base
+ CTL
, R9
, MIE
| NV
);
916 outb_p( pt_sercfg
|= PT_EI
, lp
->cardbase
+ INT_CFG
);
917 restore_flags(flags
);
919 lp
->open_time
= jiffies
;
931 static int pt_send_packet(struct sk_buff
*skb
, struct device
*dev
)
933 struct pt_local
*lp
= (struct pt_local
*) dev
->priv
;
936 printk(KERN_DEBUG
"PT: pt_send_packet(): (%d)\n", lp
->base
& CHANA
);
938 hardware_send_packet(lp
, skb
);
939 dev
->trans_start
= jiffies
;
946 /* The inverse routine to pt_open() */
947 static int pt_close(struct device
*dev
)
950 struct pt_local
*lp
= dev
->priv
;
951 struct sk_buff
*ptr
= NULL
;
954 cmd
= lp
->base
+ CTL
;
959 /* Reset SCC or channel */
961 disable_dma(lp
->dmachan
);
967 /* Free any buffers left in the hardware transmit queue */
968 while ((ptr
= skb_dequeue(&lp
->sndq
)) != NULL
)
971 restore_flags(flags
);
974 printk(KERN_DEBUG
"PT: pt_close(): Closing down channel (%d).\n", lp
->base
& CHANA
);
983 static int pt_ioctl(struct device
*dev
, struct ifreq
*ifr
, int cmd
)
987 struct pt_local
*lp
= (struct pt_local
*) dev
->priv
;
989 int ret
= verify_area(VERIFY_WRITE
, ifr
->ifr_data
, sizeof(struct pt_req
));
993 if (cmd
!= SIOCDEVPRIVATE
)
996 copy_from_user(&rq
, ifr
->ifr_data
, sizeof(struct pt_req
));
1005 lp
->txdelay
= rq
.txdelay
;
1006 lp
->persist
= rq
.persist
;
1007 lp
->slotime
= rq
.slotime
;
1008 lp
->squeldelay
= rq
.squeldelay
;
1009 lp
->clockmode
= rq
.clockmode
;
1010 lp
->speed
= rq
.speed
;
1012 restore_flags(flags
);
1021 if (dev
->base_addr
& CHANA
) { /* if A channel */
1022 if (rq
.dmachan
< 1 || rq
.dmachan
> 3)
1027 free_dma(lp
->dmachan
);
1028 dev
->dma
= lp
->dmachan
= rq
.dmachan
;
1029 if (request_dma(lp
->dmachan
,"pt"))
1032 restore_flags(flags
);
1037 ret
= -EINVAL
; /* add this later */
1044 rq
.speed
= lp
->speed
;
1045 rq
.txdelay
= lp
->txdelay
;
1046 rq
.persist
= lp
->persist
;
1047 rq
.slotime
= lp
->slotime
;
1048 rq
.squeldelay
= lp
->squeldelay
;
1049 rq
.clockmode
= lp
->clockmode
;
1050 rq
.dmachan
= lp
->dmachan
;
1052 copy_to_user(ifr
->ifr_data
, &rq
, sizeof(struct pt_req
));
1063 * Get the current statistics.
1064 * This may be called with the card open or closed.
1067 static struct net_device_stats
*pt_get_stats(struct device
*dev
)
1069 struct pt_local
*lp
= (struct pt_local
*) dev
->priv
;
1076 * compile-command: "gcc -D__KERNEL__ -I/usr/src/linux/net/inet -Wall -Wstrict-prototypes -O6 -m486 -c skeleton.c"
1077 * version-control: t
1078 * kept-new-versions: 5
1084 static void tdelay(struct pt_local
*lp
, int time
)
1086 /* For some reason, we turn off the Tx interrupts here! */
1088 wrtscc(lp
->cardbase
, lp
->base
+ CTL
, R1
, INT_ALL_Rx
| EXT_INT_ENAB
);
1090 if (lp
->base
& CHANA
)
1092 outb_p(time
& 0xff, lp
->cardbase
+ TMR1
);
1093 outb_p((time
>> 8)&0xff, lp
->cardbase
+ TMR1
);
1097 outb_p(time
& 0xff, lp
->cardbase
+ TMR2
);
1098 outb_p((time
>> 8)&0xff, lp
->cardbase
+ TMR2
);
1103 static void pt_txisr(struct pt_local
*lp
)
1105 unsigned long flags
;
1111 cmd
= lp
->base
+ CTL
;
1114 printk(KERN_DEBUG
"PT: pt_txisr(): tstate = %d (%d).\n", lp
->tstate
, lp
->base
& CHANA
);
1120 lp
->tstate
= FLAGOUT
;
1121 tdelay(lp
, lp
->squeldelay
);
1122 restore_flags(flags
);
1126 /* Transmitter idle. Find a frame for transmission */
1127 if ((lp
->sndbuf
= skb_dequeue(&lp
->sndq
)) == NULL
)
1129 /* Nothing to send - return to receive mode
1130 * Tx off now - flag should have gone
1134 restore_flags(flags
);
1139 lp
->txptr
= lp
->sndbuf
->data
;
1140 lp
->txptr
++; /* Ignore KISS control byte */
1141 lp
->txcnt
= (int) lp
->sndbuf
->len
- 1;
1143 /* If a buffer to send, drop though here */
1146 /* Check DCD - debounce it */
1147 /* See Intel Microcommunications Handbook p2-308 */
1148 wrtscc(lp
->cardbase
, cmd
, R0
, RES_EXT_INT
);
1149 wrtscc(lp
->cardbase
, cmd
, R0
, RES_EXT_INT
);
1150 if ((rdscc(lp
->cardbase
, cmd
, R0
) & DCD
) != 0)
1154 /* DEFER until DCD transition or timeout */
1155 wrtscc(lp
->cardbase
, cmd
, R15
, DCDIE
);
1156 restore_flags(flags
);
1159 if (random() > lp
->persist
)
1162 tdelay(lp
, lp
->slotime
);
1163 restore_flags(flags
);
1166 pt_rts(lp
, ON
); /* Tx on */
1168 wrtscc(lp
->cardbase
, cmd
, R5
, TxCRC_ENAB
| RTS
| Tx8
);
1169 lp
->tstate
= ST_TXDELAY
;
1170 tdelay(lp
, lp
->txdelay
);
1171 restore_flags(flags
);
1175 /* Here we are actively sending a frame */
1178 /* XLZ - checkout Gracilis PT code to see if the while
1179 * loop is better or not.
1182 /* next char is gone */
1183 wrtscc(lp
->cardbase
, cmd
, R8
, c
);
1184 /* stuffing a char satisfies interrupt condition */
1186 /* No more to send */
1187 kfree_skb(lp
->sndbuf
);
1189 if ((rdscc(lp
->cardbase
, cmd
, R0
) & TxEOM
))
1191 /* Did we underrun */
1192 lp
->stats
.tx_errors
++;
1193 lp
->stats
.tx_fifo_errors
++;
1194 wrtscc(lp
->cardbase
, cmd
, R0
, SEND_ABORT
);
1195 lp
->tstate
= FLAGOUT
;
1196 tdelay(lp
, lp
->squeldelay
);
1197 restore_flags(flags
);
1200 lp
->tstate
= UNDERRUN
;
1201 /* Send flags on underrun */
1204 wrtscc(lp
->cardbase
, cmd
, R10
, CRCPS
| NRZI
);
1206 wrtscc(lp
->cardbase
, cmd
, R10
, CRCPS
| NRZ
);
1208 /* Reset Tx interrupt pending */
1209 wrtscc(lp
->cardbase
, cmd
, R0
, RES_Tx_P
);
1211 restore_flags(flags
);
1214 printk(KERN_ERR
"PT: pt_txisr(): Invalid tstate (%d) for chan %s.\n", lp
->tstate
, (cmd
& CHANA
? "A": "B") );
1219 restore_flags(flags
);
1222 static void pt_rxisr(struct device
*dev
)
1224 struct pt_local
*lp
= (struct pt_local
*) dev
->priv
;
1225 int cmd
= lp
->base
+ CTL
;
1227 unsigned long flags
;
1229 struct sk_buff
*skb
;
1230 int sksize
, pkt_len
;
1231 struct mbuf
*cur_buf
= NULL
;
1232 unsigned char *cfix
;
1237 /* Get status byte from R1 */
1238 rse
= rdscc(lp
->cardbase
, cmd
, R1
);
1241 printk(KERN_DEBUG
"PT: pt_rxisr(): R1 = %#3x. (%d)\n", rse
, lp
->base
& CHANA
);
1244 if (lp
->dmachan
&& (rse
& Rx_OVR
))
1245 lp
->rstate
= RXERROR
;
1247 if (rdscc(lp
->cardbase
, cmd
, R0
) & Rx_CH_AV
&& !lp
->dmachan
)
1249 /* There is a char to be stored
1250 * Read special condition bits before reading the data char
1254 /* Rx overrun - toss buffer */
1255 /* wind back the pointers */
1256 lp
->rcp
= lp
->rcvbuf
->data
;
1257 lp
->rcvbuf
->cnt
= 0;
1258 lp
->rstate
= RXERROR
;
1259 lp
->stats
.rx_errors
++;
1260 lp
->stats
.rx_fifo_errors
++;
1261 } else if (lp
->rcvbuf
->cnt
>= lp
->bufsiz
)
1264 * wind back Rx buffer pointers
1266 lp
->rcp
= lp
->rcvbuf
->data
;
1267 lp
->rcvbuf
->cnt
= 0;
1268 lp
->rstate
= TOOBIG
;
1270 /* ok, we can store the Rx char if no errors */
1271 if (lp
->rstate
== ACTIVE
)
1273 *lp
->rcp
++ = rdscc(lp
->cardbase
, cmd
, R8
);
1276 /* we got an error, dump the FIFO */
1277 (void) rdscc(lp
->cardbase
, cmd
, R8
);
1278 (void) rdscc(lp
->cardbase
, cmd
, R8
);
1279 (void) rdscc(lp
->cardbase
, cmd
, R8
);
1281 /* Reset error latch */
1282 wrtscc(lp
->cardbase
, cmd
, R0
, ERR_RES
);
1283 lp
->rstate
= ACTIVE
;
1285 /* Resync the SCC */
1286 wrtscc(lp
->cardbase
, cmd
, R3
, RxENABLE
| ENT_HM
| AUTO_ENAB
| Rx8
);
1294 printk(KERN_DEBUG
"PT: pt_rxisr() Got end of a %u byte frame.\n", lp
->rcvbuf
->cnt
);
1298 clear_dma_ff(lp
->dmachan
);
1299 bytecount
= lp
->bufsiz
- get_dma_residue(lp
->dmachan
);
1301 bytecount
= lp
->rcvbuf
->cnt
;
1304 /* END OF FRAME - Make sure Rx was active */
1305 if (lp
->rcvbuf
->cnt
> 0 || lp
->dmachan
)
1307 if ((rse
& CRC_ERR
) || (lp
->rstate
> ACTIVE
) || (bytecount
< 10))
1309 if ((bytecount
>= 10) && (rse
& CRC_ERR
))
1311 lp
->stats
.rx_crc_errors
++;
1315 if (lp
->rstate
== RXERROR
)
1317 lp
->stats
.rx_errors
++;
1318 lp
->stats
.rx_over_errors
++;
1320 lp
->rstate
= ACTIVE
;
1323 /* wind back Rx buffer pointers */
1324 lp
->rcp
= lp
->rcvbuf
->data
;
1325 lp
->rcvbuf
->cnt
= 0;
1327 /* Re-sync the SCC */
1328 wrtscc(lp
->cardbase
, cmd
, R3
, RxENABLE
| ENT_HM
| AUTO_ENAB
| Rx8
);
1332 printk(KERN_DEBUG
"PT: pt_rxisr() %s error.\n", (rse
& CRC_ERR
)? "CRC" : "state");
1335 /* We have a valid frame */
1338 pkt_len
= lp
->rcvbuf
->cnt
= bytecount
- 2 +1;
1339 /* Get buffer for next frame */
1340 cur_buf
= lp
->rcvbuf
;
1344 pkt_len
= lp
->rcvbuf
->cnt
-= 2; /* Toss 2 CRC bytes */
1345 pkt_len
+= 1; /* make room for KISS control byte */
1348 /* Malloc up new buffer */
1350 skb
= dev_alloc_skb(sksize
);
1353 printk(KERN_ERR
"PT: %s: Memory squeeze, dropping packet.\n", dev
->name
);
1354 lp
->stats
.rx_dropped
++;
1355 restore_flags(flags
);
1360 /* KISS kludge = prefix with a 0 byte */
1361 cfix
=skb_put(skb
,pkt_len
);
1363 /* skb->data points to the start of sk_buff area */
1365 memcpy(cfix
, (char*)cur_buf
->data
, pkt_len
- 1);
1367 memcpy(cfix
, lp
->rcvbuf
->data
, pkt_len
- 1);
1368 skb
->protocol
= ntohs(ETH_P_AX25
);
1369 skb
->mac
.raw
=skb
->data
;
1370 lp
->stats
.rx_bytes
+=skb
->len
;
1372 lp
->stats
.rx_packets
++;
1375 /* packet queued - wind back buffer for next frame */
1376 lp
->rcp
= lp
->rcvbuf
->data
;
1377 lp
->rcvbuf
->cnt
= 0;
1380 } /* check active Rx */
1381 /* Clear error status */
1382 lp
->rstate
= ACTIVE
;
1383 /* Reset error latch */
1384 } /* end EOF check */
1385 wrtscc(lp
->cardbase
, cmd
, R0
, ERR_RES
);
1386 restore_flags(flags
);
1390 * This handles the two timer interrupts.
1391 * This is a real bugger, cause you have to rip it out of the pi's
1392 * external status code. They use the CTS line or something.
1394 static void pt_tmrisr(struct pt_local
*lp
)
1396 unsigned long flags
;
1399 printk(KERN_DEBUG
"PT: pt_tmrisr(): tstate = %d (%d).\n", lp
->tstate
, lp
->base
& CHANA
);
1408 /* Most of this stuff is in pt_exisr() */
1418 if (lp
->base
& CHANA
)
1419 printk(KERN_ERR
"PT: pt_tmrisr(): Invalid tstate %d for Channel A\n", lp
->tstate
);
1421 printk(KERN_ERR
"PT: pt_tmrisr(): Invalid tstate %d for Channel B\n", lp
->tstate
);
1424 restore_flags(flags
);
1429 * This routine is called by the kernel when there is an interrupt for the
1432 static void pt_interrupt(int irq
, void *dev_id
, struct pt_regs
*regs
)
1434 /* It's a tad dodgy here, but we assume pt0a until proven otherwise */
1435 struct device
*dev
= &pt0a
;
1436 struct pt_local
*lp
= dev
->priv
;
1437 unsigned char intreg
;
1439 register int cbase
= dev
->base_addr
& 0x3f0;
1440 unsigned long flags
;
1442 /* Read the PT's interrupt register, this is not the SCC one! */
1443 intreg
= inb_p(cbase
+ INT_REG
);
1444 while(( intreg
& 0x07) != 0x07) {
1445 /* Read interrupt register pending from Channel A */
1446 while ((st
= rdscc(cbase
, cbase
+ CHANA
+ CTL
, R3
)) != 0)
1448 /* Read interrupt vector from R2, channel B */
1450 printk(KERN_DEBUG
"PT: pt_interrupt(): R3 = %#3x", st
);
1452 /* st = rdscc(lp->cardbase, cbase + CHANB + CTL, R2) & 0x0e;*/
1454 printk(KERN_DEBUG
"PI: R2 = %#3x.\n", st
);
1458 lp
= (struct pt_local
*)pt0a
.priv
;
1460 } else if (st
& CHATxIP
) {
1462 lp
= (struct pt_local
*)pt0a
.priv
;
1464 } else if (st
& CHAEXT
) {
1465 /* Channel A External Status */
1466 lp
= (struct pt_local
*)pt0a
.priv
;
1468 } else if (st
& CHBRxIP
) {
1470 lp
= (struct pt_local
*)pt0b
.priv
;
1472 } else if (st
& CHBTxIP
) {
1474 lp
= (struct pt_local
*)pt0b
.priv
;
1476 } else if (st
& CHBEXT
) {
1477 /* Channel B External Status */
1478 lp
= (struct pt_local
*)pt0b
.priv
;
1481 /* Reset highest interrupt under service */
1484 wrtscc(lp
->cardbase
, lp
->base
+ CTL
, R0
, RES_H_IUS
);
1485 restore_flags(flags
);
1486 } /* end of SCC ints */
1488 if (!(intreg
& PT_TMR1_MSK
))
1491 inb_p(cbase
+ TMR1CLR
);
1493 pt_tmrisr( (struct pt_local
*)pt0a
.priv
);
1496 if (!(intreg
& PT_TMR2_MSK
))
1499 inb_p(cbase
+ TMR2CLR
);
1501 pt_tmrisr( (struct pt_local
*)pt0b
.priv
);
1504 /* Get the next PT interrupt vector */
1505 intreg
= inb_p(cbase
+ INT_REG
);
1506 } /* while (intreg) */
1507 } /* pt_interrupt() */
1510 static void pt_exisr(struct pt_local
*lp
)
1512 unsigned long flags
;
1513 int cmd
= lp
->base
+ CTL
;
1521 /* Get external status */
1522 st
= rdscc(lp
->cardbase
, cmd
, R0
);
1525 printk(KERN_DEBUG
"PT: exisr(): R0 = %#3x tstate = %d (%d).\n", st
, lp
->tstate
, lp
->base
& CHANA
);
1527 /* Reset external status latch */
1528 wrtscc(lp
->cardbase
, cmd
, R0
, RES_EXT_INT
);
1530 if ((lp
->rstate
>= ACTIVE
) && (st
& BRK_ABRT
) && lp
->dmachan
)
1533 lp
->rstate
= ACTIVE
;
1538 case ACTIVE
: /* Unexpected underrun */
1540 printk(KERN_DEBUG
"PT: exisr(): unexpected underrun detected.\n");
1542 kfree_skb(lp
->sndbuf
);
1546 wrtscc(lp
->cardbase
, cmd
, R0
, SEND_ABORT
);
1547 lp
->stats
.tx_errors
++;
1548 lp
->stats
.tx_fifo_errors
++;
1550 lp
->tstate
= FLAGOUT
;
1551 tdelay(lp
, lp
->squeldelay
);
1552 restore_flags(flags
);
1555 lp
->tstate
= CRCOUT
;
1556 restore_flags(flags
);
1559 /* squeldelay has timed out */
1560 /* Find a frame for transmission */
1561 if ((lp
->sndbuf
= skb_dequeue(&lp
->sndq
)) == NULL
)
1563 /* Nothing to send - return to Rx mode */
1566 restore_flags(flags
);
1571 lp
->txptr
= lp
->sndbuf
->data
;
1572 lp
->txptr
++; /* Ignore KISS control byte */
1573 lp
->txcnt
= (int) lp
->sndbuf
->len
- 1;
1575 /* Fall through if we have a packet */
1580 /* Disable DMA chan */
1581 disable_dma(lp
->dmachan
);
1583 /* Set up for TX dma */
1584 wrtscc(lp
->cardbase
, cmd
, R1
, WT_FN_RDYFN
| EXT_INT_ENAB
);
1586 length
= lp
->sndbuf
->len
- 1;
1587 memcpy(lp
->txdmabuf
, &lp
->sndbuf
->data
[1], length
);
1589 /* Setup DMA controller for Tx */
1590 setup_tx_dma(lp
, length
);
1592 enable_dma(lp
->dmachan
);
1594 /* Reset CRC, Txint pending */
1595 wrtscc(lp
->cardbase
, cmd
, R0
, RES_Tx_CRC
| RES_Tx_P
);
1597 /* Allow underrun only */
1598 wrtscc(lp
->cardbase
, cmd
, R15
, TxUIE
);
1601 wrtscc(lp
->cardbase
, cmd
, R1
, WT_RDY_ENAB
| WT_FN_RDYFN
| EXT_INT_ENAB
);
1603 /* Send CRC on underrun */
1604 wrtscc(lp
->cardbase
, cmd
, R0
, RES_EOM_L
);
1606 lp
->tstate
= ACTIVE
;
1609 /* Get first char to send */
1612 /* Reset CRC for next frame */
1613 wrtscc(lp
->cardbase
, cmd
, R0
, RES_Tx_CRC
);
1615 /* send abort on underrun */
1618 wrtscc(lp
->cardbase
, cmd
, R10
, CRCPS
| NRZI
| ABUNDER
);
1620 wrtscc(lp
->cardbase
, cmd
, R10
, CRCPS
| NRZ
| ABUNDER
);
1622 /* send first char */
1623 wrtscc(lp
->cardbase
, cmd
, R8
, c
);
1625 /* Reset end of message latch */
1626 wrtscc(lp
->cardbase
, cmd
, R0
, RES_EOM_L
);
1628 /* stuff an extra one in */
1629 /* while ((rdscc(lp->cardbase, cmd, R0) & Tx_BUF_EMP) && lp->txcnt)
1633 wrtscc(lp->cardbase, cmd, R8, c);
1636 /* select Tx interrupts to enable */
1637 /* Allow underrun int only */
1638 wrtscc(lp
->cardbase
, cmd
, R15
, TxUIE
);
1640 /* Reset external interrupts */
1641 wrtscc(lp
->cardbase
, cmd
, R0
, RES_EXT_INT
);
1643 /* Tx and Rx ints enabled */
1644 wrtscc(lp
->cardbase
, cmd
, R1
, TxINT_ENAB
| EXT_INT_ENAB
);
1646 lp
->tstate
= ACTIVE
;
1647 restore_flags(flags
);
1650 /* slotime has timed out */
1652 /* Check DCD - debounce it
1653 * see Intel Microcommunications Handbook, p2-308
1655 wrtscc(lp
->cardbase
, cmd
, R0
, RES_EXT_INT
);
1656 wrtscc(lp
->cardbase
, cmd
, R0
, RES_EXT_INT
);
1657 if ((rdscc(lp
->cardbase
, cmd
, R0
) & DCD
) != 0)
1661 /* DEFER until DCD transition or timeout */
1662 wrtscc(lp
->cardbase
, cmd
, R15
, DCDIE
);
1663 restore_flags(flags
);
1666 if (random() > lp
->persist
)
1669 tdelay(lp
, lp
->slotime
);
1670 restore_flags(flags
);
1674 wrtscc(lp
->cardbase
, cmd
, R5
, TxCRC_ENAB
| RTS
| Tx8
);
1675 pt_rts(lp
, ON
); /* Tx on */
1676 lp
->tstate
= ST_TXDELAY
;
1677 tdelay(lp
, lp
->txdelay
);
1678 restore_flags(flags
);
1681 /* Only for int driven parts */
1684 restore_flags(flags
);
1691 * This triggers when hunt mode is entered, & since an ABORT
1692 * automatically enters hunt mode, we use that to clean up
1693 * any waiting garbage
1695 if ((lp
->rstate
== ACTIVE
) && (st
& BRK_ABRT
) )
1698 printk(KERN_DEBUG
"PT: exisr(): abort detected.\n");
1700 /* read and dump all of SCC Rx FIFO */
1701 (void) rdscc(lp
->cardbase
, cmd
, R8
);
1702 (void) rdscc(lp
->cardbase
, cmd
, R8
);
1703 (void) rdscc(lp
->cardbase
, cmd
, R8
);
1705 lp
->rcp
= lp
->rcvbuf
->data
;
1706 lp
->rcvbuf
->cnt
= 0;
1708 /* Re-sync the SCC */
1709 wrtscc(lp
->cardbase
, cmd
, R3
, RxENABLE
| ENT_HM
| AUTO_ENAB
| Rx8
);
1713 /* Check for DCD transitions */
1714 if ( (st
& DCD
) != (lp
->saved_RR0
& DCD
))
1717 printk(KERN_DEBUG
"PT: pt_exisr(): DCD is now %s.\n", (st
& DCD
)? "ON" : "OFF" );
1721 /* Check that we don't already have some data */
1722 if (lp
->rcvbuf
->cnt
> 0)
1725 printk(KERN_DEBUG
"PT: pt_exisr() dumping %u bytes from buffer.\n", lp
->rcvbuf
->cnt
);
1727 /* wind back buffers */
1728 lp
->rcp
= lp
->rcvbuf
->data
;
1729 lp
->rcvbuf
->cnt
= 0;
1731 } else { /* DCD off */
1733 /* read and dump al SCC FIFO */
1734 (void)rdscc(lp
->cardbase
, cmd
, R8
);
1735 (void)rdscc(lp
->cardbase
, cmd
, R8
);
1736 (void)rdscc(lp
->cardbase
, cmd
, R8
);
1738 /* wind back buffers */
1739 lp
->rcp
= lp
->rcvbuf
->data
;
1740 lp
->rcvbuf
->cnt
= 0;
1742 /* Re-sync the SCC */
1743 wrtscc(lp
->cardbase
, cmd
, R3
, RxENABLE
| ENT_HM
| AUTO_ENAB
| Rx8
);
1747 /* Update the saved version of register RR) */
1748 lp
->saved_RR0
= st
&~ ZCOUNT
;
1749 restore_flags(flags
);
1756 MODULE_AUTHOR("Craig Small VK2XLZ <vk2xlz@vk2xlz.ampr.org>");
1757 MODULE_DESCRIPTION("AX.25 driver for the Gracillis PacketTwin HDLC card");
1759 int init_module(void)
1764 void cleanup_module(void)
1766 free_irq(pt0a
.irq
, &pt0a
); /* IRQs and IO Ports are shared */
1767 release_region(pt0a
.base_addr
& 0x3f0, PT_TOTAL_SIZE
);
1771 unregister_netdev(&pt0a
);
1775 unregister_netdev(&pt0b
);