2 pi2.c: Driver for the Ottawa Amateur Radio Club PI and PI2 interface.
3 Copyright (c) 1994 David Perry
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License version 2, as
7 published by the Free Software Foundation.
9 This program is distributed in the hope that it will be useful, but
10 WITHOUT ANY WARRANTY; without even the implied warranty of
11 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
12 General Public License for more details.
14 You should have received a copy of the GNU General Public License
15 along with this program; if not, write to the Free Software Foundation,
16 Inc., 675 Mass Ave, Cambridge MA 02139, USA.
18 The file skeleton.c by Donald Becker was used as a starting point
23 April 6, 1994 (dp) Created
25 April 10, 1994 (dp) Included cleanup, suggestions from J. P. Morrison.
27 April 13, 1994 (dp) Included address probing from JPM, autoirq
29 April 14, 1994 (ac) Sketched in the NET3 changes.
30 April 17, 1994 (dp) Finished the NET3 changes. Used init_etherdev()
31 instead of kmalloc() to ensure that DMA buffers will
32 reside under the 16 meg line.
34 April 18, 1994 (dp) Now using the kernel provided sk_buff handling functions.
35 Fixed a nasty problem with DMA.
37 June 6, 1994 (ac) Fixed to match the buffer locking changes. Added a hack to
38 fix a funny I see (search for HACK) and fixed the calls in
39 init() so it doesn't migrate module based ethernet cards up
40 to eth2 Took out the old module ideas as they are no longer
41 relevant to the PI driver.
42 July 16, 1994 (dp) Fixed the B channel rx overrun problem ac referred to
43 above. Also added a bit of a hack to improve the maximum
44 baud rate on the B channel (Search for STUFF2). Included
45 ioctl stuff from John Paul Morrison. version 0.6 ALPHA
46 Feb 9, 1995 (dp) Updated for 1.1.90 kernel
48 Apr 6, 1995 (ac) Tweaks for NET3 pre snapshot 002 AX.25
49 April 23, 1995 (dp) Fixed ioctl so it works properly with piconfig program
50 when changing the baud rate or clock mode.
52 July 17, 1995 (ac) Finally polishing of AX25.030+ support
53 Oct 29, 1995 (ac) A couple of minor fixes before this, and this release changes
54 to the proper set_mac_address semantics which will break
55 a few programs I suspect.
56 Aug 18, 1996 (jsn) Converted to be used as a module.
57 Dec 13, 1996 (jsn) Fixed to match Linux networking changes.
60 /* The following #define invokes a hack that will improve performance (baud)
61 for the B port. The up side is it makes 9600 baud work ok on the B port.
62 It may do 38400, depending on the host. The down side is it burns up
63 CPU cycles with ints locked for up to 1 character time, at the beginning
64 of each transmitted packet. If this causes you to lose sleep, #undefine it.
69 /* The default configuration */
72 #define DEF_A_SPEED 0 /* 0 means external clock */
73 #define DEF_A_TXDELAY 15 /* 15 mS transmit delay */
74 #define DEF_A_PERSIST 128 /* 50% persistence */
75 #define DEF_A_SLOTIME 15 /* 15 mS slot time */
76 #define DEF_A_SQUELDELAY 1 /* 1 mS squelch delay - allows fcs and flag */
77 #define DEF_A_CLOCKMODE 0 /* clock mode - 0 is normal */
79 #define DEF_B_SPEED 1200 /* 1200 baud */
80 #define DEF_B_TXDELAY 40 /* 400 mS */
81 #define DEF_B_PERSIST 128 /* 50% */
82 #define DEF_B_SLOTIME 30 /* 300 mS */
83 #define DEF_B_SQUELDELAY 3 /* 30 mS */
84 #define DEF_B_CLOCKMODE 0 /* Normal clock mode */
86 /* The following #define is only really required for the PI card, not
87 the PI2 - but it's safer to leave it in. */
88 #define REALLY_SLOW_IO 1
90 #include <linux/config.h>
91 #include <linux/module.h>
92 #include <linux/kernel.h>
93 #include <linux/sched.h>
94 #include <linux/types.h>
95 #include <linux/fcntl.h>
96 #include <linux/interrupt.h>
97 #include <linux/ptrace.h>
98 #include <linux/ioport.h>
100 #include <linux/malloc.h>
101 #include <linux/string.h>
102 #include <linux/errno.h>
103 #include <asm/system.h>
104 #include <asm/bitops.h>
107 #include <asm/uaccess.h>
108 #include <linux/inet.h>
109 #include <linux/netdevice.h>
110 #include <linux/etherdevice.h>
111 #include <linux/skbuff.h>
112 #include <linux/timer.h>
113 #include <linux/if_arp.h>
114 #include <linux/pi2.h>
115 #include <linux/init.h>
117 #include <net/ax25.h>
126 * The actual devices we will use
130 * PI device declarations.
133 static int pi0_preprobe(struct device
*dev
){return 0;} /* Dummy probe function */
134 static struct device pi0a
= { "pi0a", 0, 0, 0, 0, 0, 0, 0, 0, 0, NULL
, pi0_preprobe
};
135 static struct device pi0b
= { "pi0b", 0, 0, 0, 0, 0, 0, 0, 0, 0, NULL
, pi0_preprobe
};
138 /* The number of low I/O ports used by the card. */
139 #define PI_TOTAL_SIZE 8
142 /* Index to functions, as function prototypes. */
144 static int pi_probe(struct device
*dev
, int card_type
);
145 static int pi_open(struct device
*dev
);
146 static int pi_send_packet(struct sk_buff
*skb
, struct device
*dev
);
147 static void pi_interrupt(int reg_ptr
, void *dev_id
, struct pt_regs
*regs
);
148 static int pi_close(struct device
*dev
);
149 static int pi_ioctl(struct device
*dev
, struct ifreq
*ifr
, int cmd
);
150 static struct net_device_stats
*pi_get_stats(struct device
*dev
);
151 static void rts(struct pi_local
*lp
, int x
);
152 static void b_rxint(struct device
*dev
, struct pi_local
*lp
);
153 static void b_txint(struct pi_local
*lp
);
154 static void b_exint(struct pi_local
*lp
);
155 static void a_rxint(struct device
*dev
, struct pi_local
*lp
);
156 static void a_txint(struct pi_local
*lp
);
157 static void a_exint(struct pi_local
*lp
);
158 static char *get_dma_buffer(unsigned long *mem_ptr
);
159 static int valid_dma_page(unsigned long addr
, unsigned long dev_buffsize
);
161 static char ax25_bcast
[7] =
162 {'Q' << 1, 'S' << 1, 'T' << 1, ' ' << 1, ' ' << 1, ' ' << 1, '0' << 1};
163 static char ax25_test
[7] =
164 {'L' << 1, 'I' << 1, 'N' << 1, 'U' << 1, 'X' << 1, ' ' << 1, '1' << 1};
166 static int ext2_secrm_seed
= 152; /* Random generator base */
168 extern inline unsigned char random(void)
170 return (unsigned char) (ext2_secrm_seed
= ext2_secrm_seed
174 extern inline void wrtscc(int cbase
, int ctl
, int sccreg
, int val
)
176 /* assume caller disables interrupts! */
177 outb_p(0, cbase
+ DMAEN
); /* Disable DMA while we touch the scc */
178 outb_p(sccreg
, ctl
); /* Select register */
179 outb_p(val
, ctl
); /* Output value */
180 outb_p(1, cbase
+ DMAEN
); /* Enable DMA */
183 extern inline int rdscc(int cbase
, int ctl
, int sccreg
)
187 /* assume caller disables interrupts! */
188 outb_p(0, cbase
+ DMAEN
); /* Disable DMA while we touch the scc */
189 outb_p(sccreg
, ctl
); /* Select register */
191 outb_p(1, cbase
+ DMAEN
); /* Enable DMA */
195 static void switchbuffers(struct pi_local
*lp
)
197 if (lp
->rcvbuf
== lp
->rxdmabuf1
)
198 lp
->rcvbuf
= lp
->rxdmabuf2
;
200 lp
->rcvbuf
= lp
->rxdmabuf1
;
203 static void hardware_send_packet(struct pi_local
*lp
, struct sk_buff
*skb
)
208 lp
->stats
.tx_packets
++;
212 kickflag
= (skb_peek(&lp
->sndq
) == NULL
) && (lp
->sndbuf
== NULL
);
213 restore_flags(flags
);
215 skb_queue_tail(&lp
->sndq
, skb
);
218 /* simulate interrupt to xmit */
219 switch (lp
->base
& 2)
222 a_txint(lp
); /* process interrupt */
227 if (lp
->tstate
== IDLE
)
229 restore_flags(flags
);
235 static void setup_rx_dma(struct pi_local
*lp
)
239 unsigned long dma_abs
;
245 dma_abs
= (unsigned long) (lp
->rcvbuf
->data
);
246 dmachan
= lp
->dmachan
;
247 cmd
= lp
->base
+ CTL
;
249 if(!valid_dma_page(dma_abs
, DMA_BUFF_SIZE
+ sizeof(struct mbuf
)))
250 panic("PI: RX buffer violates DMA boundary!");
252 /* Get ready for RX DMA */
253 wrtscc(lp
->cardbase
, cmd
, R1
, WT_FN_RDYFN
| WT_RDY_RT
| INT_ERR_Rx
| EXT_INT_ENAB
);
255 disable_dma(dmachan
);
256 clear_dma_ff(dmachan
);
258 /* Set DMA mode register to single transfers, incrementing address,
261 set_dma_mode(dmachan
, DMA_MODE_READ
| 0x10);
262 set_dma_addr(dmachan
, dma_abs
);
263 set_dma_count(dmachan
, lp
->bufsiz
);
266 /* If a packet is already coming in, this line is supposed to
267 avoid receiving a partial packet.
269 wrtscc(lp
->cardbase
, cmd
, R0
, RES_Rx_CRC
);
272 wrtscc(lp
->cardbase
, cmd
, R1
,
273 WT_RDY_ENAB
| WT_FN_RDYFN
| WT_RDY_RT
| INT_ERR_Rx
| EXT_INT_ENAB
);
275 restore_flags(flags
);
278 static void setup_tx_dma(struct pi_local
*lp
, int length
)
280 unsigned long dma_abs
;
282 unsigned long dmachan
;
287 dmachan
= lp
->dmachan
;
288 dma_abs
= (unsigned long) (lp
->txdmabuf
);
290 if(!valid_dma_page(dma_abs
, DMA_BUFF_SIZE
+ sizeof(struct mbuf
)))
291 panic("PI: TX buffer violates DMA boundary!");
293 disable_dma(dmachan
);
294 /* Set DMA mode register to single transfers, incrementing address,
295 * no auto init, reads
297 set_dma_mode(dmachan
, DMA_MODE_WRITE
);
298 clear_dma_ff(dmachan
);
299 set_dma_addr(dmachan
, dma_abs
);
300 /* output byte count */
301 set_dma_count(dmachan
, length
);
303 restore_flags(flags
);
306 static void tdelay(struct pi_local
*lp
, int time
)
312 if (lp
->base
& 2) { /* If A channel */
315 port
= lp
->cardbase
+ TMR1
;
318 t1
= 10 * time
; /* 10s of milliseconds for the B channel */
319 port
= lp
->cardbase
+ TMR2
;
320 wrtscc(lp
->cardbase
, lp
->base
+ CTL
, R1
, INT_ALL_Rx
| EXT_INT_ENAB
);
324 outb_p(sc
| LSB_MSB
| MODE0
, lp
->cardbase
+ TMRCMD
);
326 /* times 2 to make millisecs */
327 outb_p((t1
<< 1) & 0xFF, port
);
328 outb_p((t1
>> 7) & 0xFF, port
);
330 /* Enable correct int for timeout */
331 wrtscc(lp
->cardbase
, lp
->base
+ CTL
, R15
, CTSIE
);
332 wrtscc(lp
->cardbase
, lp
->base
+ CTL
, R0
, RES_EXT_INT
);
335 static void a_txint(struct pi_local
*lp
)
343 cmd
= CTL
+ lp
->base
;
345 switch (lp
->tstate
) {
347 /* Transmitter idle. Find a frame for transmission */
348 if ((lp
->sndbuf
= skb_dequeue(&lp
->sndq
)) == NULL
) {
350 restore_flags(flags
);
353 /* If a buffer to send, we drop thru here */
355 /* we may have deferred prev xmit attempt */
356 /* Check DCD - debounce it
357 * See Intel Microcommunications Handbook, p2-308
359 wrtscc(lp
->cardbase
, cmd
, R0
, RES_EXT_INT
);
360 wrtscc(lp
->cardbase
, cmd
, R0
, RES_EXT_INT
);
361 if ((rdscc(lp
->cardbase
, cmd
, R0
) & DCD
) != 0) {
364 /* defer until DCD transition or timeout */
365 wrtscc(lp
->cardbase
, cmd
, R15
, CTSIE
| DCDIE
);
366 restore_flags(flags
);
369 if (random() > lp
->persist
) {
371 tdelay(lp
, lp
->slotime
);
372 restore_flags(flags
);
375 /* Assert RTS early minimize collision window */
376 wrtscc(lp
->cardbase
, cmd
, R5
, TxCRC_ENAB
| RTS
| Tx8
);
377 rts(lp
, ON
); /* Transmitter on */
378 lp
->tstate
= ST_TXDELAY
;
379 tdelay(lp
, lp
->txdelay
);
380 restore_flags(flags
);
384 } /* end switch(lp->state) */
386 restore_flags(flags
);
389 static void a_exint(struct pi_local
*lp
)
397 cli(); /* disable interrupts */
399 st
= rdscc(lp
->cardbase
, lp
->base
+ CTL
, R0
); /* Fetch status */
401 /* reset external status latch */
402 wrtscc(lp
->cardbase
, CTL
+ lp
->base
, R0
, RES_EXT_INT
);
403 cmd
= lp
->base
+ CTL
;
405 if ((lp
->rstate
>= ACTIVE
) && (st
& BRK_ABRT
)) {
409 switch (lp
->tstate
) {
411 kfree_skb(lp
->sndbuf
);
413 lp
->tstate
= FLAGOUT
;
414 tdelay(lp
, lp
->squeldelay
);
417 if ((lp
->sndbuf
= skb_dequeue(&lp
->sndq
)) == NULL
) {
418 /* Nothing to send - return to receive mode */
421 restore_flags(flags
);
424 /* NOTE - fall through if more to send */
426 /* Disable DMA chan */
427 disable_dma(lp
->dmachan
);
429 /* Set up for TX dma */
430 wrtscc(lp
->cardbase
, cmd
, R1
, WT_FN_RDYFN
| EXT_INT_ENAB
);
434 /* Strip KISS control byte */
435 length
= lp
->sndbuf
->len
- 1;
436 memcpy(lp
->txdmabuf
, &lp
->sndbuf
->data
[1], length
);
439 /* Setup DMA controller for tx */
440 setup_tx_dma(lp
, length
);
442 /* select transmit interrupts to enable */
443 /* Allow DMA on chan */
444 enable_dma(lp
->dmachan
);
446 /* reset CRC, Txint pend*/
447 wrtscc(lp
->cardbase
, cmd
, R0
, RES_Tx_CRC
| RES_Tx_P
);
449 /* allow Underrun int only */
450 wrtscc(lp
->cardbase
, cmd
, R15
, TxUIE
);
453 wrtscc(lp
->cardbase
, cmd
, R1
, WT_RDY_ENAB
| WT_FN_RDYFN
| EXT_INT_ENAB
);
455 /* Send CRC on underrun */
456 wrtscc(lp
->cardbase
, cmd
, R0
, RES_EOM_L
);
459 /* packet going out now */
463 /* we have deferred prev xmit attempt
464 * See Intel Microcommunications Handbook, p2-308
466 wrtscc(lp
->cardbase
, cmd
, R0
, RES_EXT_INT
);
467 wrtscc(lp
->cardbase
, cmd
, R0
, RES_EXT_INT
);
468 if ((rdscc(lp
->cardbase
, cmd
, R0
) & DCD
) != 0) {
471 /* Defer until dcd transition or 100mS timeout */
472 wrtscc(lp
->cardbase
, CTL
+ lp
->base
, R15
, CTSIE
| DCDIE
);
473 restore_flags(flags
);
476 if (random() > lp
->persist
) {
478 tdelay(lp
, lp
->slotime
);
479 restore_flags(flags
);
482 /* Assert RTS early minimize collision window */
483 wrtscc(lp
->cardbase
, cmd
, R5
, TxCRC_ENAB
| RTS
| Tx8
);
484 rts(lp
, ON
); /* Transmitter on */
485 lp
->tstate
= ST_TXDELAY
;
486 tdelay(lp
, lp
->txdelay
);
487 restore_flags(flags
);
489 } /* switch(lp->tstate) */
491 restore_flags(flags
);
494 /* Receive interrupt handler for the A channel
496 static void a_rxint(struct device
*dev
, struct pi_local
*lp
)
504 struct mbuf
*cur_buf
;
508 cli(); /* disable interrupts */
509 cmd
= lp
->base
+ CTL
;
511 rse
= rdscc(lp
->cardbase
, cmd
, R1
); /* Get special condition bits from R1 */
513 lp
->rstate
= RXERROR
;
516 /* If end of frame */
517 /* figure length of frame from 8237 */
518 clear_dma_ff(lp
->dmachan
);
519 bytecount
= lp
->bufsiz
- get_dma_residue(lp
->dmachan
);
521 if ((rse
& CRC_ERR
) || (lp
->rstate
> ACTIVE
) || (bytecount
< 10)) {
522 if ((bytecount
>= 10) && (rse
& CRC_ERR
)) {
523 lp
->stats
.rx_crc_errors
++;
525 if (lp
->rstate
== RXERROR
) {
526 lp
->stats
.rx_errors
++;
527 lp
->stats
.rx_over_errors
++;
529 /* Reset buffer pointers */
533 /* Here we have a valid frame */
534 /* Toss 2 crc bytes , add one for KISS */
535 pkt_len
= lp
->rcvbuf
->cnt
= bytecount
- 2 + 1;
537 /* Get buffer for next frame */
538 cur_buf
= lp
->rcvbuf
;
543 /* Malloc up new buffer. */
546 skb
= dev_alloc_skb(sksize
);
548 printk(KERN_ERR
"PI: %s: Memory squeeze, dropping packet.\n", dev
->name
);
549 lp
->stats
.rx_dropped
++;
550 restore_flags(flags
);
555 /* KISS kludge - prefix with a 0 byte */
556 cfix
=skb_put(skb
,pkt_len
);
558 /* 'skb->data' points to the start of sk_buff data area. */
559 memcpy(cfix
, (char *) cur_buf
->data
,
561 skb
->protocol
=htons(ETH_P_AX25
);
562 skb
->mac
.raw
=skb
->data
;
564 lp
->stats
.rx_packets
++;
565 } /* end good frame */
566 } /* end EOF check */
567 wrtscc(lp
->cardbase
, lp
->base
+ CTL
, R0
, ERR_RES
); /* error reset */
568 restore_flags(flags
);
571 static void b_rxint(struct device
*dev
, struct pi_local
*lp
)
582 cli(); /* disable interrupts */
583 cmd
= CTL
+ lp
->base
;
585 rse
= rdscc(lp
->cardbase
, cmd
, R1
); /* get status byte from R1 */
587 if ((rdscc(lp
->cardbase
, cmd
, R0
)) & Rx_CH_AV
) {
588 /* there is a char to be stored
589 * read special condition bits before reading the data char
592 /* Rx overrun - toss buffer */
593 /* reset buffer pointers */
594 lp
->rcp
= lp
->rcvbuf
->data
;
597 lp
->rstate
= RXERROR
; /* set error flag */
598 lp
->stats
.rx_errors
++;
599 lp
->stats
.rx_over_errors
++;
600 } else if (lp
->rcvbuf
->cnt
>= lp
->bufsiz
) {
601 /* Too large -- toss buffer */
602 /* reset buffer pointers */
603 lp
->rcp
= lp
->rcvbuf
->data
;
605 lp
->rstate
= TOOBIG
;/* when set, chars are not stored */
607 /* ok, we can store the received character now */
608 if (lp
->rstate
== ACTIVE
) { /* If no errors... */
609 *lp
->rcp
++ = rdscc(lp
->cardbase
, cmd
, R8
); /* char to rcv buff */
610 lp
->rcvbuf
->cnt
++; /* bump count */
612 /* got to empty FIFO */
613 (void) rdscc(lp
->cardbase
, cmd
, R8
);
614 wrtscc(lp
->cardbase
, cmd
, R0
, ERR_RES
); /* reset err latch */
619 /* END OF FRAME -- Make sure Rx was active */
620 if (lp
->rcvbuf
->cnt
> 0) {
621 if ((rse
& CRC_ERR
) || (lp
->rstate
> ACTIVE
) || (lp
->rcvbuf
->cnt
< 10)) {
622 if ((lp
->rcvbuf
->cnt
>= 10) && (rse
& CRC_ERR
)) {
623 lp
->stats
.rx_crc_errors
++;
625 lp
->rcp
= lp
->rcvbuf
->data
;
628 /* Here we have a valid frame */
629 pkt_len
= lp
->rcvbuf
->cnt
-= 2; /* Toss 2 crc bytes */
630 pkt_len
+= 1; /* Make room for KISS control byte */
632 /* Malloc up new buffer. */
634 skb
= dev_alloc_skb(sksize
);
636 printk(KERN_ERR
"PI: %s: Memory squeeze, dropping packet.\n", dev
->name
);
637 lp
->stats
.rx_dropped
++;
638 restore_flags(flags
);
643 /* KISS kludge - prefix with a 0 byte */
644 cfix
=skb_put(skb
,pkt_len
);
646 /* 'skb->data' points to the start of sk_buff data area. */
647 memcpy(cfix
, lp
->rcvbuf
->data
, pkt_len
- 1);
648 skb
->protocol
=ntohs(ETH_P_AX25
);
649 skb
->mac
.raw
=skb
->data
;
651 lp
->stats
.rx_packets
++;
652 /* packet queued - initialize buffer for next frame */
653 lp
->rcp
= lp
->rcvbuf
->data
;
656 } /* end good frame queued */
657 } /* end check for active receive upon EOF */
658 lp
->rstate
= ACTIVE
; /* and clear error status */
659 } /* end EOF check */
660 restore_flags(flags
);
664 static void b_txint(struct pi_local
*lp
)
672 cmd
= CTL
+ lp
->base
;
674 switch (lp
->tstate
) {
676 lp
->tstate
= FLAGOUT
;
677 tdelay(lp
, lp
->squeldelay
);
678 restore_flags(flags
);
681 /* Transmitter idle. Find a frame for transmission */
682 if ((lp
->sndbuf
= skb_dequeue(&lp
->sndq
)) == NULL
) {
683 /* Nothing to send - return to receive mode
684 * Tx OFF now - flag should have gone
688 restore_flags(flags
);
691 lp
->txptr
= lp
->sndbuf
->data
;
692 lp
->txptr
++; /* Ignore KISS control byte */
693 lp
->txcnt
= (int) lp
->sndbuf
->len
- 1;
694 /* If a buffer to send, we drop thru here */
695 case DEFER
: /* we may have deferred prev xmit attempt */
696 /* Check DCD - debounce it */
697 /* See Intel Microcommunications Handbook, p2-308 */
698 wrtscc(lp
->cardbase
, cmd
, R0
, RES_EXT_INT
);
699 wrtscc(lp
->cardbase
, cmd
, R0
, RES_EXT_INT
);
700 if ((rdscc(lp
->cardbase
, cmd
, R0
) & DCD
) != 0) {
703 /* defer until DCD transition or timeout */
704 wrtscc(lp
->cardbase
, cmd
, R15
, CTSIE
| DCDIE
);
705 restore_flags(flags
);
708 if (random() > lp
->persist
) {
710 tdelay(lp
, lp
->slotime
);
711 restore_flags(flags
);
714 rts(lp
, ON
); /* Transmitter on */
715 lp
->tstate
= ST_TXDELAY
;
716 tdelay(lp
, lp
->txdelay
);
717 restore_flags(flags
);
721 /* Here we are actively sending a frame */
724 /* next char is gone */
725 wrtscc(lp
->cardbase
, cmd
, R8
, c
);
726 /* stuffing a char satisfies Interrupt condition */
728 /* No more to send */
729 kfree_skb(lp
->sndbuf
);
731 if ((rdscc(lp
->cardbase
, cmd
, R0
) & 0x40)) {
732 /* Did we underrun? */
733 /* unexpected underrun */
734 lp
->stats
.tx_errors
++;
735 lp
->stats
.tx_fifo_errors
++;
736 wrtscc(lp
->cardbase
, cmd
, R0
, SEND_ABORT
);
737 lp
->tstate
= FLAGOUT
;
738 tdelay(lp
, lp
->squeldelay
);
739 restore_flags(flags
);
742 lp
->tstate
= UNDERRUN
; /* Now we expect to underrun */
743 /* Send flags on underrun */
744 if (lp
->speed
) { /* If internally clocked */
745 wrtscc(lp
->cardbase
, cmd
, R10
, CRCPS
| NRZI
);
747 wrtscc(lp
->cardbase
, cmd
, R10
, CRCPS
);
749 wrtscc(lp
->cardbase
, cmd
, R0
, RES_Tx_P
); /* reset Tx Int Pend */
751 restore_flags(flags
);
752 return; /* back to wait for interrupt */
754 restore_flags(flags
);
757 /* Pi SIO External/Status interrupts (for the B channel)
758 * This can be caused by a receiver abort, or a Tx UNDERRUN/EOM.
759 * Receiver automatically goes to Hunt on an abort.
761 * If the Tx Underrun interrupt hits, change state and
762 * issue a reset command for it, and return.
764 static void b_exint(struct pi_local
*lp
)
771 cmd
= CTL
+ lp
->base
;
773 cli(); /* disable interrupts */
774 st
= rdscc(lp
->cardbase
, cmd
, R0
); /* Fetch status */
775 /* reset external status latch */
776 wrtscc(lp
->cardbase
, cmd
, R0
, RES_EXT_INT
);
779 switch (lp
->tstate
) {
780 case ACTIVE
: /* Unexpected underrun */
781 kfree_skb(lp
->sndbuf
);
783 wrtscc(lp
->cardbase
, cmd
, R0
, SEND_ABORT
);
784 lp
->tstate
= FLAGOUT
;
785 lp
->stats
.tx_errors
++;
786 lp
->stats
.tx_fifo_errors
++;
787 tdelay(lp
, lp
->squeldelay
);
788 restore_flags(flags
);
792 restore_flags(flags
);
795 /* Find a frame for transmission */
796 if ((lp
->sndbuf
= skb_dequeue(&lp
->sndq
)) == NULL
) {
797 /* Nothing to send - return to receive mode
798 * Tx OFF now - flag should have gone
802 restore_flags(flags
);
805 lp
->txptr
= lp
->sndbuf
->data
;
806 lp
->txptr
++; /* Ignore KISS control byte */
807 lp
->txcnt
= (int) lp
->sndbuf
->len
- 1;
808 /* Get first char to send */
811 wrtscc(lp
->cardbase
, cmd
, R0
, RES_Tx_CRC
); /* reset for next frame */
813 /* Send abort on underrun */
814 if (lp
->speed
) { /* If internally clocked */
815 wrtscc(lp
->cardbase
, cmd
, R10
, CRCPS
| NRZI
| ABUNDER
);
817 wrtscc(lp
->cardbase
, cmd
, R10
, CRCPS
| ABUNDER
);
820 wrtscc(lp
->cardbase
, cmd
, R8
, c
); /* First char out now */
821 wrtscc(lp
->cardbase
, cmd
, R0
, RES_EOM_L
); /* Reset end of message latch */
824 /* stuff an extra one if we can */
828 /* Wait for tx buffer empty */
829 while((rdscc(lp
->cardbase
, cmd
, R0
) & 0x04) == 0)
831 wrtscc(lp
->cardbase
, cmd
, R8
, c
);
835 /* select transmit interrupts to enable */
837 wrtscc(lp
->cardbase
, cmd
, R15
, TxUIE
); /* allow Underrun int only */
838 wrtscc(lp
->cardbase
, cmd
, R0
, RES_EXT_INT
);
839 wrtscc(lp
->cardbase
, cmd
, R1
, TxINT_ENAB
| EXT_INT_ENAB
); /* Tx/Ext ints */
841 lp
->tstate
= ACTIVE
; /* char going out now */
842 restore_flags(flags
);
846 /* Check DCD - debounce it
847 * See Intel Microcommunications Handbook, p2-308
849 wrtscc(lp
->cardbase
, cmd
, R0
, RES_EXT_INT
);
850 wrtscc(lp
->cardbase
, cmd
, R0
, RES_EXT_INT
);
851 if ((rdscc(lp
->cardbase
, cmd
, R0
) & DCD
) != 0) {
854 /* defer until DCD transition or timeout */
855 wrtscc(lp
->cardbase
, cmd
, R15
, CTSIE
| DCDIE
);
856 restore_flags(flags
);
859 if (random() > lp
->persist
) {
861 tdelay(lp
, lp
->slotime
);
862 restore_flags(flags
);
865 rts(lp
, ON
); /* Transmitter on */
866 lp
->tstate
= ST_TXDELAY
;
867 tdelay(lp
, lp
->txdelay
);
868 restore_flags(flags
);
873 /* Get first char to send */
876 wrtscc(lp
->cardbase
, cmd
, R0
, RES_Tx_CRC
); /* reset for next frame */
878 /* Send abort on underrun */
879 if (lp
->speed
) { /* If internally clocked */
880 wrtscc(lp
->cardbase
, cmd
, R10
, CRCPS
| NRZI
| ABUNDER
);
882 wrtscc(lp
->cardbase
, cmd
, R10
, CRCPS
| ABUNDER
);
885 wrtscc(lp
->cardbase
, cmd
, R8
, c
); /* First char out now */
886 wrtscc(lp
->cardbase
, cmd
, R0
, RES_EOM_L
); /* Reset end of message latch */
889 /* stuff an extra one if we can */
893 /* Wait for tx buffer empty */
894 while((rdscc(lp
->cardbase
, cmd
, R0
) & 0x04) == 0)
896 wrtscc(lp
->cardbase
, cmd
, R8
, c
);
900 /* select transmit interrupts to enable */
902 wrtscc(lp
->cardbase
, cmd
, R15
, TxUIE
); /* allow Underrun int only */
903 wrtscc(lp
->cardbase
, cmd
, R0
, RES_EXT_INT
);
904 /* Tx/Extern ints on */
905 wrtscc(lp
->cardbase
, cmd
, R1
, TxINT_ENAB
| EXT_INT_ENAB
);
907 lp
->tstate
= ACTIVE
; /* char going out now */
908 restore_flags(flags
);
913 * This triggers when hunt mode is entered, & since an ABORT
914 * automatically enters hunt mode, we use that to clean up
915 * any waiting garbage
917 if ((lp
->rstate
== ACTIVE
) && (st
& BRK_ABRT
)) {
918 (void) rdscc(lp
->cardbase
, cmd
, R8
);
919 (void) rdscc(lp
->cardbase
, cmd
, R8
);
920 (void) rdscc(lp
->cardbase
, cmd
, R8
);
921 lp
->rcp
= lp
->rcvbuf
->data
;
922 lp
->rcvbuf
->cnt
= 0; /* rewind on DCD transition */
924 restore_flags(flags
);
927 /* Probe for a PI card. */
928 /* This routine also initializes the timer chip */
930 static int __init
hw_probe(int ioaddr
)
932 int time
= 1000; /* Number of milliseconds for test */
933 unsigned long start_time
, end_time
;
935 int base
, tmr0
, tmr1
, tmrcmd
;
939 base
= ioaddr
& 0x3f0;
942 tmrcmd
= TMRCMD
+ base
;
944 /* Set up counter chip timer 0 for 500 uS period square wave */
945 /* assuming a 3.68 mhz clock for now */
946 outb_p(SC0
| LSB_MSB
| MODE3
, tmrcmd
);
947 outb_p(922 & 0xFF, tmr0
);
948 outb_p(922 >> 8, tmr0
);
950 /* Setup timer control word for timer 1*/
951 outb_p(SC1
| LSB_MSB
| MODE0
, tmrcmd
);
952 outb_p((time
<< 1) & 0xFF, tmr1
);
953 outb_p((time
>> 7) & 0XFF, tmr1
);
955 /* wait until counter reg is loaded */
957 /* Latch count for reading */
962 start_time
= jiffies
;
964 /* Latch count for reading */
969 /* Don't wait forever - there may be no card here */
970 if ((end_time
- start_time
) > 200)
971 return 0; /* No card found */
974 /* 87 jiffies, for a 3.68 mhz clock, half that for a double speed clock */
975 if ((end_time
- start_time
) > 65) {
976 return (1); /* PI card found */
978 /* Faster crystal - tmr0 needs adjusting */
979 /* Set up counter chip */
980 /* 500 uS square wave */
981 outb_p(SC0
| LSB_MSB
| MODE3
, tmrcmd
);
982 outb_p(1844 & 0xFF, tmr0
);
983 outb_p(1844 >> 8, tmr0
);
984 return (2); /* PI2 card found */
988 static void rts(struct pi_local
*lp
, int x
)
995 /* assumes interrupts are off */
996 cmd
= CTL
+ lp
->base
;
998 /* Reprogram BRG and turn on transmitter to send flags */
999 if (x
== ON
) { /* Turn Tx ON and Receive OFF */
1000 /* Exints off first to avoid abort int */
1001 wrtscc(lp
->cardbase
, cmd
, R15
, 0);
1002 wrtscc(lp
->cardbase
, cmd
, R3
, Rx8
); /* Rx off */
1004 if (cmd
& 2) { /* if channel a */
1005 /* Set up for TX dma */
1006 wrtscc(lp
->cardbase
, cmd
, R1
, WT_FN_RDYFN
| EXT_INT_ENAB
);
1008 wrtscc(lp
->cardbase
, cmd
, R1
, 0); /* No interrupts */
1011 if (!lp
->clockmode
) {
1012 if (lp
->speed
) { /* if internally clocked */
1013 br
= lp
->speed
; /* get desired speed */
1014 tc
= (lp
->xtal
/ br
) - 2; /* calc 1X BRG divisor */
1015 wrtscc(lp
->cardbase
, cmd
, R12
, tc
& 0xFF); /* lower byte */
1016 wrtscc(lp
->cardbase
, cmd
, R13
, (tc
>> 8) & 0xFF); /* upper byte */
1019 wrtscc(lp
->cardbase
, cmd
, R5
, TxCRC_ENAB
| RTS
| TxENAB
| Tx8
| DTR
);
1020 /* Transmitter now on */
1021 } else { /* Tx OFF and Rx ON */
1023 wrtscc(lp
->cardbase
, cmd
, R5
, Tx8
| DTR
); /* TX off */
1025 if (!lp
->clockmode
) {
1026 if (lp
->speed
) { /* if internally clocked */
1027 /* Reprogram BRG for 32x clock for receive DPLL */
1028 /* BRG off, keep Pclk source */
1029 wrtscc(lp
->cardbase
, cmd
, R14
, BRSRC
);
1030 br
= lp
->speed
; /* get desired speed */
1031 /* calc 32X BRG divisor */
1032 tc
= ((lp
->xtal
/ 32) / br
) - 2;
1033 wrtscc(lp
->cardbase
, cmd
, R12
, tc
& 0xFF); /* lower byte */
1034 wrtscc(lp
->cardbase
, cmd
, R13
, (tc
>> 8) & 0xFF); /* upper byte */
1035 /* SEARCH mode, BRG source */
1036 wrtscc(lp
->cardbase
, cmd
, R14
, BRSRC
| SEARCH
);
1037 /* Enable the BRG */
1038 wrtscc(lp
->cardbase
, cmd
, R14
, BRSRC
| BRENABL
);
1042 wrtscc(lp
->cardbase
, cmd
, R3
, Rx8
); /* Make sure rx is off */
1043 wrtscc(lp
->cardbase
, cmd
, R0
, ERR_RES
); /* reset err latch */
1044 dummy
= rdscc(lp
->cardbase
, cmd
, R1
); /* get status byte from R1 */
1045 (void) rdscc(lp
->cardbase
, cmd
, R8
);
1046 (void) rdscc(lp
->cardbase
, cmd
, R8
);
1048 (void) rdscc(lp
->cardbase
, cmd
, R8
);
1050 /* Now, turn on the receiver and hunt for a flag */
1051 wrtscc(lp
->cardbase
, cmd
, R3
, RxENABLE
| Rx8
);
1052 lp
->rstate
= ACTIVE
; /* Normal state */
1054 if (cmd
& 2) { /* if channel a */
1057 /* reset buffer pointers */
1058 lp
->rcp
= lp
->rcvbuf
->data
;
1059 lp
->rcvbuf
->cnt
= 0;
1060 wrtscc(lp
->cardbase
, cmd
, R1
, (INT_ALL_Rx
| EXT_INT_ENAB
));
1062 wrtscc(lp
->cardbase
, cmd
, R15
, BRKIE
); /* allow ABORT int */
1066 static void scc_init(struct device
*dev
)
1068 unsigned long flags
;
1069 struct pi_local
*lp
= (struct pi_local
*) dev
->priv
;
1075 /* Initialize 8530 channel for SDLC operation */
1077 cmd
= CTL
+ lp
->base
;
1081 switch (cmd
& CHANA
) {
1083 wrtscc(lp
->cardbase
, cmd
, R9
, CHRA
); /* Reset channel A */
1084 wrtscc(lp
->cardbase
, cmd
, R2
, 0xff); /* Initialize interrupt vector */
1087 wrtscc(lp
->cardbase
, cmd
, R9
, CHRB
); /* Reset channel B */
1091 /* Deselect all Rx and Tx interrupts */
1092 wrtscc(lp
->cardbase
, cmd
, R1
, 0);
1094 /* Turn off external interrupts (like CTS/CD) */
1095 wrtscc(lp
->cardbase
, cmd
, R15
, 0);
1097 /* X1 clock, SDLC mode */
1098 wrtscc(lp
->cardbase
, cmd
, R4
, SDLC
| X1CLK
);
1100 /* Tx/Rx parameters */
1101 if (lp
->speed
) { /* Use internal clocking */
1102 wrtscc(lp
->cardbase
, cmd
, R10
, CRCPS
| NRZI
);
1104 /* Tx Clk from BRG. Rcv Clk from DPLL, TRxC pin outputs DPLL */
1105 wrtscc(lp
->cardbase
, cmd
, R11
, TCBR
| RCDPLL
| TRxCDP
| TRxCOI
);
1107 /* Tx Clk from DPLL, Rcv Clk from DPLL, TRxC Outputs BRG */
1108 wrtscc(lp
->cardbase
, cmd
, R11
, TCDPLL
| RCDPLL
| TRxCBR
| TRxCOI
);
1109 } else { /* Use external clocking */
1110 wrtscc(lp
->cardbase
, cmd
, R10
, CRCPS
);
1111 /* Tx Clk from Trxcl. Rcv Clk from Rtxcl, TRxC pin is input */
1112 wrtscc(lp
->cardbase
, cmd
, R11
, TCTRxCP
);
1115 /* Null out SDLC start address */
1116 wrtscc(lp
->cardbase
, cmd
, R6
, 0);
1119 wrtscc(lp
->cardbase
, cmd
, R7
, FLAG
);
1121 /* Set up the Transmitter but don't enable it
1122 * DTR, 8 bit TX chars only
1124 wrtscc(lp
->cardbase
, cmd
, R5
, Tx8
| DTR
);
1126 /* Receiver initial setup */
1127 wrtscc(lp
->cardbase
, cmd
, R3
, Rx8
); /* 8 bits/char */
1129 /* Setting up BRG now - turn it off first */
1130 wrtscc(lp
->cardbase
, cmd
, R14
, BRSRC
); /* BRG off, keep Pclk source */
1132 /* set the 32x time constant for the BRG in Receive mode */
1135 br
= lp
->speed
; /* get desired speed */
1136 tc
= ((lp
->xtal
/ 32) / br
) - 2; /* calc 32X BRG divisor */
1141 wrtscc(lp
->cardbase
, cmd
, R12
, tc
& 0xFF); /* lower byte */
1142 wrtscc(lp
->cardbase
, cmd
, R13
, (tc
>> 8) & 0xFF); /* upper byte */
1144 /* Following subroutine sets up and ENABLES the receiver */
1145 rts(lp
, OFF
); /* TX OFF and RX ON */
1148 /* DPLL frm BRG, BRG src PCLK */
1149 wrtscc(lp
->cardbase
, cmd
, R14
, BRSRC
| SSBR
);
1151 /* DPLL frm rtxc,BRG src PCLK */
1152 wrtscc(lp
->cardbase
, cmd
, R14
, BRSRC
| SSRTxC
);
1154 wrtscc(lp
->cardbase
, cmd
, R14
, BRSRC
| SEARCH
); /* SEARCH mode, keep BRG src */
1155 wrtscc(lp
->cardbase
, cmd
, R14
, BRSRC
| BRENABL
); /* Enable the BRG */
1157 if (!(cmd
& 2)) /* if channel b */
1158 wrtscc(lp
->cardbase
, cmd
, R1
, (INT_ALL_Rx
| EXT_INT_ENAB
));
1160 wrtscc(lp
->cardbase
, cmd
, R15
, BRKIE
); /* ABORT int */
1162 /* Now, turn on the receiver and hunt for a flag */
1163 wrtscc(lp
->cardbase
, cmd
, R3
, RxENABLE
| RxCRC_ENAB
| Rx8
);
1165 restore_flags(flags
);
1168 static void chipset_init(struct device
*dev
)
1171 unsigned long flags
;
1173 cardbase
= dev
->base_addr
& 0x3f0;
1177 wrtscc(cardbase
, dev
->base_addr
+ CTL
, R9
, FHWRES
); /* Hardware reset */
1178 /* Disable interrupts with master interrupt ctrl reg */
1179 wrtscc(cardbase
, dev
->base_addr
+ CTL
, R9
, 0);
1180 restore_flags(flags
);
1185 int __init
pi_init(void)
1190 int ports
[] = {0x380, 0x300, 0x320, 0x340, 0x360, 0x3a0, 0};
1192 printk(KERN_INFO
"PI: V0.8 ALPHA April 23 1995 David Perry (dp@hydra.carleton.ca)\n");
1194 /* Only one card supported for now */
1195 for (port
= &ports
[0]; *port
&& !card_type
; port
++) {
1198 if (check_region(ioaddr
, PI_TOTAL_SIZE
) == 0) {
1199 printk(KERN_INFO
"PI: Probing for card at address %#3x\n",ioaddr
);
1200 card_type
= hw_probe(ioaddr
);
1204 switch (card_type
) {
1206 printk(KERN_INFO
"PI: Found a PI card at address %#3x\n", ioaddr
);
1209 printk(KERN_INFO
"PI: Found a PI2 card at address %#3x\n", ioaddr
);
1212 printk(KERN_ERR
"PI: ERROR: No card found\n");
1216 /* Link a couple of device structures into the chain */
1217 /* For the A port */
1218 /* Allocate space for 4 buffers even though we only need 3,
1219 because one of them may cross a DMA page boundary and
1220 be rejected by get_dma_buffer().
1222 register_netdev(&pi0a
);
1224 pi0a
.priv
= kmalloc(sizeof(struct pi_local
) + (DMA_BUFF_SIZE
+ sizeof(struct mbuf
)) * 4, GFP_KERNEL
| GFP_DMA
);
1227 pi0a
.base_addr
= ioaddr
+ 2;
1230 /* And the B port */
1231 register_netdev(&pi0b
);
1232 pi0b
.base_addr
= ioaddr
;
1235 pi0b
.priv
= kmalloc(sizeof(struct pi_local
) + (DMA_BUFF_SIZE
+ sizeof(struct mbuf
)) * 4, GFP_KERNEL
| GFP_DMA
);
1237 /* Now initialize them */
1238 pi_probe(&pi0a
, card_type
);
1239 pi_probe(&pi0b
, card_type
);
1241 pi0b
.irq
= pi0a
.irq
; /* IRQ is shared */
1246 static int valid_dma_page(unsigned long addr
, unsigned long dev_buffsize
)
1248 if (((addr
& 0xffff) + dev_buffsize
) <= 0x10000)
1254 static int pi_set_mac_address(struct device
*dev
, void *addr
)
1256 struct sockaddr
*sa
= (struct sockaddr
*)addr
;
1257 memcpy(dev
->dev_addr
, sa
->sa_data
, dev
->addr_len
); /* addr is an AX.25 shifted ASCII */
1258 return 0; /* mac address */
1261 /* Allocate a buffer which does not cross a DMA page boundary */
1263 get_dma_buffer(unsigned long *mem_ptr
)
1267 ret
= (char *)*mem_ptr
;
1269 if(!valid_dma_page(*mem_ptr
, DMA_BUFF_SIZE
+ sizeof(struct mbuf
))){
1270 *mem_ptr
+= (DMA_BUFF_SIZE
+ sizeof(struct mbuf
));
1271 ret
= (char *)*mem_ptr
;
1273 *mem_ptr
+= (DMA_BUFF_SIZE
+ sizeof(struct mbuf
));
1277 static int pi_probe(struct device
*dev
, int card_type
)
1280 struct pi_local
*lp
;
1281 unsigned long flags
;
1282 unsigned long mem_ptr
;
1284 ioaddr
= dev
->base_addr
;
1286 /* Initialize the device structure. */
1287 /* Must be done before chipset_init */
1288 /* Make certain the data structures used by the PI2 are aligned. */
1289 dev
->priv
= (void *) (((int) dev
->priv
+ 7) & ~7);
1290 lp
= (struct pi_local
*) dev
->priv
;
1292 memset(dev
->priv
, 0, sizeof(struct pi_local
));
1294 /* Allocate some buffers which do not cross DMA page boundaries */
1295 mem_ptr
= (unsigned long) dev
->priv
+ sizeof(struct pi_local
);
1296 lp
->txdmabuf
= get_dma_buffer(&mem_ptr
);
1297 lp
->rxdmabuf1
= (struct mbuf
*) get_dma_buffer(&mem_ptr
);
1298 lp
->rxdmabuf2
= (struct mbuf
*) get_dma_buffer(&mem_ptr
);
1300 /* Initialize rx buffer */
1301 lp
->rcvbuf
= lp
->rxdmabuf1
;
1302 lp
->rcp
= lp
->rcvbuf
->data
;
1303 lp
->rcvbuf
->cnt
= 0;
1305 /* Initialize the transmit queue head structure */
1306 skb_queue_head_init(&lp
->sndq
);
1308 /* These need to be initialized before scc_init is called. */
1310 lp
->xtal
= (unsigned long) SINGLE
/ 2;
1312 lp
->xtal
= (unsigned long) DOUBLE
/ 2;
1313 lp
->base
= dev
->base_addr
;
1314 lp
->cardbase
= dev
->base_addr
& 0x3f0;
1315 if (dev
->base_addr
& CHANA
) {
1316 lp
->speed
= DEF_A_SPEED
;
1317 /* default channel access Params */
1318 lp
->txdelay
= DEF_A_TXDELAY
;
1319 lp
->persist
= DEF_A_PERSIST
;
1320 lp
->slotime
= DEF_A_SLOTIME
;
1321 lp
->squeldelay
= DEF_A_SQUELDELAY
;
1322 lp
->clockmode
= DEF_A_CLOCKMODE
;
1325 lp
->speed
= DEF_B_SPEED
;
1326 /* default channel access Params */
1327 lp
->txdelay
= DEF_B_TXDELAY
;
1328 lp
->persist
= DEF_B_PERSIST
;
1329 lp
->slotime
= DEF_B_SLOTIME
;
1330 lp
->squeldelay
= DEF_B_SQUELDELAY
;
1331 lp
->clockmode
= DEF_B_CLOCKMODE
;
1333 lp
->bufsiz
= DMA_BUFF_SIZE
;
1338 if (dev
->base_addr
& CHANA
) { /* Do these things only for the A port */
1339 /* Note that a single IRQ services 2 devices (A and B channels) */
1341 lp
->dmachan
= dev
->dma
;
1342 if (lp
->dmachan
< 1 || lp
->dmachan
> 3)
1343 printk(KERN_ERR
"PI: DMA channel %d out of range\n", lp
->dmachan
);
1345 /* chipset_init() was already called */
1351 wrtscc(lp
->cardbase
, CTL
+ lp
->base
, R1
, EXT_INT_ENAB
);
1352 /* enable PI card interrupts */
1353 wrtscc(lp
->cardbase
, CTL
+ lp
->base
, R9
, MIE
| NV
);
1354 restore_flags(flags
);
1355 /* request a timer interrupt for 1 mS hence */
1357 /* 20 "jiffies" should be plenty of time... */
1358 dev
->irq
= autoirq_report(20);
1360 printk(KERN_ERR
"PI: Failed to detect IRQ line.\n");
1364 wrtscc(lp
->cardbase
, dev
->base_addr
+ CTL
, R9
, FHWRES
); /* Hardware reset */
1365 /* Disable interrupts with master interrupt ctrl reg */
1366 wrtscc(lp
->cardbase
, dev
->base_addr
+ CTL
, R9
, 0);
1367 restore_flags(flags
);
1370 printk(KERN_INFO
"PI: Autodetected IRQ %d, assuming DMA %d.\n",
1371 dev
->irq
, dev
->dma
);
1373 /* This board has jumpered interrupts. Snarf the interrupt vector
1374 now. There is no point in waiting since no other device can use
1375 the interrupt, and this marks the 'irqaction' as busy. */
1377 int irqval
= request_irq(dev
->irq
, &pi_interrupt
,0, "pi2", dev
);
1379 printk(KERN_ERR
"PI: unable to get IRQ %d (irqval=%d).\n",
1385 /* Grab the region */
1386 request_region(ioaddr
& 0x3f0, PI_TOTAL_SIZE
, "pi2" );
1389 } /* Only for A port */
1390 dev
->open
= pi_open
;
1391 dev
->stop
= pi_close
;
1392 dev
->do_ioctl
= pi_ioctl
;
1393 dev
->hard_start_xmit
= pi_send_packet
;
1394 dev
->get_stats
= pi_get_stats
;
1396 /* Fill in the fields of the device structure */
1398 dev_init_buffers(dev
);
1400 #if defined(CONFIG_AX25) || defined(CONFIG_AX25_MODULE)
1401 dev
->hard_header
= ax25_encapsulate
;
1402 dev
->rebuild_header
= ax25_rebuild_header
;
1405 dev
->set_mac_address
= pi_set_mac_address
;
1407 dev
->type
= ARPHRD_AX25
; /* AF_AX25 device */
1408 dev
->hard_header_len
= 73; /* We do digipeaters now */
1409 dev
->mtu
= 1500; /* eth_mtu is the default */
1410 dev
->addr_len
= 7; /* sizeof an ax.25 address */
1411 memcpy(dev
->broadcast
, ax25_bcast
, 7);
1412 memcpy(dev
->dev_addr
, ax25_test
, 7);
1414 /* New-style flags. */
1419 /* Open/initialize the board. This is called (in the current kernel)
1420 sometime after booting when the 'ifconfig' program is run.
1422 This routine should set everything up anew at each open, even
1423 registers that "should" only need to be set once at boot, so that
1424 there is non-reboot way to recover if something goes wrong.
1426 static int pi_open(struct device
*dev
)
1428 unsigned long flags
;
1429 static first_time
= 1;
1431 struct pi_local
*lp
= (struct pi_local
*) dev
->priv
;
1433 if (dev
->base_addr
& 2) { /* if A channel */
1435 if (request_dma(dev
->dma
,"pi2")) {
1436 free_irq(dev
->irq
, dev
);
1440 /* Reset the hardware here. */
1445 if (dev
->base_addr
& 2) { /* if A channel */
1446 scc_init(dev
); /* Called once for each channel */
1447 scc_init(dev
->next
);
1449 /* master interrupt enable */
1452 wrtscc(lp
->cardbase
, CTL
+ lp
->base
, R9
, MIE
| NV
);
1453 restore_flags(flags
);
1455 lp
->open_time
= jiffies
;
1467 static int pi_send_packet(struct sk_buff
*skb
, struct device
*dev
)
1469 struct pi_local
*lp
= (struct pi_local
*) dev
->priv
;
1471 hardware_send_packet(lp
, skb
);
1472 dev
->trans_start
= jiffies
;
1477 /* The typical workload of the driver:
1478 Handle the network interface interrupts. */
1479 static void pi_interrupt(int reg_ptr
, void *dev_id
, struct pt_regs
*regs
)
1481 /* int irq = -(((struct pt_regs *) reg_ptr)->orig_eax + 2);*/
1482 struct pi_local
*lp
;
1484 unsigned long flags
;
1486 /* dev_b = dev_a->next; Relies on the order defined in Space.c */
1489 if (dev_a
== NULL
) {
1490 printk(KERN_ERR
"PI: pi_interrupt(): irq %d for unknown device.\n", irq
);
1494 /* Read interrupt status register (only valid from channel A)
1495 * Process all pending interrupts in while loop
1497 lp
= (struct pi_local
*) pi0a
.priv
; /* Assume channel A */
1498 while ((st
= rdscc(lp
->cardbase
, pi0a
.base_addr
| CHANA
| CTL
, R3
)) != 0) {
1500 /* Channel B Transmit Int Pending */
1501 lp
= (struct pi_local
*) pi0b
.priv
;
1503 } else if (st
& CHARxIP
) {
1504 /* Channel A Rcv Interrupt Pending */
1505 lp
= (struct pi_local
*) pi0a
.priv
;
1507 } else if (st
& CHATxIP
) {
1508 /* Channel A Transmit Int Pending */
1509 lp
= (struct pi_local
*) pi0a
.priv
;
1511 } else if (st
& CHAEXT
) {
1512 /* Channel A External Status Int */
1513 lp
= (struct pi_local
*) pi0a
.priv
;
1515 } else if (st
& CHBRxIP
) {
1516 /* Channel B Rcv Interrupt Pending */
1517 lp
= (struct pi_local
*) pi0b
.priv
;
1519 } else if (st
& CHBEXT
) {
1520 /* Channel B External Status Int */
1521 lp
= (struct pi_local
*) pi0b
.priv
;
1524 /* Reset highest interrupt under service */
1527 wrtscc(lp
->cardbase
, lp
->base
+ CTL
, R0
, RES_H_IUS
);
1528 restore_flags(flags
);
1529 } /* End of while loop on int processing */
1533 /* The inverse routine to pi_open(). */
1534 static int pi_close(struct device
*dev
)
1536 unsigned long flags
;
1537 struct pi_local
*lp
;
1538 struct sk_buff
*ptr
;
1543 lp
= (struct pi_local
*) dev
->priv
;
1546 chipset_init(dev
); /* reset the scc */
1547 disable_dma(lp
->dmachan
);
1554 /* Free any buffers left in the hardware transmit queue */
1555 while ((ptr
= skb_dequeue(&lp
->sndq
)) != NULL
)
1558 restore_flags(flags
);
1565 static int pi_ioctl(struct device
*dev
, struct ifreq
*ifr
, int cmd
)
1567 unsigned long flags
;
1569 struct pi_local
*lp
= (struct pi_local
*) dev
->priv
;
1571 int ret
= verify_area(VERIFY_WRITE
, ifr
->ifr_data
, sizeof(struct pi_req
));
1575 if(cmd
!=SIOCDEVPRIVATE
)
1578 copy_from_user(&rq
, ifr
->ifr_data
, sizeof(struct pi_req
));
1587 lp
->txdelay
= rq
.txdelay
;
1588 lp
->persist
= rq
.persist
;
1589 lp
->slotime
= rq
.slotime
;
1590 lp
->squeldelay
= rq
.squeldelay
;
1591 lp
->clockmode
= rq
.clockmode
;
1592 lp
->speed
= rq
.speed
;
1593 pi_open(&pi0a
); /* both channels get reset %%% */
1594 restore_flags(flags
);
1603 if (dev
->base_addr
& 2) { /* if A channel */
1604 if (rq
.dmachan
< 1 || rq
.dmachan
> 3)
1609 free_dma(lp
->dmachan
);
1610 dev
->dma
= lp
->dmachan
= rq
.dmachan
;
1611 if (request_dma(lp
->dmachan
,"pi2"))
1614 restore_flags(flags
);
1619 ret
= -EINVAL
; /* add this later */
1626 rq
.speed
= lp
->speed
;
1627 rq
.txdelay
= lp
->txdelay
;
1628 rq
.persist
= lp
->persist
;
1629 rq
.slotime
= lp
->slotime
;
1630 rq
.squeldelay
= lp
->squeldelay
;
1631 rq
.clockmode
= lp
->clockmode
;
1632 rq
.dmachan
= lp
->dmachan
;
1634 copy_to_user(ifr
->ifr_data
, &rq
, sizeof(struct pi_req
));
1644 /* Get the current statistics. This may be called with the card open or
1646 static struct net_device_stats
*pi_get_stats(struct device
*dev
)
1648 struct pi_local
*lp
= (struct pi_local
*) dev
->priv
;
1656 MODULE_AUTHOR("David Perry <dp@hydra.carleton.ca>");
1657 MODULE_DESCRIPTION("AX.25 driver for the Ottawa PI and PI/2 HDLC cards");
1659 int init_module(void)
1664 void cleanup_module(void)
1666 free_irq(pi0a
.irq
, &pi0a
); /* IRQs and IO Ports are shared */
1667 release_region(pi0a
.base_addr
& 0x3f0, PI_TOTAL_SIZE
);
1671 unregister_netdev(&pi0a
);
1675 unregister_netdev(&pi0b
);