drivers/net/hamradio/dmascc.c

   1 /*
   2  * $Id: dmascc.c,v 1.3 1998/09/07 04:41:56 kudielka Exp $
   3  *
   4  * Driver for high-speed SCC boards (those with DMA support)
   5  * Copyright (C) 1997 Klaus Kudielka
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  20  */
  21
  22
  23 #include <linux/module.h>
  24 #include <linux/delay.h>
  25 #include <linux/dmascc.h>
  26 #include <linux/errno.h>
  27 #include <linux/if_arp.h>
  28 #include <linux/in.h>
  29 #include <linux/interrupt.h>
  30 #include <linux/ioport.h>
  31 #include <linux/kernel.h>
  32 #include <linux/mm.h>
  33 #include <linux/netdevice.h>
  34 #include <linux/sockios.h>
  35 #include <linux/tqueue.h>
  36 #include <linux/version.h>
  37 #include <asm/atomic.h>
  38 #include <asm/bitops.h>
  39 #include <asm/dma.h>
  40 #include <asm/io.h>
  41 #include <asm/irq.h>
  42 #include <asm/segment.h>
  43 #include <net/ax25.h>
  44 #include "z8530.h"
  45
  46
  47 /* Linux 2.0 compatibility */
  48
  49 #if LINUX_VERSION_CODE < 0x20100
  50
  51
  52 #define __init
  53 #define __initdata
  54 #define __initfunc(x) x
  55
  56 #define MODULE_AUTHOR(x)
  57 #define MODULE_DESCRIPTION(x)
  58 #define MODULE_PARM(x,y)
  59
  60 #define copy_to_user(x,y,z) memcpy_tofs(x,y,z)
  61 #define copy_from_user(x,y,z) memcpy_fromfs(x,y,z)
  62 #define test_and_set_bit(x,y) set_bit(x,y)
  63 #define register_netdevice(x) register_netdev(x)
  64 #define unregister_netdevice(x) unregister_netdev(x)
  65 #define dev_kfree_skb(x) dev_kfree_skb(x,FREE_WRITE)
  66 #define SET_DEV_INIT(x) (x=dmascc_dev_init)
  67
  68 #define SHDLCE  0x01 /* WR15 */
  69
  70 #define AUTOEOM 0x02 /* WR7' */
  71 #define RXFIFOH 0x08
  72 #define TXFIFOE 0x20
  73
  74 static int dmascc_dev_init(struct device *dev)
  75 {
  76   return 0;
  77 }
  78
  79 static void dev_init_buffers(struct device *dev)
  80 {
  81   int i;
  82
  83   for (i = 0; i < DEV_NUMBUFFS; i++)
  84     skb_queue_head_init(&dev->buffs[i]);
  85 }
  86
  87
  88 #else
  89
  90
  91 #include <linux/init.h>
  92 #include <asm/uaccess.h>
  93
  94 #define SET_DEV_INIT(x)
  95
  96
  97 #endif
  98
  99
 100 /* Number of buffers per channel */
 101
 102 #define NUM_TX_BUF      2          /* NUM_TX_BUF >= 1 (2 recommended) */
 103 #define NUM_RX_BUF      2          /* NUM_RX_BUF >= 1 (2 recommended) */
 104 #define BUF_SIZE        2016
 105
 106
 107 /* Cards supported */
 108
 109 #define HW_PI           { "Ottawa PI", 0x300, 0x20, 0x10, 8, \
 110                             0, 8, 1843200, 3686400 }
 111 #define HW_PI2          { "Ottawa PI2", 0x300, 0x20, 0x10, 8, \
 112                             0, 8, 3686400, 7372800 }
 113 #define HW_TWIN         { "Gracilis PackeTwin", 0x200, 0x10, 0x10, 32, \
 114                             0, 4, 6144000, 6144000 }
 115
 116 #define HARDWARE        { HW_PI, HW_PI2, HW_TWIN }
 117
 118 #define TYPE_PI         0
 119 #define TYPE_PI2        1
 120 #define TYPE_TWIN       2
 121 #define NUM_TYPES       3
 122
 123 #define MAX_NUM_DEVS    32
 124
 125
 126 /* SCC chips supported */
 127
 128 #define Z8530           0
 129 #define Z85C30          1
 130 #define Z85230          2
 131
 132 #define CHIPNAMES       { "Z8530", "Z85C30", "Z85230" }
 133
 134
 135 /* I/O registers */
 136
 137 /* 8530 registers relative to card base */
 138 #define SCCB_CMD        0x00
 139 #define SCCB_DATA       0x01
 140 #define SCCA_CMD        0x02
 141 #define SCCA_DATA       0x03
 142
 143 /* 8253/8254 registers relative to card base */
 144 #define TMR_CNT0        0x00
 145 #define TMR_CNT1        0x01
 146 #define TMR_CNT2        0x02
 147 #define TMR_CTRL        0x03
 148
 149 /* Additional PI/PI2 registers relative to card base */
 150 #define PI_DREQ_MASK    0x04
 151
 152 /* Additional PackeTwin registers relative to card base */
 153 #define TWIN_INT_REG    0x08
 154 #define TWIN_CLR_TMR1   0x09
 155 #define TWIN_CLR_TMR2   0x0a
 156 #define TWIN_SPARE_1    0x0b
 157 #define TWIN_DMA_CFG    0x08
 158 #define TWIN_SERIAL_CFG 0x09
 159 #define TWIN_DMA_CLR_FF 0x0a
 160 #define TWIN_SPARE_2    0x0b
 161
 162
 163 /* PackeTwin I/O register values */
 164
 165 /* INT_REG */
 166 #define TWIN_SCC_MSK       0x01
 167 #define TWIN_TMR1_MSK      0x02
 168 #define TWIN_TMR2_MSK      0x04
 169 #define TWIN_INT_MSK       0x07
 170
 171 /* SERIAL_CFG */
 172 #define TWIN_DTRA_ON       0x01
 173 #define TWIN_DTRB_ON       0x02
 174 #define TWIN_EXTCLKA       0x04
 175 #define TWIN_EXTCLKB       0x08
 176 #define TWIN_LOOPA_ON      0x10
 177 #define TWIN_LOOPB_ON      0x20
 178 #define TWIN_EI            0x80
 179
 180 /* DMA_CFG */
 181 #define TWIN_DMA_HDX_T1    0x08
 182 #define TWIN_DMA_HDX_R1    0x0a
 183 #define TWIN_DMA_HDX_T3    0x14
 184 #define TWIN_DMA_HDX_R3    0x16
 185 #define TWIN_DMA_FDX_T3R1  0x1b
 186 #define TWIN_DMA_FDX_T1R3  0x1d
 187
 188
 189 /* Status values */
 190
 191 /* tx_state */
 192 #define TX_IDLE    0
 193 #define TX_OFF     1
 194 #define TX_TXDELAY 2
 195 #define TX_ACTIVE  3
 196 #define TX_SQDELAY 4
 197
 198
 199 /* Data types */
 200
 201 struct scc_hardware {
 202   char *name;
 203   int io_region;
 204   int io_delta;
 205   int io_size;
 206   int num_devs;
 207   int scc_offset;
 208   int tmr_offset;
 209   int tmr_hz;
 210   int pclk_hz;
 211 };
 212
 213 struct scc_priv {
 214   char name[10];
 215   struct enet_statistics stats;
 216   struct scc_info *info;
 217   int channel;
 218   int cmd, data, tmr;
 219   struct scc_param param;
 220   char rx_buf[NUM_RX_BUF][BUF_SIZE];
 221   int rx_len[NUM_RX_BUF];
 222   int rx_ptr;
 223   struct tq_struct rx_task;
 224   int rx_head, rx_tail, rx_count;
 225   int rx_over;
 226   char tx_buf[NUM_TX_BUF][BUF_SIZE];
 227   int tx_len[NUM_TX_BUF];
 228   int tx_ptr;
 229   int tx_head, tx_tail, tx_count;
 230   int tx_sem, tx_state;
 231   unsigned long tx_start;
 232   int status;
 233 };
 234
 235 struct scc_info {
 236   int type;
 237   int chip;
 238   int open;
 239   int scc_base;
 240   int tmr_base;
 241   int twin_serial_cfg;
 242   struct device dev[2];
 243   struct scc_priv priv[2];
 244   struct scc_info *next;
 245 };
 246
 247
 248 /* Function declarations */
 249
 250 int dmascc_init(void) __init;
 251 static int setup_adapter(int io, int h, int n) __init;
 252
 253 static inline void write_scc(int ctl, int reg, int val);
 254 static inline int read_scc(int ctl, int reg);
 255 static int scc_open(struct device *dev);
 256 static int scc_close(struct device *dev);
 257 static int scc_ioctl(struct device *dev, struct ifreq *ifr, int cmd);
 258 static int scc_send_packet(struct sk_buff *skb, struct device *dev);
 259 static struct enet_statistics *scc_get_stats(struct device *dev);
 260 static int scc_set_mac_address(struct device *dev, void *sa);
 261 static void scc_isr(int irq, void *dev_id, struct pt_regs * regs);
 262 static inline void z8530_isr(struct scc_info *info);
 263 static void rx_isr(struct device *dev);
 264 static void special_condition(struct device *dev, int rc);
 265 static void rx_bh(void *arg);
 266 static void tx_isr(struct device *dev);
 267 static void es_isr(struct device *dev);
 268 static void tm_isr(struct device *dev);
 269 static inline void delay(struct device *dev, int t);
 270 static inline unsigned char random(void);
 271
 272
 273 /* Initialization variables */
 274
 275 static int io[MAX_NUM_DEVS] __initdata = { 0, };
 276 /* Beware! hw[] is also used in cleanup_module(). If __initdata also applies
 277    to modules, we may not declare hw[] as __initdata */
 278 static struct scc_hardware hw[NUM_TYPES] __initdata = HARDWARE;
 279 static char ax25_broadcast[7] __initdata =
 280   { 'Q'<<1, 'S'<<1, 'T'<<1, ' '<<1, ' '<<1, ' '<<1, '0'<<1 };
 281 static char ax25_test[7] __initdata =
 282   { 'L'<<1, 'I'<<1, 'N'<<1, 'U'<<1, 'X'<<1, ' '<<1, '1'<<1 };
 283
 284
 285 /* Global variables */
 286
 287 static struct scc_info *first = NULL;
 288 static unsigned long rand;
 289
 290
 291
 292 /* Module functions */
 293
 294 #ifdef MODULE
 295
 296
 297 MODULE_AUTHOR("Klaus Kudielka");
 298 MODULE_DESCRIPTION("Driver for high-speed SCC boards");
 299 MODULE_PARM(io, "1-" __MODULE_STRING(MAX_NUM_DEVS) "i");
 300
 301
 302 int init_module(void)
 303 {
 304   return dmascc_init();
 305 }
 306
 307
 308 void cleanup_module(void)
 309 {
 310   int i;
 311   struct scc_info *info;
 312
 313   while (first) {
 314     info = first;
 315
 316     /* Unregister devices */
 317     for (i = 0; i < 2; i++) {
 318       if (info->dev[i].name)
 319         unregister_netdevice(&info->dev[i]);
 320     }
 321
 322     /* Reset board */
 323     if (info->type == TYPE_TWIN)
 324       outb_p(0, info->dev[0].base_addr + TWIN_SERIAL_CFG);
 325     write_scc(info->priv[0].cmd, R9, FHWRES);
 326     release_region(info->dev[0].base_addr,
 327                    hw[info->type].io_size);
 328
 329     /* Free memory */
 330     first = info->next;
 331     kfree_s(info, sizeof(struct scc_info));
 332   }
 333 }
 334
 335
 336 #else
 337
 338
 339 void __init dmascc_setup(char *str, int *ints)
 340 {
 341    int i;
 342
 343    for (i = 0; i < MAX_NUM_DEVS && i < ints[0]; i++)
 344       io[i] = ints[i+1];
 345 }
 346
 347
 348 #endif
 349
 350
 351 /* Initialization functions */
 352
 353 int __init dmascc_init(void)
 354 {
 355   int h, i, j, n;
 356   int base[MAX_NUM_DEVS], tcmd[MAX_NUM_DEVS], t0[MAX_NUM_DEVS],
 357     t1[MAX_NUM_DEVS];
 358   unsigned t_val;
 359   unsigned long time, start[MAX_NUM_DEVS], delay[MAX_NUM_DEVS],
 360     counting[MAX_NUM_DEVS];
 361
 362   /* Initialize random number generator */
 363   rand = jiffies;
 364   /* Cards found = 0 */
 365   n = 0;
 366   /* Warning message */
 367   if (!io[0]) printk("dmascc: autoprobing (dangerous)\n");
 368
 369   /* Run autodetection for each card type */
 370   for (h = 0; h < NUM_TYPES; h++) {
 371
 372     if (io[0]) {
 373       /* User-specified I/O address regions */
 374       for (i = 0; i < hw[h].num_devs; i++) base[i] = 0;
 375       for (i = 0; i < MAX_NUM_DEVS && io[i]; i++) {
 376         j = (io[i] - hw[h].io_region) / hw[h].io_delta;
 377         if (j >= 0 &&
 378             j < hw[h].num_devs &&
 379             hw[h].io_region + j * hw[h].io_delta == io[i]) {
 380           base[j] = io[i];
 381         }
 382       }
 383     } else {
 384       /* Default I/O address regions */
 385       for (i = 0; i < hw[h].num_devs; i++) {
 386         base[i] = hw[h].io_region + i * hw[h].io_delta;
 387       }
 388     }
 389
 390     /* Check valid I/O address regions */
 391     for (i = 0; i < hw[h].num_devs; i++)
 392       if (base[i]) {
 393         if (check_region(base[i], hw[h].io_size))
 394           base[i] = 0;
 395         else {
 396           tcmd[i] = base[i] + hw[h].tmr_offset + TMR_CTRL;
 397           t0[i]   = base[i] + hw[h].tmr_offset + TMR_CNT0;
 398           t1[i]   = base[i] + hw[h].tmr_offset + TMR_CNT1;
 399         }
 400       }
 401
 402     /* Start timers */
 403     for (i = 0; i < hw[h].num_devs; i++)
 404       if (base[i]) {
 405         /* Timer 0: LSB+MSB, Mode 3, TMR_0_HZ */
 406         outb_p(0x36, tcmd[i]);
 407         outb_p((hw[h].tmr_hz/TMR_0_HZ) & 0xFF, t0[i]);
 408         outb_p((hw[h].tmr_hz/TMR_0_HZ) >> 8, t0[i]);
 409         /* Timer 1: LSB+MSB, Mode 0, HZ/10 */
 410         outb_p(0x70, tcmd[i]);
 411         outb_p((TMR_0_HZ/HZ*10) & 0xFF, t1[i]);
 412         outb_p((TMR_0_HZ/HZ*10) >> 8, t1[i]);
 413         start[i] = jiffies;
 414         delay[i] = 0;
 415         counting[i] = 1;
 416         /* Timer 2: LSB+MSB, Mode 0 */
 417         outb_p(0xb0, tcmd[i]);
 418       }
 419     time = jiffies;
 420     /* Wait until counter registers are loaded */
 421     udelay(2000000/TMR_0_HZ);
 422
 423     /* Timing loop */
 424     while (jiffies - time < 13) {
 425       for (i = 0; i < hw[h].num_devs; i++)
 426         if (base[i] && counting[i]) {
 427           /* Read back Timer 1: latch; read LSB; read MSB */
 428           outb_p(0x40, tcmd[i]);
 429           t_val = inb_p(t1[i]) + (inb_p(t1[i]) << 8);
 430           /* Also check whether counter did wrap */
 431           if (t_val == 0 || t_val > TMR_0_HZ/HZ*10) counting[i] = 0;
 432           delay[i] = jiffies - start[i];
 433         }
 434     }
 435
 436     /* Evaluate measurements */
 437     for (i = 0; i < hw[h].num_devs; i++)
 438       if (base[i]) {
 439         if (delay[i] >= 9 && delay[i] <= 11) {
 440           /* Ok, we have found an adapter */
 441           if (setup_adapter(base[i], h, n) == 0)
 442             n++;
 443         }
 444       }
 445
 446   } /* NUM_TYPES */
 447
 448   /* If any adapter was successfully initialized, return ok */
 449   if (n) return 0;
 450
 451   /* If no adapter found, return error */
 452   printk("dmascc: no adapters found\n");
 453   return -EIO;
 454 }
 455
 456 int __init setup_adapter(int io, int h, int n)
 457 {
 458   int i, irq, chip;
 459   struct scc_info *info;
 460   struct device *dev;
 461   struct scc_priv *priv;
 462   unsigned long time;
 463   unsigned int irqs;
 464   int tmr = io + hw[h].tmr_offset;
 465   int scc = io + hw[h].scc_offset;
 466   int cmd = scc + SCCA_CMD;
 467   char *chipnames[] = CHIPNAMES;
 468
 469   /* Reset 8530 */
 470   write_scc(cmd, R9, FHWRES | MIE | NV);
 471
 472   /* Determine type of chip by enabling SDLC/HDLC enhancements */
 473   write_scc(cmd, R15, SHDLCE);
 474   if (!read_scc(cmd, R15)) {
 475     /* WR7' not present. This is an ordinary Z8530 SCC. */
 476     chip = Z8530;
 477   } else {
 478     /* Put one character in TX FIFO */
 479     write_scc(cmd, R8, 0);
 480     if (read_scc(cmd, R0) & Tx_BUF_EMP) {
 481       /* TX FIFO not full. This is a Z85230 ESCC with a 4-byte FIFO. */
 482       chip = Z85230;
 483     } else {
 484       /* TX FIFO full. This is a Z85C30 SCC with a 1-byte FIFO. */
 485       chip = Z85C30;
 486     }
 487   }
 488   write_scc(cmd, R15, 0);
 489
 490   /* Start IRQ auto-detection */
 491   sti();
 492   irqs = probe_irq_on();
 493
 494   /* Enable interrupts */
 495   switch (h) {
 496   case TYPE_PI:
 497   case TYPE_PI2:
 498     outb_p(0, io + PI_DREQ_MASK);
 499     write_scc(cmd, R15, CTSIE);
 500     write_scc(cmd, R0, RES_EXT_INT);
 501     write_scc(cmd, R1, EXT_INT_ENAB);
 502     break;
 503   case TYPE_TWIN:
 504     outb_p(0, io + TWIN_DMA_CFG);
 505     inb_p(io + TWIN_CLR_TMR1);
 506     inb_p(io + TWIN_CLR_TMR2);
 507     outb_p(TWIN_EI, io + TWIN_SERIAL_CFG);
 508     break;
 509   }
 510
 511   /* Start timer */
 512   outb_p(1, tmr + TMR_CNT1);
 513   outb_p(0, tmr + TMR_CNT1);
 514   /* Wait and detect IRQ */
 515   time = jiffies; while (jiffies - time < 2 + HZ / TMR_0_HZ);
 516   irq = probe_irq_off(irqs);
 517
 518   /* Clear pending interrupt, disable interrupts */
 519   switch (h) {
 520   case TYPE_PI:
 521   case TYPE_PI2:
 522     write_scc(cmd, R1, 0);
 523     write_scc(cmd, R15, 0);
 524     write_scc(cmd, R0, RES_EXT_INT);
 525     break;
 526   case TYPE_TWIN:
 527     inb_p(io + TWIN_CLR_TMR1);
 528     outb_p(0, io + TWIN_SERIAL_CFG);
 529     break;
 530   }
 531
 532   if (irq <= 0) {
 533     printk("dmascc: could not find irq of %s at %#3x (irq=%d)\n",
 534            hw[h].name, io, irq);
 535     return -1;
 536   }
 537
 538   /* Allocate memory */
 539   info = kmalloc(sizeof(struct scc_info), GFP_KERNEL | GFP_DMA);
 540   if (!info) {
 541     printk("dmascc: could not allocate memory for %s at %#3x\n",
 542            hw[h].name, io);
 543     return -1;
 544   }
 545
 546   /* Set up data structures */
 547   memset(info, 0, sizeof(struct scc_info));
 548   info->type = h;
 549   info->chip = chip;
 550   info->scc_base = io + hw[h].scc_offset;
 551   info->tmr_base = io + hw[h].tmr_offset;
 552   info->twin_serial_cfg = 0;
 553   for (i = 0; i < 2; i++) {
 554     dev = &info->dev[i];
 555     priv = &info->priv[i];
 556     sprintf(priv->name, "dmascc%i", 2*n+i);
 557     priv->info = info;
 558     priv->channel = i;
 559     priv->cmd = info->scc_base + (i ? SCCB_CMD : SCCA_CMD);
 560     priv->data = info->scc_base + (i ? SCCB_DATA : SCCA_DATA);
 561     priv->tmr = info->tmr_base + (i ? TMR_CNT2 : TMR_CNT1);
 562     priv->param.pclk_hz = hw[h].pclk_hz;
 563     priv->param.brg_tc = -1;
 564     priv->param.clocks = TCTRxCP | RCRTxCP;
 565     priv->param.txdelay = TMR_0_HZ * 10 / 1000;
 566     priv->param.txtime = HZ * 3;
 567     priv->param.sqdelay = TMR_0_HZ * 1 / 1000;
 568     priv->param.slottime = TMR_0_HZ * 10 / 1000;
 569     priv->param.waittime = TMR_0_HZ * 100 / 1000;
 570     priv->param.persist = 32;
 571     priv->rx_task.routine = rx_bh;
 572     priv->rx_task.data = dev;
 573     dev->priv = priv;
 574     dev->name = priv->name;
 575     dev->base_addr = io;
 576     dev->irq = irq;
 577     dev->open = scc_open;
 578     dev->stop = scc_close;
 579     dev->do_ioctl = scc_ioctl;
 580     dev->hard_start_xmit = scc_send_packet;
 581     dev->get_stats = scc_get_stats;
 582     dev->hard_header = ax25_encapsulate;
 583     dev->rebuild_header = ax25_rebuild_header;
 584     dev->set_mac_address = scc_set_mac_address;
 585     SET_DEV_INIT(dev->init);
 586     dev->type = ARPHRD_AX25;
 587     dev->hard_header_len = 73;
 588     dev->mtu = 1500;
 589     dev->addr_len = 7;
 590     dev->tx_queue_len = 64;
 591     memcpy(dev->broadcast, ax25_broadcast, 7);
 592     memcpy(dev->dev_addr, ax25_test, 7);
 593     dev_init_buffers(dev);
 594     if (register_netdevice(dev)) {
 595       printk("dmascc: could not register %s\n", dev->name);
 596       dev->name = NULL;
 597     }
 598   }
 599
 600   request_region(io, hw[h].io_size, "dmascc");
 601
 602   info->next = first;
 603   first = info;
 604   printk("dmascc: found %s (%s) at %#3x, irq %d\n", hw[h].name,
 605          chipnames[chip], io, irq);
 606   return 0;
 607 }
 608
 609
 610 /* Driver functions */
 611
 612 static inline void write_scc(int ctl, int reg, int val)
 613 {
 614   outb_p(reg, ctl);
 615   outb_p(val, ctl);
 616 }
 617
 618
 619 static inline int read_scc(int ctl, int reg)
 620 {
 621   outb_p(reg, ctl);
 622   return inb_p(ctl);
 623 }
 624
 625
 626 static int scc_open(struct device *dev)
 627 {
 628   struct scc_priv *priv = dev->priv;
 629   struct scc_info *info = priv->info;
 630   int io = dev->base_addr;
 631   int cmd = priv->cmd;
 632
 633   /* Request IRQ if not already used by other channel */
 634   if (!info->open) {
 635     if (request_irq(dev->irq, scc_isr, SA_INTERRUPT, "dmascc", info))
 636       return -EAGAIN;
 637   }
 638
 639   /* Request DMA if required */
 640   if (dev->dma && request_dma(dev->dma, "dmascc")) {
 641     if (!info->open) free_irq(dev->irq, info);
 642     return -EAGAIN;
 643   }
 644
 645   /* Initialize local variables */
 646   dev->tbusy = 0;
 647   priv->rx_ptr = 0;
 648   priv->rx_over = 0;
 649   priv->rx_head = priv->rx_tail = priv->rx_count = 0;
 650   priv->tx_state = TX_IDLE;
 651   priv->tx_head = priv->tx_tail = priv->tx_count = 0;
 652   priv->tx_ptr = 0;
 653   priv->tx_sem = 0;
 654
 655   /* Reset channel */
 656   write_scc(cmd, R9, (priv->channel ? CHRB : CHRA) | MIE | NV);
 657   /* X1 clock, SDLC mode */
 658   write_scc(cmd, R4, SDLC | X1CLK);
 659   /* DMA */
 660   write_scc(cmd, R1, EXT_INT_ENAB | WT_FN_RDYFN);
 661   /* 8 bit RX char, RX disable */
 662   write_scc(cmd, R3, Rx8);
 663   /* 8 bit TX char, TX disable */
 664   write_scc(cmd, R5, Tx8);
 665   /* SDLC address field */
 666   write_scc(cmd, R6, 0);
 667   /* SDLC flag */
 668   write_scc(cmd, R7, FLAG);
 669   switch (info->chip) {
 670   case Z85C30:
 671     /* Select WR7' */
 672     write_scc(cmd, R15, SHDLCE);
 673     /* Auto EOM reset */
 674     write_scc(cmd, R7, AUTOEOM);
 675     write_scc(cmd, R15, 0);
 676     break;
 677   case Z85230:
 678     /* Select WR7' */
 679     write_scc(cmd, R15, SHDLCE);
 680     /* RX FIFO half full (interrupt only), Auto EOM reset,
 681        TX FIFO empty (DMA only) */
 682     write_scc(cmd, R7, AUTOEOM | (dev->dma ? TXFIFOE : RXFIFOH));
 683     write_scc(cmd, R15, 0);
 684     break;
 685   }
 686   /* Preset CRC, NRZ(I) encoding */
 687   write_scc(cmd, R10, CRCPS | (priv->param.nrzi ? NRZI : NRZ));
 688
 689   /* Configure baud rate generator */
 690   if (priv->param.brg_tc >= 0) {
 691     /* Program BR generator */
 692     write_scc(cmd, R12, priv->param.brg_tc & 0xFF);
 693     write_scc(cmd, R13, (priv->param.brg_tc>>8) & 0xFF);
 694     /* BRG source = SYS CLK; enable BRG; DTR REQ function (required by
 695        PackeTwin, not connected on the PI2); set DPLL source to BRG */
 696     write_scc(cmd, R14, SSBR | DTRREQ | BRSRC | BRENABL);
 697     /* Enable DPLL */
 698     write_scc(cmd, R14, SEARCH | DTRREQ | BRSRC | BRENABL);
 699   } else {
 700     /* Disable BR generator */
 701     write_scc(cmd, R14, DTRREQ | BRSRC);
 702   }
 703
 704   /* Configure clocks */
 705   if (info->type == TYPE_TWIN) {
 706     /* Disable external TX clock receiver */
 707     outb_p((info->twin_serial_cfg &=
 708             ~(priv->channel ? TWIN_EXTCLKB : TWIN_EXTCLKA)),
 709            io + TWIN_SERIAL_CFG);
 710   }
 711   write_scc(cmd, R11, priv->param.clocks);
 712   if ((info->type == TYPE_TWIN) && !(priv->param.clocks & TRxCOI)) {
 713     /* Enable external TX clock receiver */
 714     outb_p((info->twin_serial_cfg |=
 715             (priv->channel ? TWIN_EXTCLKB : TWIN_EXTCLKA)),
 716            io + TWIN_SERIAL_CFG);
 717   }
 718
 719   /* Configure PackeTwin */
 720   if (info->type == TYPE_TWIN) {
 721     /* Assert DTR, enable interrupts */
 722     outb_p((info->twin_serial_cfg |= TWIN_EI |
 723             (priv->channel ? TWIN_DTRB_ON : TWIN_DTRA_ON)),
 724            io + TWIN_SERIAL_CFG);
 725   }
 726
 727   /* Read current status */
 728   priv->status = read_scc(cmd, R0);
 729   /* Enable SYNC, DCD, and CTS interrupts */
 730   write_scc(cmd, R15, DCDIE | CTSIE | SYNCIE);
 731
 732   /* Configure PI2 DMA */
 733   if (info->type <= TYPE_PI2) outb_p(1, io + PI_DREQ_MASK);
 734
 735   dev->start = 1;
 736   info->open++;
 737   MOD_INC_USE_COUNT;
 738
 739   return 0;
 740 }
 741
 742
 743 static int scc_close(struct device *dev)
 744 {
 745   struct scc_priv *priv = dev->priv;
 746   struct scc_info *info = priv->info;
 747   int io = dev->base_addr;
 748   int cmd = priv->cmd;
 749
 750   dev->start = 0;
 751   info->open--;
 752   MOD_DEC_USE_COUNT;
 753
 754   if (info->type == TYPE_TWIN)
 755     /* Drop DTR */
 756     outb_p((info->twin_serial_cfg &=
 757             (priv->channel ? ~TWIN_DTRB_ON : ~TWIN_DTRA_ON)),
 758            io + TWIN_SERIAL_CFG);
 759
 760   /* Reset channel, free DMA */
 761   write_scc(cmd, R9, (priv->channel ? CHRB : CHRA) | MIE | NV);
 762   if (dev->dma) {
 763     if (info->type == TYPE_TWIN) outb_p(0, io + TWIN_DMA_CFG);
 764     free_dma(dev->dma);
 765   }
 766
 767   if (!info->open) {
 768     if (info->type <= TYPE_PI2) outb_p(0, io + PI_DREQ_MASK);
 769     free_irq(dev->irq, info);
 770   }
 771   return 0;
 772 }
 773
 774
 775 static int scc_ioctl(struct device *dev, struct ifreq *ifr, int cmd)
 776 {
 777   int rc;
 778   struct scc_priv *priv = dev->priv;
 779
 780   switch (cmd) {
 781   case SIOCGSCCPARAM:
 782     rc = verify_area(VERIFY_WRITE, ifr->ifr_data, sizeof(struct scc_param));
 783     if (rc) return rc;
 784     copy_to_user(ifr->ifr_data, &priv->param, sizeof(struct scc_param));
 785     return 0;
 786   case SIOCSSCCPARAM:
 787     if (!suser()) return -EPERM;
 788     rc = verify_area(VERIFY_READ, ifr->ifr_data, sizeof(struct scc_param));
 789     if (rc) return rc;
 790     if (dev->start) return -EAGAIN;
 791     copy_from_user(&priv->param, ifr->ifr_data, sizeof(struct scc_param));
 792     dev->dma = priv->param.dma;
 793     return 0;
 794   default:
 795     return -EINVAL;
 796   }
 797 }
 798
 799
 800 static int scc_send_packet(struct sk_buff *skb, struct device *dev)
 801 {
 802   struct scc_priv *priv = dev->priv;
 803   struct scc_info *info = priv->info;
 804   int cmd = priv->cmd;
 805   unsigned long flags;
 806   int i;
 807
 808   /* Block a timer-based transmit from overlapping */
 809   if (test_and_set_bit(0, (void *) &priv->tx_sem) != 0) {
 810     atomic_inc((void *) &priv->stats.tx_dropped);
 811     dev_kfree_skb(skb);
 812     return 0;
 813   }
 814
 815   /* Return with an error if we cannot accept more data */
 816   if (dev->tbusy) {
 817     priv->tx_sem = 0;
 818     return -1;
 819   }
 820
 821   /* Transfer data to DMA buffer */
 822   i = priv->tx_head;
 823   memcpy(priv->tx_buf[i], skb->data+1, skb->len-1);
 824   priv->tx_len[i] = skb->len-1;
 825
 826   save_flags(flags);
 827   cli();
 828
 829   /* Set the busy flag if we just filled up the last buffer */
 830   priv->tx_head = (i + 1) % NUM_TX_BUF;
 831   priv->tx_count++;
 832   if (priv->tx_count == NUM_TX_BUF) dev->tbusy = 1;
 833
 834   /* Set new TX state */
 835   if (priv->tx_state == TX_IDLE) {
 836     /* Assert RTS, start timer */
 837     priv->tx_state = TX_TXDELAY;
 838     if (info->type <= TYPE_PI2) outb_p(0, dev->base_addr + PI_DREQ_MASK);
 839     write_scc(cmd, R5, TxCRC_ENAB | RTS | TxENAB | Tx8);
 840     if (info->type <= TYPE_PI2) outb_p(1, dev->base_addr + PI_DREQ_MASK);
 841     priv->tx_start = jiffies;
 842     delay(dev, priv->param.txdelay);
 843   }
 844
 845   restore_flags(flags);
 846
 847   dev_kfree_skb(skb);
 848
 849   priv->tx_sem = 0;
 850   return 0;
 851 }
 852
 853
 854 static struct enet_statistics *scc_get_stats(struct device *dev)
 855 {
 856   struct scc_priv *priv = dev->priv;
 857
 858   return &priv->stats;
 859 }
 860
 861
 862 static int scc_set_mac_address(struct device *dev, void *sa)
 863 {
 864   memcpy(dev->dev_addr, ((struct sockaddr *)sa)->sa_data, dev->addr_len);
 865   return 0;
 866 }
 867
 868
 869 static void scc_isr(int irq, void *dev_id, struct pt_regs * regs)
 870 {
 871   struct scc_info *info = dev_id;
 872   int is, io = info->dev[0].base_addr;
 873
 874   /* We're a fast IRQ handler and are called with interrupts disabled */
 875
 876   /* IRQ sharing doesn't make sense due to ISA's edge-triggered
 877      interrupts, hence it is safe to return if we have found and
 878      processed a single device. */
 879
 880   /* Interrupt processing: We loop until we know that the IRQ line is
 881      low. If another positive edge occurs afterwards during the ISR,
 882      another interrupt will be triggered by the interrupt controller
 883      as soon as the IRQ level is enabled again (see asm/irq.h). */
 884
 885   switch (info->type) {
 886   case TYPE_PI:
 887   case TYPE_PI2:
 888     outb_p(0, io + PI_DREQ_MASK);
 889     z8530_isr(info);
 890     outb_p(1, io + PI_DREQ_MASK);
 891     return;
 892   case TYPE_TWIN:
 893     while ((is = ~inb_p(io + TWIN_INT_REG)) &
 894            TWIN_INT_MSK) {
 895       if (is & TWIN_SCC_MSK) {
 896         z8530_isr(info);
 897       } else if (is & TWIN_TMR1_MSK) {
 898         inb_p(io + TWIN_CLR_TMR1);
 899         tm_isr(&info->dev[0]);
 900       } else {
 901         inb_p(io + TWIN_CLR_TMR2);
 902         tm_isr(&info->dev[1]);
 903       }
 904     }
 905     /* No interrupts pending from the PackeTwin */
 906     return;
 907   }
 908 }
 909
 910
 911 static inline void z8530_isr(struct scc_info *info)
 912 {
 913   int is, a_cmd;
 914
 915   a_cmd = info->scc_base + SCCA_CMD;
 916
 917   while ((is = read_scc(a_cmd, R3))) {
 918     if (is & CHARxIP) {
 919       rx_isr(&info->dev[0]);
 920     } else if (is & CHATxIP) {
 921       tx_isr(&info->dev[0]);
 922     } else if (is & CHAEXT) {
 923       es_isr(&info->dev[0]);
 924     } else if (is & CHBRxIP) {
 925       rx_isr(&info->dev[1]);
 926     } else if (is & CHBTxIP) {
 927       tx_isr(&info->dev[1]);
 928     } else {
 929       es_isr(&info->dev[1]);
 930     }
 931   }
 932   /* Ok, no interrupts pending from this 8530. The INT line should
 933      be inactive now. */
 934 }
 935
 936
 937 static void rx_isr(struct device *dev)
 938 {
 939   struct scc_priv *priv = dev->priv;
 940   int cmd = priv->cmd;
 941
 942   if (dev->dma) {
 943     /* Check special condition and perform error reset. See 2.4.7.5. */
 944     special_condition(dev, read_scc(cmd, R1));
 945     write_scc(cmd, R0, ERR_RES);
 946   } else {
 947     /* Check special condition for each character. Error reset not necessary.
 948        Same algorithm for SCC and ESCC. See 2.4.7.1 and 2.4.7.4. */
 949     int rc;
 950     while (read_scc(cmd, R0) & Rx_CH_AV) {
 951       rc = read_scc(cmd, R1);
 952       if (priv->rx_ptr < BUF_SIZE)
 953         priv->rx_buf[priv->rx_head][priv->rx_ptr++] = read_scc(cmd, R8);
 954       else {
 955         priv->rx_over = 2;
 956         read_scc(cmd, R8);
 957       }
 958       special_condition(dev, rc);
 959     }
 960   }
 961 }
 962
 963
 964 static void special_condition(struct device *dev, int rc)
 965 {
 966   struct scc_priv *priv = dev->priv;
 967   int cb, cmd = priv->cmd;
 968   unsigned long flags;
 969
 970   /* See Figure 2-15. Only overrun and EOF need to be checked. */
 971
 972   if (rc & Rx_OVR) {
 973     /* Receiver overrun */
 974     priv->rx_over = 1;
 975     if (!dev->dma) write_scc(cmd, R0, ERR_RES);
 976   } else if (rc & END_FR) {
 977     /* End of frame. Get byte count */
 978     if (dev->dma) {
 979         flags=claim_dma_lock();
 980         disable_dma(dev->dma);
 981         clear_dma_ff(dev->dma);
 982         cb = BUF_SIZE - get_dma_residue(dev->dma) - 2;
 983         release_dma_lock(flags);
 984
 985     } else {
 986         cb = priv->rx_ptr - 2;
 987     }
 988     if (priv->rx_over) {
 989       /* We had an overrun */
 990       priv->stats.rx_errors++;
 991       if (priv->rx_over == 2) priv->stats.rx_length_errors++;
 992       else priv->stats.rx_fifo_errors++;
 993       priv->rx_over = 0;
 994     } else if (rc & CRC_ERR) {
 995       /* Count invalid CRC only if packet length >= minimum */
 996       if (cb >= 8) {
 997         priv->stats.rx_errors++;
 998         priv->stats.rx_crc_errors++;
 999       }
1000     } else {
1001       if (cb >= 8) {
1002         /* Put good frame in FIFO */
1003         priv->rx_len[priv->rx_head] = cb;
1004         priv->rx_head = (priv->rx_head + 1) % NUM_RX_BUF;
1005         priv->rx_count++;
1006         if (priv->rx_count == NUM_RX_BUF) {
1007           /* Disable receiver if FIFO full */
1008           write_scc(cmd, R3, Rx8);
1009           priv->stats.rx_errors++;
1010           priv->stats.rx_over_errors++;
1011         }
1012         /* Mark bottom half handler */
1013         queue_task(&priv->rx_task, &tq_immediate);
1014         mark_bh(IMMEDIATE_BH);
1015       }
1016     }
1017     /* Get ready for new frame */
1018     if (dev->dma) {
1019
1020       flags=claim_dma_lock();
1021       set_dma_addr(dev->dma, (int) priv->rx_buf[priv->rx_head]);
1022       set_dma_count(dev->dma, BUF_SIZE);
1023       enable_dma(dev->dma);
1024       release_dma_lock(flags);
1025
1026     } else {
1027       priv->rx_ptr = 0;
1028     }
1029   }
1030 }
1031
1032
1033 static void rx_bh(void *arg)
1034 {
1035   struct device *dev = arg;
1036   struct scc_priv *priv = dev->priv;
1037   struct scc_info *info = priv->info;
1038   int cmd = priv->cmd;
1039   int i = priv->rx_tail;
1040   int cb;
1041   unsigned long flags;
1042   struct sk_buff *skb;
1043   unsigned char *data;
1044
1045   save_flags(flags);
1046   cli();
1047
1048   while (priv->rx_count) {
1049     restore_flags(flags);
1050     cb = priv->rx_len[i];
1051     /* Allocate buffer */
1052     skb = dev_alloc_skb(cb+1);
1053     if (skb == NULL) {
1054       /* Drop packet */
1055       priv->stats.rx_dropped++;
1056     } else {
1057       /* Fill buffer */
1058       data = skb_put(skb, cb+1);
1059       data[0] = 0;
1060       memcpy(&data[1], priv->rx_buf[i], cb);
1061       skb->dev = dev;
1062       skb->protocol = ntohs(ETH_P_AX25);
1063       skb->mac.raw = skb->data;
1064       netif_rx(skb);
1065       priv->stats.rx_packets++;
1066     }
1067     save_flags(flags);
1068     cli();
1069     /* Enable receiver if RX buffers have been unavailable */
1070     if ((priv->rx_count == NUM_RX_BUF) && (priv->status & DCD)) {
1071       if (info->type <= TYPE_PI2) outb_p(0, dev->base_addr + PI_DREQ_MASK);
1072       write_scc(cmd, R3, RxENABLE | Rx8 | RxCRC_ENAB);
1073       if (info->type <= TYPE_PI2) outb_p(1, dev->base_addr + PI_DREQ_MASK);
1074     }
1075     /* Move tail */
1076     priv->rx_tail = i = (i + 1) % NUM_RX_BUF;
1077     priv->rx_count--;
1078   }
1079
1080   restore_flags(flags);
1081 }
1082
1083
1084 static void tx_isr(struct device *dev)
1085 {
1086   struct scc_priv *priv = dev->priv;
1087   int cmd = priv->cmd;
1088   int i = priv->tx_tail, p = priv->tx_ptr;
1089
1090   /* Suspend TX interrupts if we don't want to send anything.
1091      See Figure 2-22. */
1092   if (p ==  priv->tx_len[i]) {
1093     write_scc(cmd, R0, RES_Tx_P);
1094     return;
1095   }
1096
1097   /* Write characters */
1098   while ((read_scc(cmd, R0) & Tx_BUF_EMP) && p < priv->tx_len[i]) {
1099     write_scc(cmd, R8, priv->tx_buf[i][p++]);
1100   }
1101   priv->tx_ptr = p;
1102
1103 }
1104
1105
1106 static void es_isr(struct device *dev)
1107 {
1108   struct scc_priv *priv = dev->priv;
1109   struct scc_info *info = priv->info;
1110   int i, cmd = priv->cmd;
1111   int st, dst, res;
1112   unsigned long flags;
1113
1114   /* Read status and reset interrupt bit */
1115   st = read_scc(cmd, R0);
1116   write_scc(cmd, R0, RES_EXT_INT);
1117   dst = priv->status ^ st;
1118   priv->status = st;
1119
1120   /* Since the EOM latch is reset automatically, we assume that
1121      it has been zero if and only if we are in the TX_ACTIVE state.
1122      Otherwise we follow 2.4.9.6. */
1123
1124   /* Transmit underrun */
1125   if ((priv->tx_state == TX_ACTIVE) && (st & TxEOM)) {
1126     /* Get remaining bytes */
1127     i = priv->tx_tail;
1128     if (dev->dma) {
1129       flags=claim_dma_lock();
1130       disable_dma(dev->dma);
1131       clear_dma_ff(dev->dma);
1132       res = get_dma_residue(dev->dma);
1133       release_dma_lock(flags);
1134     } else {
1135       res = priv->tx_len[i] - priv->tx_ptr;
1136       if (res) write_scc(cmd, R0, RES_Tx_P);
1137       priv->tx_ptr = 0;
1138     }
1139     /* Remove frame from FIFO */
1140     priv->tx_tail = (i + 1) % NUM_TX_BUF;
1141     priv->tx_count--;
1142     dev->tbusy = 0;
1143     /* Check if another frame is available and we are allowed to transmit */
1144     if (priv->tx_count && (jiffies - priv->tx_start) < priv->param.txtime) {
1145       if (dev->dma) {
1146         flags=claim_dma_lock();
1147         set_dma_addr(dev->dma, (int) priv->tx_buf[priv->tx_tail]);
1148         set_dma_count(dev->dma, priv->tx_len[priv->tx_tail]);
1149         enable_dma(dev->dma);
1150         release_dma_lock(flags);
1151       } else {
1152         /* If we have an ESCC, we are allowed to write data bytes
1153            immediately. Otherwise we have to wait for the next
1154            TX interrupt. See Figure 2-22. */
1155         if (info->chip == Z85230) {
1156           tx_isr(dev);
1157         }
1158       }
1159     } else {
1160       /* No frame available. Disable interrupts. */
1161       priv->tx_state = TX_SQDELAY;
1162       delay(dev, priv->param.sqdelay);
1163       write_scc(cmd, R15, DCDIE | CTSIE | SYNCIE);
1164       write_scc(cmd, R1, EXT_INT_ENAB | WT_FN_RDYFN);
1165     }
1166     /* Update packet statistics */
1167     if (res) {
1168       priv->stats.tx_errors++;
1169       priv->stats.tx_fifo_errors++;
1170     } else {
1171       priv->stats.tx_packets++;
1172     }
1173     /* Inform upper layers */
1174     mark_bh(NET_BH);
1175   }
1176
1177   /* DCD transition */
1178   if ((priv->tx_state < TX_TXDELAY) && (dst & DCD)) {
1179     /* Transmitter state change */
1180     priv->tx_state = TX_OFF;
1181     /* Enable or disable receiver */
1182     if (st & DCD) {
1183       if (dev->dma) {
1184         /* Program DMA controller */
1185         flags=claim_dma_lock();
1186         disable_dma(dev->dma);
1187         clear_dma_ff(dev->dma);
1188         set_dma_mode(dev->dma, DMA_MODE_READ);
1189         set_dma_addr(dev->dma, (int) priv->rx_buf[priv->rx_head]);
1190         set_dma_count(dev->dma, BUF_SIZE);
1191         enable_dma(dev->dma);
1192         release_dma_lock(flags);
1193         /* Configure PackeTwin DMA */
1194         if (info->type == TYPE_TWIN) {
1195           outb_p((dev->dma == 1) ? TWIN_DMA_HDX_R1 : TWIN_DMA_HDX_R3,
1196                  dev->base_addr + TWIN_DMA_CFG);
1197         }
1198         /* Sp. cond. intr. only, ext int enable */
1199         write_scc(cmd, R1, EXT_INT_ENAB | INT_ERR_Rx |
1200                   WT_RDY_RT | WT_FN_RDYFN | WT_RDY_ENAB);
1201       } else {
1202         /* Intr. on all Rx characters and Sp. cond., ext int enable */
1203         write_scc(cmd, R1, EXT_INT_ENAB | INT_ALL_Rx | WT_RDY_RT |
1204                   WT_FN_RDYFN);
1205       }
1206       if (priv->rx_count < NUM_RX_BUF) {
1207         /* Enable receiver */
1208         write_scc(cmd, R3, RxENABLE | Rx8 | RxCRC_ENAB);
1209       }
1210     } else {
1211       /* Disable DMA */
1212       if (dev->dma)
1213       {
1214         flags=claim_dma_lock();
1215         disable_dma(dev->dma);
1216         release_dma_lock(flags);
1217       }
1218       /* Disable receiver */
1219       write_scc(cmd, R3, Rx8);
1220       /* DMA disable, RX int disable, Ext int enable */
1221       write_scc(cmd, R1, EXT_INT_ENAB | WT_RDY_RT | WT_FN_RDYFN);
1222       /* Transmitter state change */
1223       if (random() > priv->param.persist)
1224         delay(dev, priv->param.slottime);
1225       else {
1226         if (priv->tx_count) {
1227           priv->tx_state = TX_TXDELAY;
1228           write_scc(cmd, R5, TxCRC_ENAB | RTS | TxENAB | Tx8);
1229           priv->tx_start = jiffies;
1230           delay(dev, priv->param.txdelay);
1231         } else {
1232           priv->tx_state = TX_IDLE;
1233         }
1234       }
1235     }
1236   }
1237
1238   /* CTS transition */
1239   if ((info->type <= TYPE_PI2) && (dst & CTS) && (~st & CTS)) {
1240     /* Timer has expired */
1241     tm_isr(dev);
1242   }
1243
1244   /* /SYNC/HUNT transition */
1245   if ((dst & SYNC_HUNT) && (~st & SYNC_HUNT)) {
1246     /* Reset current frame and clear RX FIFO */
1247     while (read_scc(cmd, R0) & Rx_CH_AV) read_scc(cmd, R8);
1248     priv->rx_over = 0;
1249     if (dev->dma) {
1250       flags=claim_dma_lock();
1251       disable_dma(dev->dma);
1252       clear_dma_ff(dev->dma);
1253       set_dma_addr(dev->dma, (int) priv->rx_buf[priv->rx_head]);
1254       set_dma_count(dev->dma, BUF_SIZE);
1255       enable_dma(dev->dma);
1256       release_dma_lock(flags);
1257     } else {
1258       priv->rx_ptr = 0;
1259     }
1260   }
1261 }
1262
1263
1264 static void tm_isr(struct device *dev)
1265 {
1266   struct scc_priv *priv = dev->priv;
1267   struct scc_info *info = priv->info;
1268   int cmd = priv->cmd;
1269   unsigned long flags;
1270
1271   switch (priv->tx_state) {
1272   case TX_OFF:
1273     if (~priv->status & DCD) {
1274       if (random() > priv->param.persist) delay(dev, priv->param.slottime);
1275       else {
1276         if (priv->tx_count) {
1277           priv->tx_state = TX_TXDELAY;
1278           write_scc(cmd, R5, TxCRC_ENAB | RTS | TxENAB | Tx8);
1279           priv->tx_start = jiffies;
1280           delay(dev, priv->param.txdelay);
1281         } else {
1282           priv->tx_state = TX_IDLE;
1283         }
1284       }
1285     }
1286     break;
1287   case TX_TXDELAY:
1288     priv->tx_state = TX_ACTIVE;
1289     if (dev->dma) {
1290       /* Program DMA controller */
1291
1292       flags=claim_dma_lock();
1293       disable_dma(dev->dma);
1294       clear_dma_ff(dev->dma);
1295       set_dma_mode(dev->dma, DMA_MODE_WRITE);
1296       set_dma_addr(dev->dma, (int) priv->tx_buf[priv->tx_tail]);
1297       set_dma_count(dev->dma, priv->tx_len[priv->tx_tail]);
1298       enable_dma(dev->dma);
1299       release_dma_lock(flags);
1300
1301       /* Configure PackeTwin DMA */
1302       if (info->type == TYPE_TWIN) {
1303         outb_p((dev->dma == 1) ? TWIN_DMA_HDX_T1 : TWIN_DMA_HDX_T3,
1304                dev->base_addr + TWIN_DMA_CFG);
1305       }
1306       /* Enable interrupts and DMA. On the PackeTwin, the DTR//REQ pin
1307          is used for TX DMA requests, but we enable the WAIT/DMA request
1308          pin, anyway */
1309       write_scc(cmd, R15, TxUIE | DCDIE | CTSIE | SYNCIE);
1310       write_scc(cmd, R1, EXT_INT_ENAB | WT_FN_RDYFN | WT_RDY_ENAB);
1311     } else {
1312       write_scc(cmd, R15, TxUIE | DCDIE | CTSIE | SYNCIE);
1313       write_scc(cmd, R1, EXT_INT_ENAB | WT_FN_RDYFN | TxINT_ENAB);
1314       tx_isr(dev);
1315     }
1316     if (info->chip == Z8530) write_scc(cmd, R0, RES_EOM_L);
1317     break;
1318   case TX_SQDELAY:
1319     /* Disable transmitter */
1320     write_scc(cmd, R5, TxCRC_ENAB | Tx8);
1321     /* Transmitter state change: Switch to TX_OFF and wait at least
1322        1 slottime. */
1323     priv->tx_state = TX_OFF;
1324     if (~priv->status & DCD) delay(dev, priv->param.waittime);
1325   }
1326 }
1327
1328
1329 static inline void delay(struct device *dev, int t)
1330 {
1331   struct scc_priv *priv = dev->priv;
1332   int tmr = priv->tmr;
1333
1334   outb_p(t & 0xFF, tmr);
1335   outb_p((t >> 8) & 0xFF, tmr);
1336 }
1337
1338
1339 static inline unsigned char random(void)
1340 {
1341   /* See "Numerical Recipes in C", second edition, p. 284 */
1342   rand = rand * 1664525L + 1013904223L;
1343   return (unsigned char) (rand >> 24);
1344 }
1345
1346