drivers/net/a2065.h

   1 /*
   2  * Amiga Linux/68k A2065 Ethernet Driver
   3  *
   4  * (C) Copyright 1995 by Geert Uytterhoeven
   5  *                      (Geert.Uytterhoeven@cs.kuleuven.ac.be)
   6  *
   7  * ---------------------------------------------------------------------------
   8  *
   9  * This program is based on
  10  *
  11  *      ariadne.?:      Amiga Linux/68k Ariadne Ethernet Driver
  12  *                      (C) Copyright 1995 by Geert Uytterhoeven,
  13  *                      Peter De Schrijver
  14  *
  15  *      lance.c:        An AMD LANCE ethernet driver for linux.
  16  *                      Written 1993-94 by Donald Becker.
  17  *
  18  *      Am79C960:       PCnet(tm)-ISA Single-Chip Ethernet Controller
  19  *                      Advanced Micro Devices
  20  *                      Publication #16907, Rev. B, Amendment/0, May 1994
  21  *
  22  * ---------------------------------------------------------------------------
  23  *
  24  * This file is subject to the terms and conditions of the GNU General Public
  25  * License.  See the file COPYING in the main directory of the Linux
  26  * distribution for more details.
  27  *
  28  * ---------------------------------------------------------------------------
  29  *
  30  * The A2065 is a Zorro-II board made by Commodore/Ameristar. It contains:
  31  *
  32  *      - an Am7990 Local Area Network Controller for Ethernet (LANCE) with
  33  *        both 10BASE-2 (thin coax) and AUI (DB-15) connectors
  34  */
  35
  36
  37 /*
  38  *              Am7990 Local Area Network Controller for Ethernet (LANCE)
  39  */
  40
  41 struct lance_regs {
  42         unsigned short rdp;             /* Register Data Port */
  43         unsigned short rap;             /* Register Address Port */
  44 };
  45
  46
  47 #define CRC_POLYNOMIAL_BE 0x04c11db7UL  /* Ethernet CRC, big endian */
  48 #define CRC_POLYNOMIAL_LE 0xedb88320UL  /* Ethernet CRC, little endian */
  49
  50 /*
  51  *              Am7990 Control and Status Registers
  52  */
  53
  54 #define LE_CSR0         0x0000          /* LANCE Controller Status */
  55 #define LE_CSR1         0x0001          /* IADR[15:0] */
  56 #define LE_CSR2         0x0002          /* IADR[23:16] */
  57 #define LE_CSR3         0x0003          /* Misc */
  58
  59
  60 /*
  61  *              Bit definitions for CSR0 (LANCE Controller Status)
  62  */
  63
  64 #define LE_C0_ERR       0x8000          /* Error */
  65 #define LE_C0_BABL      0x4000          /* Babble: Transmitted too many bits */
  66 #define LE_C0_CERR      0x2000          /* No Heartbeat (10BASE-T) */
  67 #define LE_C0_MISS      0x1000          /* Missed Frame */
  68 #define LE_C0_MERR      0x0800          /* Memory Error */
  69 #define LE_C0_RINT      0x0400          /* Receive Interrupt */
  70 #define LE_C0_TINT      0x0200          /* Transmit Interrupt */
  71 #define LE_C0_IDON      0x0100          /* Initialization Done */
  72 #define LE_C0_INTR      0x0080          /* Interrupt Flag */
  73 #define LE_C0_INEA      0x0040          /* Interrupt Enable */
  74 #define LE_C0_RXON      0x0020          /* Receive On */
  75 #define LE_C0_TXON      0x0010          /* Transmit On */
  76 #define LE_C0_TDMD      0x0008          /* Transmit Demand */
  77 #define LE_C0_STOP      0x0004          /* Stop */
  78 #define LE_C0_STRT      0x0002          /* Start */
  79 #define LE_C0_INIT      0x0001          /* Initialize */
  80
  81
  82 /*
  83  *              Bit definitions for CSR3
  84  */
  85
  86 #define LE_C3_BSWP      0x0004          /* Byte Swap
  87                                            (on for big endian byte order) */
  88 #define LE_C3_ACON      0x0002          /* ALE Control
  89                                            (on for active low ALE) */
  90 #define LE_C3_BCON      0x0001          /* Byte Control */
  91
  92
  93 /*
  94  *              Mode Flags
  95  */
  96
  97 #define LE_MO_PROM      0x8000          /* Promiscuous Mode */
  98 #define LE_MO_INTL      0x0040          /* Internal Loopback */
  99 #define LE_MO_DRTY      0x0020          /* Disable Retry */
 100 #define LE_MO_FCOLL     0x0010          /* Force Collision */
 101 #define LE_MO_DXMTFCS   0x0008          /* Disable Transmit CRC */
 102 #define LE_MO_LOOP      0x0004          /* Loopback Enable */
 103 #define LE_MO_DTX       0x0002          /* Disable Transmitter */
 104 #define LE_MO_DRX       0x0001          /* Disable Receiver */
 105
 106
 107 struct lance_rx_desc {
 108         unsigned short rmd0;        /* low address of packet */
 109         unsigned char  rmd1_bits;   /* descriptor bits */
 110         unsigned char  rmd1_hadr;   /* high address of packet */
 111         short    length;            /* This length is 2s complement (negative)!
 112                                      * Buffer length
 113                                      */
 114         unsigned short mblength;    /* Aactual number of bytes received */
 115 };
 116
 117 struct lance_tx_desc {
 118         unsigned short tmd0;        /* low address of packet */
 119         unsigned char  tmd1_bits;   /* descriptor bits */
 120         unsigned char  tmd1_hadr;   /* high address of packet */
 121         short    length;            /* Length is 2s complement (negative)! */
 122         unsigned short misc;
 123 };
 124
 125
 126 /*
 127  *              Receive Flags
 128  */
 129
 130 #define LE_R1_OWN       0x80            /* LANCE owns the descriptor */
 131 #define LE_R1_ERR       0x40            /* Error */
 132 #define LE_R1_FRA       0x20            /* Framing Error */
 133 #define LE_R1_OFL       0x10            /* Overflow Error */
 134 #define LE_R1_CRC       0x08            /* CRC Error */
 135 #define LE_R1_BUF       0x04            /* Buffer Error */
 136 #define LE_R1_SOP       0x02            /* Start of Packet */
 137 #define LE_R1_EOP       0x01            /* End of Packet */
 138 #define LE_R1_POK       0x03            /* Packet is complete: SOP + EOP */
 139
 140
 141 /*
 142  *              Transmit Flags
 143  */
 144
 145 #define LE_T1_OWN       0x80            /* LANCE owns the descriptor */
 146 #define LE_T1_ERR       0x40            /* Error */
 147 #define LE_T1_RES       0x20            /* Reserved,
 148                                            LANCE writes this with a zero */
 149 #define LE_T1_EMORE     0x10            /* More than one retry needed */
 150 #define LE_T1_EONE      0x08            /* One retry needed */
 151 #define LE_T1_EDEF      0x04            /* Deferred */
 152 #define LE_T1_SOP       0x02            /* Start of Packet */
 153 #define LE_T1_EOP       0x01            /* End of Packet */
 154 #define LE_T1_POK       0x03            /* Packet is complete: SOP + EOP */
 155
 156
 157 /*
 158  *              Error Flags
 159  */
 160
 161 #define LE_T3_BUF       0x8000          /* Buffer Error */
 162 #define LE_T3_UFL       0x4000          /* Underflow Error */
 163 #define LE_T3_LCOL      0x1000          /* Late Collision */
 164 #define LE_T3_CLOS      0x0800          /* Loss of Carrier */
 165 #define LE_T3_RTY       0x0400          /* Retry Error */
 166 #define LE_T3_TDR       0x03ff          /* Time Domain Reflectometry */
 167
 168
 169 /*
 170  *              A2065 Expansion Board Structure
 171  */
 172
 173 struct A2065Board {
 174         u_char Pad1[0x4000];
 175         volatile struct lance_regs Lance;
 176         u_char Pad2[0x3ffc];
 177         volatile u_char RAM[0x8000];
 178 };