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1 /* $Id: amd7930.c,v 1.2 1998/02/12 23:07:10 keil Exp $
3 * HiSax ISDN driver - chip specific routines for AMD 7930
5 * Author Brent Baccala (baccala@FreeSoft.org)
9 * $Log: amd7930.c,v $
10 * Revision 1.2 1998/02/12 23:07:10 keil
11 * change for 2.1.86 (removing FREE_READ/FREE_WRITE from [dev]_kfree_skb()
13 * Revision 1.1 1998/02/03 23:20:51 keil
14 * New files for SPARC isdn support
16 * Revision 1.1 1998/01/08 04:17:12 baccala
17 * ISDN comes to the Sparc. Key points:
19 * - Existing ISDN HiSax driver provides all the smarts
20 * - it compiles, runs, talks to an isolated phone switch, connects
21 * to a Cisco, pings go through
22 * - AMD 7930 support only (no DBRI yet)
23 * - no US NI-1 support (may not work on US phone system - untested)
24 * - periodic packet loss, apparently due to lost interrupts
25 * - ISDN sometimes freezes, requiring reboot before it will work again
27 * The code is unreliable enough to be consider alpha
30 * Advanced Micro Devices' Am79C30A is an ISDN/audio chip used in the
31 * SparcStation 1+. The chip provides microphone and speaker interfaces
32 * which provide mono-channel audio at 8K samples per second via either
33 * 8-bit A-law or 8-bit mu-law encoding. Also, the chip features an
34 * ISDN BRI Line Interface Unit (LIU), I.430 S/T physical interface,
35 * which performs basic D channel LAPD processing and provides raw
36 * B channel data. The digital audio channel, the two ISDN B channels,
37 * and two 64 Kbps channels to the microprocessor are all interconnected
38 * via a multiplexer.
40 * This driver interfaces to the Linux HiSax ISDN driver, which performs
41 * all high-level Q.921 and Q.931 ISDN functions. The file is not
42 * itself a hardware driver; rather it uses functions exported by
43 * the AMD7930 driver in the sparcaudio subsystem (drivers/sbus/audio),
44 * allowing the chip to be simultaneously used for both audio and ISDN data.
45 * The hardware driver does _no_ buffering, but provides several callbacks
46 * which are called during interrupt service and should therefore run quickly.
48 * D channel transmission is performed by passing the hardware driver the
49 * address and size of an skb's data area, then waiting for a callback
50 * to signal successful transmission of the packet. A task is then
51 * queued to notify the HiSax driver that another packet may be transmitted.
53 * D channel reception is quite simple, mainly because of:
54 * 1) the slow speed of the D channel - 16 kbps, and
55 * 2) the presence of an 8- or 32-byte (depending on chip version) FIFO
56 * to buffer the D channel data on the chip
57 * Worst case scenario of back-to-back packets with the 8 byte buffer
58 * at 16 kbps yields an service time of 4 ms - long enough to preclude
59 * the need for fancy buffering. We queue a background task that copies
60 * data out of the receive buffer into an skb, and the hardware driver
61 * simply does nothing until we're done with the receive buffer and
62 * reset it for a new packet.
64 * B channel processing is more complex, because of:
65 * 1) the faster speed - 64 kbps,
66 * 2) the lack of any on-chip buffering (it interrupts for every byte), and
67 * 3) the lack of any chip support for HDLC encapsulation
69 * The HiSax driver can put each B channel into one of three modes -
70 * L1_MODE_NULL (channel disabled), L1_MODE_TRANS (transparent data relay),
71 * and L1_MODE_HDLC (HDLC encapsulation by low-level driver).
72 * L1_MODE_HDLC is the most common, used for almost all "pure" digital
73 * data sessions. L1_MODE_TRANS is used for ISDN audio.
75 * HDLC B channel transmission is performed via a large buffer into
76 * which the skb is copied while performing HDLC bit-stuffing. A CRC
77 * is computed and attached to the end of the buffer, which is then
78 * passed to the low-level routines for raw transmission. Once
79 * transmission is complete, the hardware driver is set to enter HDLC
80 * idle by successive transmission of mark (all 1) bytes, waiting for
81 * the ISDN driver to prepare another packet for transmission and
82 * deliver it.
84 * HDLC B channel reception is performed via an X-byte ring buffer
85 * divided into N sections of X/N bytes each. Defaults: X=256 bytes, N=4.
86 * As the hardware driver notifies us that each section is full, we
87 * hand it the next section and schedule a background task to peruse
88 * the received section, bit-by-bit, with an HDLC decoder. As
89 * packets are detected, they are copied into a large buffer while
90 * decoding HDLC bit-stuffing. The ending CRC is verified, and if
91 * it is correct, we alloc a new skb of the correct length (which we
92 * now know), copy the packet into it, and hand it to the upper layers.
93 * Optimization: for large packets, we hand the buffer (which also
94 * happens to be an skb) directly to the upper layer after an skb_trim,
95 * and alloc a new large buffer for future packets, thus avoiding a copy.
96 * Then we return to HDLC processing; state is saved between calls.
100 #define __NO_VERSION__
101 #include "hisax.h"
102 #include "../../sbus/audio/amd7930.h"
103 #include "isac.h"
104 #include "isdnl1.h"
105 #include "rawhdlc.h"
106 #include <linux/interrupt.h>
108 static const char *amd7930_revision = "$Revision: 1.2 $";
110 #define RCV_BUFSIZE 1024 /* Size of raw receive buffer in bytes */
111 #define RCV_BUFBLKS 4 /* Number of blocks to divide buffer into
112 * (must divide RCV_BUFSIZE) */
114 static void Bchan_fill_fifo(struct BCState *, struct sk_buff *);
116 static void
117 Bchan_xmt_bh(struct BCState *bcs)
119 struct sk_buff *skb;
121 if (bcs->hw.amd7930.tx_skb != NULL) {
122 dev_kfree_skb(bcs->hw.amd7930.tx_skb);
123 bcs->hw.amd7930.tx_skb = NULL;
126 if ((skb = skb_dequeue(&bcs->squeue))) {
127 Bchan_fill_fifo(bcs, skb);
128 } else {
129 clear_bit(BC_FLG_BUSY, &bcs->Flag);
130 bcs->event |= 1 << B_XMTBUFREADY;
131 queue_task(&bcs->tqueue, &tq_immediate);
132 mark_bh(IMMEDIATE_BH);
136 static void
137 Bchan_xmit_callback(struct BCState *bcs)
139 queue_task(&bcs->hw.amd7930.tq_xmt, &tq_immediate);
140 mark_bh(IMMEDIATE_BH);
143 /* B channel transmission: two modes (three, if you count L1_MODE_NULL)
145 * L1_MODE_HDLC - We need to do HDLC encapsulation before transmiting
146 * the packet (i.e. make_raw_hdlc_data). Since this can be a
147 * time-consuming operation, our completion callback just schedules
148 * a bottom half to do encapsulation for the next packet. In between,
149 * the link will just idle
151 * L1_MODE_TRANS - Data goes through, well, transparent. No HDLC encap,
152 * and we can't just let the link idle, so the "bottom half" actually
153 * gets called during the top half (it's our callback routine in this case),
154 * but it's a lot faster now since we don't call make_raw_hdlc_data
157 static void
158 Bchan_fill_fifo(struct BCState *bcs, struct sk_buff *skb)
160 struct IsdnCardState *cs = bcs->cs;
161 int len;
163 if ((cs->debug & L1_DEB_HSCX) || (cs->debug & L1_DEB_HSCX_FIFO)) {
164 char tmp[1024];
165 char *t = tmp;
167 t += sprintf(t, "amd7930_fill_fifo %c cnt %d",
168 bcs->channel ? 'B' : 'A', skb->len);
169 if (cs->debug & L1_DEB_HSCX_FIFO)
170 QuickHex(t, skb->data, skb->len);
171 debugl1(cs, tmp);
174 if (bcs->mode == L1_MODE_HDLC) {
175 len = make_raw_hdlc_data(skb->data, skb->len,
176 bcs->hw.amd7930.tx_buff, RAW_BUFMAX);
177 if (len > 0)
178 amd7930_bxmit(0, bcs->channel,
179 bcs->hw.amd7930.tx_buff, len,
180 (void *) &Bchan_xmit_callback,
181 (void *) bcs);
182 dev_kfree_skb(skb);
183 } else if (bcs->mode == L1_MODE_TRANS) {
184 amd7930_bxmit(0, bcs->channel,
185 bcs->hw.amd7930.tx_buff, skb->len,
186 (void *) &Bchan_xmt_bh,
187 (void *) bcs);
188 bcs->hw.amd7930.tx_skb = skb;
189 } else {
190 dev_kfree_skb(skb);
194 static void
195 Bchan_mode(struct BCState *bcs, int mode, int bc)
197 struct IsdnCardState *cs = bcs->cs;
199 if (cs->debug & L1_DEB_HSCX) {
200 char tmp[40];
201 sprintf(tmp, "AMD 7930 mode %d bchan %d/%d",
202 mode, bc, bcs->channel);
203 debugl1(cs, tmp);
205 bcs->mode = mode;
208 /* Bchan_l2l1 is the entry point for upper layer routines that want to
209 * transmit on the B channel. PH_DATA_REQ is a normal packet that
210 * we either start transmitting (if idle) or queue (if busy).
211 * PH_PULL_REQ can be called to request a callback message (PH_PULL_CNF)
212 * once the link is idle. After a "pull" callback, the upper layer
213 * routines can use PH_PULL_IND to send data.
216 static void
217 Bchan_l2l1(struct PStack *st, int pr, void *arg)
219 struct sk_buff *skb = arg;
221 switch (pr) {
222 case (PH_DATA_REQ):
223 if (test_bit(BC_FLG_BUSY, &st->l1.bcs->Flag)) {
224 skb_queue_tail(&st->l1.bcs->squeue, skb);
225 } else {
226 test_and_set_bit(BC_FLG_BUSY, &st->l1.bcs->Flag);
227 Bchan_fill_fifo(st->l1.bcs, skb);
229 break;
230 case (PH_PULL_IND):
231 if (test_bit(BC_FLG_BUSY, &st->l1.bcs->Flag)) {
232 printk(KERN_WARNING "amd7930: this shouldn't happen\n");
233 break;
235 test_and_set_bit(BC_FLG_BUSY, &st->l1.bcs->Flag);
236 Bchan_fill_fifo(st->l1.bcs, skb);
237 break;
238 case (PH_PULL_REQ):
239 if (!test_bit(BC_FLG_BUSY, &st->l1.bcs->Flag)) {
240 clear_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
241 st->l1.l1l2(st, PH_PULL_CNF, NULL);
242 } else
243 set_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
244 break;
248 /* Receiver callback and bottom half - decodes HDLC at leisure (if
249 * L1_MODE_HDLC) and passes newly received skb on via bcs->rqueue. If
250 * a large packet is received, stick rv_skb (the buffer that the
251 * packet has been decoded into) on the receive queue and alloc a new
252 * (large) skb to act as buffer for future receives. If a small
253 * packet is received, leave rv_skb alone, alloc a new skb of the
254 * correct size, and copy the packet into it
257 static void
258 Bchan_recv_callback(struct BCState *bcs)
260 struct amd7930_hw *hw = &bcs->hw.amd7930;
262 hw->rv_buff_in += RCV_BUFSIZE/RCV_BUFBLKS;
263 hw->rv_buff_in %= RCV_BUFSIZE;
265 if (hw->rv_buff_in != hw->rv_buff_out) {
266 amd7930_brecv(0, bcs->channel,
267 hw->rv_buff + hw->rv_buff_in,
268 RCV_BUFSIZE/RCV_BUFBLKS,
269 (void *) &Bchan_recv_callback, (void *) bcs);
272 queue_task(&hw->tq_rcv, &tq_immediate);
273 mark_bh(IMMEDIATE_BH);
276 static void
277 Bchan_rcv_bh(struct BCState *bcs)
279 struct IsdnCardState *cs = bcs->cs;
280 struct amd7930_hw *hw = &bcs->hw.amd7930;
281 struct sk_buff *skb;
282 int len;
284 if (cs->debug & L1_DEB_HSCX) {
285 char tmp[1024];
287 sprintf(tmp, "amd7930_Bchan_rcv (%d/%d)",
288 hw->rv_buff_in, hw->rv_buff_out);
289 debugl1(cs, tmp);
290 QuickHex(tmp, hw->rv_buff + hw->rv_buff_out,
291 RCV_BUFSIZE/RCV_BUFBLKS);
292 debugl1(cs, tmp);
295 do {
296 if (bcs->mode == L1_MODE_HDLC) {
297 while ((len = read_raw_hdlc_data(hw->hdlc_state,
298 hw->rv_buff + hw->rv_buff_out, RCV_BUFSIZE/RCV_BUFBLKS,
299 hw->rv_skb->tail, HSCX_BUFMAX))) {
300 if (len > 0 && (cs->debug & L1_DEB_HSCX_FIFO)) {
301 char tmp[1024];
302 char *t = tmp;
304 t += sprintf(t, "amd7930_Bchan_rcv %c cnt %d", bcs->channel ? 'B' : 'A', len);
305 QuickHex(t, hw->rv_skb->tail, len);
306 debugl1(cs, tmp);
309 if (len > HSCX_BUFMAX/2) {
310 /* Large packet received */
312 if (!(skb = dev_alloc_skb(HSCX_BUFMAX))) {
313 printk(KERN_WARNING "amd7930: receive out of memory");
314 } else {
315 skb_put(hw->rv_skb, len);
316 skb_queue_tail(&bcs->rqueue, hw->rv_skb);
317 hw->rv_skb = skb;
318 bcs->event |= 1 << B_RCVBUFREADY;
319 queue_task(&bcs->tqueue, &tq_immediate);
321 } else if (len > 0) {
322 /* Small packet received */
324 if (!(skb = dev_alloc_skb(len))) {
325 printk(KERN_WARNING "amd7930: receive out of memory\n");
326 } else {
327 memcpy(skb_put(skb, len), hw->rv_skb->tail, len);
328 skb_queue_tail(&bcs->rqueue, skb);
329 bcs->event |= 1 << B_RCVBUFREADY;
330 queue_task(&bcs->tqueue, &tq_immediate);
331 mark_bh(IMMEDIATE_BH);
333 } else {
334 /* Reception Error */
335 /* printk("amd7930: B channel receive error\n"); */
338 } else if (bcs->mode == L1_MODE_TRANS) {
339 if (!(skb = dev_alloc_skb(RCV_BUFSIZE/RCV_BUFBLKS))) {
340 printk(KERN_WARNING "amd7930: receive out of memory\n");
341 } else {
342 memcpy(skb_put(skb, RCV_BUFSIZE/RCV_BUFBLKS),
343 hw->rv_buff + hw->rv_buff_out,
344 RCV_BUFSIZE/RCV_BUFBLKS);
345 skb_queue_tail(&bcs->rqueue, skb);
346 bcs->event |= 1 << B_RCVBUFREADY;
347 queue_task(&bcs->tqueue, &tq_immediate);
348 mark_bh(IMMEDIATE_BH);
352 if (hw->rv_buff_in == hw->rv_buff_out) {
353 /* Buffer was filled up - need to restart receiver */
354 amd7930_brecv(0, bcs->channel,
355 hw->rv_buff + hw->rv_buff_in,
356 RCV_BUFSIZE/RCV_BUFBLKS,
357 (void *) &Bchan_recv_callback,
358 (void *) bcs);
361 hw->rv_buff_out += RCV_BUFSIZE/RCV_BUFBLKS;
362 hw->rv_buff_out %= RCV_BUFSIZE;
364 } while (hw->rv_buff_in != hw->rv_buff_out);
367 static void
368 Bchan_close(struct BCState *bcs)
370 struct sk_buff *skb;
372 Bchan_mode(bcs, 0, 0);
373 amd7930_bclose(0, bcs->channel);
375 if (test_bit(BC_FLG_INIT, &bcs->Flag)) {
376 while ((skb = skb_dequeue(&bcs->rqueue))) {
377 dev_kfree_skb(skb);
379 while ((skb = skb_dequeue(&bcs->squeue))) {
380 dev_kfree_skb(skb);
383 test_and_clear_bit(BC_FLG_INIT, &bcs->Flag);
386 static int
387 Bchan_open(struct BCState *bcs)
389 struct amd7930_hw *hw = &bcs->hw.amd7930;
391 if (!test_and_set_bit(BC_FLG_INIT, &bcs->Flag)) {
392 skb_queue_head_init(&bcs->rqueue);
393 skb_queue_head_init(&bcs->squeue);
395 test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
397 amd7930_bopen(0, bcs->channel, 0xff);
398 hw->rv_buff_in = 0;
399 hw->rv_buff_out = 0;
400 hw->tx_skb = NULL;
401 init_hdlc_state(hw->hdlc_state, 0);
402 amd7930_brecv(0, bcs->channel,
403 hw->rv_buff + hw->rv_buff_in, RCV_BUFSIZE/RCV_BUFBLKS,
404 (void *) &Bchan_recv_callback, (void *) bcs);
406 bcs->event = 0;
407 bcs->tx_cnt = 0;
408 return (0);
411 static void
412 Bchan_init(struct BCState *bcs)
414 if (!(bcs->hw.amd7930.tx_buff = kmalloc(RAW_BUFMAX, GFP_ATOMIC))) {
415 printk(KERN_WARNING
416 "HiSax: No memory for amd7930.tx_buff\n");
417 return;
419 if (!(bcs->hw.amd7930.rv_buff = kmalloc(RCV_BUFSIZE, GFP_ATOMIC))) {
420 printk(KERN_WARNING
421 "HiSax: No memory for amd7930.rv_buff\n");
422 return;
424 if (!(bcs->hw.amd7930.rv_skb = dev_alloc_skb(HSCX_BUFMAX))) {
425 printk(KERN_WARNING
426 "HiSax: No memory for amd7930.rv_skb\n");
427 return;
429 if (!(bcs->hw.amd7930.hdlc_state = kmalloc(sizeof(struct hdlc_state),
430 GFP_ATOMIC))) {
431 printk(KERN_WARNING
432 "HiSax: No memory for amd7930.hdlc_state\n");
433 return;
436 bcs->hw.amd7930.tq_rcv.sync = 0;
437 bcs->hw.amd7930.tq_rcv.routine = (void (*)(void *)) &Bchan_rcv_bh;
438 bcs->hw.amd7930.tq_rcv.data = (void *) bcs;
440 bcs->hw.amd7930.tq_xmt.sync = 0;
441 bcs->hw.amd7930.tq_xmt.routine = (void (*)(void *)) &Bchan_xmt_bh;
442 bcs->hw.amd7930.tq_xmt.data = (void *) bcs;
445 static void
446 Bchan_manl1(struct PStack *st, int pr,
447 void *arg)
449 switch (pr) {
450 case (PH_ACTIVATE_REQ):
451 test_and_set_bit(BC_FLG_ACTIV, &st->l1.bcs->Flag);
452 Bchan_mode(st->l1.bcs, st->l1.mode, st->l1.bc);
453 st->l1.l1man(st, PH_ACTIVATE_CNF, NULL);
454 break;
455 case (PH_DEACTIVATE_REQ):
456 if (!test_bit(BC_FLG_BUSY, &st->l1.bcs->Flag))
457 Bchan_mode(st->l1.bcs, 0, 0);
458 test_and_clear_bit(BC_FLG_ACTIV, &st->l1.bcs->Flag);
459 break;
464 setstack_amd7930(struct PStack *st, struct BCState *bcs)
466 if (Bchan_open(bcs))
467 return (-1);
468 st->l1.bcs = bcs;
469 st->l2.l2l1 = Bchan_l2l1;
470 st->ma.manl1 = Bchan_manl1;
471 setstack_manager(st);
472 bcs->st = st;
473 return (0);
477 static void
478 amd7930_drecv_callback(void *arg, int error, unsigned int count)
480 struct IsdnCardState *cs = (struct IsdnCardState *) arg;
481 static struct tq_struct task;
482 struct sk_buff *skb;
484 /* NOTE: This function is called directly from an interrupt handler */
486 if (1) {
487 if (!(skb = alloc_skb(count, GFP_ATOMIC)))
488 printk(KERN_WARNING "HiSax: D receive out of memory\n");
489 else {
490 memcpy(skb_put(skb, count), cs->rcvbuf, count);
491 skb_queue_tail(&cs->rq, skb);
494 task.routine = (void *) DChannel_proc_rcv;
495 task.data = (void *) cs;
496 queue_task(&task, &tq_immediate);
497 mark_bh(IMMEDIATE_BH);
500 if (cs->debug & L1_DEB_ISAC_FIFO) {
501 char tmp[128];
502 char *t = tmp;
504 t += sprintf(t, "amd7930 Drecv cnt %d", count);
505 if (error) t += sprintf(t, " ERR %x", error);
506 QuickHex(t, cs->rcvbuf, count);
507 debugl1(cs, tmp);
510 amd7930_drecv(0, cs->rcvbuf, MAX_DFRAME_LEN,
511 &amd7930_drecv_callback, cs);
514 static void
515 amd7930_dxmit_callback(void *arg, int error)
517 struct IsdnCardState *cs = (struct IsdnCardState *) arg;
518 static struct tq_struct task;
520 /* NOTE: This function is called directly from an interrupt handler */
522 /* may wish to do retransmission here, if error indicates collision */
524 if (cs->debug & L1_DEB_ISAC_FIFO) {
525 char tmp[128];
526 char *t = tmp;
528 t += sprintf(t, "amd7930 Dxmit cnt %d", cs->tx_skb->len);
529 if (error) t += sprintf(t, " ERR %x", error);
530 QuickHex(t, cs->tx_skb->data, cs->tx_skb->len);
531 debugl1(cs, tmp);
534 cs->tx_skb = NULL;
536 task.routine = (void *) DChannel_proc_xmt;
537 task.data = (void *) cs;
538 queue_task(&task, &tq_immediate);
539 mark_bh(IMMEDIATE_BH);
542 static void
543 amd7930_Dchan_l2l1(struct PStack *st, int pr, void *arg)
545 struct IsdnCardState *cs = (struct IsdnCardState *) st->l1.hardware;
546 struct sk_buff *skb = arg;
547 char str[64];
549 switch (pr) {
550 case (PH_DATA_REQ):
551 if (cs->tx_skb) {
552 skb_queue_tail(&cs->sq, skb);
553 #ifdef L2FRAME_DEBUG /* psa */
554 if (cs->debug & L1_DEB_LAPD)
555 Logl2Frame(cs, skb, "PH_DATA Queued", 0);
556 #endif
557 } else {
558 if ((cs->dlogflag) && (!(skb->data[2] & 1))) {
559 /* I-FRAME */
560 LogFrame(cs, skb->data, skb->len);
561 sprintf(str, "Q.931 frame user->network tei %d", st->l2.tei);
562 dlogframe(cs, skb->data+4, skb->len-4,
563 str);
565 cs->tx_skb = skb;
566 cs->tx_cnt = 0;
567 #ifdef L2FRAME_DEBUG /* psa */
568 if (cs->debug & L1_DEB_LAPD)
569 Logl2Frame(cs, skb, "PH_DATA", 0);
570 #endif
571 amd7930_dxmit(0, skb->data, skb->len,
572 &amd7930_dxmit_callback, cs);
574 break;
575 case (PH_PULL_IND):
576 if (cs->tx_skb) {
577 if (cs->debug & L1_DEB_WARN)
578 debugl1(cs, " l2l1 tx_skb exist this shouldn't happen");
579 skb_queue_tail(&cs->sq, skb);
580 break;
582 if ((cs->dlogflag) && (!(skb->data[2] & 1))) { /* I-FRAME */
583 LogFrame(cs, skb->data, skb->len);
584 sprintf(str, "Q.931 frame user->network tei %d", st->l2.tei);
585 dlogframe(cs, skb->data + 4, skb->len - 4,
586 str);
588 cs->tx_skb = skb;
589 cs->tx_cnt = 0;
590 #ifdef L2FRAME_DEBUG /* psa */
591 if (cs->debug & L1_DEB_LAPD)
592 Logl2Frame(cs, skb, "PH_DATA_PULLED", 0);
593 #endif
594 amd7930_dxmit(0, cs->tx_skb->data, cs->tx_skb->len,
595 &amd7930_dxmit_callback, cs);
596 break;
597 case (PH_PULL_REQ):
598 #ifdef L2FRAME_DEBUG /* psa */
599 if (cs->debug & L1_DEB_LAPD)
600 debugl1(cs, "-> PH_REQUEST_PULL");
601 #endif
602 if (!cs->tx_skb) {
603 test_and_clear_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
604 st->l1.l1l2(st, PH_PULL_CNF, NULL);
605 } else
606 test_and_set_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
607 break;
612 setDstack_amd7930(struct PStack *st, struct IsdnCardState *cs)
614 st->l2.l2l1 = amd7930_Dchan_l2l1;
615 if (! cs->rcvbuf) {
616 printk("setDstack_amd7930: No cs->rcvbuf!\n");
617 } else {
618 amd7930_drecv(0, cs->rcvbuf, MAX_DFRAME_LEN,
619 &amd7930_drecv_callback, cs);
621 return (0);
624 static void
625 manl1_msg(struct IsdnCardState *cs, int msg, void *arg) {
626 struct PStack *st;
628 st = cs->stlist;
629 while (st) {
630 st->ma.manl1(st, msg, arg);
631 st = st->next;
635 static void
636 amd7930_new_ph(struct IsdnCardState *cs)
638 switch (amd7930_get_liu_state(0)) {
639 case 3:
640 manl1_msg(cs, PH_POWERUP_CNF, NULL);
641 break;
643 case 7:
644 manl1_msg(cs, PH_I4_P8_IND, NULL);
645 break;
647 case 8:
648 manl1_msg(cs, PH_RSYNC_IND, NULL);
649 break;
653 /* amd7930 LIU state change callback */
655 static void
656 amd7930_liu_callback(struct IsdnCardState *cs)
658 static struct tq_struct task;
660 if (!cs)
661 return;
663 if (cs->debug & L1_DEB_ISAC) {
664 char tmp[32];
665 sprintf(tmp, "amd7930_liu state %d", amd7930_get_liu_state(0));
666 debugl1(cs, tmp);
669 task.sync = 0;
670 task.routine = (void *) &amd7930_new_ph;
671 task.data = (void *) cs;
672 queue_task(&task, &tq_immediate);
673 mark_bh(IMMEDIATE_BH);
676 void
677 amd7930_l1cmd(struct IsdnCardState *cs, int msg, void *arg)
679 u_char val;
680 char tmp[32];
682 if (cs->debug & L1_DEB_ISAC) {
683 char tmp[32];
684 sprintf(tmp, "amd7930_l1cmd msg %x", msg);
685 debugl1(cs, tmp);
688 switch(msg) {
689 case PH_RESET_REQ:
690 if (amd7930_get_liu_state(0) <= 3)
691 amd7930_liu_activate(0,0);
692 else
693 amd7930_liu_deactivate(0);
694 break;
695 case PH_ENABLE_REQ:
696 break;
697 case PH_INFO3_REQ:
698 amd7930_liu_activate(0,0);
699 break;
700 case PH_TESTLOOP_REQ:
701 break;
702 default:
703 if (cs->debug & L1_DEB_WARN) {
704 sprintf(tmp, "amd7930_l1cmd unknown %4x", msg);
705 debugl1(cs, tmp);
707 break;
711 static void init_amd7930(struct IsdnCardState *cs)
713 Bchan_init(&cs->bcs[0]);
714 Bchan_init(&cs->bcs[1]);
715 cs->bcs[0].BC_SetStack = setstack_amd7930;
716 cs->bcs[1].BC_SetStack = setstack_amd7930;
717 cs->bcs[0].BC_Close = Bchan_close;
718 cs->bcs[1].BC_Close = Bchan_close;
719 Bchan_mode(cs->bcs, 0, 0);
720 Bchan_mode(cs->bcs + 1, 0, 0);
723 void
724 release_amd7930(struct IsdnCardState *cs)
728 static int
729 amd7930_card_msg(struct IsdnCardState *cs, int mt, void *arg)
731 switch (mt) {
732 case CARD_RESET:
733 return(0);
734 case CARD_RELEASE:
735 release_amd7930(cs);
736 return(0);
737 case CARD_SETIRQ:
738 return(0);
739 case CARD_INIT:
740 cs->l1cmd = amd7930_l1cmd;
741 amd7930_liu_init(0, &amd7930_liu_callback, (void *)cs);
742 init_amd7930(cs);
743 return(0);
744 case CARD_TEST:
745 return(0);
747 return(0);
750 int __init
751 setup_amd7930(struct IsdnCard *card)
753 struct IsdnCardState *cs = card->cs;
754 char tmp[64];
756 strcpy(tmp, amd7930_revision);
757 printk(KERN_INFO "HiSax: AMD7930 driver Rev. %s\n", HiSax_getrev(tmp));
758 if (cs->typ != ISDN_CTYPE_AMD7930)
759 return (0);
761 cs->irq = amd7930_get_irqnum(0);
762 if (cs->irq == 0)
763 return (0);
765 cs->cardmsg = &amd7930_card_msg;
767 return (1);