drivers/net/tulip/tulip.h

   1 /*
   2         drivers/net/tulip/tulip.h
   3
   4         Copyright 2000  The Linux Kernel Team
   5         Written/copyright 1994-1999 by Donald Becker.
   6
   7         This software may be used and distributed according to the terms
   8         of the GNU Public License, incorporated herein by reference.
   9
  10 */
  11
  12 #ifndef __NET_TULIP_H__
  13 #define __NET_TULIP_H__
  14
  15 #include <linux/kernel.h>
  16 #include <linux/types.h>
  17 #include <linux/spinlock.h>
  18 #include <linux/netdevice.h>
  19 #include <linux/timer.h>
  20 #include <asm/io.h>
  21
  22
  23
  24 /* undefine, or define to various debugging levels (>4 == obscene levels) */
  25 #undef TULIP_DEBUG
  26
  27
  28 #ifdef TULIP_DEBUG
  29 /* note: prints function name for you */
  30 #define DPRINTK(fmt, args...) printk(KERN_DEBUG "%s: " fmt, __FUNCTION__ , ## args)
  31 #else
  32 #define DPRINTK(fmt, args...)
  33 #endif
  34
  35
  36
  37
  38 struct tulip_chip_table {
  39         char *chip_name;
  40         int io_size;
  41         int valid_intrs;        /* CSR7 interrupt enable settings */
  42         int flags;
  43         void (*media_timer) (unsigned long data);
  44 };
  45
  46
  47 enum tbl_flag {
  48         HAS_MII = 1,
  49         HAS_MEDIA_TABLE = 2,
  50         CSR12_IN_SROM = 4,
  51         ALWAYS_CHECK_MII = 8,
  52         HAS_ACPI = 0x10,
  53         MC_HASH_ONLY = 0x20,    /* Hash-only multicast filter. */
  54         HAS_PNICNWAY = 0x80,
  55         HAS_NWAY = 0x40,        /* Uses internal NWay xcvr. */
  56         HAS_INTR_MITIGATION = 0x100,
  57         IS_ASIX = 0x200,
  58         HAS_8023X = 0x400,
  59 };
  60
  61
  62 /* chip types.  careful!  order is VERY IMPORTANT here, as these
  63  * are used throughout the driver as indices into arrays */
  64 /* Note 21142 == 21143. */
  65 enum chips {
  66         DC21040 = 0,
  67         DC21041 = 1,
  68         DC21140 = 2,
  69         DC21142 = 3, DC21143 = 3,
  70         LC82C168,
  71         MX98713,
  72         MX98715,
  73         MX98725,
  74         AX88140,
  75         PNIC2,
  76         COMET,
  77         COMPEX9881,
  78         I21145,
  79 };
  80
  81
  82 enum MediaIs {
  83         MediaIsFD = 1,
  84         MediaAlwaysFD = 2,
  85         MediaIsMII = 4,
  86         MediaIsFx = 8,
  87         MediaIs100 = 16
  88 };
  89
  90
  91 /* Offsets to the Command and Status Registers, "CSRs".  All accesses
  92    must be longword instructions and quadword aligned. */
  93 enum tulip_offsets {
  94         CSR0 = 0,
  95         CSR1 = 0x08,
  96         CSR2 = 0x10,
  97         CSR3 = 0x18,
  98         CSR4 = 0x20,
  99         CSR5 = 0x28,
 100         CSR6 = 0x30,
 101         CSR7 = 0x38,
 102         CSR8 = 0x40,
 103         CSR9 = 0x48,
 104         CSR10 = 0x50,
 105         CSR11 = 0x58,
 106         CSR12 = 0x60,
 107         CSR13 = 0x68,
 108         CSR14 = 0x70,
 109         CSR15 = 0x78
 110 };
 111
 112
 113 /* The bits in the CSR5 status registers, mostly interrupt sources. */
 114 enum status_bits {
 115         TimerInt = 0x800,
 116         SytemError = 0x2000,
 117         TPLnkFail = 0x1000,
 118         TPLnkPass = 0x10,
 119         NormalIntr = 0x10000,
 120         AbnormalIntr = 0x8000,
 121         RxJabber = 0x200,
 122         RxDied = 0x100,
 123         RxNoBuf = 0x80,
 124         RxIntr = 0x40,
 125         TxFIFOUnderflow = 0x20,
 126         TxJabber = 0x08,
 127         TxNoBuf = 0x04,
 128         TxDied = 0x02,
 129         TxIntr = 0x01,
 130 };
 131
 132
 133 /* The Tulip Rx and Tx buffer descriptors. */
 134 struct tulip_rx_desc {
 135         s32 status;
 136         s32 length;
 137         u32 buffer1;
 138         u32 buffer2;
 139 };
 140
 141
 142 struct tulip_tx_desc {
 143         s32 status;
 144         s32 length;
 145         u32 buffer1;
 146         u32 buffer2;            /* We use only buffer 1.  */
 147 };
 148
 149
 150 enum desc_status_bits {
 151         DescOwned = 0x80000000,
 152         RxDescFatalErr = 0x8000,
 153         RxWholePkt = 0x0300,
 154 };
 155
 156
 157 enum t21041_csr13_bits {
 158         csr13_eng = (0xEF0<<4), /* for eng. purposes only, hardcode at EF0h */
 159         csr13_aui = (1<<3), /* clear to force 10bT, set to force AUI/BNC */
 160         csr13_cac = (1<<2), /* CSR13/14/15 autoconfiguration */
 161         csr13_srl = (1<<0), /* When reset, resets all SIA functions, machines */
 162
 163         csr13_mask_auibnc = (csr13_eng | csr13_aui | csr13_cac | csr13_srl),
 164         csr13_mask_10bt = (csr13_eng | csr13_cac | csr13_srl),
 165 };
 166
 167 enum t21143_csr6_bits {
 168         csr6_sc = (1<<31),
 169         csr6_ra = (1<<30),
 170         csr6_ign_dest_msb = (1<<26),
 171         csr6_mbo = (1<<25),
 172         csr6_scr = (1<<24),  /* scramble mode flag: can't be set */
 173         csr6_pcs = (1<<23),  /* Enables PCS functions (symbol mode requires csr6_ps be set) default is set */
 174         csr6_ttm = (1<<22),  /* Transmit Threshold Mode, set for 10baseT, 0 for 100BaseTX */
 175         csr6_sf = (1<<21),   /* Store and forward. If set ignores TR bits */
 176         csr6_hbd = (1<<19),  /* Heart beat disable. Disables SQE function in 10baseT */
 177         csr6_ps = (1<<18),   /* Port Select. 0 (defualt) = 10baseT, 1 = 100baseTX: can't be set */
 178         csr6_ca = (1<<17),   /* Collision Offset Enable. If set uses special algorithm in low collision situations */
 179         csr6_trh = (1<<15),  /* Transmit Threshold high bit */
 180         csr6_trl = (1<<14),  /* Transmit Threshold low bit */
 181
 182         /***************************************************************
 183          * This table shows transmit threshold values based on media   *
 184          * and these two registers (from PNIC1 & 2 docs) Note: this is *
 185          * all meaningless if sf is set.                               *
 186          ***************************************************************/
 187
 188         /***********************************
 189          * (trh,trl) * 100BaseTX * 10BaseT *
 190          ***********************************
 191          *   (0,0)   *     128   *    72   *
 192          *   (0,1)   *     256   *    96   *
 193          *   (1,0)   *     512   *   128   *
 194          *   (1,1)   *    1024   *   160   *
 195          ***********************************/
 196
 197         csr6_st = (1<<13),   /* Transmit conrol: 1 = transmit, 0 = stop */
 198         csr6_fc = (1<<12),   /* Forces a collision in next transmission (for testing in loopback mode) */
 199         csr6_om_int_loop = (1<<10), /* internal (FIFO) loopback flag */
 200         csr6_om_ext_loop = (1<<11), /* external (PMD) loopback flag */
 201         /* set both and you get (PHY) loopback */
 202         csr6_fd = (1<<9),    /* Full duplex mode, disables hearbeat, no loopback */
 203         csr6_pm = (1<<7),    /* Pass All Multicast */
 204         csr6_pr = (1<<6),    /* Promiscuous mode */
 205         csr6_sb = (1<<5),    /* Start(1)/Stop(0) backoff counter */
 206         csr6_if = (1<<4),    /* Inverse Filtering, rejects only addresses in address table: can't be set */
 207         csr6_pb = (1<<3),    /* Pass Bad Frames, (1) causes even bad frames to be passed on */
 208         csr6_ho = (1<<2),    /* Hash-only filtering mode: can't be set */
 209         csr6_sr = (1<<1),    /* Start(1)/Stop(0) Receive */
 210         csr6_hp = (1<<0),    /* Hash/Perfect Receive Filtering Mode: can't be set */
 211
 212         csr6_mask_capture = (csr6_sc | csr6_ca),
 213         csr6_mask_defstate = (csr6_mask_capture | csr6_mbo),
 214         csr6_mask_hdcap = (csr6_mask_defstate | csr6_hbd | csr6_ps),
 215         csr6_mask_hdcaptt = (csr6_mask_hdcap  | csr6_trh | csr6_trl),
 216         csr6_mask_fullcap = (csr6_mask_hdcaptt | csr6_fd),
 217         csr6_mask_fullpromisc = (csr6_pr | csr6_pm),
 218         csr6_mask_filters = (csr6_hp | csr6_ho | csr6_if),
 219         csr6_mask_100bt = (csr6_scr | csr6_pcs | csr6_hbd),
 220 };
 221
 222
 223 /* Keep the ring sizes a power of two for efficiency.
 224    Making the Tx ring too large decreases the effectiveness of channel
 225    bonding and packet priority.
 226    There are no ill effects from too-large receive rings. */
 227 #define TX_RING_SIZE    16
 228 #define RX_RING_SIZE    32
 229
 230
 231 #define PKT_BUF_SZ              1536    /* Size of each temporary Rx buffer. */
 232
 233
 234 /* Ring-wrap flag in length field, use for last ring entry.
 235         0x01000000 means chain on buffer2 address,
 236         0x02000000 means use the ring start address in CSR2/3.
 237    Note: Some work-alike chips do not function correctly in chained mode.
 238    The ASIX chip works only in chained mode.
 239    Thus we indicates ring mode, but always write the 'next' field for
 240    chained mode as well.
 241 */
 242 #define DESC_RING_WRAP 0x02000000
 243
 244
 245 /*  EEPROM_Ctrl bits. */
 246 #define EE_SHIFT_CLK    0x02    /* EEPROM shift clock. */
 247 #define EE_CS                   0x01    /* EEPROM chip select. */
 248 #define EE_DATA_WRITE   0x04    /* Data from the Tulip to EEPROM. */
 249 #define EE_WRITE_0              0x01
 250 #define EE_WRITE_1              0x05
 251 #define EE_DATA_READ    0x08    /* Data from the EEPROM chip. */
 252 #define EE_ENB                  (0x4800 | EE_CS)
 253
 254 /* Delay between EEPROM clock transitions.
 255    Even at 33Mhz current PCI implementations don't overrun the EEPROM clock.
 256    We add a bus turn-around to insure that this remains true. */
 257 #define eeprom_delay()  inl(ee_addr)
 258
 259 /* The EEPROM commands include the alway-set leading bit. */
 260 #define EE_READ_CMD             (6)
 261
 262 #define EEPROM_SIZE 128         /* 2 << EEPROM_ADDRLEN */
 263
 264
 265 /* The maximum data clock rate is 2.5 Mhz.  The minimum timing is usually
 266    met by back-to-back PCI I/O cycles, but we insert a delay to avoid
 267    "overclocking" issues or future 66Mhz PCI. */
 268 #define mdio_delay() inl(mdio_addr)
 269
 270 /* Read and write the MII registers using software-generated serial
 271    MDIO protocol.  It is just different enough from the EEPROM protocol
 272    to not share code.  The maxium data clock rate is 2.5 Mhz. */
 273 #define MDIO_SHIFT_CLK  0x10000
 274 #define MDIO_DATA_WRITE0 0x00000
 275 #define MDIO_DATA_WRITE1 0x20000
 276 #define MDIO_ENB                0x00000         /* Ignore the 0x02000 databook setting. */
 277 #define MDIO_ENB_IN             0x40000
 278 #define MDIO_DATA_READ  0x80000
 279
 280
 281 #define RUN_AT(x) (jiffies + (x))
 282
 283
 284 #if defined(__i386__)                   /* AKA get_unaligned() */
 285 #define get_u16(ptr) (*(u16 *)(ptr))
 286 #else
 287 #define get_u16(ptr) (((u8*)(ptr))[0] + (((u8*)(ptr))[1]<<8))
 288 #endif
 289
 290 struct medialeaf {
 291         u8 type;
 292         u8 media;
 293         unsigned char *leafdata;
 294 };
 295
 296
 297 struct mediatable {
 298         u16 defaultmedia;
 299         u8 leafcount;
 300         u8 csr12dir;            /* General purpose pin directions. */
 301         unsigned has_mii:1;
 302         unsigned has_nonmii:1;
 303         unsigned has_reset:6;
 304         u32 csr15dir;
 305         u32 csr15val;           /* 21143 NWay setting. */
 306         struct medialeaf mleaf[0];
 307 };
 308
 309
 310 struct mediainfo {
 311         struct mediainfo *next;
 312         int info_type;
 313         int index;
 314         unsigned char *info;
 315 };
 316
 317 struct ring_info {
 318         struct sk_buff  *skb;
 319         dma_addr_t      mapping;
 320 };
 321
 322
 323 struct tulip_private {
 324         const char *product_name;
 325         struct net_device *next_module;
 326         struct tulip_rx_desc *rx_ring;
 327         struct tulip_tx_desc *tx_ring;
 328         dma_addr_t rx_ring_dma;
 329         dma_addr_t tx_ring_dma;
 330         /* The saved address of a sent-in-place packet/buffer, for skfree(). */
 331         struct ring_info tx_buffers[TX_RING_SIZE];
 332         /* The addresses of receive-in-place skbuffs. */
 333         struct ring_info rx_buffers[RX_RING_SIZE];
 334         u16 setup_frame[96];    /* Pseudo-Tx frame to init address table. */
 335         int chip_id;
 336         int revision;
 337         int flags;
 338         struct net_device_stats stats;
 339         struct timer_list timer;        /* Media selection timer. */
 340         spinlock_t lock;
 341         unsigned int cur_rx, cur_tx;    /* The next free ring entry */
 342         unsigned int dirty_rx, dirty_tx;        /* The ring entries to be free()ed. */
 343         unsigned int full_duplex:1;     /* Full-duplex operation requested. */
 344         unsigned int full_duplex_lock:1;
 345         unsigned int fake_addr:1;       /* Multiport board faked address. */
 346         unsigned int default_port:4;    /* Last dev->if_port value. */
 347         unsigned int media2:4;  /* Secondary monitored media port. */
 348         unsigned int medialock:1;       /* Don't sense media type. */
 349         unsigned int mediasense:1;      /* Media sensing in progress. */
 350         unsigned int nway:1, nwayset:1;         /* 21143 internal NWay. */
 351         unsigned int csr0;      /* CSR0 setting. */
 352         unsigned int csr6;      /* Current CSR6 control settings. */
 353         unsigned char eeprom[EEPROM_SIZE];      /* Serial EEPROM contents. */
 354         void (*link_change) (struct net_device * dev, int csr5);
 355         u16 to_advertise;       /* NWay capabilities advertised.  */
 356         u16 lpar;               /* 21143 Link partner ability. */
 357         u16 advertising[4];
 358         signed char phys[4], mii_cnt;   /* MII device addresses. */
 359         struct mediatable *mtable;
 360         int cur_index;          /* Current media index. */
 361         int saved_if_port;
 362         struct pci_dev *pdev;
 363         int ttimer;
 364         int susp_rx;
 365         unsigned long nir;
 366         unsigned long base_addr;
 367         int pad0, pad1;         /* Used for 8-byte alignment */
 368 };
 369
 370
 371 struct eeprom_fixup {
 372         char *name;
 373         unsigned char addr0;
 374         unsigned char addr1;
 375         unsigned char addr2;
 376         u16 newtable[32];       /* Max length below. */
 377 };
 378
 379
 380 /* 21142.c */
 381 extern u16 t21142_csr14[];
 382 void t21142_timer(unsigned long data);
 383 void t21142_start_nway(struct net_device *dev);
 384 void t21142_lnk_change(struct net_device *dev, int csr5);
 385
 386 /* eeprom.c */
 387 void tulip_parse_eeprom(struct net_device *dev);
 388 int tulip_read_eeprom(long ioaddr, int location, int addr_len);
 389
 390 /* interrupt.c */
 391 extern unsigned int tulip_max_interrupt_work;
 392 extern int tulip_rx_copybreak;
 393 void tulip_interrupt(int irq, void *dev_instance, struct pt_regs *regs);
 394
 395 /* media.c */
 396 int tulip_mdio_read(struct net_device *dev, int phy_id, int location);
 397 void tulip_mdio_write(struct net_device *dev, int phy_id, int location, int value);
 398 void tulip_select_media(struct net_device *dev, int startup);
 399 int tulip_check_duplex(struct net_device *dev);
 400
 401 /* pnic.c */
 402 void pnic_do_nway(struct net_device *dev);
 403 void pnic_lnk_change(struct net_device *dev, int csr5);
 404 void pnic_timer(unsigned long data);
 405
 406 /* timer.c */
 407 void tulip_timer(unsigned long data);
 408 void mxic_timer(unsigned long data);
 409 void comet_timer(unsigned long data);
 410
 411 /* tulip_core.c */
 412 extern int tulip_debug;
 413 extern const char * const medianame[];
 414 extern const char tulip_media_cap[];
 415 extern struct tulip_chip_table tulip_tbl[];
 416 extern u8 t21040_csr13[];
 417 extern u16 t21041_csr13[];
 418 extern u16 t21041_csr14[];
 419 extern u16 t21041_csr15[];
 420
 421
 422 static inline void tulip_outl_csr (struct tulip_private *tp, u32 newValue, enum tulip_offsets offset)
 423 {
 424         outl (newValue, tp->base_addr + offset);
 425 }
 426
 427 static inline void tulip_stop_rxtx(struct tulip_private *tp, u32 csr6mask)
 428 {
 429         tulip_outl_csr(tp, csr6mask & ~(csr6_st | csr6_sr), CSR6);
 430 }
 431
 432 static inline void tulip_restart_rxtx(struct tulip_private *tp, u32 csr6mask)
 433 {
 434         tulip_outl_csr(tp, csr6mask | csr6_sr, CSR6);
 435         tulip_outl_csr(tp, csr6mask | csr6_st | csr6_sr, CSR6);
 436 }
 437
 438 #endif /* __NET_TULIP_H__ */