include/asm-m68k/pgtable.h

   1 #ifndef _M68K_PGTABLE_H
   2 #define _M68K_PGTABLE_H
   3
   4 #include <linux/config.h>
   5 #include <asm/setup.h>
   6
   7 #ifndef __ASSEMBLY__
   8 #include <asm/processor.h>
   9 #include <linux/threads.h>
  10
  11 /*
  12  * This file contains the functions and defines necessary to modify and use
  13  * the m68k page table tree.
  14  */
  15
  16 #include <asm/virtconvert.h>
  17
  18 /*
  19  * Cache handling functions
  20  */
  21
  22 #define flush_icache()                                  \
  23 do {                                                    \
  24         if (CPU_IS_040_OR_060)                          \
  25                 asm __volatile__ ("nop\n\t"             \
  26                                   ".chip 68040\n\t"     \
  27                                   "cinva %%ic\n\t"      \
  28                                   ".chip 68k" : );      \
  29         else {                                          \
  30                 unsigned long _tmp;                     \
  31                 asm __volatile__ ("movec %%cacr,%0\n\t" \
  32                      "orw %1,%0\n\t"                    \
  33                      "movec %0,%%cacr"                  \
  34                      : "=&d" (_tmp)                     \
  35                      : "id" (FLUSH_I));                 \
  36         }                                               \
  37 } while (0)
  38
  39 /*
  40  * invalidate the cache for the specified memory range.
  41  * It starts at the physical address specified for
  42  * the given number of bytes.
  43  */
  44 extern void cache_clear (unsigned long paddr, int len);
  45 /*
  46  * push any dirty cache in the specified memory range.
  47  * It starts at the physical address specified for
  48  * the given number of bytes.
  49  */
  50 extern void cache_push (unsigned long paddr, int len);
  51
  52 /*
  53  * push and invalidate pages in the specified user virtual
  54  * memory range.
  55  */
  56 extern void cache_push_v (unsigned long vaddr, int len);
  57
  58 /* cache code */
  59 #define FLUSH_I_AND_D   (0x00000808)
  60 #define FLUSH_I         (0x00000008)
  61
  62 /* This is needed whenever the virtual mapping of the current
  63    process changes.  */
  64 #define __flush_cache_all()                                             \
  65     do {                                                                \
  66         if (CPU_IS_040_OR_060)                                          \
  67                 __asm__ __volatile__ ("nop\n\t"                         \
  68                                       ".chip 68040\n\t"                 \
  69                                       "cpusha %dc\n\t"                  \
  70                                       ".chip 68k");                     \
  71         else {                                                          \
  72                 unsigned long _tmp;                                     \
  73                 __asm__ __volatile__ ("movec %%cacr,%0\n\t"             \
  74                                       "orw %1,%0\n\t"                   \
  75                                       "movec %0,%%cacr"                 \
  76                                       : "=&d" (_tmp)                    \
  77                                       : "di" (FLUSH_I_AND_D));          \
  78         }                                                               \
  79     } while (0)
  80
  81 #define __flush_cache_030()                                             \
  82     do {                                                                \
  83         if (CPU_IS_020_OR_030) {                                        \
  84                 unsigned long _tmp;                                     \
  85                 __asm__ __volatile__ ("movec %%cacr,%0\n\t"             \
  86                                       "orw %1,%0\n\t"                   \
  87                                       "movec %0,%%cacr"                 \
  88                                       : "=&d" (_tmp)                    \
  89                                       : "di" (FLUSH_I_AND_D));          \
  90         }                                                               \
  91     } while (0)
  92
  93 #define flush_cache_all() __flush_cache_all()
  94
  95 extern inline void flush_cache_mm(struct mm_struct *mm)
  96 {
  97         if (mm == current->mm)
  98                 __flush_cache_030();
  99 }
 100
 101 extern inline void flush_cache_range(struct mm_struct *mm,
 102                                      unsigned long start,
 103                                      unsigned long end)
 104 {
 105         if (mm == current->mm)
 106                 __flush_cache_030();
 107 }
 108
 109 extern inline void flush_cache_page(struct vm_area_struct *vma,
 110                                     unsigned long vmaddr)
 111 {
 112         if (vma->vm_mm == current->mm)
 113                 __flush_cache_030();
 114 }
 115
 116 /* Push the page at kernel virtual address and clear the icache */
 117 extern inline void flush_page_to_ram (unsigned long address)
 118 {
 119     if (CPU_IS_040_OR_060) {
 120         __asm__ __volatile__ ("nop\n\t"
 121                               ".chip 68040\n\t"
 122                               "cpushp %%dc,(%0)\n\t"
 123                               "cinvp %%ic,(%0)\n\t"
 124                               ".chip 68k"
 125                               : : "a" (virt_to_phys((void *)address)));
 126     }
 127     else {
 128         unsigned long _tmp;
 129         __asm volatile ("movec %%cacr,%0\n\t"
 130                         "orw %1,%0\n\t"
 131                         "movec %0,%%cacr"
 132                         : "=&d" (_tmp)
 133                         : "di" (FLUSH_I));
 134     }
 135 }
 136
 137 /* Push n pages at kernel virtual address and clear the icache */
 138 extern inline void flush_icache_range (unsigned long address,
 139                                        unsigned long endaddr)
 140 {
 141     if (CPU_IS_040_OR_060) {
 142         short n = (endaddr - address + PAGE_SIZE - 1) / PAGE_SIZE;
 143
 144         while (n--) {
 145             __asm__ __volatile__ ("nop\n\t"
 146                                   ".chip 68040\n\t"
 147                                   "cpushp %%dc,(%0)\n\t"
 148                                   "cinvp %%ic,(%0)\n\t"
 149                                   ".chip 68k"
 150                                   : : "a" (virt_to_phys((void *)address)));
 151             address += PAGE_SIZE;
 152         }
 153     }
 154     else {
 155         unsigned long _tmp;
 156         __asm volatile ("movec %%cacr,%0\n\t"
 157                         "orw %1,%0\n\t"
 158                         "movec %0,%%cacr"
 159                         : "=&d" (_tmp)
 160                         : "di" (FLUSH_I));
 161     }
 162 }
 163
 164
 165 /*
 166  * flush all user-space atc entries.
 167  */
 168 static inline void __flush_tlb(void)
 169 {
 170         if (CPU_IS_040_OR_060)
 171                 __asm__ __volatile__(".chip 68040\n\t"
 172                                      "pflushan\n\t"
 173                                      ".chip 68k");
 174         else
 175                 __asm__ __volatile__("pflush #0,#4");
 176 }
 177
 178 static inline void __flush_tlb_one(unsigned long addr)
 179 {
 180         if (CPU_IS_040_OR_060) {
 181                 __asm__ __volatile__(".chip 68040\n\t"
 182                                      "pflush (%0)\n\t"
 183                                      ".chip 68k"
 184                                      : : "a" (addr));
 185         } else
 186                 __asm__ __volatile__("pflush #0,#4,(%0)" : : "a" (addr));
 187 }
 188
 189 #define flush_tlb() __flush_tlb()
 190
 191 /*
 192  * flush all atc entries (both kernel and user-space entries).
 193  */
 194 static inline void flush_tlb_all(void)
 195 {
 196         if (CPU_IS_040_OR_060)
 197                 __asm__ __volatile__(".chip 68040\n\t"
 198                                      "pflusha\n\t"
 199                                      ".chip 68k");
 200         else
 201                 __asm__ __volatile__("pflusha");
 202 }
 203
 204 static inline void flush_tlb_mm(struct mm_struct *mm)
 205 {
 206         if (mm == current->mm)
 207                 __flush_tlb();
 208 }
 209
 210 static inline void flush_tlb_page(struct vm_area_struct *vma,
 211         unsigned long addr)
 212 {
 213         if (vma->vm_mm == current->mm)
 214                 __flush_tlb_one(addr);
 215 }
 216
 217 static inline void flush_tlb_range(struct mm_struct *mm,
 218         unsigned long start, unsigned long end)
 219 {
 220         if (mm == current->mm)
 221                 __flush_tlb();
 222 }
 223
 224 extern inline void flush_tlb_kernel_page(unsigned long addr)
 225 {
 226         if (CPU_IS_040_OR_060) {
 227                 mm_segment_t old_fs = get_fs();
 228                 set_fs(KERNEL_DS);
 229                 __asm__ __volatile__(".chip 68040\n\t"
 230                                      "pflush (%0)\n\t"
 231                                      ".chip 68k"
 232                                      : : "a" (addr));
 233                 set_fs(old_fs);
 234         } else
 235                 __asm__ __volatile__("pflush #4,#4,(%0)" : : "a" (addr));
 236 }
 237
 238 /* Certain architectures need to do special things when pte's
 239  * within a page table are directly modified.  Thus, the following
 240  * hook is made available.
 241  */
 242 #define set_pte(pteptr, pteval)                                 \
 243         do{                                                     \
 244                 *(pteptr) = (pteval);                           \
 245         } while(0)
 246
 247
 248 /* PMD_SHIFT determines the size of the area a second-level page table can map */
 249 #define PMD_SHIFT       22
 250 #define PMD_SIZE        (1UL << PMD_SHIFT)
 251 #define PMD_MASK        (~(PMD_SIZE-1))
 252
 253 /* PGDIR_SHIFT determines what a third-level page table entry can map */
 254 #define PGDIR_SHIFT     25
 255 #define PGDIR_SIZE      (1UL << PGDIR_SHIFT)
 256 #define PGDIR_MASK      (~(PGDIR_SIZE-1))
 257
 258 /*
 259  * entries per page directory level: the m68k is configured as three-level,
 260  * so we do have PMD level physically.
 261  */
 262 #define PTRS_PER_PTE    1024
 263 #define PTRS_PER_PMD    8
 264 #define PTRS_PER_PGD    128
 265 #define USER_PTRS_PER_PGD       (TASK_SIZE/PGDIR_SIZE)
 266
 267 /* Virtual address region for use by kernel_map() */
 268 #define KMAP_START      0xd0000000
 269 #define KMAP_END        0xf0000000
 270
 271 /* Just any arbitrary offset to the start of the vmalloc VM area: the
 272  * current 8MB value just means that there will be a 8MB "hole" after the
 273  * physical memory until the kernel virtual memory starts.  That means that
 274  * any out-of-bounds memory accesses will hopefully be caught.
 275  * The vmalloc() routines leaves a hole of 4kB between each vmalloced
 276  * area for the same reason. ;)
 277  */
 278 #define VMALLOC_OFFSET  (8*1024*1024)
 279 #define VMALLOC_START (((unsigned long) high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1))
 280 #define VMALLOC_VMADDR(x) ((unsigned long)(x))
 281 #define VMALLOC_END KMAP_START
 282
 283 #endif /* __ASSEMBLY__ */
 284
 285 /*
 286  * Definitions for MMU descriptors
 287  */
 288 #define _PAGE_PRESENT   0x001
 289 #define _PAGE_SHORT     0x002
 290 #define _PAGE_RONLY     0x004
 291 #define _PAGE_ACCESSED  0x008
 292 #define _PAGE_DIRTY     0x010
 293 #define _PAGE_SUPER     0x080   /* 68040 supervisor only */
 294 #define _PAGE_FAKE_SUPER 0x200  /* fake supervisor only on 680[23]0 */
 295 #define _PAGE_GLOBAL040 0x400   /* 68040 global bit, used for kva descs */
 296 #define _PAGE_COW       0x800   /* implemented in software */
 297 #define _PAGE_NOCACHE030 0x040  /* 68030 no-cache mode */
 298 #define _PAGE_NOCACHE   0x060   /* 68040 cache mode, non-serialized */
 299 #define _PAGE_NOCACHE_S 0x040   /* 68040 no-cache mode, serialized */
 300 #define _PAGE_CACHE040  0x020   /* 68040 cache mode, cachable, copyback */
 301 #define _PAGE_CACHE040W 0x000   /* 68040 cache mode, cachable, write-through */
 302
 303 #define _DESCTYPE_MASK  0x003
 304
 305 #define _CACHEMASK040   (~0x060)
 306 #define _TABLE_MASK     (0xfffffe00)
 307
 308 #define _PAGE_TABLE     (_PAGE_SHORT)
 309 #define _PAGE_CHG_MASK  (PAGE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_NOCACHE)
 310
 311 #ifndef __ASSEMBLY__
 312
 313 /* This is the cache mode to be used for pages containing page descriptors for
 314  * processors >= '040. It is in pte_mknocache(), and the variable is defined
 315  * and initialized in head.S */
 316 extern int m68k_pgtable_cachemode;
 317
 318 /* This is the cache mode for normal pages, for supervisor access on
 319  * processors >= '040. It is used in pte_mkcache(), and the variable is
 320  * defined and initialized in head.S */
 321
 322 #if defined(CONFIG_060_WRITETHROUGH)
 323 extern int m68k_supervisor_cachemode;
 324 #else
 325 #define m68k_supervisor_cachemode _PAGE_CACHE040
 326 #endif
 327
 328 #if defined(CPU_M68040_OR_M68060_ONLY)
 329 #define mm_cachebits _PAGE_CACHE040
 330 #elif defined(CPU_M68020_OR_M68030_ONLY)
 331 #define mm_cachebits 0
 332 #else
 333 extern unsigned long mm_cachebits;
 334 #endif
 335
 336 #define PAGE_NONE       __pgprot(_PAGE_PRESENT | _PAGE_RONLY | _PAGE_ACCESSED | mm_cachebits)
 337 #define PAGE_SHARED     __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED | mm_cachebits)
 338 #define PAGE_COPY       __pgprot(_PAGE_PRESENT | _PAGE_RONLY | _PAGE_ACCESSED | mm_cachebits)
 339 #define PAGE_READONLY   __pgprot(_PAGE_PRESENT | _PAGE_RONLY | _PAGE_ACCESSED | mm_cachebits)
 340 #define PAGE_KERNEL     __pgprot(_PAGE_PRESENT | _PAGE_DIRTY | _PAGE_ACCESSED | mm_cachebits)
 341
 342 /* Alternate definitions that are compile time constants, for
 343    initializing protection_map.  The cachebits are fixed later.  */
 344 #define PAGE_NONE_C     __pgprot(_PAGE_PRESENT | _PAGE_RONLY | _PAGE_ACCESSED)
 345 #define PAGE_SHARED_C   __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED)
 346 #define PAGE_COPY_C     __pgprot(_PAGE_PRESENT | _PAGE_RONLY | _PAGE_ACCESSED)
 347 #define PAGE_READONLY_C __pgprot(_PAGE_PRESENT | _PAGE_RONLY | _PAGE_ACCESSED)
 348
 349 /*
 350  * The m68k can't do page protection for execute, and considers that the same are read.
 351  * Also, write permissions imply read permissions. This is the closest we can get..
 352  */
 353 #define __P000  PAGE_NONE_C
 354 #define __P001  PAGE_READONLY_C
 355 #define __P010  PAGE_COPY_C
 356 #define __P011  PAGE_COPY_C
 357 #define __P100  PAGE_READONLY_C
 358 #define __P101  PAGE_READONLY_C
 359 #define __P110  PAGE_COPY_C
 360 #define __P111  PAGE_COPY_C
 361
 362 #define __S000  PAGE_NONE_C
 363 #define __S001  PAGE_READONLY_C
 364 #define __S010  PAGE_SHARED_C
 365 #define __S011  PAGE_SHARED_C
 366 #define __S100  PAGE_READONLY_C
 367 #define __S101  PAGE_READONLY_C
 368 #define __S110  PAGE_SHARED_C
 369 #define __S111  PAGE_SHARED_C
 370
 371 /* zero page used for uninitialized stuff */
 372 extern unsigned long empty_zero_page;
 373
 374 /*
 375  * BAD_PAGETABLE is used when we need a bogus page-table, while
 376  * BAD_PAGE is used for a bogus page.
 377  *
 378  * ZERO_PAGE is a global shared page that is always zero: used
 379  * for zero-mapped memory areas etc..
 380  */
 381 extern pte_t __bad_page(void);
 382 extern pte_t * __bad_pagetable(void);
 383
 384 #define BAD_PAGETABLE __bad_pagetable()
 385 #define BAD_PAGE __bad_page()
 386 #define ZERO_PAGE(vaddr) empty_zero_page
 387
 388 /* number of bits that fit into a memory pointer */
 389 #define BITS_PER_PTR                    (8*sizeof(unsigned long))
 390
 391 /* to align the pointer to a pointer address */
 392 #define PTR_MASK                        (~(sizeof(void*)-1))
 393
 394 /* sizeof(void*)==1<<SIZEOF_PTR_LOG2 */
 395 /* 64-bit machines, beware!  SRB. */
 396 #define SIZEOF_PTR_LOG2                 2
 397
 398 /* to find an entry in a page-table */
 399 #define PAGE_PTR(address) \
 400 ((unsigned long)(address)>>(PAGE_SHIFT-SIZEOF_PTR_LOG2)&PTR_MASK&~PAGE_MASK)
 401
 402 /*
 403  * Conversion functions: convert a page and protection to a page entry,
 404  * and a page entry and page directory to the page they refer to.
 405  */
 406 #define mk_pte(page, pgprot) \
 407 ({ pte_t __pte; pte_val(__pte) = virt_to_phys((void *)page) + pgprot_val(pgprot); __pte; })
 408 #define mk_pte_phys(physpage, pgprot) \
 409 ({ pte_t __pte; pte_val(__pte) = (unsigned long)physpage + pgprot_val(pgprot); __pte; })
 410
 411 extern inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
 412 { pte_val(pte) = (pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot); return pte; }
 413
 414 extern inline void pmd_set(pmd_t * pmdp, pte_t * ptep)
 415 {
 416         int i;
 417         unsigned long ptbl;
 418         ptbl = virt_to_phys(ptep) | _PAGE_TABLE | _PAGE_ACCESSED;
 419         for (i = 0; i < 16; i++, ptbl += (sizeof(pte_t)*PTRS_PER_PTE/16))
 420                 pmdp->pmd[i] = ptbl;
 421 }
 422
 423 extern inline void pgd_set(pgd_t * pgdp, pmd_t * pmdp)
 424 { pgd_val(*pgdp) = _PAGE_TABLE | _PAGE_ACCESSED | virt_to_phys(pmdp); }
 425
 426 extern inline unsigned long pte_page(pte_t pte)
 427 { return (unsigned long)phys_to_virt(pte_val(pte) & PAGE_MASK); }
 428
 429 extern inline unsigned long pmd_page2(pmd_t *pmd)
 430 { return (unsigned long)phys_to_virt(pmd_val(*pmd) & _TABLE_MASK); }
 431 #define pmd_page(pmd) pmd_page2(&(pmd))
 432
 433 extern inline unsigned long pgd_page(pgd_t pgd)
 434 { return (unsigned long)phys_to_virt(pgd_val(pgd) & _TABLE_MASK); }
 435
 436 extern inline int pte_none(pte_t pte)           { return !pte_val(pte); }
 437 extern inline int pte_present(pte_t pte)        { return pte_val(pte) & (_PAGE_PRESENT | _PAGE_FAKE_SUPER); }
 438 extern inline void pte_clear(pte_t *ptep)       { pte_val(*ptep) = 0; }
 439
 440 extern inline int pmd_none2(pmd_t *pmd)         { return !pmd_val(*pmd); }
 441 #define pmd_none(pmd) pmd_none2(&(pmd))
 442 extern inline int pmd_bad2(pmd_t *pmd)          { return (pmd_val(*pmd) & _DESCTYPE_MASK) != _PAGE_TABLE; }
 443 #define pmd_bad(pmd) pmd_bad2(&(pmd))
 444 extern inline int pmd_present2(pmd_t *pmd)      { return pmd_val(*pmd) & _PAGE_TABLE; }
 445 #define pmd_present(pmd) pmd_present2(&(pmd))
 446 extern inline void pmd_clear(pmd_t * pmdp)
 447 {
 448         short i;
 449
 450         for (i = 15; i >= 0; i--)
 451                 pmdp->pmd[i] = 0;
 452 }
 453
 454 extern inline int pgd_none(pgd_t pgd)           { return !pgd_val(pgd); }
 455 extern inline int pgd_bad(pgd_t pgd)            { return (pgd_val(pgd) & _DESCTYPE_MASK) != _PAGE_TABLE; }
 456 extern inline int pgd_present(pgd_t pgd)        { return pgd_val(pgd) & _PAGE_TABLE; }
 457
 458 extern inline void pgd_clear(pgd_t * pgdp)      { pgd_val(*pgdp) = 0; }
 459
 460 /*
 461  * The following only work if pte_present() is true.
 462  * Undefined behaviour if not..
 463  */
 464 extern inline int pte_read(pte_t pte)           { return 1; }
 465 extern inline int pte_write(pte_t pte)          { return !(pte_val(pte) & _PAGE_RONLY); }
 466 extern inline int pte_exec(pte_t pte)           { return 1; }
 467 extern inline int pte_dirty(pte_t pte)          { return pte_val(pte) & _PAGE_DIRTY; }
 468 extern inline int pte_young(pte_t pte)          { return pte_val(pte) & _PAGE_ACCESSED; }
 469
 470 extern inline pte_t pte_wrprotect(pte_t pte)    { pte_val(pte) |= _PAGE_RONLY; return pte; }
 471 extern inline pte_t pte_rdprotect(pte_t pte)    { return pte; }
 472 extern inline pte_t pte_exprotect(pte_t pte)    { return pte; }
 473 extern inline pte_t pte_mkclean(pte_t pte)      { pte_val(pte) &= ~_PAGE_DIRTY; return pte; }
 474 extern inline pte_t pte_mkold(pte_t pte)        { pte_val(pte) &= ~_PAGE_ACCESSED; return pte; }
 475 extern inline pte_t pte_mkwrite(pte_t pte)      { pte_val(pte) &= ~_PAGE_RONLY; return pte; }
 476 extern inline pte_t pte_mkread(pte_t pte)       { return pte; }
 477 extern inline pte_t pte_mkexec(pte_t pte)       { return pte; }
 478 extern inline pte_t pte_mkdirty(pte_t pte)      { pte_val(pte) |= _PAGE_DIRTY; return pte; }
 479 extern inline pte_t pte_mkyoung(pte_t pte)      { pte_val(pte) |= _PAGE_ACCESSED; return pte; }
 480 extern inline pte_t pte_mknocache(pte_t pte)
 481 {
 482         pte_val(pte) = (pte_val(pte) & _CACHEMASK040) | m68k_pgtable_cachemode;
 483         return pte;
 484 }
 485 extern inline pte_t pte_mkcache(pte_t pte)      { pte_val(pte) = (pte_val(pte) & _CACHEMASK040) | m68k_supervisor_cachemode; return pte; }
 486
 487 #define PAGE_DIR_OFFSET(tsk,address) pgd_offset((tsk),(address))
 488
 489 /* to find an entry in a page-table-directory */
 490 extern inline pgd_t * pgd_offset(struct mm_struct * mm, unsigned long address)
 491 {
 492         return mm->pgd + (address >> PGDIR_SHIFT);
 493 }
 494
 495 #define swapper_pg_dir kernel_pg_dir
 496 extern pgd_t kernel_pg_dir[128];
 497
 498 extern inline pgd_t * pgd_offset_k(unsigned long address)
 499 {
 500         return kernel_pg_dir + (address >> PGDIR_SHIFT);
 501 }
 502
 503
 504 /* Find an entry in the second-level page table.. */
 505 extern inline pmd_t * pmd_offset(pgd_t * dir, unsigned long address)
 506 {
 507         return (pmd_t *) pgd_page(*dir) + ((address >> PMD_SHIFT) & (PTRS_PER_PMD-1));
 508 }
 509
 510 /* Find an entry in the third-level page table.. */
 511 extern inline pte_t * pte_offset(pmd_t * pmdp, unsigned long address)
 512 {
 513         return (pte_t *) pmd_page(*pmdp) + ((address >> PAGE_SHIFT) & (PTRS_PER_PTE - 1));
 514 }
 515
 516 /*
 517  * Allocate and free page tables. The xxx_kernel() versions are
 518  * used to allocate a kernel page table - this turns on ASN bits
 519  * if any.
 520  */
 521
 522 /* Prior to calling these routines, the page should have been flushed
 523  * from both the cache and ATC, or the CPU might not notice that the
 524  * cache setting for the page has been changed. -jskov
 525  */
 526 static inline void nocache_page (unsigned long vaddr)
 527 {
 528         if (CPU_IS_040_OR_060) {
 529                 pgd_t *dir;
 530                 pmd_t *pmdp;
 531                 pte_t *ptep;
 532
 533                 dir = pgd_offset_k(vaddr);
 534                 pmdp = pmd_offset(dir,vaddr);
 535                 ptep = pte_offset(pmdp,vaddr);
 536                 *ptep = pte_mknocache(*ptep);
 537         }
 538 }
 539
 540 static inline void cache_page (unsigned long vaddr)
 541 {
 542         if (CPU_IS_040_OR_060) {
 543                 pgd_t *dir;
 544                 pmd_t *pmdp;
 545                 pte_t *ptep;
 546
 547                 dir = pgd_offset_k(vaddr);
 548                 pmdp = pmd_offset(dir,vaddr);
 549                 ptep = pte_offset(pmdp,vaddr);
 550                 *ptep = pte_mkcache(*ptep);
 551         }
 552 }
 553
 554 extern struct pgtable_cache_struct {
 555         unsigned long *pmd_cache;
 556         unsigned long *pte_cache;
 557 /* This counts in units of pointer tables, of which can be eight per page. */
 558         unsigned long pgtable_cache_sz;
 559 } quicklists;
 560
 561 #define pgd_quicklist ((unsigned long *)0)
 562 #define pmd_quicklist (quicklists.pmd_cache)
 563 #define pte_quicklist (quicklists.pte_cache)
 564 /* This isn't accurate because of fragmentation of allocated pages for
 565    pointer tables, but that should not be a problem. */
 566 #define pgtable_cache_size ((quicklists.pgtable_cache_sz+7)/8)
 567
 568 extern pte_t *get_pte_slow(pmd_t *pmd, unsigned long offset);
 569 extern pmd_t *get_pmd_slow(pgd_t *pgd, unsigned long offset);
 570
 571 extern pmd_t *get_pointer_table(void);
 572 extern int free_pointer_table(pmd_t *);
 573
 574 extern __inline__ pte_t *get_pte_fast(void)
 575 {
 576         unsigned long *ret;
 577
 578         ret = pte_quicklist;
 579         if (ret) {
 580                 pte_quicklist = (unsigned long *)*ret;
 581                 ret[0] = 0;
 582                 quicklists.pgtable_cache_sz -= 8;
 583         }
 584         return (pte_t *)ret;
 585 }
 586
 587 extern __inline__ void free_pte_fast(pte_t *pte)
 588 {
 589         *(unsigned long *)pte = (unsigned long)pte_quicklist;
 590         pte_quicklist = (unsigned long *)pte;
 591         quicklists.pgtable_cache_sz += 8;
 592 }
 593
 594 extern __inline__ void free_pte_slow(pte_t *pte)
 595 {
 596         cache_page((unsigned long)pte);
 597         free_page((unsigned long) pte);
 598 }
 599
 600 extern __inline__ pmd_t *get_pmd_fast(void)
 601 {
 602         unsigned long *ret;
 603
 604         ret = pmd_quicklist;
 605         if (ret) {
 606                 pmd_quicklist = (unsigned long *)*ret;
 607                 ret[0] = 0;
 608                 quicklists.pgtable_cache_sz--;
 609         }
 610         return (pmd_t *)ret;
 611 }
 612
 613 extern __inline__ void free_pmd_fast(pmd_t *pmd)
 614 {
 615         *(unsigned long *)pmd = (unsigned long)pmd_quicklist;
 616         pmd_quicklist = (unsigned long *) pmd;
 617         quicklists.pgtable_cache_sz++;
 618 }
 619
 620 extern __inline__ int free_pmd_slow(pmd_t *pmd)
 621 {
 622         return free_pointer_table(pmd);
 623 }
 624
 625 /* The pgd cache is folded into the pmd cache, so these are dummy routines. */
 626 extern __inline__ pgd_t *get_pgd_fast(void)
 627 {
 628         return (pgd_t *)0;
 629 }
 630
 631 extern __inline__ void free_pgd_fast(pgd_t *pgd)
 632 {
 633 }
 634
 635 extern __inline__ void free_pgd_slow(pgd_t *pgd)
 636 {
 637 }
 638
 639 extern void __bad_pte(pmd_t *pmd);
 640 extern void __bad_pmd(pgd_t *pgd);
 641
 642 extern inline void pte_free(pte_t * pte)
 643 {
 644         free_pte_fast(pte);
 645 }
 646
 647 extern inline pte_t * pte_alloc(pmd_t * pmd, unsigned long address)
 648 {
 649         address = (address >> PAGE_SHIFT) & (PTRS_PER_PTE - 1);
 650         if (pmd_none(*pmd)) {
 651                 pte_t * page = get_pte_fast();
 652
 653                 if (!page)
 654                         return get_pte_slow(pmd, address);
 655                 pmd_set(pmd,page);
 656                 return page + address;
 657         }
 658         if (pmd_bad(*pmd)) {
 659                 __bad_pte(pmd);
 660                 return NULL;
 661         }
 662         return (pte_t *) pmd_page(*pmd) + address;
 663 }
 664
 665 extern inline void pmd_free(pmd_t * pmd)
 666 {
 667         free_pmd_fast(pmd);
 668 }
 669
 670 extern inline pmd_t * pmd_alloc(pgd_t * pgd, unsigned long address)
 671 {
 672         address = (address >> PMD_SHIFT) & (PTRS_PER_PMD - 1);
 673         if (pgd_none(*pgd)) {
 674                 pmd_t *page = get_pmd_fast();
 675
 676                 if (!page)
 677                         return get_pmd_slow(pgd, address);
 678                 pgd_set(pgd, page);
 679                 return page + address;
 680         }
 681         if (pgd_bad(*pgd)) {
 682                 __bad_pmd(pgd);
 683                 return NULL;
 684         }
 685         return (pmd_t *) pgd_page(*pgd) + address;
 686 }
 687
 688 extern inline void pte_free_kernel(pte_t * pte)
 689 {
 690         free_pte_fast(pte);
 691 }
 692
 693 extern inline pte_t * pte_alloc_kernel(pmd_t * pmd, unsigned long address)
 694 {
 695         return pte_alloc(pmd, address);
 696 }
 697
 698 extern inline void pmd_free_kernel(pmd_t * pmd)
 699 {
 700         free_pmd_fast(pmd);
 701 }
 702
 703 extern inline pmd_t * pmd_alloc_kernel(pgd_t * pgd, unsigned long address)
 704 {
 705         return pmd_alloc(pgd, address);
 706 }
 707
 708 extern inline void pgd_free(pgd_t * pgd)
 709 {
 710         free_pmd_fast((pmd_t *)pgd);
 711 }
 712
 713 extern inline pgd_t * pgd_alloc(void)
 714 {
 715         pgd_t *pgd = (pgd_t *)get_pmd_fast();
 716         if (!pgd)
 717                 pgd = (pgd_t *)get_pointer_table();
 718         return pgd;
 719 }
 720
 721 extern int do_check_pgt_cache(int, int);
 722
 723 extern inline void set_pgdir(unsigned long address, pgd_t entry)
 724 {
 725 }
 726
 727 /*
 728  * Check if the addr/len goes up to the end of a physical
 729  * memory chunk.  Used for DMA functions.
 730  */
 731 #ifdef CONFIG_SINGLE_MEMORY_CHUNK
 732 /*
 733  * It makes no sense to consider whether we cross a memory boundary if
 734  * we support just one physical chunk of memory.
 735  */
 736 extern inline int mm_end_of_chunk (unsigned long addr, int len)
 737 {
 738         return 0;
 739 }
 740 #else
 741 int mm_end_of_chunk (unsigned long addr, int len);
 742 #endif
 743
 744 extern void kernel_set_cachemode(void *addr, unsigned long size, int cmode);
 745
 746 /*
 747  * The m68k doesn't have any external MMU info: the kernel page
 748  * tables contain all the necessary information.
 749  */
 750 extern inline void update_mmu_cache(struct vm_area_struct * vma,
 751         unsigned long address, pte_t pte)
 752 {
 753 }
 754
 755 /*
 756  * I don't know what is going on here, but since these were changed,
 757  * swapping hasn't been working on the 68040.
 758  */
 759 /* With the new handling of PAGE_NONE the old definitions definitely
 760    don't work any more.  */
 761
 762 #define SWP_TYPE(entry)  (((entry) >> 2) & 0x7f)
 763 #if 0
 764 #define SWP_OFFSET(entry) ((entry) >> 9)
 765 #define SWP_ENTRY(type,offset) (((type) << 2) | ((offset) << 9))
 766 #else
 767 #define SWP_OFFSET(entry) ((entry) >> PAGE_SHIFT)
 768 #define SWP_ENTRY(type,offset) (((type) << 2) | ((offset) << PAGE_SHIFT))
 769 #endif
 770
 771 #endif /* __ASSEMBLY__ */
 772
 773 #define module_map      vmalloc
 774 #define module_unmap    vfree
 775
 776 /* Needs to be defined here and not in linux/mm.h, as it is arch dependent */
 777 #define PageSkip(page)          (0)
 778 #define kern_addr_valid(addr)   (1)
 779
 780 #endif /* _M68K_PGTABLE_H */