4 #define flush_cache_all() do { } while (0)
5 #define flush_cache_mm(mm) do { } while (0)
6 #define flush_cache_range(mm,start,end) do { } while (0)
7 #define flush_cache_page(vma,vmaddr) do { } while (0)
8 #define flush_page_to_ram(page) do { } while (0)
9 #define flush_icache_page(vma,page) do { } while (0)
10 #define flush_icache_range(start,end) do { } while (0)
15 * - flush_tlb_all() flushes all processes TLBs
16 * - flush_tlb_mm(mm) flushes the specified mm context TLB's
17 * - flush_tlb_page(vma, vmaddr) flushes one page
18 * - flush_tlb_range(mm, start, end) flushes a range of pages
20 #define flush_tlb_all() memc_update_all()
21 #define flush_tlb_mm(mm) do { } while (0)
22 #define flush_tlb_range(mm, start, end) do { (void)(start); (void)(end); } while (0)
23 #define flush_tlb_page(vma, vmaddr) do { } while (0)
26 * The following handle the weird MEMC chip
28 extern __inline__
void memc_update_all(void)
30 struct task_struct
*p
;
32 cpu_memc_update_all(init_mm
.pgd
);
36 cpu_memc_update_all(p
->mm
->pgd
);
38 processor
._set_pgd(current
->active_mm
->pgd
);
41 extern __inline__
void memc_update_mm(struct mm_struct
*mm
)
43 cpu_memc_update_all(mm
->pgd
);
45 if (mm
== current
->active_mm
)
46 processor
._set_pgd(mm
->pgd
);
49 extern __inline__
void
50 memc_update_addr(struct mm_struct
*mm
, pte_t pte
, unsigned long vaddr
)
52 cpu_memc_update_entry(mm
->pgd
, pte_val(pte
), vaddr
);
54 if (mm
== current
->active_mm
)
55 processor
._set_pgd(mm
->pgd
);
58 extern __inline__
void
59 memc_clear(struct mm_struct
*mm
, struct page
*page
)
61 cpu_memc_update_entry(mm
->pgd
, page_address(page
), 0);
63 if (mm
== current
->active_mm
)
64 processor
._set_pgd(mm
->pgd
);
67 #define __flush_entry_to_ram(entry)